projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Linux 3.1-rc1
[deliverable/linux.git] / drivers / block / cciss.c
CommitLineData
1da177e4 1/*
bd4f36d6
MM		 2 * Disk Array driver for HP Smart Array controllers.
3 * (C) Copyright 2000, 2007 Hewlett-Packard Development Company, L.P.
1da177e4
LT		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
bd4f36d6 7 * the Free Software Foundation; version 2 of the License.
1da177e4
LT		 8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
bd4f36d6
MM		 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
1da177e4
LT		 13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
bd4f36d6
MM		 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
17 * 02111-1307, USA.
1da177e4
LT		 18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22
1da177e4
LT		 23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/types.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/major.h>
31#include <linux/fs.h>
32#include <linux/bio.h>
33#include <linux/blkpg.h>
34#include <linux/timer.h>
35#include <linux/proc_fs.h>
89b6e743 36#include <linux/seq_file.h>
7c832835 37#include <linux/init.h>
4d761609 38#include <linux/jiffies.h>
1da177e4
LT		 39#include <linux/hdreg.h>
40#include <linux/spinlock.h>
41#include <linux/compat.h>
b368c9dd 42#include <linux/mutex.h>
1da177e4
LT		 43#include <asm/uaccess.h>
44#include <asm/io.h>
45
eb0df996 46#include <linux/dma-mapping.h>
1da177e4
LT		 47#include <linux/blkdev.h>
48#include <linux/genhd.h>
49#include <linux/completion.h>
d5d3b736 50#include <scsi/scsi.h>
03bbfee5
MMOD		 51#include <scsi/sg.h>
52#include <scsi/scsi_ioctl.h>
53#include <linux/cdrom.h>
231bc2a2 54#include <linux/scatterlist.h>
0a9279cc 55#include <linux/kthread.h>
1da177e4
LT		 56
57#define CCISS_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
841fdffd
MM		 58#define DRIVER_NAME "HP CISS Driver (v 3.6.26)"
59#define DRIVER_VERSION CCISS_DRIVER_VERSION(3, 6, 26)
1da177e4
LT		 60
61/* Embedded module documentation macros - see modules.h */
62MODULE_AUTHOR("Hewlett-Packard Company");
24aac480 63MODULE_DESCRIPTION("Driver for HP Smart Array Controllers");
841fdffd
MM		 64MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
65MODULE_VERSION("3.6.26");
1da177e4 66MODULE_LICENSE("GPL");
8a4ec67b
SC		 67static int cciss_tape_cmds = 6;
68module_param(cciss_tape_cmds, int, 0644);
69MODULE_PARM_DESC(cciss_tape_cmds,
70 "number of commands to allocate for tape devices (default: 6)");
1da177e4 71
2a48fc0a 72static DEFINE_MUTEX(cciss_mutex);
bbe425cd 73static struct proc_dir_entry *proc_cciss;
2ec24ff1 74
1da177e4
LT		 75#include "cciss_cmd.h"
76#include "cciss.h"
77#include <linux/cciss_ioctl.h>
78
79/* define the PCI info for the cards we can control */
80static const struct pci_device_id cciss_pci_device_id[] = {
f82ccdb9
BH		 81 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISS, 0x0E11, 0x4070},
82 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4080},
83 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4082},
84 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4083},
85 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x4091},
86 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409A},
87 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409B},
88 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409C},
89 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409D},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSA, 0x103C, 0x3225},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3223},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3234},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3235},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3211},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3212},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3213},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3214},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3215},
de923916 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3237},
9cff3b38 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x323D},
1da177e4
LT		 101 {0,}
102};
7c832835 103
1da177e4
LT		 104MODULE_DEVICE_TABLE(pci, cciss_pci_device_id);
105
1da177e4
LT		 106/* board_id = Subsystem Device ID & Vendor ID
107 * product = Marketing Name for the board
7c832835 108 * access = Address of the struct of function pointers
1da177e4
LT		 109 */
110static struct board_type products[] = {
49153998
MM		 111 {0x40700E11, "Smart Array 5300", &SA5_access},
112 {0x40800E11, "Smart Array 5i", &SA5B_access},
113 {0x40820E11, "Smart Array 532", &SA5B_access},
114 {0x40830E11, "Smart Array 5312", &SA5B_access},
115 {0x409A0E11, "Smart Array 641", &SA5_access},
116 {0x409B0E11, "Smart Array 642", &SA5_access},
117 {0x409C0E11, "Smart Array 6400", &SA5_access},
118 {0x409D0E11, "Smart Array 6400 EM", &SA5_access},
119 {0x40910E11, "Smart Array 6i", &SA5_access},
120 {0x3225103C, "Smart Array P600", &SA5_access},
4205df34
SC		 121 {0x3223103C, "Smart Array P800", &SA5_access},
122 {0x3234103C, "Smart Array P400", &SA5_access},
49153998
MM		 123 {0x3235103C, "Smart Array P400i", &SA5_access},
124 {0x3211103C, "Smart Array E200i", &SA5_access},
125 {0x3212103C, "Smart Array E200", &SA5_access},
126 {0x3213103C, "Smart Array E200i", &SA5_access},
127 {0x3214103C, "Smart Array E200i", &SA5_access},
128 {0x3215103C, "Smart Array E200i", &SA5_access},
129 {0x3237103C, "Smart Array E500", &SA5_access},
2ec24ff1
SC		 130 {0x3223103C, "Smart Array P800", &SA5_access},
131 {0x3234103C, "Smart Array P400", &SA5_access},
49153998 132 {0x323D103C, "Smart Array P700m", &SA5_access},
1da177e4
LT		 133};
134
d14c4ab5 135/* How long to wait (in milliseconds) for board to go into simple mode */
7c832835 136#define MAX_CONFIG_WAIT 30000
1da177e4
LT		 137#define MAX_IOCTL_CONFIG_WAIT 1000
138
139/*define how many times we will try a command because of bus resets */
140#define MAX_CMD_RETRIES 3
141
1da177e4
LT		 142#define MAX_CTLR 32
143
144/* Originally cciss driver only supports 8 major numbers */
145#define MAX_CTLR_ORIG 8
146
1da177e4
LT		 147static ctlr_info_t *hba[MAX_CTLR];
148
b368c9dd
AP		 149static struct task_struct *cciss_scan_thread;
150static DEFINE_MUTEX(scan_mutex);
151static LIST_HEAD(scan_q);
152
165125e1 153static void do_cciss_request(struct request_queue *q);
0c2b3908
MM		 154static irqreturn_t do_cciss_intx(int irq, void *dev_id);
155static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
ef7822c2 156static int cciss_open(struct block_device *bdev, fmode_t mode);
6e9624b8 157static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
ef7822c2 158static int cciss_release(struct gendisk *disk, fmode_t mode);
8a6cfeb6
AB		 159static int do_ioctl(struct block_device *bdev, fmode_t mode,
160 unsigned int cmd, unsigned long arg);
ef7822c2 161static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
7c832835 162 unsigned int cmd, unsigned long arg);
a885c8c4 163static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
1da177e4 164
1da177e4 165static int cciss_revalidate(struct gendisk *disk);
2d11d993 166static int rebuild_lun_table(ctlr_info_t *h, int first_time, int via_ioctl);
a0ea8622 167static int deregister_disk(ctlr_info_t *h, int drv_index,
2d11d993 168 int clear_all, int via_ioctl);
1da177e4 169
f70dba83 170static void cciss_read_capacity(ctlr_info_t *h, int logvol,
00988a35 171 sector_t *total_size, unsigned int *block_size);
f70dba83 172static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
00988a35 173 sector_t *total_size, unsigned int *block_size);
f70dba83 174static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
7b838bde 175 sector_t total_size,
00988a35 176 unsigned int block_size, InquiryData_struct *inq_buff,
7c832835 177 drive_info_struct *drv);
dac5488a 178static void __devinit cciss_interrupt_mode(ctlr_info_t *);
7c832835 179static void start_io(ctlr_info_t *h);
f70dba83 180static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
b57695fe 181 __u8 page_code, unsigned char scsi3addr[],
182 int cmd_type);
85cc61ae 183static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
184 int attempt_retry);
185static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c);
1da177e4 186
d6f4965d 187static int add_to_scan_list(struct ctlr_info *h);
0a9279cc
MM		 188static int scan_thread(void *data);
189static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c);
617e1344
SC		 190static void cciss_hba_release(struct device *dev);
191static void cciss_device_release(struct device *dev);
361e9b07 192static void cciss_free_gendisk(ctlr_info_t *h, int drv_index);
9cef0d2f 193static void cciss_free_drive_info(ctlr_info_t *h, int drv_index);
29979a71 194static inline u32 next_command(ctlr_info_t *h);
a6528d01
SC		 195static int __devinit cciss_find_cfg_addrs(struct pci_dev *pdev,
196 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
197 u64 *cfg_offset);
198static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,
199 unsigned long *memory_bar);
16011131 200static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag);
62710ae1
SC		 201static __devinit int write_driver_ver_to_cfgtable(
202 CfgTable_struct __iomem *cfgtable);
33079b21 203
5e216153
MM		 204/* performant mode helper functions */
205static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,
206 int *bucket_map);
207static void cciss_put_controller_into_performant_mode(ctlr_info_t *h);
33079b21 208
1da177e4 209#ifdef CONFIG_PROC_FS
f70dba83 210static void cciss_procinit(ctlr_info_t *h);
1da177e4 211#else
f70dba83 212static void cciss_procinit(ctlr_info_t *h)
7c832835
BH		 213{
214}
215#endif /* CONFIG_PROC_FS */
1da177e4
LT		 216
217#ifdef CONFIG_COMPAT
ef7822c2
AV		 218static int cciss_compat_ioctl(struct block_device *, fmode_t,
219 unsigned, unsigned long);
1da177e4
LT		 220#endif
221
83d5cde4 222static const struct block_device_operations cciss_fops = {
7c832835 223 .owner = THIS_MODULE,
6e9624b8 224 .open = cciss_unlocked_open,
ef7822c2 225 .release = cciss_release,
8a6cfeb6 226 .ioctl = do_ioctl,
7c832835 227 .getgeo = cciss_getgeo,
1da177e4 228#ifdef CONFIG_COMPAT
ef7822c2 229 .compat_ioctl = cciss_compat_ioctl,
1da177e4 230#endif
7c832835 231 .revalidate_disk = cciss_revalidate,
1da177e4
LT		 232};
233
5e216153
MM		 234/* set_performant_mode: Modify the tag for cciss performant
235 * set bit 0 for pull model, bits 3-1 for block fetch
236 * register number
237 */
238static void set_performant_mode(ctlr_info_t *h, CommandList_struct *c)
239{
0498cc2a 240 if (likely(h->transMethod & CFGTBL_Trans_Performant))
5e216153
MM		 241 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
242}
243
1da177e4
LT		 244/*
245 * Enqueuing and dequeuing functions for cmdlists.
246 */
e6e1ee93 247static inline void addQ(struct list_head *list, CommandList_struct *c)
1da177e4 248{
e6e1ee93 249 list_add_tail(&c->list, list);
1da177e4
LT		 250}
251
8a3173de 252static inline void removeQ(CommandList_struct *c)
1da177e4 253{
b59e64d0
HR		 254 /*
255 * After kexec/dump some commands might still
256 * be in flight, which the firmware will try
257 * to complete. Resetting the firmware doesn't work
258 * with old fw revisions, so we have to mark
259 * them off as 'stale' to prevent the driver from
260 * falling over.
261 */
e6e1ee93 262 if (WARN_ON(list_empty(&c->list))) {
b59e64d0 263 c->cmd_type = CMD_MSG_STALE;
8a3173de 264 return;
b59e64d0 265 }
8a3173de 266
e6e1ee93 267 list_del_init(&c->list);
1da177e4
LT		 268}
269
664a717d
MM		 270static void enqueue_cmd_and_start_io(ctlr_info_t *h,
271 CommandList_struct *c)
272{
273 unsigned long flags;
5e216153 274 set_performant_mode(h, c);
664a717d
MM		 275 spin_lock_irqsave(&h->lock, flags);
276 addQ(&h->reqQ, c);
277 h->Qdepth++;
2a643ec6
SC		 278 if (h->Qdepth > h->maxQsinceinit)
279 h->maxQsinceinit = h->Qdepth;
664a717d
MM		 280 start_io(h);
281 spin_unlock_irqrestore(&h->lock, flags);
282}
283
dccc9b56 284static void cciss_free_sg_chain_blocks(SGDescriptor_struct **cmd_sg_list,
49fc5601
SC		 285 int nr_cmds)
286{
287 int i;
288
289 if (!cmd_sg_list)
290 return;
291 for (i = 0; i < nr_cmds; i++) {
dccc9b56
SC		 292 kfree(cmd_sg_list[i]);
293 cmd_sg_list[i] = NULL;
49fc5601
SC		 294 }
295 kfree(cmd_sg_list);
296}
297
dccc9b56
SC		 298static SGDescriptor_struct **cciss_allocate_sg_chain_blocks(
299 ctlr_info_t *h, int chainsize, int nr_cmds)
49fc5601
SC		 300{
301 int j;
dccc9b56 302 SGDescriptor_struct **cmd_sg_list;
49fc5601
SC		 303
304 if (chainsize <= 0)
305 return NULL;
306
307 cmd_sg_list = kmalloc(sizeof(*cmd_sg_list) * nr_cmds, GFP_KERNEL);
308 if (!cmd_sg_list)
309 return NULL;
310
311 /* Build up chain blocks for each command */
312 for (j = 0; j < nr_cmds; j++) {
49fc5601 313 /* Need a block of chainsized s/g elements. */
dccc9b56
SC		 314 cmd_sg_list[j] = kmalloc((chainsize *
315 sizeof(*cmd_sg_list[j])), GFP_KERNEL);
316 if (!cmd_sg_list[j]) {
49fc5601
SC		 317 dev_err(&h->pdev->dev, "Cannot get memory "
318 "for s/g chains.\n");
319 goto clean;
320 }
321 }
322 return cmd_sg_list;
323clean:
324 cciss_free_sg_chain_blocks(cmd_sg_list, nr_cmds);
325 return NULL;
326}
327
d45033ef
SC		 328static void cciss_unmap_sg_chain_block(ctlr_info_t *h, CommandList_struct *c)
329{
330 SGDescriptor_struct *chain_sg;
331 u64bit temp64;
332
333 if (c->Header.SGTotal <= h->max_cmd_sgentries)
334 return;
335
336 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
337 temp64.val32.lower = chain_sg->Addr.lower;
338 temp64.val32.upper = chain_sg->Addr.upper;
339 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
340}
341
342static void cciss_map_sg_chain_block(ctlr_info_t *h, CommandList_struct *c,
343 SGDescriptor_struct *chain_block, int len)
344{
345 SGDescriptor_struct *chain_sg;
346 u64bit temp64;
347
348 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
349 chain_sg->Ext = CCISS_SG_CHAIN;
350 chain_sg->Len = len;
351 temp64.val = pci_map_single(h->pdev, chain_block, len,
352 PCI_DMA_TODEVICE);
353 chain_sg->Addr.lower = temp64.val32.lower;
354 chain_sg->Addr.upper = temp64.val32.upper;
355}
356
1da177e4
LT		 357#include "cciss_scsi.c" /* For SCSI tape support */
358
1e6f2dc1
AB		 359static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
360 "UNKNOWN"
361};
0e4a9d03 362#define RAID_UNKNOWN (ARRAY_SIZE(raid_label)-1)
0f5486ec 363
1da177e4
LT		 364#ifdef CONFIG_PROC_FS
365
366/*
367 * Report information about this controller.
368 */
369#define ENG_GIG 1000000000
370#define ENG_GIG_FACTOR (ENG_GIG/512)
89b6e743 371#define ENGAGE_SCSI "engage scsi"
1da177e4 372
89b6e743 373static void cciss_seq_show_header(struct seq_file *seq)
1da177e4 374{
89b6e743
MM		 375 ctlr_info_t *h = seq->private;
376
377 seq_printf(seq, "%s: HP %s Controller\n"
378 "Board ID: 0x%08lx\n"
379 "Firmware Version: %c%c%c%c\n"
380 "IRQ: %d\n"
381 "Logical drives: %d\n"
382 "Current Q depth: %d\n"
383 "Current # commands on controller: %d\n"
384 "Max Q depth since init: %d\n"
385 "Max # commands on controller since init: %d\n"
386 "Max SG entries since init: %d\n",
387 h->devname,
388 h->product_name,
389 (unsigned long)h->board_id,
390 h->firm_ver[0], h->firm_ver[1], h->firm_ver[2],
5e216153 391 h->firm_ver[3], (unsigned int)h->intr[PERF_MODE_INT],
89b6e743
MM		 392 h->num_luns,
393 h->Qdepth, h->commands_outstanding,
394 h->maxQsinceinit, h->max_outstanding, h->maxSG);
395
396#ifdef CONFIG_CISS_SCSI_TAPE
f70dba83 397 cciss_seq_tape_report(seq, h);
89b6e743
MM		 398#endif /* CONFIG_CISS_SCSI_TAPE */
399}
1da177e4 400
89b6e743
MM		 401static void *cciss_seq_start(struct seq_file *seq, loff_t *pos)
402{
403 ctlr_info_t *h = seq->private;
89b6e743 404 unsigned long flags;
1da177e4
LT		 405
406 /* prevent displaying bogus info during configuration
407 * or deconfiguration of a logical volume
408 */
f70dba83 409 spin_lock_irqsave(&h->lock, flags);
1da177e4 410 if (h->busy_configuring) {
f70dba83 411 spin_unlock_irqrestore(&h->lock, flags);
89b6e743 412 return ERR_PTR(-EBUSY);
1da177e4
LT		 413 }
414 h->busy_configuring = 1;
f70dba83 415 spin_unlock_irqrestore(&h->lock, flags);
1da177e4 416
89b6e743
MM		 417 if (*pos == 0)
418 cciss_seq_show_header(seq);
419
420 return pos;
421}
422
423static int cciss_seq_show(struct seq_file *seq, void *v)
424{
425 sector_t vol_sz, vol_sz_frac;
426 ctlr_info_t *h = seq->private;
427 unsigned ctlr = h->ctlr;
428 loff_t *pos = v;
9cef0d2f 429 drive_info_struct *drv = h->drv[*pos];
89b6e743
MM		 430
431 if (*pos > h->highest_lun)
432 return 0;
433
531c2dc7
SC		 434 if (drv == NULL) /* it's possible for h->drv[] to have holes. */
435 return 0;
436
89b6e743
MM		 437 if (drv->heads == 0)
438 return 0;
439
440 vol_sz = drv->nr_blocks;
441 vol_sz_frac = sector_div(vol_sz, ENG_GIG_FACTOR);
442 vol_sz_frac *= 100;
443 sector_div(vol_sz_frac, ENG_GIG_FACTOR);
444
fa52bec9 445 if (drv->raid_level < 0 || drv->raid_level > RAID_UNKNOWN)
89b6e743
MM		 446 drv->raid_level = RAID_UNKNOWN;
447 seq_printf(seq, "cciss/c%dd%d:"
448 "\t%4u.%02uGB\tRAID %s\n",
449 ctlr, (int) *pos, (int)vol_sz, (int)vol_sz_frac,
450 raid_label[drv->raid_level]);
451 return 0;
452}
453
454static void *cciss_seq_next(struct seq_file *seq, void *v, loff_t *pos)
455{
456 ctlr_info_t *h = seq->private;
457
458 if (*pos > h->highest_lun)
459 return NULL;
460 *pos += 1;
461
462 return pos;
463}
464
465static void cciss_seq_stop(struct seq_file *seq, void *v)
466{
467 ctlr_info_t *h = seq->private;
468
469 /* Only reset h->busy_configuring if we succeeded in setting
470 * it during cciss_seq_start. */
471 if (v == ERR_PTR(-EBUSY))
472 return;
7c832835 473
1da177e4 474 h->busy_configuring = 0;
1da177e4
LT		 475}
476
88e9d34c 477static const struct seq_operations cciss_seq_ops = {
89b6e743
MM		 478 .start = cciss_seq_start,
479 .show = cciss_seq_show,
480 .next = cciss_seq_next,
481 .stop = cciss_seq_stop,
482};
483
484static int cciss_seq_open(struct inode *inode, struct file *file)
485{
486 int ret = seq_open(file, &cciss_seq_ops);
487 struct seq_file *seq = file->private_data;
488
489 if (!ret)
490 seq->private = PDE(inode)->data;
491
492 return ret;
493}
494
495static ssize_t
496cciss_proc_write(struct file *file, const char __user *buf,
497 size_t length, loff_t *ppos)
1da177e4 498{
89b6e743
MM		 499 int err;
500 char *buffer;
501
502#ifndef CONFIG_CISS_SCSI_TAPE
503 return -EINVAL;
1da177e4
LT		 504#endif
505
89b6e743 506 if (!buf || length > PAGE_SIZE - 1)
7c832835 507 return -EINVAL;
89b6e743
MM		 508
509 buffer = (char *)__get_free_page(GFP_KERNEL);
510 if (!buffer)
511 return -ENOMEM;
512
513 err = -EFAULT;
514 if (copy_from_user(buffer, buf, length))
515 goto out;
516 buffer[length] = '\0';
517
518#ifdef CONFIG_CISS_SCSI_TAPE
519 if (strncmp(ENGAGE_SCSI, buffer, sizeof ENGAGE_SCSI - 1) == 0) {
520 struct seq_file *seq = file->private_data;
521 ctlr_info_t *h = seq->private;
89b6e743 522
f70dba83 523 err = cciss_engage_scsi(h);
8721c81f 524 if (err == 0)
89b6e743
MM		 525 err = length;
526 } else
527#endif /* CONFIG_CISS_SCSI_TAPE */
528 err = -EINVAL;
7c832835
BH		 529 /* might be nice to have "disengage" too, but it's not
530 safely possible. (only 1 module use count, lock issues.) */
89b6e743
MM		 531
532out:
533 free_page((unsigned long)buffer);
534 return err;
1da177e4
LT		 535}
536
828c0950 537static const struct file_operations cciss_proc_fops = {
89b6e743
MM		 538 .owner = THIS_MODULE,
539 .open = cciss_seq_open,
540 .read = seq_read,
541 .llseek = seq_lseek,
542 .release = seq_release,
543 .write = cciss_proc_write,
544};
545
f70dba83 546static void __devinit cciss_procinit(ctlr_info_t *h)
1da177e4
LT		 547{
548 struct proc_dir_entry *pde;
549
89b6e743 550 if (proc_cciss == NULL)
928b4d8c 551 proc_cciss = proc_mkdir("driver/cciss", NULL);
89b6e743
MM		 552 if (!proc_cciss)
553 return;
f70dba83 554 pde = proc_create_data(h->devname, S_IWUSR | S_IRUSR | S_IRGRP |
89b6e743 555 S_IROTH, proc_cciss,
f70dba83 556 &cciss_proc_fops, h);
1da177e4 557}
7c832835 558#endif /* CONFIG_PROC_FS */
1da177e4 559
7fe06326
AP		 560#define MAX_PRODUCT_NAME_LEN 19
561
562#define to_hba(n) container_of(n, struct ctlr_info, dev)
563#define to_drv(n) container_of(n, drive_info_struct, dev)
564
ec52d5f1 565/* List of controllers which cannot be hard reset on kexec with reset_devices */
957c2ec5
SC		 566static u32 unresettable_controller[] = {
567 0x324a103C, /* Smart Array P712m */
568 0x324b103C, /* SmartArray P711m */
569 0x3223103C, /* Smart Array P800 */
570 0x3234103C, /* Smart Array P400 */
571 0x3235103C, /* Smart Array P400i */
572 0x3211103C, /* Smart Array E200i */
573 0x3212103C, /* Smart Array E200 */
574 0x3213103C, /* Smart Array E200i */
575 0x3214103C, /* Smart Array E200i */
576 0x3215103C, /* Smart Array E200i */
577 0x3237103C, /* Smart Array E500 */
578 0x323D103C, /* Smart Array P700m */
579 0x409C0E11, /* Smart Array 6400 */
580 0x409D0E11, /* Smart Array 6400 EM */
581};
582
ec52d5f1
SC		 583/* List of controllers which cannot even be soft reset */
584static u32 soft_unresettable_controller[] = {
585 0x409C0E11, /* Smart Array 6400 */
586 0x409D0E11, /* Smart Array 6400 EM */
587};
588
589static int ctlr_is_hard_resettable(u32 board_id)
957c2ec5
SC		 590{
591 int i;
592
593 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
ec52d5f1 594 if (unresettable_controller[i] == board_id)
957c2ec5
SC		 595 return 0;
596 return 1;
597}
598
ec52d5f1
SC		 599static int ctlr_is_soft_resettable(u32 board_id)
600{
601 int i;
602
603 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
604 if (soft_unresettable_controller[i] == board_id)
605 return 0;
606 return 1;
607}
608
609static int ctlr_is_resettable(u32 board_id)
610{
611 return ctlr_is_hard_resettable(board_id) ||
612 ctlr_is_soft_resettable(board_id);
613}
614
957c2ec5
SC		 615static ssize_t host_show_resettable(struct device *dev,
616 struct device_attribute *attr,
617 char *buf)
618{
619 struct ctlr_info *h = to_hba(dev);
620
ec52d5f1 621 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
957c2ec5
SC		 622}
623static DEVICE_ATTR(resettable, S_IRUGO, host_show_resettable, NULL);
624
d6f4965d
AP		 625static ssize_t host_store_rescan(struct device *dev,
626 struct device_attribute *attr,
627 const char *buf, size_t count)
628{
629 struct ctlr_info *h = to_hba(dev);
630
631 add_to_scan_list(h);
632 wake_up_process(cciss_scan_thread);
633 wait_for_completion_interruptible(&h->scan_wait);
634
635 return count;
636}
8ba95c69 637static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
7fe06326
AP		 638
639static ssize_t dev_show_unique_id(struct device *dev,
640 struct device_attribute *attr,
641 char *buf)
642{
643 drive_info_struct *drv = to_drv(dev);
644 struct ctlr_info *h = to_hba(drv->dev.parent);
645 __u8 sn[16];
646 unsigned long flags;
647 int ret = 0;
648
f70dba83 649 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 650 if (h->busy_configuring)
651 ret = -EBUSY;
652 else
653 memcpy(sn, drv->serial_no, sizeof(sn));
f70dba83 654 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 655
656 if (ret)
657 return ret;
658 else
659 return snprintf(buf, 16 * 2 + 2,
660 "%02X%02X%02X%02X%02X%02X%02X%02X"
661 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
662 sn[0], sn[1], sn[2], sn[3],
663 sn[4], sn[5], sn[6], sn[7],
664 sn[8], sn[9], sn[10], sn[11],
665 sn[12], sn[13], sn[14], sn[15]);
666}
8ba95c69 667static DEVICE_ATTR(unique_id, S_IRUGO, dev_show_unique_id, NULL);
7fe06326
AP		 668
669static ssize_t dev_show_vendor(struct device *dev,
670 struct device_attribute *attr,
671 char *buf)
672{
673 drive_info_struct *drv = to_drv(dev);
674 struct ctlr_info *h = to_hba(drv->dev.parent);
675 char vendor[VENDOR_LEN + 1];
676 unsigned long flags;
677 int ret = 0;
678
f70dba83 679 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 680 if (h->busy_configuring)
681 ret = -EBUSY;
682 else
683 memcpy(vendor, drv->vendor, VENDOR_LEN + 1);
f70dba83 684 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 685
686 if (ret)
687 return ret;
688 else
689 return snprintf(buf, sizeof(vendor) + 1, "%s\n", drv->vendor);
690}
8ba95c69 691static DEVICE_ATTR(vendor, S_IRUGO, dev_show_vendor, NULL);
7fe06326
AP		 692
693static ssize_t dev_show_model(struct device *dev,
694 struct device_attribute *attr,
695 char *buf)
696{
697 drive_info_struct *drv = to_drv(dev);
698 struct ctlr_info *h = to_hba(drv->dev.parent);
699 char model[MODEL_LEN + 1];
700 unsigned long flags;
701 int ret = 0;
702
f70dba83 703 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 704 if (h->busy_configuring)
705 ret = -EBUSY;
706 else
707 memcpy(model, drv->model, MODEL_LEN + 1);
f70dba83 708 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 709
710 if (ret)
711 return ret;
712 else
713 return snprintf(buf, sizeof(model) + 1, "%s\n", drv->model);
714}
8ba95c69 715static DEVICE_ATTR(model, S_IRUGO, dev_show_model, NULL);
7fe06326
AP		 716
717static ssize_t dev_show_rev(struct device *dev,
718 struct device_attribute *attr,
719 char *buf)
720{
721 drive_info_struct *drv = to_drv(dev);
722 struct ctlr_info *h = to_hba(drv->dev.parent);
723 char rev[REV_LEN + 1];
724 unsigned long flags;
725 int ret = 0;
726
f70dba83 727 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 728 if (h->busy_configuring)
729 ret = -EBUSY;
730 else
731 memcpy(rev, drv->rev, REV_LEN + 1);
f70dba83 732 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 733
734 if (ret)
735 return ret;
736 else
737 return snprintf(buf, sizeof(rev) + 1, "%s\n", drv->rev);
738}
8ba95c69 739static DEVICE_ATTR(rev, S_IRUGO, dev_show_rev, NULL);
7fe06326 740
ce84a8ae
SC		 741static ssize_t cciss_show_lunid(struct device *dev,
742 struct device_attribute *attr, char *buf)
743{
9cef0d2f
SC		 744 drive_info_struct *drv = to_drv(dev);
745 struct ctlr_info *h = to_hba(drv->dev.parent);
ce84a8ae
SC		 746 unsigned long flags;
747 unsigned char lunid[8];
748
f70dba83 749 spin_lock_irqsave(&h->lock, flags);
ce84a8ae 750 if (h->busy_configuring) {
f70dba83 751 spin_unlock_irqrestore(&h->lock, flags);
ce84a8ae
SC		 752 return -EBUSY;
753 }
754 if (!drv->heads) {
f70dba83 755 spin_unlock_irqrestore(&h->lock, flags);
ce84a8ae
SC		 756 return -ENOTTY;
757 }
758 memcpy(lunid, drv->LunID, sizeof(lunid));
f70dba83 759 spin_unlock_irqrestore(&h->lock, flags);
ce84a8ae
SC		 760 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
761 lunid[0], lunid[1], lunid[2], lunid[3],
762 lunid[4], lunid[5], lunid[6], lunid[7]);
763}
8ba95c69 764static DEVICE_ATTR(lunid, S_IRUGO, cciss_show_lunid, NULL);
ce84a8ae 765
3ff1111d
SC		 766static ssize_t cciss_show_raid_level(struct device *dev,
767 struct device_attribute *attr, char *buf)
768{
9cef0d2f
SC		 769 drive_info_struct *drv = to_drv(dev);
770 struct ctlr_info *h = to_hba(drv->dev.parent);
3ff1111d
SC		 771 int raid;
772 unsigned long flags;
773
f70dba83 774 spin_lock_irqsave(&h->lock, flags);
3ff1111d 775 if (h->busy_configuring) {
f70dba83 776 spin_unlock_irqrestore(&h->lock, flags);
3ff1111d
SC		 777 return -EBUSY;
778 }
779 raid = drv->raid_level;
f70dba83 780 spin_unlock_irqrestore(&h->lock, flags);
3ff1111d
SC		 781 if (raid < 0 || raid > RAID_UNKNOWN)
782 raid = RAID_UNKNOWN;
783
784 return snprintf(buf, strlen(raid_label[raid]) + 7, "RAID %s\n",
785 raid_label[raid]);
786}
8ba95c69 787static DEVICE_ATTR(raid_level, S_IRUGO, cciss_show_raid_level, NULL);
3ff1111d 788
e272afec
SC		 789static ssize_t cciss_show_usage_count(struct device *dev,
790 struct device_attribute *attr, char *buf)
791{
9cef0d2f
SC		 792 drive_info_struct *drv = to_drv(dev);
793 struct ctlr_info *h = to_hba(drv->dev.parent);
e272afec
SC		 794 unsigned long flags;
795 int count;
796
f70dba83 797 spin_lock_irqsave(&h->lock, flags);
e272afec 798 if (h->busy_configuring) {
f70dba83 799 spin_unlock_irqrestore(&h->lock, flags);
e272afec
SC		 800 return -EBUSY;
801 }
802 count = drv->usage_count;
f70dba83 803 spin_unlock_irqrestore(&h->lock, flags);
e272afec
SC		 804 return snprintf(buf, 20, "%d\n", count);
805}
8ba95c69 806static DEVICE_ATTR(usage_count, S_IRUGO, cciss_show_usage_count, NULL);
e272afec 807
d6f4965d
AP		 808static struct attribute *cciss_host_attrs[] = {
809 &dev_attr_rescan.attr,
957c2ec5 810 &dev_attr_resettable.attr,
d6f4965d
AP		 811 NULL
812};
813
814static struct attribute_group cciss_host_attr_group = {
815 .attrs = cciss_host_attrs,
816};
817
9f792d9f 818static const struct attribute_group *cciss_host_attr_groups[] = {
d6f4965d
AP		 819 &cciss_host_attr_group,
820 NULL
821};
822
823static struct device_type cciss_host_type = {
824 .name = "cciss_host",
825 .groups = cciss_host_attr_groups,
617e1344 826 .release = cciss_hba_release,
d6f4965d
AP		 827};
828
7fe06326
AP		 829static struct attribute *cciss_dev_attrs[] = {
830 &dev_attr_unique_id.attr,
831 &dev_attr_model.attr,
832 &dev_attr_vendor.attr,
833 &dev_attr_rev.attr,
ce84a8ae 834 &dev_attr_lunid.attr,
3ff1111d 835 &dev_attr_raid_level.attr,
e272afec 836 &dev_attr_usage_count.attr,
7fe06326
AP		 837 NULL
838};
839
840static struct attribute_group cciss_dev_attr_group = {
841 .attrs = cciss_dev_attrs,
842};
843
a4dbd674 844static const struct attribute_group *cciss_dev_attr_groups[] = {
7fe06326
AP		 845 &cciss_dev_attr_group,
846 NULL
847};
848
849static struct device_type cciss_dev_type = {
850 .name = "cciss_device",
851 .groups = cciss_dev_attr_groups,
617e1344 852 .release = cciss_device_release,
7fe06326
AP		 853};
854
855static struct bus_type cciss_bus_type = {
856 .name = "cciss",
857};
858
617e1344
SC		 859/*
860 * cciss_hba_release is called when the reference count
861 * of h->dev goes to zero.
862 */
863static void cciss_hba_release(struct device *dev)
864{
865 /*
866 * nothing to do, but need this to avoid a warning
867 * about not having a release handler from lib/kref.c.
868 */
869}
7fe06326
AP		 870
871/*
872 * Initialize sysfs entry for each controller. This sets up and registers
873 * the 'cciss#' directory for each individual controller under
874 * /sys/bus/pci/devices/<dev>/.
875 */
876static int cciss_create_hba_sysfs_entry(struct ctlr_info *h)
877{
878 device_initialize(&h->dev);
879 h->dev.type = &cciss_host_type;
880 h->dev.bus = &cciss_bus_type;
881 dev_set_name(&h->dev, "%s", h->devname);
882 h->dev.parent = &h->pdev->dev;
883
884 return device_add(&h->dev);
885}
886
887/*
888 * Remove sysfs entries for an hba.
889 */
890static void cciss_destroy_hba_sysfs_entry(struct ctlr_info *h)
891{
892 device_del(&h->dev);
617e1344
SC		 893 put_device(&h->dev); /* final put. */
894}
895
896/* cciss_device_release is called when the reference count
9cef0d2f 897 * of h->drv[x]dev goes to zero.
617e1344
SC		 898 */
899static void cciss_device_release(struct device *dev)
900{
9cef0d2f
SC		 901 drive_info_struct *drv = to_drv(dev);
902 kfree(drv);
7fe06326
AP		 903}
904
905/*
906 * Initialize sysfs for each logical drive. This sets up and registers
907 * the 'c#d#' directory for each individual logical drive under
908 * /sys/bus/pci/devices/<dev/ccis#/. We also create a link from
909 * /sys/block/cciss!c#d# to this entry.
910 */
617e1344 911static long cciss_create_ld_sysfs_entry(struct ctlr_info *h,
7fe06326
AP		 912 int drv_index)
913{
617e1344
SC		 914 struct device *dev;
915
9cef0d2f 916 if (h->drv[drv_index]->device_initialized)
8ce51966
SC		 917 return 0;
918
9cef0d2f 919 dev = &h->drv[drv_index]->dev;
617e1344
SC		 920 device_initialize(dev);
921 dev->type = &cciss_dev_type;
922 dev->bus = &cciss_bus_type;
923 dev_set_name(dev, "c%dd%d", h->ctlr, drv_index);
924 dev->parent = &h->dev;
9cef0d2f 925 h->drv[drv_index]->device_initialized = 1;
617e1344 926 return device_add(dev);
7fe06326
AP		 927}
928
929/*
930 * Remove sysfs entries for a logical drive.
931 */
8ce51966
SC		 932static void cciss_destroy_ld_sysfs_entry(struct ctlr_info *h, int drv_index,
933 int ctlr_exiting)
7fe06326 934{
9cef0d2f 935 struct device *dev = &h->drv[drv_index]->dev;
8ce51966
SC		 936
937 /* special case for c*d0, we only destroy it on controller exit */
938 if (drv_index == 0 && !ctlr_exiting)
939 return;
940
617e1344
SC		 941 device_del(dev);
942 put_device(dev); /* the "final" put. */
9cef0d2f 943 h->drv[drv_index] = NULL;
7fe06326
AP		 944}
945
7c832835
BH		 946/*
947 * For operations that cannot sleep, a command block is allocated at init,
1da177e4 948 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6b4d96b8 949 * which ones are free or in use.
7c832835 950 */
6b4d96b8 951static CommandList_struct *cmd_alloc(ctlr_info_t *h)
1da177e4
LT		 952{
953 CommandList_struct *c;
7c832835 954 int i;
1da177e4
LT		 955 u64bit temp64;
956 dma_addr_t cmd_dma_handle, err_dma_handle;
957
6b4d96b8
SC		 958 do {
959 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
960 if (i == h->nr_cmds)
7c832835 961 return NULL;
6b4d96b8
SC		 962 } while (test_and_set_bit(i & (BITS_PER_LONG - 1),
963 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
6b4d96b8
SC		 964 c = h->cmd_pool + i;
965 memset(c, 0, sizeof(CommandList_struct));
966 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(CommandList_struct);
967 c->err_info = h->errinfo_pool + i;
968 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
969 err_dma_handle = h->errinfo_pool_dhandle
970 + i * sizeof(ErrorInfo_struct);
971 h->nr_allocs++;
1da177e4 972
6b4d96b8 973 c->cmdindex = i;
33079b21 974
e6e1ee93 975 INIT_LIST_HEAD(&c->list);
6b4d96b8
SC		 976 c->busaddr = (__u32) cmd_dma_handle;
977 temp64.val = (__u64) err_dma_handle;
978 c->ErrDesc.Addr.lower = temp64.val32.lower;
979 c->ErrDesc.Addr.upper = temp64.val32.upper;
980 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
7c832835 981
6b4d96b8
SC		 982 c->ctlr = h->ctlr;
983 return c;
984}
33079b21 985
6b4d96b8
SC		 986/* allocate a command using pci_alloc_consistent, used for ioctls,
987 * etc., not for the main i/o path.
988 */
989static CommandList_struct *cmd_special_alloc(ctlr_info_t *h)
990{
991 CommandList_struct *c;
992 u64bit temp64;
993 dma_addr_t cmd_dma_handle, err_dma_handle;
994
995 c = (CommandList_struct *) pci_alloc_consistent(h->pdev,
996 sizeof(CommandList_struct), &cmd_dma_handle);
997 if (c == NULL)
998 return NULL;
999 memset(c, 0, sizeof(CommandList_struct));
1000
1001 c->cmdindex = -1;
1002
1003 c->err_info = (ErrorInfo_struct *)
1004 pci_alloc_consistent(h->pdev, sizeof(ErrorInfo_struct),
1005 &err_dma_handle);
1006
1007 if (c->err_info == NULL) {
1008 pci_free_consistent(h->pdev,
1009 sizeof(CommandList_struct), c, cmd_dma_handle);
1010 return NULL;
7c832835 1011 }
6b4d96b8 1012 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
1da177e4 1013
e6e1ee93 1014 INIT_LIST_HEAD(&c->list);
1da177e4 1015 c->busaddr = (__u32) cmd_dma_handle;
7c832835 1016 temp64.val = (__u64) err_dma_handle;
1da177e4
LT		 1017 c->ErrDesc.Addr.lower = temp64.val32.lower;
1018 c->ErrDesc.Addr.upper = temp64.val32.upper;
1019 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
1da177e4 1020
7c832835
BH		 1021 c->ctlr = h->ctlr;
1022 return c;
1da177e4
LT		 1023}
1024
6b4d96b8 1025static void cmd_free(ctlr_info_t *h, CommandList_struct *c)
1da177e4
LT		 1026{
1027 int i;
6b4d96b8
SC		 1028
1029 i = c - h->cmd_pool;
1030 clear_bit(i & (BITS_PER_LONG - 1),
1031 h->cmd_pool_bits + (i / BITS_PER_LONG));
1032 h->nr_frees++;
1033}
1034
1035static void cmd_special_free(ctlr_info_t *h, CommandList_struct *c)
1036{
1da177e4
LT		 1037 u64bit temp64;
1038
6b4d96b8
SC		 1039 temp64.val32.lower = c->ErrDesc.Addr.lower;
1040 temp64.val32.upper = c->ErrDesc.Addr.upper;
1041 pci_free_consistent(h->pdev, sizeof(ErrorInfo_struct),
1042 c->err_info, (dma_addr_t) temp64.val);
16011131
SC		 1043 pci_free_consistent(h->pdev, sizeof(CommandList_struct), c,
1044 (dma_addr_t) cciss_tag_discard_error_bits(h, (u32) c->busaddr));
1da177e4
LT		 1045}
1046
1047static inline ctlr_info_t *get_host(struct gendisk *disk)
1048{
7c832835 1049 return disk->queue->queuedata;
1da177e4
LT		 1050}
1051
1052static inline drive_info_struct *get_drv(struct gendisk *disk)
1053{
1054 return disk->private_data;
1055}
1056
1057/*
1058 * Open. Make sure the device is really there.
1059 */
ef7822c2 1060static int cciss_open(struct block_device *bdev, fmode_t mode)
1da177e4 1061{
f70dba83 1062 ctlr_info_t *h = get_host(bdev->bd_disk);
ef7822c2 1063 drive_info_struct *drv = get_drv(bdev->bd_disk);
1da177e4 1064
b2a4a43d 1065 dev_dbg(&h->pdev->dev, "cciss_open %s\n", bdev->bd_disk->disk_name);
2e043986 1066 if (drv->busy_configuring)
ddd47442 1067 return -EBUSY;
1da177e4
LT		 1068 /*
1069 * Root is allowed to open raw volume zero even if it's not configured
1070 * so array config can still work. Root is also allowed to open any
1071 * volume that has a LUN ID, so it can issue IOCTL to reread the
1072 * disk information. I don't think I really like this
1073 * but I'm already using way to many device nodes to claim another one
1074 * for "raw controller".
1075 */
7a06f789 1076 if (drv->heads == 0) {
ef7822c2 1077 if (MINOR(bdev->bd_dev) != 0) { /* not node 0? */
1da177e4 1078 /* if not node 0 make sure it is a partition = 0 */
ef7822c2 1079 if (MINOR(bdev->bd_dev) & 0x0f) {
7c832835 1080 return -ENXIO;
1da177e4 1081 /* if it is, make sure we have a LUN ID */
39ccf9a6
SC		 1082 } else if (memcmp(drv->LunID, CTLR_LUNID,
1083 sizeof(drv->LunID))) {
1da177e4
LT		 1084 return -ENXIO;
1085 }
1086 }
1087 if (!capable(CAP_SYS_ADMIN))
1088 return -EPERM;
1089 }
1090 drv->usage_count++;
f70dba83 1091 h->usage_count++;
1da177e4
LT		 1092 return 0;
1093}
7c832835 1094
6e9624b8
AB		 1095static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode)
1096{
1097 int ret;
1098
2a48fc0a 1099 mutex_lock(&cciss_mutex);
6e9624b8 1100 ret = cciss_open(bdev, mode);
2a48fc0a 1101 mutex_unlock(&cciss_mutex);
6e9624b8
AB		 1102
1103 return ret;
1104}
1105
1da177e4
LT		 1106/*
1107 * Close. Sync first.
1108 */
ef7822c2 1109static int cciss_release(struct gendisk *disk, fmode_t mode)
1da177e4 1110{
f70dba83 1111 ctlr_info_t *h;
6e9624b8 1112 drive_info_struct *drv;
1da177e4 1113
2a48fc0a 1114 mutex_lock(&cciss_mutex);
f70dba83 1115 h = get_host(disk);
6e9624b8 1116 drv = get_drv(disk);
b2a4a43d 1117 dev_dbg(&h->pdev->dev, "cciss_release %s\n", disk->disk_name);
1da177e4 1118 drv->usage_count--;
f70dba83 1119 h->usage_count--;
2a48fc0a 1120 mutex_unlock(&cciss_mutex);
1da177e4
LT		 1121 return 0;
1122}
1123
ef7822c2
AV		 1124static int do_ioctl(struct block_device *bdev, fmode_t mode,
1125 unsigned cmd, unsigned long arg)
1da177e4
LT		 1126{
1127 int ret;
2a48fc0a 1128 mutex_lock(&cciss_mutex);
ef7822c2 1129 ret = cciss_ioctl(bdev, mode, cmd, arg);
2a48fc0a 1130 mutex_unlock(&cciss_mutex);
1da177e4
LT		 1131 return ret;
1132}
1133
8a6cfeb6
AB		 1134#ifdef CONFIG_COMPAT
1135
ef7822c2
AV		 1136static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1137 unsigned cmd, unsigned long arg);
1138static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1139 unsigned cmd, unsigned long arg);
1da177e4 1140
ef7822c2
AV		 1141static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
1142 unsigned cmd, unsigned long arg)
1da177e4
LT		 1143{
1144 switch (cmd) {
1145 case CCISS_GETPCIINFO:
1146 case CCISS_GETINTINFO:
1147 case CCISS_SETINTINFO:
1148 case CCISS_GETNODENAME:
1149 case CCISS_SETNODENAME:
1150 case CCISS_GETHEARTBEAT:
1151 case CCISS_GETBUSTYPES:
1152 case CCISS_GETFIRMVER:
1153 case CCISS_GETDRIVVER:
1154 case CCISS_REVALIDVOLS:
1155 case CCISS_DEREGDISK:
1156 case CCISS_REGNEWDISK:
1157 case CCISS_REGNEWD:
1158 case CCISS_RESCANDISK:
1159 case CCISS_GETLUNINFO:
ef7822c2 1160 return do_ioctl(bdev, mode, cmd, arg);
1da177e4
LT		 1161
1162 case CCISS_PASSTHRU32:
ef7822c2 1163 return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
1da177e4 1164 case CCISS_BIG_PASSTHRU32:
ef7822c2 1165 return cciss_ioctl32_big_passthru(bdev, mode, cmd, arg);
1da177e4
LT		 1166
1167 default:
1168 return -ENOIOCTLCMD;
1169 }
1170}
1171
ef7822c2
AV		 1172static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1173 unsigned cmd, unsigned long arg)
1da177e4
LT		 1174{
1175 IOCTL32_Command_struct __user *arg32 =
7c832835 1176 (IOCTL32_Command_struct __user *) arg;
1da177e4
LT		 1177 IOCTL_Command_struct arg64;
1178 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
1179 int err;
1180 u32 cp;
1181
1182 err = 0;
7c832835
BH		 1183 err |=
1184 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1185 sizeof(arg64.LUN_info));
1186 err |=
1187 copy_from_user(&arg64.Request, &arg32->Request,
1188 sizeof(arg64.Request));
1189 err |=
1190 copy_from_user(&arg64.error_info, &arg32->error_info,
1191 sizeof(arg64.error_info));
1da177e4
LT		 1192 err |= get_user(arg64.buf_size, &arg32->buf_size);
1193 err |= get_user(cp, &arg32->buf);
1194 arg64.buf = compat_ptr(cp);
1195 err |= copy_to_user(p, &arg64, sizeof(arg64));
1196
1197 if (err)
1198 return -EFAULT;
1199
ef7822c2 1200 err = do_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
1da177e4
LT		 1201 if (err)
1202 return err;
7c832835
BH		 1203 err |=
1204 copy_in_user(&arg32->error_info, &p->error_info,
1205 sizeof(arg32->error_info));
1da177e4
LT		 1206 if (err)
1207 return -EFAULT;
1208 return err;
1209}
1210
ef7822c2
AV		 1211static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1212 unsigned cmd, unsigned long arg)
1da177e4
LT		 1213{
1214 BIG_IOCTL32_Command_struct __user *arg32 =
7c832835 1215 (BIG_IOCTL32_Command_struct __user *) arg;
1da177e4 1216 BIG_IOCTL_Command_struct arg64;
7c832835
BH		 1217 BIG_IOCTL_Command_struct __user *p =
1218 compat_alloc_user_space(sizeof(arg64));
1da177e4
LT		 1219 int err;
1220 u32 cp;
1221
7ab5118d 1222 memset(&arg64, 0, sizeof(arg64));
1da177e4 1223 err = 0;
7c832835
BH		 1224 err |=
1225 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1226 sizeof(arg64.LUN_info));
1227 err |=
1228 copy_from_user(&arg64.Request, &arg32->Request,
1229 sizeof(arg64.Request));
1230 err |=
1231 copy_from_user(&arg64.error_info, &arg32->error_info,
1232 sizeof(arg64.error_info));
1da177e4
LT		 1233 err |= get_user(arg64.buf_size, &arg32->buf_size);
1234 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
1235 err |= get_user(cp, &arg32->buf);
1236 arg64.buf = compat_ptr(cp);
1237 err |= copy_to_user(p, &arg64, sizeof(arg64));
1238
1239 if (err)
7c832835 1240 return -EFAULT;
1da177e4 1241
ef7822c2 1242 err = do_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
1da177e4
LT		 1243 if (err)
1244 return err;
7c832835
BH		 1245 err |=
1246 copy_in_user(&arg32->error_info, &p->error_info,
1247 sizeof(arg32->error_info));
1da177e4
LT		 1248 if (err)
1249 return -EFAULT;
1250 return err;
1251}
1252#endif
a885c8c4
CH		 1253
1254static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1255{
1256 drive_info_struct *drv = get_drv(bdev->bd_disk);
1257
1258 if (!drv->cylinders)
1259 return -ENXIO;
1260
1261 geo->heads = drv->heads;
1262 geo->sectors = drv->sectors;
1263 geo->cylinders = drv->cylinders;
1264 return 0;
1265}
1266
f70dba83 1267static void check_ioctl_unit_attention(ctlr_info_t *h, CommandList_struct *c)
0a9279cc
MM		 1268{
1269 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
1270 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
f70dba83 1271 (void)check_for_unit_attention(h, c);
0a9279cc 1272}
0a25a5ae
SC		 1273
1274static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
1da177e4 1275{
0a25a5ae 1276 cciss_pci_info_struct pciinfo;
1da177e4 1277
0a25a5ae
SC		 1278 if (!argp)
1279 return -EINVAL;
1280 pciinfo.domain = pci_domain_nr(h->pdev->bus);
1281 pciinfo.bus = h->pdev->bus->number;
1282 pciinfo.dev_fn = h->pdev->devfn;
1283 pciinfo.board_id = h->board_id;
1284 if (copy_to_user(argp, &pciinfo, sizeof(cciss_pci_info_struct)))
1285 return -EFAULT;
1286 return 0;
1287}
1da177e4 1288
576e661c
SC		 1289static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
1290{
1291 cciss_coalint_struct intinfo;
1da177e4 1292
576e661c
SC		 1293 if (!argp)
1294 return -EINVAL;
1295 intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
1296 intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
1297 if (copy_to_user
1298 (argp, &intinfo, sizeof(cciss_coalint_struct)))
1299 return -EFAULT;
1300 return 0;
1301}
1da177e4 1302
4c800eed
SC		 1303static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
1304{
1305 cciss_coalint_struct intinfo;
1306 unsigned long flags;
1307 int i;
1da177e4 1308
4c800eed
SC		 1309 if (!argp)
1310 return -EINVAL;
1311 if (!capable(CAP_SYS_ADMIN))
1312 return -EPERM;
1313 if (copy_from_user(&intinfo, argp, sizeof(intinfo)))
1314 return -EFAULT;
1315 if ((intinfo.delay == 0) && (intinfo.count == 0))
1316 return -EINVAL;
1317 spin_lock_irqsave(&h->lock, flags);
1318 /* Update the field, and then ring the doorbell */
1319 writel(intinfo.delay, &(h->cfgtable->HostWrite.CoalIntDelay));
1320 writel(intinfo.count, &(h->cfgtable->HostWrite.CoalIntCount));
1321 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1322
1323 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1324 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1325 break;
1326 udelay(1000); /* delay and try again */
1327 }
1328 spin_unlock_irqrestore(&h->lock, flags);
1329 if (i >= MAX_IOCTL_CONFIG_WAIT)
1330 return -EAGAIN;
1331 return 0;
1332}
1da177e4 1333
25216109
SC		 1334static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
1335{
1336 NodeName_type NodeName;
1337 int i;
1da177e4 1338
25216109
SC		 1339 if (!argp)
1340 return -EINVAL;
1341 for (i = 0; i < 16; i++)
1342 NodeName[i] = readb(&h->cfgtable->ServerName[i]);
1343 if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
1344 return -EFAULT;
1345 return 0;
1346}
7c832835 1347
4f43f32c
SC		 1348static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
1349{
1350 NodeName_type NodeName;
1351 unsigned long flags;
1352 int i;
7c832835 1353
4f43f32c
SC		 1354 if (!argp)
1355 return -EINVAL;
1356 if (!capable(CAP_SYS_ADMIN))
1357 return -EPERM;
1358 if (copy_from_user(NodeName, argp, sizeof(NodeName_type)))
1359 return -EFAULT;
1360 spin_lock_irqsave(&h->lock, flags);
1361 /* Update the field, and then ring the doorbell */
1362 for (i = 0; i < 16; i++)
1363 writeb(NodeName[i], &h->cfgtable->ServerName[i]);
1364 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1365 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1366 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1367 break;
1368 udelay(1000); /* delay and try again */
1369 }
1370 spin_unlock_irqrestore(&h->lock, flags);
1371 if (i >= MAX_IOCTL_CONFIG_WAIT)
1372 return -EAGAIN;
1373 return 0;
1374}
7c832835 1375
93c74931
SC		 1376static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
1377{
1378 Heartbeat_type heartbeat;
7c832835 1379
93c74931
SC		 1380 if (!argp)
1381 return -EINVAL;
1382 heartbeat = readl(&h->cfgtable->HeartBeat);
1383 if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
1384 return -EFAULT;
1385 return 0;
1386}
0a9279cc 1387
d18dfad4
SC		 1388static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
1389{
1390 BusTypes_type BusTypes;
7c832835 1391
d18dfad4
SC		 1392 if (!argp)
1393 return -EINVAL;
1394 BusTypes = readl(&h->cfgtable->BusTypes);
1395 if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
1396 return -EFAULT;
1397 return 0;
1398}
1399
8a4f7fbf
SC		 1400static int cciss_getfirmver(ctlr_info_t *h, void __user *argp)
1401{
1402 FirmwareVer_type firmware;
1403
1404 if (!argp)
1405 return -EINVAL;
1406 memcpy(firmware, h->firm_ver, 4);
1407
1408 if (copy_to_user
1409 (argp, firmware, sizeof(FirmwareVer_type)))
1410 return -EFAULT;
1411 return 0;
1412}
1413
c525919d
SC		 1414static int cciss_getdrivver(ctlr_info_t *h, void __user *argp)
1415{
1416 DriverVer_type DriverVer = DRIVER_VERSION;
1417
1418 if (!argp)
1419 return -EINVAL;
1420 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
1421 return -EFAULT;
1422 return 0;
1423}
1424
0894b32c
SC		 1425static int cciss_getluninfo(ctlr_info_t *h,
1426 struct gendisk *disk, void __user *argp)
1427{
1428 LogvolInfo_struct luninfo;
1429 drive_info_struct *drv = get_drv(disk);
1430
1431 if (!argp)
1432 return -EINVAL;
1433 memcpy(&luninfo.LunID, drv->LunID, sizeof(luninfo.LunID));
1434 luninfo.num_opens = drv->usage_count;
1435 luninfo.num_parts = 0;
1436 if (copy_to_user(argp, &luninfo, sizeof(LogvolInfo_struct)))
1437 return -EFAULT;
1438 return 0;
1439}
1440
f32f125b
SC		 1441static int cciss_passthru(ctlr_info_t *h, void __user *argp)
1442{
1443 IOCTL_Command_struct iocommand;
1444 CommandList_struct *c;
1445 char *buff = NULL;
1446 u64bit temp64;
1447 DECLARE_COMPLETION_ONSTACK(wait);
1448
1449 if (!argp)
1450 return -EINVAL;
1451
1452 if (!capable(CAP_SYS_RAWIO))
1453 return -EPERM;
1454
1455 if (copy_from_user
1456 (&iocommand, argp, sizeof(IOCTL_Command_struct)))
1457 return -EFAULT;
1458 if ((iocommand.buf_size < 1) &&
1459 (iocommand.Request.Type.Direction != XFER_NONE)) {
1460 return -EINVAL;
1461 }
1462 if (iocommand.buf_size > 0) {
1463 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
1464 if (buff == NULL)
1465 return -EFAULT;
1466 }
1467 if (iocommand.Request.Type.Direction == XFER_WRITE) {
1468 /* Copy the data into the buffer we created */
1469 if (copy_from_user(buff, iocommand.buf, iocommand.buf_size)) {
1470 kfree(buff);
1471 return -EFAULT;
1472 }
1473 } else {
1474 memset(buff, 0, iocommand.buf_size);
1475 }
1476 c = cmd_special_alloc(h);
1477 if (!c) {
1478 kfree(buff);
1479 return -ENOMEM;
1480 }
1481 /* Fill in the command type */
1482 c->cmd_type = CMD_IOCTL_PEND;
1483 /* Fill in Command Header */
1484 c->Header.ReplyQueue = 0; /* unused in simple mode */
1485 if (iocommand.buf_size > 0) { /* buffer to fill */
1486 c->Header.SGList = 1;
1487 c->Header.SGTotal = 1;
1488 } else { /* no buffers to fill */
1489 c->Header.SGList = 0;
1490 c->Header.SGTotal = 0;
1491 }
1492 c->Header.LUN = iocommand.LUN_info;
1493 /* use the kernel address the cmd block for tag */
1494 c->Header.Tag.lower = c->busaddr;
1495
1496 /* Fill in Request block */
1497 c->Request = iocommand.Request;
1498
1499 /* Fill in the scatter gather information */
1500 if (iocommand.buf_size > 0) {
1501 temp64.val = pci_map_single(h->pdev, buff,
1502 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
1503 c->SG[0].Addr.lower = temp64.val32.lower;
1504 c->SG[0].Addr.upper = temp64.val32.upper;
1505 c->SG[0].Len = iocommand.buf_size;
1506 c->SG[0].Ext = 0; /* we are not chaining */
1507 }
1508 c->waiting = &wait;
1509
1510 enqueue_cmd_and_start_io(h, c);
1511 wait_for_completion(&wait);
1512
1513 /* unlock the buffers from DMA */
1514 temp64.val32.lower = c->SG[0].Addr.lower;
1515 temp64.val32.upper = c->SG[0].Addr.upper;
1516 pci_unmap_single(h->pdev, (dma_addr_t) temp64.val, iocommand.buf_size,
1517 PCI_DMA_BIDIRECTIONAL);
1518 check_ioctl_unit_attention(h, c);
1519
1520 /* Copy the error information out */
1521 iocommand.error_info = *(c->err_info);
1522 if (copy_to_user(argp, &iocommand, sizeof(IOCTL_Command_struct))) {
1523 kfree(buff);
1524 cmd_special_free(h, c);
1525 return -EFAULT;
1526 }
1527
1528 if (iocommand.Request.Type.Direction == XFER_READ) {
1529 /* Copy the data out of the buffer we created */
1530 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
7c832835 1531 kfree(buff);
6b4d96b8 1532 cmd_special_free(h, c);
f32f125b 1533 return -EFAULT;
1da177e4 1534 }
f32f125b
SC		 1535 }
1536 kfree(buff);
1537 cmd_special_free(h, c);
1538 return 0;
1539}
1540
0c9f5ba7
SC		 1541static int cciss_bigpassthru(ctlr_info_t *h, void __user *argp)
1542{
1543 BIG_IOCTL_Command_struct *ioc;
1544 CommandList_struct *c;
1545 unsigned char **buff = NULL;
1546 int *buff_size = NULL;
1547 u64bit temp64;
1548 BYTE sg_used = 0;
1549 int status = 0;
1550 int i;
1551 DECLARE_COMPLETION_ONSTACK(wait);
1552 __u32 left;
1553 __u32 sz;
1554 BYTE __user *data_ptr;
1555
1556 if (!argp)
1557 return -EINVAL;
1558 if (!capable(CAP_SYS_RAWIO))
1559 return -EPERM;
fcab1c11 1560 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
0c9f5ba7
SC		 1561 if (!ioc) {
1562 status = -ENOMEM;
1563 goto cleanup1;
1564 }
1565 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
1566 status = -EFAULT;
1567 goto cleanup1;
1568 }
1569 if ((ioc->buf_size < 1) &&
1570 (ioc->Request.Type.Direction != XFER_NONE)) {
1571 status = -EINVAL;
1572 goto cleanup1;
1573 }
1574 /* Check kmalloc limits using all SGs */
1575 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
1576 status = -EINVAL;
1577 goto cleanup1;
1578 }
1579 if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
1580 status = -EINVAL;
1581 goto cleanup1;
1582 }
1583 buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
1584 if (!buff) {
1585 status = -ENOMEM;
1586 goto cleanup1;
1587 }
1588 buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
1589 if (!buff_size) {
1590 status = -ENOMEM;
1591 goto cleanup1;
1592 }
1593 left = ioc->buf_size;
1594 data_ptr = ioc->buf;
1595 while (left) {
1596 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
1597 buff_size[sg_used] = sz;
1598 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
1599 if (buff[sg_used] == NULL) {
1600 status = -ENOMEM;
1601 goto cleanup1;
1602 }
1603 if (ioc->Request.Type.Direction == XFER_WRITE) {
1604 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
7c832835
BH		 1605 status = -EFAULT;
1606 goto cleanup1;
1607 }
0c9f5ba7
SC		 1608 } else {
1609 memset(buff[sg_used], 0, sz);
1610 }
1611 left -= sz;
1612 data_ptr += sz;
1613 sg_used++;
1614 }
1615 c = cmd_special_alloc(h);
1616 if (!c) {
1617 status = -ENOMEM;
1618 goto cleanup1;
1619 }
1620 c->cmd_type = CMD_IOCTL_PEND;
1621 c->Header.ReplyQueue = 0;
fcfb5c0c
SC		 1622 c->Header.SGList = sg_used;
1623 c->Header.SGTotal = sg_used;
0c9f5ba7
SC		 1624 c->Header.LUN = ioc->LUN_info;
1625 c->Header.Tag.lower = c->busaddr;
1626
1627 c->Request = ioc->Request;
fcfb5c0c
SC		 1628 for (i = 0; i < sg_used; i++) {
1629 temp64.val = pci_map_single(h->pdev, buff[i], buff_size[i],
0c9f5ba7 1630 PCI_DMA_BIDIRECTIONAL);
fcfb5c0c
SC		 1631 c->SG[i].Addr.lower = temp64.val32.lower;
1632 c->SG[i].Addr.upper = temp64.val32.upper;
1633 c->SG[i].Len = buff_size[i];
1634 c->SG[i].Ext = 0; /* we are not chaining */
0c9f5ba7
SC		 1635 }
1636 c->waiting = &wait;
1637 enqueue_cmd_and_start_io(h, c);
1638 wait_for_completion(&wait);
1639 /* unlock the buffers from DMA */
1640 for (i = 0; i < sg_used; i++) {
1641 temp64.val32.lower = c->SG[i].Addr.lower;
1642 temp64.val32.upper = c->SG[i].Addr.upper;
1643 pci_unmap_single(h->pdev,
1644 (dma_addr_t) temp64.val, buff_size[i],
1645 PCI_DMA_BIDIRECTIONAL);
1646 }
1647 check_ioctl_unit_attention(h, c);
1648 /* Copy the error information out */
1649 ioc->error_info = *(c->err_info);
1650 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
1651 cmd_special_free(h, c);
1652 status = -EFAULT;
1653 goto cleanup1;
1654 }
1655 if (ioc->Request.Type.Direction == XFER_READ) {
1656 /* Copy the data out of the buffer we created */
1657 BYTE __user *ptr = ioc->buf;
1658 for (i = 0; i < sg_used; i++) {
1659 if (copy_to_user(ptr, buff[i], buff_size[i])) {
6b4d96b8 1660 cmd_special_free(h, c);
7c832835
BH		 1661 status = -EFAULT;
1662 goto cleanup1;
1663 }
0c9f5ba7 1664 ptr += buff_size[i];
1da177e4 1665 }
0c9f5ba7
SC		 1666 }
1667 cmd_special_free(h, c);
1668 status = 0;
1669cleanup1:
1670 if (buff) {
1671 for (i = 0; i < sg_used; i++)
1672 kfree(buff[i]);
1673 kfree(buff);
1674 }
1675 kfree(buff_size);
1676 kfree(ioc);
1677 return status;
1678}
1679
ef7822c2 1680static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
c525919d 1681 unsigned int cmd, unsigned long arg)
1da177e4 1682{
1da177e4 1683 struct gendisk *disk = bdev->bd_disk;
f70dba83 1684 ctlr_info_t *h = get_host(disk);
1da177e4
LT		 1685 void __user *argp = (void __user *)arg;
1686
b2a4a43d
SC		 1687 dev_dbg(&h->pdev->dev, "cciss_ioctl: Called with cmd=%x %lx\n",
1688 cmd, arg);
7c832835 1689 switch (cmd) {
1da177e4 1690 case CCISS_GETPCIINFO:
0a25a5ae 1691 return cciss_getpciinfo(h, argp);
1da177e4 1692 case CCISS_GETINTINFO:
576e661c 1693 return cciss_getintinfo(h, argp);
1da177e4 1694 case CCISS_SETINTINFO:
4c800eed 1695 return cciss_setintinfo(h, argp);
1da177e4 1696 case CCISS_GETNODENAME:
25216109 1697 return cciss_getnodename(h, argp);
1da177e4 1698 case CCISS_SETNODENAME:
4f43f32c 1699 return cciss_setnodename(h, argp);
1da177e4 1700 case CCISS_GETHEARTBEAT:
93c74931 1701 return cciss_getheartbeat(h, argp);
1da177e4 1702 case CCISS_GETBUSTYPES:
d18dfad4 1703 return cciss_getbustypes(h, argp);
1da177e4 1704 case CCISS_GETFIRMVER:
8a4f7fbf 1705 return cciss_getfirmver(h, argp);
7c832835 1706 case CCISS_GETDRIVVER:
c525919d 1707 return cciss_getdrivver(h, argp);
6ae5ce8e
MM		 1708 case CCISS_DEREGDISK:
1709 case CCISS_REGNEWD:
1da177e4 1710 case CCISS_REVALIDVOLS:
f70dba83 1711 return rebuild_lun_table(h, 0, 1);
0894b32c
SC		 1712 case CCISS_GETLUNINFO:
1713 return cciss_getluninfo(h, disk, argp);
1da177e4 1714 case CCISS_PASSTHRU:
f32f125b 1715 return cciss_passthru(h, argp);
0c9f5ba7
SC		 1716 case CCISS_BIG_PASSTHRU:
1717 return cciss_bigpassthru(h, argp);
03bbfee5
MMOD		 1718
1719 /* scsi_cmd_ioctl handles these, below, though some are not */
1720 /* very meaningful for cciss. SG_IO is the main one people want. */
1721
1722 case SG_GET_VERSION_NUM:
1723 case SG_SET_TIMEOUT:
1724 case SG_GET_TIMEOUT:
1725 case SG_GET_RESERVED_SIZE:
1726 case SG_SET_RESERVED_SIZE:
1727 case SG_EMULATED_HOST:
1728 case SG_IO:
1729 case SCSI_IOCTL_SEND_COMMAND:
ef7822c2 1730 return scsi_cmd_ioctl(disk->queue, disk, mode, cmd, argp);
03bbfee5
MMOD		 1731
1732 /* scsi_cmd_ioctl would normally handle these, below, but */
1733 /* they aren't a good fit for cciss, as CD-ROMs are */
1734 /* not supported, and we don't have any bus/target/lun */
1735 /* which we present to the kernel. */
1736
1737 case CDROM_SEND_PACKET:
1738 case CDROMCLOSETRAY:
1739 case CDROMEJECT:
1740 case SCSI_IOCTL_GET_IDLUN:
1741 case SCSI_IOCTL_GET_BUS_NUMBER:
1da177e4
LT		 1742 default:
1743 return -ENOTTY;
1744 }
1da177e4
LT		 1745}
1746
7b30f092
JA		 1747static void cciss_check_queues(ctlr_info_t *h)
1748{
1749 int start_queue = h->next_to_run;
1750 int i;
1751
1752 /* check to see if we have maxed out the number of commands that can
1753 * be placed on the queue. If so then exit. We do this check here
1754 * in case the interrupt we serviced was from an ioctl and did not
1755 * free any new commands.
1756 */
f880632f 1757 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds)
7b30f092
JA		 1758 return;
1759
1760 /* We have room on the queue for more commands. Now we need to queue
1761 * them up. We will also keep track of the next queue to run so
1762 * that every queue gets a chance to be started first.
1763 */
1764 for (i = 0; i < h->highest_lun + 1; i++) {
1765 int curr_queue = (start_queue + i) % (h->highest_lun + 1);
1766 /* make sure the disk has been added and the drive is real
1767 * because this can be called from the middle of init_one.
1768 */
9cef0d2f
SC		 1769 if (!h->drv[curr_queue])
1770 continue;
1771 if (!(h->drv[curr_queue]->queue) ||
1772 !(h->drv[curr_queue]->heads))
7b30f092
JA		 1773 continue;
1774 blk_start_queue(h->gendisk[curr_queue]->queue);
1775
1776 /* check to see if we have maxed out the number of commands
1777 * that can be placed on the queue.
1778 */
f880632f 1779 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds) {
7b30f092
JA		 1780 if (curr_queue == start_queue) {
1781 h->next_to_run =
1782 (start_queue + 1) % (h->highest_lun + 1);
1783 break;
1784 } else {
1785 h->next_to_run = curr_queue;
1786 break;
1787 }
7b30f092
JA		 1788 }
1789 }
1790}
1791
ca1e0484
MM		 1792static void cciss_softirq_done(struct request *rq)
1793{
f70dba83
SC		 1794 CommandList_struct *c = rq->completion_data;
1795 ctlr_info_t *h = hba[c->ctlr];
1796 SGDescriptor_struct *curr_sg = c->SG;
ca1e0484 1797 u64bit temp64;
664a717d 1798 unsigned long flags;
ca1e0484 1799 int i, ddir;
5c07a311 1800 int sg_index = 0;
ca1e0484 1801
f70dba83 1802 if (c->Request.Type.Direction == XFER_READ)
ca1e0484
MM		 1803 ddir = PCI_DMA_FROMDEVICE;
1804 else
1805 ddir = PCI_DMA_TODEVICE;
1806
1807 /* command did not need to be retried */
1808 /* unmap the DMA mapping for all the scatter gather elements */
f70dba83 1809 for (i = 0; i < c->Header.SGList; i++) {
5c07a311 1810 if (curr_sg[sg_index].Ext == CCISS_SG_CHAIN) {
f70dba83 1811 cciss_unmap_sg_chain_block(h, c);
5c07a311 1812 /* Point to the next block */
f70dba83 1813 curr_sg = h->cmd_sg_list[c->cmdindex];
5c07a311
DB		 1814 sg_index = 0;
1815 }
1816 temp64.val32.lower = curr_sg[sg_index].Addr.lower;
1817 temp64.val32.upper = curr_sg[sg_index].Addr.upper;
1818 pci_unmap_page(h->pdev, temp64.val, curr_sg[sg_index].Len,
1819 ddir);
1820 ++sg_index;
ca1e0484
MM		 1821 }
1822
b2a4a43d 1823 dev_dbg(&h->pdev->dev, "Done with %p\n", rq);
ca1e0484 1824
c3a4d78c 1825 /* set the residual count for pc requests */
33659ebb 1826 if (rq->cmd_type == REQ_TYPE_BLOCK_PC)
f70dba83 1827 rq->resid_len = c->err_info->ResidualCnt;
ac44e5b2 1828
c3a4d78c 1829 blk_end_request_all(rq, (rq->errors == 0) ? 0 : -EIO);
3daeea29 1830
ca1e0484 1831 spin_lock_irqsave(&h->lock, flags);
6b4d96b8 1832 cmd_free(h, c);
7b30f092 1833 cciss_check_queues(h);
ca1e0484
MM		 1834 spin_unlock_irqrestore(&h->lock, flags);
1835}
1836
39ccf9a6
SC		 1837static inline void log_unit_to_scsi3addr(ctlr_info_t *h,
1838 unsigned char scsi3addr[], uint32_t log_unit)
b57695fe 1839{
9cef0d2f
SC		 1840 memcpy(scsi3addr, h->drv[log_unit]->LunID,
1841 sizeof(h->drv[log_unit]->LunID));
b57695fe 1842}
1843
7fe06326
AP		 1844/* This function gets the SCSI vendor, model, and revision of a logical drive
1845 * via the inquiry page 0. Model, vendor, and rev are set to empty strings if
1846 * they cannot be read.
1847 */
f70dba83 1848static void cciss_get_device_descr(ctlr_info_t *h, int logvol,
7fe06326
AP		 1849 char *vendor, char *model, char *rev)
1850{
1851 int rc;
1852 InquiryData_struct *inq_buf;
b57695fe 1853 unsigned char scsi3addr[8];
7fe06326
AP		 1854
1855 *vendor = '\0';
1856 *model = '\0';
1857 *rev = '\0';
1858
1859 inq_buf = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
1860 if (!inq_buf)
1861 return;
1862
f70dba83
SC		 1863 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1864 rc = sendcmd_withirq(h, CISS_INQUIRY, inq_buf, sizeof(*inq_buf), 0,
7b838bde 1865 scsi3addr, TYPE_CMD);
7fe06326
AP		 1866 if (rc == IO_OK) {
1867 memcpy(vendor, &inq_buf->data_byte[8], VENDOR_LEN);
1868 vendor[VENDOR_LEN] = '\0';
1869 memcpy(model, &inq_buf->data_byte[16], MODEL_LEN);
1870 model[MODEL_LEN] = '\0';
1871 memcpy(rev, &inq_buf->data_byte[32], REV_LEN);
1872 rev[REV_LEN] = '\0';
1873 }
1874
1875 kfree(inq_buf);
1876 return;
1877}
1878
a72da29b
MM		 1879/* This function gets the serial number of a logical drive via
1880 * inquiry page 0x83. Serial no. is 16 bytes. If the serial
1881 * number cannot be had, for whatever reason, 16 bytes of 0xff
1882 * are returned instead.
1883 */
f70dba83 1884static void cciss_get_serial_no(ctlr_info_t *h, int logvol,
a72da29b
MM		 1885 unsigned char *serial_no, int buflen)
1886{
1887#define PAGE_83_INQ_BYTES 64
1888 int rc;
1889 unsigned char *buf;
b57695fe 1890 unsigned char scsi3addr[8];
a72da29b
MM		 1891
1892 if (buflen > 16)
1893 buflen = 16;
1894 memset(serial_no, 0xff, buflen);
1895 buf = kzalloc(PAGE_83_INQ_BYTES, GFP_KERNEL);
1896 if (!buf)
1897 return;
1898 memset(serial_no, 0, buflen);
f70dba83
SC		 1899 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1900 rc = sendcmd_withirq(h, CISS_INQUIRY, buf,
7b838bde 1901 PAGE_83_INQ_BYTES, 0x83, scsi3addr, TYPE_CMD);
a72da29b
MM		 1902 if (rc == IO_OK)
1903 memcpy(serial_no, &buf[8], buflen);
1904 kfree(buf);
1905 return;
1906}
1907
617e1344
SC		 1908/*
1909 * cciss_add_disk sets up the block device queue for a logical drive
1910 */
1911static int cciss_add_disk(ctlr_info_t *h, struct gendisk *disk,
6ae5ce8e
MM		 1912 int drv_index)
1913{
1914 disk->queue = blk_init_queue(do_cciss_request, &h->lock);
e8074f79
SC		 1915 if (!disk->queue)
1916 goto init_queue_failure;
6ae5ce8e
MM		 1917 sprintf(disk->disk_name, "cciss/c%dd%d", h->ctlr, drv_index);
1918 disk->major = h->major;
1919 disk->first_minor = drv_index << NWD_SHIFT;
1920 disk->fops = &cciss_fops;
9cef0d2f
SC		 1921 if (cciss_create_ld_sysfs_entry(h, drv_index))
1922 goto cleanup_queue;
1923 disk->private_data = h->drv[drv_index];
1924 disk->driverfs_dev = &h->drv[drv_index]->dev;
6ae5ce8e
MM		 1925
1926 /* Set up queue information */
1927 blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask);
1928
1929 /* This is a hardware imposed limit. */
8a78362c 1930 blk_queue_max_segments(disk->queue, h->maxsgentries);
6ae5ce8e 1931
086fa5ff 1932 blk_queue_max_hw_sectors(disk->queue, h->cciss_max_sectors);
6ae5ce8e
MM		 1933
1934 blk_queue_softirq_done(disk->queue, cciss_softirq_done);
1935
1936 disk->queue->queuedata = h;
1937
e1defc4f 1938 blk_queue_logical_block_size(disk->queue,
9cef0d2f 1939 h->drv[drv_index]->block_size);
6ae5ce8e
MM		 1940
1941 /* Make sure all queue data is written out before */
9cef0d2f 1942 /* setting h->drv[drv_index]->queue, as setting this */
6ae5ce8e
MM		 1943 /* allows the interrupt handler to start the queue */
1944 wmb();
9cef0d2f 1945 h->drv[drv_index]->queue = disk->queue;
6ae5ce8e 1946 add_disk(disk);
617e1344
SC		 1947 return 0;
1948
1949cleanup_queue:
1950 blk_cleanup_queue(disk->queue);
1951 disk->queue = NULL;
e8074f79 1952init_queue_failure:
617e1344 1953 return -1;
6ae5ce8e
MM		 1954}
1955
ddd47442 1956/* This function will check the usage_count of the drive to be updated/added.
a72da29b
MM		 1957 * If the usage_count is zero and it is a heretofore unknown drive, or,
1958 * the drive's capacity, geometry, or serial number has changed,
1959 * then the drive information will be updated and the disk will be
1960 * re-registered with the kernel. If these conditions don't hold,
1961 * then it will be left alone for the next reboot. The exception to this
1962 * is disk 0 which will always be left registered with the kernel since it
1963 * is also the controller node. Any changes to disk 0 will show up on
1964 * the next reboot.
7c832835 1965 */
f70dba83
SC		 1966static void cciss_update_drive_info(ctlr_info_t *h, int drv_index,
1967 int first_time, int via_ioctl)
7c832835 1968{
ddd47442 1969 struct gendisk *disk;
ddd47442
MM		 1970 InquiryData_struct *inq_buff = NULL;
1971 unsigned int block_size;
00988a35 1972 sector_t total_size;
ddd47442
MM		 1973 unsigned long flags = 0;
1974 int ret = 0;
a72da29b
MM		 1975 drive_info_struct *drvinfo;
1976
1977 /* Get information about the disk and modify the driver structure */
1978 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
9cef0d2f 1979 drvinfo = kzalloc(sizeof(*drvinfo), GFP_KERNEL);
a72da29b
MM		 1980 if (inq_buff == NULL || drvinfo == NULL)
1981 goto mem_msg;
1982
1983 /* testing to see if 16-byte CDBs are already being used */
1984 if (h->cciss_read == CCISS_READ_16) {
f70dba83 1985 cciss_read_capacity_16(h, drv_index,
a72da29b
MM		 1986 &total_size, &block_size);
1987
1988 } else {
f70dba83 1989 cciss_read_capacity(h, drv_index, &total_size, &block_size);
a72da29b
MM		 1990 /* if read_capacity returns all F's this volume is >2TB */
1991 /* in size so we switch to 16-byte CDB's for all */
1992 /* read/write ops */
1993 if (total_size == 0xFFFFFFFFULL) {
f70dba83 1994 cciss_read_capacity_16(h, drv_index,
a72da29b
MM		 1995 &total_size, &block_size);
1996 h->cciss_read = CCISS_READ_16;
1997 h->cciss_write = CCISS_WRITE_16;
1998 } else {
1999 h->cciss_read = CCISS_READ_10;
2000 h->cciss_write = CCISS_WRITE_10;
2001 }
2002 }
2003
f70dba83 2004 cciss_geometry_inquiry(h, drv_index, total_size, block_size,
a72da29b
MM		 2005 inq_buff, drvinfo);
2006 drvinfo->block_size = block_size;
2007 drvinfo->nr_blocks = total_size + 1;
2008
f70dba83 2009 cciss_get_device_descr(h, drv_index, drvinfo->vendor,
7fe06326 2010 drvinfo->model, drvinfo->rev);
f70dba83 2011 cciss_get_serial_no(h, drv_index, drvinfo->serial_no,
a72da29b 2012 sizeof(drvinfo->serial_no));
9cef0d2f
SC		 2013 /* Save the lunid in case we deregister the disk, below. */
2014 memcpy(drvinfo->LunID, h->drv[drv_index]->LunID,
2015 sizeof(drvinfo->LunID));
a72da29b
MM		 2016
2017 /* Is it the same disk we already know, and nothing's changed? */
9cef0d2f 2018 if (h->drv[drv_index]->raid_level != -1 &&
a72da29b 2019 ((memcmp(drvinfo->serial_no,
9cef0d2f
SC		 2020 h->drv[drv_index]->serial_no, 16) == 0) &&
2021 drvinfo->block_size == h->drv[drv_index]->block_size &&
2022 drvinfo->nr_blocks == h->drv[drv_index]->nr_blocks &&
2023 drvinfo->heads == h->drv[drv_index]->heads &&
2024 drvinfo->sectors == h->drv[drv_index]->sectors &&
2025 drvinfo->cylinders == h->drv[drv_index]->cylinders))
a72da29b
MM		 2026 /* The disk is unchanged, nothing to update */
2027 goto freeret;
a72da29b 2028
6ae5ce8e
MM		 2029 /* If we get here it's not the same disk, or something's changed,
2030 * so we need to * deregister it, and re-register it, if it's not
2031 * in use.
2032 * If the disk already exists then deregister it before proceeding
2033 * (unless it's the first disk (for the controller node).
2034 */
9cef0d2f 2035 if (h->drv[drv_index]->raid_level != -1 && drv_index != 0) {
b2a4a43d 2036 dev_warn(&h->pdev->dev, "disk %d has changed.\n", drv_index);
f70dba83 2037 spin_lock_irqsave(&h->lock, flags);
9cef0d2f 2038 h->drv[drv_index]->busy_configuring = 1;
f70dba83 2039 spin_unlock_irqrestore(&h->lock, flags);
e14ac670 2040
9cef0d2f 2041 /* deregister_disk sets h->drv[drv_index]->queue = NULL
6ae5ce8e
MM		 2042 * which keeps the interrupt handler from starting
2043 * the queue.
2044 */
2d11d993 2045 ret = deregister_disk(h, drv_index, 0, via_ioctl);
ddd47442
MM		 2046 }
2047
2048 /* If the disk is in use return */
2049 if (ret)
a72da29b
MM		 2050 goto freeret;
2051
6ae5ce8e 2052 /* Save the new information from cciss_geometry_inquiry
9cef0d2f
SC		 2053 * and serial number inquiry. If the disk was deregistered
2054 * above, then h->drv[drv_index] will be NULL.
6ae5ce8e 2055 */
9cef0d2f
SC		 2056 if (h->drv[drv_index] == NULL) {
2057 drvinfo->device_initialized = 0;
2058 h->drv[drv_index] = drvinfo;
2059 drvinfo = NULL; /* so it won't be freed below. */
2060 } else {
2061 /* special case for cxd0 */
2062 h->drv[drv_index]->block_size = drvinfo->block_size;
2063 h->drv[drv_index]->nr_blocks = drvinfo->nr_blocks;
2064 h->drv[drv_index]->heads = drvinfo->heads;
2065 h->drv[drv_index]->sectors = drvinfo->sectors;
2066 h->drv[drv_index]->cylinders = drvinfo->cylinders;
2067 h->drv[drv_index]->raid_level = drvinfo->raid_level;
2068 memcpy(h->drv[drv_index]->serial_no, drvinfo->serial_no, 16);
2069 memcpy(h->drv[drv_index]->vendor, drvinfo->vendor,
2070 VENDOR_LEN + 1);
2071 memcpy(h->drv[drv_index]->model, drvinfo->model, MODEL_LEN + 1);
2072 memcpy(h->drv[drv_index]->rev, drvinfo->rev, REV_LEN + 1);
2073 }
ddd47442
MM		 2074
2075 ++h->num_luns;
2076 disk = h->gendisk[drv_index];
9cef0d2f 2077 set_capacity(disk, h->drv[drv_index]->nr_blocks);
ddd47442 2078
6ae5ce8e
MM		 2079 /* If it's not disk 0 (drv_index != 0)
2080 * or if it was disk 0, but there was previously
2081 * no actual corresponding configured logical drive
2082 * (raid_leve == -1) then we want to update the
2083 * logical drive's information.
2084 */
361e9b07
SC		 2085 if (drv_index || first_time) {
2086 if (cciss_add_disk(h, disk, drv_index) != 0) {
2087 cciss_free_gendisk(h, drv_index);
9cef0d2f 2088 cciss_free_drive_info(h, drv_index);
b2a4a43d
SC		 2089 dev_warn(&h->pdev->dev, "could not update disk %d\n",
2090 drv_index);
361e9b07
SC		 2091 --h->num_luns;
2092 }
2093 }
ddd47442 2094
6ae5ce8e 2095freeret:
ddd47442 2096 kfree(inq_buff);
a72da29b 2097 kfree(drvinfo);
ddd47442 2098 return;
6ae5ce8e 2099mem_msg:
b2a4a43d 2100 dev_err(&h->pdev->dev, "out of memory\n");
ddd47442
MM		 2101 goto freeret;
2102}
2103
2104/* This function will find the first index of the controllers drive array
9cef0d2f
SC		 2105 * that has a null drv pointer and allocate the drive info struct and
2106 * will return that index This is where new drives will be added.
2107 * If the index to be returned is greater than the highest_lun index for
2108 * the controller then highest_lun is set * to this new index.
2109 * If there are no available indexes or if tha allocation fails, then -1
2110 * is returned. * "controller_node" is used to know if this is a real
2111 * logical drive, or just the controller node, which determines if this
2112 * counts towards highest_lun.
7c832835 2113 */
9cef0d2f 2114static int cciss_alloc_drive_info(ctlr_info_t *h, int controller_node)
ddd47442
MM		 2115{
2116 int i;
9cef0d2f 2117 drive_info_struct *drv;
ddd47442 2118
9cef0d2f 2119 /* Search for an empty slot for our drive info */
7c832835 2120 for (i = 0; i < CISS_MAX_LUN; i++) {
9cef0d2f
SC		 2121
2122 /* if not cxd0 case, and it's occupied, skip it. */
2123 if (h->drv[i] && i != 0)
2124 continue;
2125 /*
2126 * If it's cxd0 case, and drv is alloc'ed already, and a
2127 * disk is configured there, skip it.
2128 */
2129 if (i == 0 && h->drv[i] && h->drv[i]->raid_level != -1)
2130 continue;
2131
2132 /*
2133 * We've found an empty slot. Update highest_lun
2134 * provided this isn't just the fake cxd0 controller node.
2135 */
2136 if (i > h->highest_lun && !controller_node)
2137 h->highest_lun = i;
2138
2139 /* If adding a real disk at cxd0, and it's already alloc'ed */
2140 if (i == 0 && h->drv[i] != NULL)
ddd47442 2141 return i;
9cef0d2f
SC		 2142
2143 /*
2144 * Found an empty slot, not already alloc'ed. Allocate it.
2145 * Mark it with raid_level == -1, so we know it's new later on.
2146 */
2147 drv = kzalloc(sizeof(*drv), GFP_KERNEL);
2148 if (!drv)
2149 return -1;
2150 drv->raid_level = -1; /* so we know it's new */
2151 h->drv[i] = drv;
2152 return i;
ddd47442
MM		 2153 }
2154 return -1;
2155}
2156
9cef0d2f
SC		 2157static void cciss_free_drive_info(ctlr_info_t *h, int drv_index)
2158{
2159 kfree(h->drv[drv_index]);
2160 h->drv[drv_index] = NULL;
2161}
2162
361e9b07
SC		 2163static void cciss_free_gendisk(ctlr_info_t *h, int drv_index)
2164{
2165 put_disk(h->gendisk[drv_index]);
2166 h->gendisk[drv_index] = NULL;
2167}
2168
6ae5ce8e
MM		 2169/* cciss_add_gendisk finds a free hba[]->drv structure
2170 * and allocates a gendisk if needed, and sets the lunid
2171 * in the drvinfo structure. It returns the index into
2172 * the ->drv[] array, or -1 if none are free.
2173 * is_controller_node indicates whether highest_lun should
2174 * count this disk, or if it's only being added to provide
2175 * a means to talk to the controller in case no logical
2176 * drives have yet been configured.
2177 */
39ccf9a6
SC		 2178static int cciss_add_gendisk(ctlr_info_t *h, unsigned char lunid[],
2179 int controller_node)
6ae5ce8e
MM		 2180{
2181 int drv_index;
2182
9cef0d2f 2183 drv_index = cciss_alloc_drive_info(h, controller_node);
6ae5ce8e
MM		 2184 if (drv_index == -1)
2185 return -1;
8ce51966 2186
6ae5ce8e
MM		 2187 /*Check if the gendisk needs to be allocated */
2188 if (!h->gendisk[drv_index]) {
2189 h->gendisk[drv_index] =
2190 alloc_disk(1 << NWD_SHIFT);
2191 if (!h->gendisk[drv_index]) {
b2a4a43d
SC		 2192 dev_err(&h->pdev->dev,
2193 "could not allocate a new disk %d\n",
2194 drv_index);
9cef0d2f 2195 goto err_free_drive_info;
6ae5ce8e
MM		 2196 }
2197 }
9cef0d2f
SC		 2198 memcpy(h->drv[drv_index]->LunID, lunid,
2199 sizeof(h->drv[drv_index]->LunID));
2200 if (cciss_create_ld_sysfs_entry(h, drv_index))
7fe06326 2201 goto err_free_disk;
6ae5ce8e
MM		 2202 /* Don't need to mark this busy because nobody */
2203 /* else knows about this disk yet to contend */
2204 /* for access to it. */
9cef0d2f 2205 h->drv[drv_index]->busy_configuring = 0;
6ae5ce8e
MM		 2206 wmb();
2207 return drv_index;
7fe06326
AP		 2208
2209err_free_disk:
361e9b07 2210 cciss_free_gendisk(h, drv_index);
9cef0d2f
SC		 2211err_free_drive_info:
2212 cciss_free_drive_info(h, drv_index);
7fe06326 2213 return -1;
6ae5ce8e
MM		 2214}
2215
2216/* This is for the special case of a controller which
2217 * has no logical drives. In this case, we still need
2218 * to register a disk so the controller can be accessed
2219 * by the Array Config Utility.
2220 */
2221static void cciss_add_controller_node(ctlr_info_t *h)
2222{
2223 struct gendisk *disk;
2224 int drv_index;
2225
2226 if (h->gendisk[0] != NULL) /* already did this? Then bail. */
2227 return;
2228
39ccf9a6 2229 drv_index = cciss_add_gendisk(h, CTLR_LUNID, 1);
361e9b07
SC		 2230 if (drv_index == -1)
2231 goto error;
9cef0d2f
SC		 2232 h->drv[drv_index]->block_size = 512;
2233 h->drv[drv_index]->nr_blocks = 0;
2234 h->drv[drv_index]->heads = 0;
2235 h->drv[drv_index]->sectors = 0;
2236 h->drv[drv_index]->cylinders = 0;
2237 h->drv[drv_index]->raid_level = -1;
2238 memset(h->drv[drv_index]->serial_no, 0, 16);
6ae5ce8e 2239 disk = h->gendisk[drv_index];
361e9b07
SC		 2240 if (cciss_add_disk(h, disk, drv_index) == 0)
2241 return;
2242 cciss_free_gendisk(h, drv_index);
9cef0d2f 2243 cciss_free_drive_info(h, drv_index);
361e9b07 2244error:
b2a4a43d 2245 dev_warn(&h->pdev->dev, "could not add disk 0.\n");
361e9b07 2246 return;
6ae5ce8e
MM		 2247}
2248
ddd47442 2249/* This function will add and remove logical drives from the Logical
d14c4ab5 2250 * drive array of the controller and maintain persistency of ordering
ddd47442
MM		 2251 * so that mount points are preserved until the next reboot. This allows
2252 * for the removal of logical drives in the middle of the drive array
2253 * without a re-ordering of those drives.
2254 * INPUT
2255 * h = The controller to perform the operations on
7c832835 2256 */
2d11d993
SC		 2257static int rebuild_lun_table(ctlr_info_t *h, int first_time,
2258 int via_ioctl)
1da177e4 2259{
ddd47442
MM		 2260 int num_luns;
2261 ReportLunData_struct *ld_buff = NULL;
ddd47442
MM		 2262 int return_code;
2263 int listlength = 0;
2264 int i;
2265 int drv_found;
2266 int drv_index = 0;
39ccf9a6 2267 unsigned char lunid[8] = CTLR_LUNID;
1da177e4 2268 unsigned long flags;
ddd47442 2269
6ae5ce8e
MM		 2270 if (!capable(CAP_SYS_RAWIO))
2271 return -EPERM;
2272
ddd47442 2273 /* Set busy_configuring flag for this operation */
f70dba83 2274 spin_lock_irqsave(&h->lock, flags);
7c832835 2275 if (h->busy_configuring) {
f70dba83 2276 spin_unlock_irqrestore(&h->lock, flags);
ddd47442
MM		 2277 return -EBUSY;
2278 }
2279 h->busy_configuring = 1;
f70dba83 2280 spin_unlock_irqrestore(&h->lock, flags);
ddd47442 2281
a72da29b
MM		 2282 ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL);
2283 if (ld_buff == NULL)
2284 goto mem_msg;
2285
f70dba83 2286 return_code = sendcmd_withirq(h, CISS_REPORT_LOG, ld_buff,
b57695fe 2287 sizeof(ReportLunData_struct),
2288 0, CTLR_LUNID, TYPE_CMD);
ddd47442 2289
a72da29b
MM		 2290 if (return_code == IO_OK)
2291 listlength = be32_to_cpu(*(__be32 *) ld_buff->LUNListLength);
2292 else { /* reading number of logical volumes failed */
b2a4a43d
SC		 2293 dev_warn(&h->pdev->dev,
2294 "report logical volume command failed\n");
a72da29b
MM		 2295 listlength = 0;
2296 goto freeret;
2297 }
2298
2299 num_luns = listlength / 8; /* 8 bytes per entry */
2300 if (num_luns > CISS_MAX_LUN) {
2301 num_luns = CISS_MAX_LUN;
b2a4a43d 2302 dev_warn(&h->pdev->dev, "more luns configured"
a72da29b
MM		 2303 " on controller than can be handled by"
2304 " this driver.\n");
2305 }
2306
6ae5ce8e
MM		 2307 if (num_luns == 0)
2308 cciss_add_controller_node(h);
2309
2310 /* Compare controller drive array to driver's drive array
2311 * to see if any drives are missing on the controller due
2312 * to action of Array Config Utility (user deletes drive)
2313 * and deregister logical drives which have disappeared.
2314 */
a72da29b
MM		 2315 for (i = 0; i <= h->highest_lun; i++) {
2316 int j;
2317 drv_found = 0;
d8a0be6a
SC		 2318
2319 /* skip holes in the array from already deleted drives */
9cef0d2f 2320 if (h->drv[i] == NULL)
d8a0be6a
SC		 2321 continue;
2322
a72da29b 2323 for (j = 0; j < num_luns; j++) {
39ccf9a6 2324 memcpy(lunid, &ld_buff->LUN[j][0], sizeof(lunid));
9cef0d2f 2325 if (memcmp(h->drv[i]->LunID, lunid,
39ccf9a6 2326 sizeof(lunid)) == 0) {
a72da29b
MM		 2327 drv_found = 1;
2328 break;
2329 }
2330 }
2331 if (!drv_found) {
2332 /* Deregister it from the OS, it's gone. */
f70dba83 2333 spin_lock_irqsave(&h->lock, flags);
9cef0d2f 2334 h->drv[i]->busy_configuring = 1;
f70dba83 2335 spin_unlock_irqrestore(&h->lock, flags);
2d11d993 2336 return_code = deregister_disk(h, i, 1, via_ioctl);
9cef0d2f
SC		 2337 if (h->drv[i] != NULL)
2338 h->drv[i]->busy_configuring = 0;
ddd47442 2339 }
a72da29b 2340 }
ddd47442 2341
a72da29b
MM		 2342 /* Compare controller drive array to driver's drive array.
2343 * Check for updates in the drive information and any new drives
2344 * on the controller due to ACU adding logical drives, or changing
2345 * a logical drive's size, etc. Reregister any new/changed drives
2346 */
2347 for (i = 0; i < num_luns; i++) {
2348 int j;
ddd47442 2349
a72da29b 2350 drv_found = 0;
ddd47442 2351
39ccf9a6 2352 memcpy(lunid, &ld_buff->LUN[i][0], sizeof(lunid));
a72da29b
MM		 2353 /* Find if the LUN is already in the drive array
2354 * of the driver. If so then update its info
2355 * if not in use. If it does not exist then find
2356 * the first free index and add it.
2357 */
2358 for (j = 0; j <= h->highest_lun; j++) {
9cef0d2f
SC		 2359 if (h->drv[j] != NULL &&
2360 memcmp(h->drv[j]->LunID, lunid,
2361 sizeof(h->drv[j]->LunID)) == 0) {
a72da29b
MM		 2362 drv_index = j;
2363 drv_found = 1;
2364 break;
ddd47442 2365 }
a72da29b 2366 }
ddd47442 2367
a72da29b
MM		 2368 /* check if the drive was found already in the array */
2369 if (!drv_found) {
eece695f 2370 drv_index = cciss_add_gendisk(h, lunid, 0);
a72da29b
MM		 2371 if (drv_index == -1)
2372 goto freeret;
a72da29b 2373 }
f70dba83 2374 cciss_update_drive_info(h, drv_index, first_time, via_ioctl);
a72da29b 2375 } /* end for */
ddd47442 2376
6ae5ce8e 2377freeret:
ddd47442
MM		 2378 kfree(ld_buff);
2379 h->busy_configuring = 0;
2380 /* We return -1 here to tell the ACU that we have registered/updated
2381 * all of the drives that we can and to keep it from calling us
2382 * additional times.
7c832835 2383 */
ddd47442 2384 return -1;
6ae5ce8e 2385mem_msg:
b2a4a43d 2386 dev_err(&h->pdev->dev, "out of memory\n");
a72da29b 2387 h->busy_configuring = 0;
ddd47442
MM		 2388 goto freeret;
2389}
2390
9ddb27b4
SC		 2391static void cciss_clear_drive_info(drive_info_struct *drive_info)
2392{
2393 /* zero out the disk size info */
2394 drive_info->nr_blocks = 0;
2395 drive_info->block_size = 0;
2396 drive_info->heads = 0;
2397 drive_info->sectors = 0;
2398 drive_info->cylinders = 0;
2399 drive_info->raid_level = -1;
2400 memset(drive_info->serial_no, 0, sizeof(drive_info->serial_no));
2401 memset(drive_info->model, 0, sizeof(drive_info->model));
2402 memset(drive_info->rev, 0, sizeof(drive_info->rev));
2403 memset(drive_info->vendor, 0, sizeof(drive_info->vendor));
2404 /*
2405 * don't clear the LUNID though, we need to remember which
2406 * one this one is.
2407 */
2408}
2409
ddd47442
MM		 2410/* This function will deregister the disk and it's queue from the
2411 * kernel. It must be called with the controller lock held and the
2412 * drv structures busy_configuring flag set. It's parameters are:
2413 *
2414 * disk = This is the disk to be deregistered
2415 * drv = This is the drive_info_struct associated with the disk to be
2416 * deregistered. It contains information about the disk used
2417 * by the driver.
2418 * clear_all = This flag determines whether or not the disk information
2419 * is going to be completely cleared out and the highest_lun
2420 * reset. Sometimes we want to clear out information about
d14c4ab5 2421 * the disk in preparation for re-adding it. In this case
ddd47442
MM		 2422 * the highest_lun should be left unchanged and the LunID
2423 * should not be cleared.
2d11d993
SC		 2424 * via_ioctl
2425 * This indicates whether we've reached this path via ioctl.
2426 * This affects the maximum usage count allowed for c0d0 to be messed with.
2427 * If this path is reached via ioctl(), then the max_usage_count will
2428 * be 1, as the process calling ioctl() has got to have the device open.
2429 * If we get here via sysfs, then the max usage count will be zero.
ddd47442 2430*/
a0ea8622 2431static int deregister_disk(ctlr_info_t *h, int drv_index,
2d11d993 2432 int clear_all, int via_ioctl)
ddd47442 2433{
799202cb 2434 int i;
a0ea8622
SC		 2435 struct gendisk *disk;
2436 drive_info_struct *drv;
9cef0d2f 2437 int recalculate_highest_lun;
1da177e4
LT		 2438
2439 if (!capable(CAP_SYS_RAWIO))
2440 return -EPERM;
2441
9cef0d2f 2442 drv = h->drv[drv_index];
a0ea8622
SC		 2443 disk = h->gendisk[drv_index];
2444
1da177e4 2445 /* make sure logical volume is NOT is use */
7c832835 2446 if (clear_all || (h->gendisk[0] == disk)) {
2d11d993 2447 if (drv->usage_count > via_ioctl)
7c832835
BH		 2448 return -EBUSY;
2449 } else if (drv->usage_count > 0)
2450 return -EBUSY;
1da177e4 2451
9cef0d2f
SC		 2452 recalculate_highest_lun = (drv == h->drv[h->highest_lun]);
2453
ddd47442
MM		 2454 /* invalidate the devices and deregister the disk. If it is disk
2455 * zero do not deregister it but just zero out it's values. This
2456 * allows us to delete disk zero but keep the controller registered.
7c832835
BH		 2457 */
2458 if (h->gendisk[0] != disk) {
5a9df732 2459 struct request_queue *q = disk->queue;
097d0264 2460 if (disk->flags & GENHD_FL_UP) {
8ce51966 2461 cciss_destroy_ld_sysfs_entry(h, drv_index, 0);
5a9df732 2462 del_gendisk(disk);
5a9df732 2463 }
9cef0d2f 2464 if (q)
5a9df732 2465 blk_cleanup_queue(q);
5a9df732
AB		 2466 /* If clear_all is set then we are deleting the logical
2467 * drive, not just refreshing its info. For drives
2468 * other than disk 0 we will call put_disk. We do not
2469 * do this for disk 0 as we need it to be able to
2470 * configure the controller.
a72da29b 2471 */
5a9df732
AB		 2472 if (clear_all){
2473 /* This isn't pretty, but we need to find the
2474 * disk in our array and NULL our the pointer.
2475 * This is so that we will call alloc_disk if
2476 * this index is used again later.
a72da29b 2477 */
5a9df732 2478 for (i=0; i < CISS_MAX_LUN; i++){
a72da29b 2479 if (h->gendisk[i] == disk) {
5a9df732
AB		 2480 h->gendisk[i] = NULL;
2481 break;
799202cb 2482 }
799202cb 2483 }
5a9df732 2484 put_disk(disk);
ddd47442 2485 }
799202cb
MM		 2486 } else {
2487 set_capacity(disk, 0);
9cef0d2f 2488 cciss_clear_drive_info(drv);
ddd47442
MM		 2489 }
2490
2491 --h->num_luns;
ddd47442 2492
9cef0d2f
SC		 2493 /* if it was the last disk, find the new hightest lun */
2494 if (clear_all && recalculate_highest_lun) {
c2d45b4d 2495 int newhighest = -1;
9cef0d2f
SC		 2496 for (i = 0; i <= h->highest_lun; i++) {
2497 /* if the disk has size > 0, it is available */
2498 if (h->drv[i] && h->drv[i]->heads)
2499 newhighest = i;
1da177e4 2500 }
9cef0d2f 2501 h->highest_lun = newhighest;
ddd47442 2502 }
e2019b58 2503 return 0;
1da177e4 2504}
ddd47442 2505
f70dba83 2506static int fill_cmd(ctlr_info_t *h, CommandList_struct *c, __u8 cmd, void *buff,
b57695fe 2507 size_t size, __u8 page_code, unsigned char *scsi3addr,
2508 int cmd_type)
1da177e4 2509{
1da177e4
LT		 2510 u64bit buff_dma_handle;
2511 int status = IO_OK;
2512
2513 c->cmd_type = CMD_IOCTL_PEND;
2514 c->Header.ReplyQueue = 0;
7c832835 2515 if (buff != NULL) {
1da177e4 2516 c->Header.SGList = 1;
7c832835 2517 c->Header.SGTotal = 1;
1da177e4
LT		 2518 } else {
2519 c->Header.SGList = 0;
7c832835 2520 c->Header.SGTotal = 0;
1da177e4
LT		 2521 }
2522 c->Header.Tag.lower = c->busaddr;
b57695fe 2523 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
1da177e4
LT		 2524
2525 c->Request.Type.Type = cmd_type;
2526 if (cmd_type == TYPE_CMD) {
7c832835
BH		 2527 switch (cmd) {
2528 case CISS_INQUIRY:
1da177e4 2529 /* are we trying to read a vital product page */
7c832835 2530 if (page_code != 0) {
1da177e4
LT		 2531 c->Request.CDB[1] = 0x01;
2532 c->Request.CDB[2] = page_code;
2533 }
2534 c->Request.CDBLen = 6;
7c832835 2535 c->Request.Type.Attribute = ATTR_SIMPLE;
1da177e4
LT		 2536 c->Request.Type.Direction = XFER_READ;
2537 c->Request.Timeout = 0;
7c832835
BH		 2538 c->Request.CDB[0] = CISS_INQUIRY;
2539 c->Request.CDB[4] = size & 0xFF;
2540 break;
1da177e4
LT		 2541 case CISS_REPORT_LOG:
2542 case CISS_REPORT_PHYS:
7c832835 2543 /* Talking to controller so It's a physical command
1da177e4 2544 mode = 00 target = 0. Nothing to write.
7c832835 2545 */
1da177e4
LT		 2546 c->Request.CDBLen = 12;
2547 c->Request.Type.Attribute = ATTR_SIMPLE;
2548 c->Request.Type.Direction = XFER_READ;
2549 c->Request.Timeout = 0;
2550 c->Request.CDB[0] = cmd;
b028461d 2551 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
1da177e4
LT		 2552 c->Request.CDB[7] = (size >> 16) & 0xFF;
2553 c->Request.CDB[8] = (size >> 8) & 0xFF;
2554 c->Request.CDB[9] = size & 0xFF;
2555 break;
2556
2557 case CCISS_READ_CAPACITY:
1da177e4
LT		 2558 c->Request.CDBLen = 10;
2559 c->Request.Type.Attribute = ATTR_SIMPLE;
2560 c->Request.Type.Direction = XFER_READ;
2561 c->Request.Timeout = 0;
2562 c->Request.CDB[0] = cmd;
7c832835 2563 break;
00988a35 2564 case CCISS_READ_CAPACITY_16:
00988a35
MMOD		 2565 c->Request.CDBLen = 16;
2566 c->Request.Type.Attribute = ATTR_SIMPLE;
2567 c->Request.Type.Direction = XFER_READ;
2568 c->Request.Timeout = 0;
2569 c->Request.CDB[0] = cmd;
2570 c->Request.CDB[1] = 0x10;
2571 c->Request.CDB[10] = (size >> 24) & 0xFF;
2572 c->Request.CDB[11] = (size >> 16) & 0xFF;
2573 c->Request.CDB[12] = (size >> 8) & 0xFF;
2574 c->Request.CDB[13] = size & 0xFF;
2575 c->Request.Timeout = 0;
2576 c->Request.CDB[0] = cmd;
2577 break;
1da177e4
LT		 2578 case CCISS_CACHE_FLUSH:
2579 c->Request.CDBLen = 12;
2580 c->Request.Type.Attribute = ATTR_SIMPLE;
2581 c->Request.Type.Direction = XFER_WRITE;
2582 c->Request.Timeout = 0;
2583 c->Request.CDB[0] = BMIC_WRITE;
2584 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
7c832835 2585 break;
88f627ae 2586 case TEST_UNIT_READY:
88f627ae
SC		 2587 c->Request.CDBLen = 6;
2588 c->Request.Type.Attribute = ATTR_SIMPLE;
2589 c->Request.Type.Direction = XFER_NONE;
2590 c->Request.Timeout = 0;
2591 break;
1da177e4 2592 default:
b2a4a43d 2593 dev_warn(&h->pdev->dev, "Unknown Command 0x%c\n", cmd);
e2019b58 2594 return IO_ERROR;
1da177e4
LT		 2595 }
2596 } else if (cmd_type == TYPE_MSG) {
2597 switch (cmd) {
8f71bb82 2598 case CCISS_ABORT_MSG:
3da8b713 2599 c->Request.CDBLen = 12;
2600 c->Request.Type.Attribute = ATTR_SIMPLE;
2601 c->Request.Type.Direction = XFER_WRITE;
2602 c->Request.Timeout = 0;
7c832835
BH		 2603 c->Request.CDB[0] = cmd; /* abort */
2604 c->Request.CDB[1] = 0; /* abort a command */
3da8b713 2605 /* buff contains the tag of the command to abort */
2606 memcpy(&c->Request.CDB[4], buff, 8);
2607 break;
8f71bb82 2608 case CCISS_RESET_MSG:
88f627ae 2609 c->Request.CDBLen = 16;
3da8b713 2610 c->Request.Type.Attribute = ATTR_SIMPLE;
88f627ae 2611 c->Request.Type.Direction = XFER_NONE;
3da8b713 2612 c->Request.Timeout = 0;
2613 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
7c832835 2614 c->Request.CDB[0] = cmd; /* reset */
8f71bb82 2615 c->Request.CDB[1] = CCISS_RESET_TYPE_TARGET;
00988a35 2616 break;
8f71bb82 2617 case CCISS_NOOP_MSG:
1da177e4
LT		 2618 c->Request.CDBLen = 1;
2619 c->Request.Type.Attribute = ATTR_SIMPLE;
2620 c->Request.Type.Direction = XFER_WRITE;
2621 c->Request.Timeout = 0;
2622 c->Request.CDB[0] = cmd;
2623 break;
2624 default:
b2a4a43d
SC		 2625 dev_warn(&h->pdev->dev,
2626 "unknown message type %d\n", cmd);
1da177e4
LT		 2627 return IO_ERROR;
2628 }
2629 } else {
b2a4a43d 2630 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
1da177e4
LT		 2631 return IO_ERROR;
2632 }
2633 /* Fill in the scatter gather information */
2634 if (size > 0) {
2635 buff_dma_handle.val = (__u64) pci_map_single(h->pdev,
7c832835
BH		 2636 buff, size,
2637 PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2638 c->SG[0].Addr.lower = buff_dma_handle.val32.lower;
2639 c->SG[0].Addr.upper = buff_dma_handle.val32.upper;
2640 c->SG[0].Len = size;
7c832835 2641 c->SG[0].Ext = 0; /* we are not chaining */
1da177e4
LT		 2642 }
2643 return status;
2644}
7c832835 2645
edc83d47
JA		 2646static int __devinit cciss_send_reset(ctlr_info_t *h, unsigned char *scsi3addr,
2647 u8 reset_type)
2648{
2649 CommandList_struct *c;
2650 int return_status;
2651
2652 c = cmd_alloc(h);
2653 if (!c)
2654 return -ENOMEM;
2655 return_status = fill_cmd(h, c, CCISS_RESET_MSG, NULL, 0, 0,
2656 CTLR_LUNID, TYPE_MSG);
2657 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
2658 if (return_status != IO_OK) {
2659 cmd_special_free(h, c);
2660 return return_status;
2661 }
2662 c->waiting = NULL;
2663 enqueue_cmd_and_start_io(h, c);
2664 /* Don't wait for completion, the reset won't complete. Don't free
2665 * the command either. This is the last command we will send before
2666 * re-initializing everything, so it doesn't matter and won't leak.
2667 */
2668 return 0;
2669}
2670
3c2ab402 2671static int check_target_status(ctlr_info_t *h, CommandList_struct *c)
2672{
2673 switch (c->err_info->ScsiStatus) {
2674 case SAM_STAT_GOOD:
2675 return IO_OK;
2676 case SAM_STAT_CHECK_CONDITION:
2677 switch (0xf & c->err_info->SenseInfo[2]) {
2678 case 0: return IO_OK; /* no sense */
2679 case 1: return IO_OK; /* recovered error */
2680 default:
c08fac65
SC		 2681 if (check_for_unit_attention(h, c))
2682 return IO_NEEDS_RETRY;
b2a4a43d 2683 dev_warn(&h->pdev->dev, "cmd 0x%02x "
3c2ab402 2684 "check condition, sense key = 0x%02x\n",
b2a4a43d 2685 c->Request.CDB[0], c->err_info->SenseInfo[2]);
3c2ab402 2686 }
2687 break;
2688 default:
b2a4a43d
SC		 2689 dev_warn(&h->pdev->dev, "cmd 0x%02x"
2690 "scsi status = 0x%02x\n",
3c2ab402 2691 c->Request.CDB[0], c->err_info->ScsiStatus);
2692 break;
2693 }
2694 return IO_ERROR;
2695}
2696
789a424a 2697static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c)
1da177e4 2698{
5390cfc3 2699 int return_status = IO_OK;
7c832835 2700
789a424a 2701 if (c->err_info->CommandStatus == CMD_SUCCESS)
2702 return IO_OK;
5390cfc3 2703
2704 switch (c->err_info->CommandStatus) {
2705 case CMD_TARGET_STATUS:
3c2ab402 2706 return_status = check_target_status(h, c);
5390cfc3 2707 break;
2708 case CMD_DATA_UNDERRUN:
2709 case CMD_DATA_OVERRUN:
2710 /* expected for inquiry and report lun commands */
2711 break;
2712 case CMD_INVALID:
b2a4a43d 2713 dev_warn(&h->pdev->dev, "cmd 0x%02x is "
5390cfc3 2714 "reported invalid\n", c->Request.CDB[0]);
2715 return_status = IO_ERROR;
2716 break;
2717 case CMD_PROTOCOL_ERR:
b2a4a43d
SC		 2718 dev_warn(&h->pdev->dev, "cmd 0x%02x has "
2719 "protocol error\n", c->Request.CDB[0]);
5390cfc3 2720 return_status = IO_ERROR;
2721 break;
2722 case CMD_HARDWARE_ERR:
b2a4a43d 2723 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
5390cfc3 2724 " hardware error\n", c->Request.CDB[0]);
2725 return_status = IO_ERROR;
2726 break;
2727 case CMD_CONNECTION_LOST:
b2a4a43d 2728 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
5390cfc3 2729 "connection lost\n", c->Request.CDB[0]);
2730 return_status = IO_ERROR;
2731 break;
2732 case CMD_ABORTED:
b2a4a43d 2733 dev_warn(&h->pdev->dev, "cmd 0x%02x was "
5390cfc3 2734 "aborted\n", c->Request.CDB[0]);
2735 return_status = IO_ERROR;
2736 break;
2737 case CMD_ABORT_FAILED:
b2a4a43d 2738 dev_warn(&h->pdev->dev, "cmd 0x%02x reports "
5390cfc3 2739 "abort failed\n", c->Request.CDB[0]);
2740 return_status = IO_ERROR;
2741 break;
2742 case CMD_UNSOLICITED_ABORT:
b2a4a43d 2743 dev_warn(&h->pdev->dev, "unsolicited abort 0x%02x\n",
5390cfc3 2744 c->Request.CDB[0]);
789a424a 2745 return_status = IO_NEEDS_RETRY;
5390cfc3 2746 break;
6d9a4f9e
SC		 2747 case CMD_UNABORTABLE:
2748 dev_warn(&h->pdev->dev, "cmd unabortable\n");
2749 return_status = IO_ERROR;
2750 break;
5390cfc3 2751 default:
b2a4a43d 2752 dev_warn(&h->pdev->dev, "cmd 0x%02x returned "
5390cfc3 2753 "unknown status %x\n", c->Request.CDB[0],
2754 c->err_info->CommandStatus);
2755 return_status = IO_ERROR;
7c832835 2756 }
789a424a 2757 return return_status;
2758}
2759
2760static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
2761 int attempt_retry)
2762{
2763 DECLARE_COMPLETION_ONSTACK(wait);
2764 u64bit buff_dma_handle;
789a424a 2765 int return_status = IO_OK;
2766
2767resend_cmd2:
2768 c->waiting = &wait;
664a717d 2769 enqueue_cmd_and_start_io(h, c);
789a424a 2770
2771 wait_for_completion(&wait);
2772
2773 if (c->err_info->CommandStatus == 0 || !attempt_retry)
2774 goto command_done;
2775
2776 return_status = process_sendcmd_error(h, c);
2777
2778 if (return_status == IO_NEEDS_RETRY &&
2779 c->retry_count < MAX_CMD_RETRIES) {
b2a4a43d 2780 dev_warn(&h->pdev->dev, "retrying 0x%02x\n",
789a424a 2781 c->Request.CDB[0]);
2782 c->retry_count++;
2783 /* erase the old error information */
2784 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
2785 return_status = IO_OK;
2786 INIT_COMPLETION(wait);
2787 goto resend_cmd2;
2788 }
5390cfc3 2789
2790command_done:
1da177e4 2791 /* unlock the buffers from DMA */
bb2a37bf
MM		 2792 buff_dma_handle.val32.lower = c->SG[0].Addr.lower;
2793 buff_dma_handle.val32.upper = c->SG[0].Addr.upper;
7c832835
BH		 2794 pci_unmap_single(h->pdev, (dma_addr_t) buff_dma_handle.val,
2795 c->SG[0].Len, PCI_DMA_BIDIRECTIONAL);
5390cfc3 2796 return return_status;
2797}
2798
f70dba83 2799static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
b57695fe 2800 __u8 page_code, unsigned char scsi3addr[],
2801 int cmd_type)
5390cfc3 2802{
5390cfc3 2803 CommandList_struct *c;
2804 int return_status;
2805
6b4d96b8 2806 c = cmd_special_alloc(h);
5390cfc3 2807 if (!c)
2808 return -ENOMEM;
f70dba83 2809 return_status = fill_cmd(h, c, cmd, buff, size, page_code,
b57695fe 2810 scsi3addr, cmd_type);
5390cfc3 2811 if (return_status == IO_OK)
789a424a 2812 return_status = sendcmd_withirq_core(h, c, 1);
2813
6b4d96b8 2814 cmd_special_free(h, c);
7c832835 2815 return return_status;
1da177e4 2816}
7c832835 2817
f70dba83 2818static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
7b838bde 2819 sector_t total_size,
7c832835
BH		 2820 unsigned int block_size,
2821 InquiryData_struct *inq_buff,
2822 drive_info_struct *drv)
1da177e4
LT		 2823{
2824 int return_code;
00988a35 2825 unsigned long t;
b57695fe 2826 unsigned char scsi3addr[8];
00988a35 2827
1da177e4 2828 memset(inq_buff, 0, sizeof(InquiryData_struct));
f70dba83
SC		 2829 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2830 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
7b838bde 2831 sizeof(*inq_buff), 0xC1, scsi3addr, TYPE_CMD);
1da177e4 2832 if (return_code == IO_OK) {
7c832835 2833 if (inq_buff->data_byte[8] == 0xFF) {
b2a4a43d
SC		 2834 dev_warn(&h->pdev->dev,
2835 "reading geometry failed, volume "
7c832835 2836 "does not support reading geometry\n");
1da177e4 2837 drv->heads = 255;
b028461d 2838 drv->sectors = 32; /* Sectors per track */
7f42d3b8 2839 drv->cylinders = total_size + 1;
89f97ad1 2840 drv->raid_level = RAID_UNKNOWN;
1da177e4 2841 } else {
1da177e4
LT		 2842 drv->heads = inq_buff->data_byte[6];
2843 drv->sectors = inq_buff->data_byte[7];
2844 drv->cylinders = (inq_buff->data_byte[4] & 0xff) << 8;
2845 drv->cylinders += inq_buff->data_byte[5];
2846 drv->raid_level = inq_buff->data_byte[8];
3f7705ea
MW		 2847 }
2848 drv->block_size = block_size;
97c06978 2849 drv->nr_blocks = total_size + 1;
3f7705ea
MW		 2850 t = drv->heads * drv->sectors;
2851 if (t > 1) {
97c06978
MMOD		 2852 sector_t real_size = total_size + 1;
2853 unsigned long rem = sector_div(real_size, t);
3f7705ea 2854 if (rem)
97c06978
MMOD		 2855 real_size++;
2856 drv->cylinders = real_size;
1da177e4 2857 }
7c832835 2858 } else { /* Get geometry failed */
b2a4a43d 2859 dev_warn(&h->pdev->dev, "reading geometry failed\n");
1da177e4 2860 }
1da177e4 2861}
7c832835 2862
1da177e4 2863static void
f70dba83 2864cciss_read_capacity(ctlr_info_t *h, int logvol, sector_t *total_size,
7c832835 2865 unsigned int *block_size)
1da177e4 2866{
00988a35 2867 ReadCapdata_struct *buf;
1da177e4 2868 int return_code;
b57695fe 2869 unsigned char scsi3addr[8];
1aebe187
MK		 2870
2871 buf = kzalloc(sizeof(ReadCapdata_struct), GFP_KERNEL);
2872 if (!buf) {
b2a4a43d 2873 dev_warn(&h->pdev->dev, "out of memory\n");
00988a35
MMOD		 2874 return;
2875 }
1aebe187 2876
f70dba83
SC		 2877 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2878 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY, buf,
7b838bde 2879 sizeof(ReadCapdata_struct), 0, scsi3addr, TYPE_CMD);
1da177e4 2880 if (return_code == IO_OK) {
4c1f2b31
AV		 2881 *total_size = be32_to_cpu(*(__be32 *) buf->total_size);
2882 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
7c832835 2883 } else { /* read capacity command failed */
b2a4a43d 2884 dev_warn(&h->pdev->dev, "read capacity failed\n");
1da177e4
LT		 2885 *total_size = 0;
2886 *block_size = BLOCK_SIZE;
2887 }
00988a35 2888 kfree(buf);
00988a35
MMOD		 2889}
2890
f70dba83 2891static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
7b838bde 2892 sector_t *total_size, unsigned int *block_size)
00988a35
MMOD		 2893{
2894 ReadCapdata_struct_16 *buf;
2895 int return_code;
b57695fe 2896 unsigned char scsi3addr[8];
1aebe187
MK		 2897
2898 buf = kzalloc(sizeof(ReadCapdata_struct_16), GFP_KERNEL);
2899 if (!buf) {
b2a4a43d 2900 dev_warn(&h->pdev->dev, "out of memory\n");
00988a35
MMOD		 2901 return;
2902 }
1aebe187 2903
f70dba83
SC		 2904 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2905 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY_16,
2906 buf, sizeof(ReadCapdata_struct_16),
7b838bde 2907 0, scsi3addr, TYPE_CMD);
00988a35 2908 if (return_code == IO_OK) {
4c1f2b31
AV		 2909 *total_size = be64_to_cpu(*(__be64 *) buf->total_size);
2910 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
00988a35 2911 } else { /* read capacity command failed */
b2a4a43d 2912 dev_warn(&h->pdev->dev, "read capacity failed\n");
00988a35
MMOD		 2913 *total_size = 0;
2914 *block_size = BLOCK_SIZE;
2915 }
b2a4a43d 2916 dev_info(&h->pdev->dev, " blocks= %llu block_size= %d\n",
97c06978 2917 (unsigned long long)*total_size+1, *block_size);
00988a35 2918 kfree(buf);
1da177e4
LT		 2919}
2920
1da177e4
LT		 2921static int cciss_revalidate(struct gendisk *disk)
2922{
2923 ctlr_info_t *h = get_host(disk);
2924 drive_info_struct *drv = get_drv(disk);
2925 int logvol;
7c832835 2926 int FOUND = 0;
1da177e4 2927 unsigned int block_size;
00988a35 2928 sector_t total_size;
1da177e4
LT		 2929 InquiryData_struct *inq_buff = NULL;
2930
68264e9d 2931 for (logvol = 0; logvol <= h->highest_lun; logvol++) {
0fc13c89 2932 if (!h->drv[logvol])
453434cf 2933 continue;
9cef0d2f 2934 if (memcmp(h->drv[logvol]->LunID, drv->LunID,
39ccf9a6 2935 sizeof(drv->LunID)) == 0) {
7c832835 2936 FOUND = 1;
1da177e4
LT		 2937 break;
2938 }
2939 }
2940
7c832835
BH		 2941 if (!FOUND)
2942 return 1;
1da177e4 2943
7c832835
BH		 2944 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
2945 if (inq_buff == NULL) {
b2a4a43d 2946 dev_warn(&h->pdev->dev, "out of memory\n");
7c832835
BH		 2947 return 1;
2948 }
00988a35 2949 if (h->cciss_read == CCISS_READ_10) {
f70dba83 2950 cciss_read_capacity(h, logvol,
00988a35
MMOD		 2951 &total_size, &block_size);
2952 } else {
f70dba83 2953 cciss_read_capacity_16(h, logvol,
00988a35
MMOD		 2954 &total_size, &block_size);
2955 }
f70dba83 2956 cciss_geometry_inquiry(h, logvol, total_size, block_size,
7c832835 2957 inq_buff, drv);
1da177e4 2958
e1defc4f 2959 blk_queue_logical_block_size(drv->queue, drv->block_size);
1da177e4
LT		 2960 set_capacity(disk, drv->nr_blocks);
2961
1da177e4
LT		 2962 kfree(inq_buff);
2963 return 0;
2964}
2965
1da177e4
LT		 2966/*
2967 * Map (physical) PCI mem into (virtual) kernel space
2968 */
2969static void __iomem *remap_pci_mem(ulong base, ulong size)
2970{
7c832835
BH		 2971 ulong page_base = ((ulong) base) & PAGE_MASK;
2972 ulong page_offs = ((ulong) base) - page_base;
2973 void __iomem *page_remapped = ioremap(page_base, page_offs + size);
1da177e4 2974
7c832835 2975 return page_remapped ? (page_remapped + page_offs) : NULL;
1da177e4
LT		 2976}
2977
7c832835
BH		 2978/*
2979 * Takes jobs of the Q and sends them to the hardware, then puts it on
2980 * the Q to wait for completion.
2981 */
2982static void start_io(ctlr_info_t *h)
1da177e4
LT		 2983{
2984 CommandList_struct *c;
7c832835 2985
e6e1ee93
JA		 2986 while (!list_empty(&h->reqQ)) {
2987 c = list_entry(h->reqQ.next, CommandList_struct, list);
1da177e4
LT		 2988 /* can't do anything if fifo is full */
2989 if ((h->access.fifo_full(h))) {
b2a4a43d 2990 dev_warn(&h->pdev->dev, "fifo full\n");
1da177e4
LT		 2991 break;
2992 }
2993
7c832835 2994 /* Get the first entry from the Request Q */
8a3173de 2995 removeQ(c);
1da177e4 2996 h->Qdepth--;
7c832835
BH		 2997
2998 /* Tell the controller execute command */
1da177e4 2999 h->access.submit_command(h, c);
7c832835
BH		 3000
3001 /* Put job onto the completed Q */
8a3173de 3002 addQ(&h->cmpQ, c);
1da177e4
LT		 3003 }
3004}
7c832835 3005
f70dba83 3006/* Assumes that h->lock is held. */
1da177e4
LT		 3007/* Zeros out the error record and then resends the command back */
3008/* to the controller */
7c832835 3009static inline void resend_cciss_cmd(ctlr_info_t *h, CommandList_struct *c)
1da177e4
LT		 3010{
3011 /* erase the old error information */
3012 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
3013
3014 /* add it to software queue and then send it to the controller */
8a3173de 3015 addQ(&h->reqQ, c);
1da177e4 3016 h->Qdepth++;
7c832835 3017 if (h->Qdepth > h->maxQsinceinit)
1da177e4
LT		 3018 h->maxQsinceinit = h->Qdepth;
3019
3020 start_io(h);
3021}
a9925a06 3022
1a614f50
SC		 3023static inline unsigned int make_status_bytes(unsigned int scsi_status_byte,
3024 unsigned int msg_byte, unsigned int host_byte,
3025 unsigned int driver_byte)
3026{
3027 /* inverse of macros in scsi.h */
3028 return (scsi_status_byte & 0xff) |
3029 ((msg_byte & 0xff) << 8) |
3030 ((host_byte & 0xff) << 16) |
3031 ((driver_byte & 0xff) << 24);
3032}
3033
0a9279cc
MM		 3034static inline int evaluate_target_status(ctlr_info_t *h,
3035 CommandList_struct *cmd, int *retry_cmd)
03bbfee5
MMOD		 3036{
3037 unsigned char sense_key;
1a614f50
SC		 3038 unsigned char status_byte, msg_byte, host_byte, driver_byte;
3039 int error_value;
3040
0a9279cc 3041 *retry_cmd = 0;
1a614f50
SC		 3042 /* If we get in here, it means we got "target status", that is, scsi status */
3043 status_byte = cmd->err_info->ScsiStatus;
3044 driver_byte = DRIVER_OK;
3045 msg_byte = cmd->err_info->CommandStatus; /* correct? seems too device specific */
3046
33659ebb 3047 if (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC)
1a614f50
SC		 3048 host_byte = DID_PASSTHROUGH;
3049 else
3050 host_byte = DID_OK;
3051
3052 error_value = make_status_bytes(status_byte, msg_byte,
3053 host_byte, driver_byte);
03bbfee5 3054
1a614f50 3055 if (cmd->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) {
33659ebb 3056 if (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC)
b2a4a43d 3057 dev_warn(&h->pdev->dev, "cmd %p "
03bbfee5
MMOD		 3058 "has SCSI Status 0x%x\n",
3059 cmd, cmd->err_info->ScsiStatus);
1a614f50 3060 return error_value;
03bbfee5
MMOD		 3061 }
3062
3063 /* check the sense key */
3064 sense_key = 0xf & cmd->err_info->SenseInfo[2];
3065 /* no status or recovered error */
33659ebb
CH		 3066 if (((sense_key == 0x0) || (sense_key == 0x1)) &&
3067 (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC))
1a614f50 3068 error_value = 0;
03bbfee5 3069
0a9279cc 3070 if (check_for_unit_attention(h, cmd)) {
33659ebb 3071 *retry_cmd = !(cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC);
0a9279cc
MM		 3072 return 0;
3073 }
3074
33659ebb
CH		 3075 /* Not SG_IO or similar? */
3076 if (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC) {
1a614f50 3077 if (error_value != 0)
b2a4a43d 3078 dev_warn(&h->pdev->dev, "cmd %p has CHECK CONDITION"
03bbfee5 3079 " sense key = 0x%x\n", cmd, sense_key);
1a614f50 3080 return error_value;
03bbfee5
MMOD		 3081 }
3082
3083 /* SG_IO or similar, copy sense data back */
3084 if (cmd->rq->sense) {
3085 if (cmd->rq->sense_len > cmd->err_info->SenseLen)
3086 cmd->rq->sense_len = cmd->err_info->SenseLen;
3087 memcpy(cmd->rq->sense, cmd->err_info->SenseInfo,
3088 cmd->rq->sense_len);
3089 } else
3090 cmd->rq->sense_len = 0;
3091
1a614f50 3092 return error_value;
03bbfee5
MMOD		 3093}
3094
7c832835 3095/* checks the status of the job and calls complete buffers to mark all
a9925a06
JA		 3096 * buffers for the completed job. Note that this function does not need
3097 * to hold the hba/queue lock.
7c832835
BH		 3098 */
3099static inline void complete_command(ctlr_info_t *h, CommandList_struct *cmd,
3100 int timeout)
1da177e4 3101{
1da177e4 3102 int retry_cmd = 0;
198b7660
MMOD		 3103 struct request *rq = cmd->rq;
3104
3105 rq->errors = 0;
7c832835 3106
1da177e4 3107 if (timeout)
1a614f50 3108 rq->errors = make_status_bytes(0, 0, 0, DRIVER_TIMEOUT);
1da177e4 3109
d38ae168
MMOD		 3110 if (cmd->err_info->CommandStatus == 0) /* no error has occurred */
3111 goto after_error_processing;
7c832835 3112
d38ae168 3113 switch (cmd->err_info->CommandStatus) {
d38ae168 3114 case CMD_TARGET_STATUS:
0a9279cc 3115 rq->errors = evaluate_target_status(h, cmd, &retry_cmd);
d38ae168
MMOD		 3116 break;
3117 case CMD_DATA_UNDERRUN:
33659ebb 3118 if (cmd->rq->cmd_type == REQ_TYPE_FS) {
b2a4a43d 3119 dev_warn(&h->pdev->dev, "cmd %p has"
03bbfee5
MMOD		 3120 " completed with data underrun "
3121 "reported\n", cmd);
c3a4d78c 3122 cmd->rq->resid_len = cmd->err_info->ResidualCnt;
03bbfee5 3123 }
d38ae168
MMOD		 3124 break;
3125 case CMD_DATA_OVERRUN:
33659ebb 3126 if (cmd->rq->cmd_type == REQ_TYPE_FS)
b2a4a43d 3127 dev_warn(&h->pdev->dev, "cciss: cmd %p has"
03bbfee5
MMOD		 3128 " completed with data overrun "
3129 "reported\n", cmd);
d38ae168
MMOD		 3130 break;
3131 case CMD_INVALID:
b2a4a43d 3132 dev_warn(&h->pdev->dev, "cciss: cmd %p is "
d38ae168 3133 "reported invalid\n", cmd);
1a614f50
SC		 3134 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3135 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3136 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3137 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3138 break;
3139 case CMD_PROTOCOL_ERR:
b2a4a43d
SC		 3140 dev_warn(&h->pdev->dev, "cciss: cmd %p has "
3141 "protocol error\n", cmd);
1a614f50
SC		 3142 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3143 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3144 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3145 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3146 break;
3147 case CMD_HARDWARE_ERR:
b2a4a43d 3148 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
d38ae168 3149 " hardware error\n", cmd);
1a614f50
SC		 3150 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3151 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3152 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3153 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3154 break;
3155 case CMD_CONNECTION_LOST:
b2a4a43d 3156 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
d38ae168 3157 "connection lost\n", cmd);
1a614f50
SC		 3158 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3159 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3160 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3161 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3162 break;
3163 case CMD_ABORTED:
b2a4a43d 3164 dev_warn(&h->pdev->dev, "cciss: cmd %p was "
d38ae168 3165 "aborted\n", cmd);
1a614f50
SC		 3166 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3167 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3168 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3169 DID_PASSTHROUGH : DID_ABORT);
d38ae168
MMOD		 3170 break;
3171 case CMD_ABORT_FAILED:
b2a4a43d 3172 dev_warn(&h->pdev->dev, "cciss: cmd %p reports "
d38ae168 3173 "abort failed\n", cmd);
1a614f50
SC		 3174 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3175 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3176 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3177 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3178 break;
3179 case CMD_UNSOLICITED_ABORT:
b2a4a43d 3180 dev_warn(&h->pdev->dev, "cciss%d: unsolicited "
d38ae168
MMOD		 3181 "abort %p\n", h->ctlr, cmd);
3182 if (cmd->retry_count < MAX_CMD_RETRIES) {
3183 retry_cmd = 1;
b2a4a43d 3184 dev_warn(&h->pdev->dev, "retrying %p\n", cmd);
d38ae168
MMOD		 3185 cmd->retry_count++;
3186 } else
b2a4a43d
SC		 3187 dev_warn(&h->pdev->dev,
3188 "%p retried too many times\n", cmd);
1a614f50
SC		 3189 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3190 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3191 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3192 DID_PASSTHROUGH : DID_ABORT);
d38ae168
MMOD		 3193 break;
3194 case CMD_TIMEOUT:
b2a4a43d 3195 dev_warn(&h->pdev->dev, "cmd %p timedout\n", cmd);
1a614f50
SC		 3196 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3197 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3198 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3199 DID_PASSTHROUGH : DID_ERROR);
d38ae168 3200 break;
6d9a4f9e
SC		 3201 case CMD_UNABORTABLE:
3202 dev_warn(&h->pdev->dev, "cmd %p unabortable\n", cmd);
3203 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3204 cmd->err_info->CommandStatus, DRIVER_OK,
3205 cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC ?
3206 DID_PASSTHROUGH : DID_ERROR);
3207 break;
d38ae168 3208 default:
b2a4a43d 3209 dev_warn(&h->pdev->dev, "cmd %p returned "
d38ae168
MMOD		 3210 "unknown status %x\n", cmd,
3211 cmd->err_info->CommandStatus);
1a614f50
SC		 3212 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3213 cmd->err_info->CommandStatus, DRIVER_OK,
33659ebb
CH		 3214 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3215 DID_PASSTHROUGH : DID_ERROR);
1da177e4 3216 }
d38ae168
MMOD		 3217
3218after_error_processing:
3219
1da177e4 3220 /* We need to return this command */
7c832835
BH		 3221 if (retry_cmd) {
3222 resend_cciss_cmd(h, cmd);
1da177e4 3223 return;
7c832835 3224 }
03bbfee5 3225 cmd->rq->completion_data = cmd;
a9925a06 3226 blk_complete_request(cmd->rq);
1da177e4
LT		 3227}
3228
0c2b3908
MM		 3229static inline u32 cciss_tag_contains_index(u32 tag)
3230{
5e216153 3231#define DIRECT_LOOKUP_BIT 0x10
0c2b3908
MM		 3232 return tag & DIRECT_LOOKUP_BIT;
3233}
3234
3235static inline u32 cciss_tag_to_index(u32 tag)
3236{
5e216153 3237#define DIRECT_LOOKUP_SHIFT 5
0c2b3908
MM		 3238 return tag >> DIRECT_LOOKUP_SHIFT;
3239}
3240
0498cc2a 3241static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag)
0c2b3908 3242{
0498cc2a
SC		 3243#define CCISS_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
3244#define CCISS_SIMPLE_ERROR_BITS 0x03
3245 if (likely(h->transMethod & CFGTBL_Trans_Performant))
3246 return tag & ~CCISS_PERF_ERROR_BITS;
3247 return tag & ~CCISS_SIMPLE_ERROR_BITS;
0c2b3908
MM		 3248}
3249
3250static inline void cciss_mark_tag_indexed(u32 *tag)
3251{
3252 *tag |= DIRECT_LOOKUP_BIT;
3253}
3254
3255static inline void cciss_set_tag_index(u32 *tag, u32 index)
3256{
3257 *tag |= (index << DIRECT_LOOKUP_SHIFT);
3258}
3259
7c832835
BH		 3260/*
3261 * Get a request and submit it to the controller.
1da177e4 3262 */
165125e1 3263static void do_cciss_request(struct request_queue *q)
1da177e4 3264{
7c832835 3265 ctlr_info_t *h = q->queuedata;
1da177e4 3266 CommandList_struct *c;
00988a35
MMOD		 3267 sector_t start_blk;
3268 int seg;
1da177e4
LT		 3269 struct request *creq;
3270 u64bit temp64;
5c07a311
DB		 3271 struct scatterlist *tmp_sg;
3272 SGDescriptor_struct *curr_sg;
1da177e4
LT		 3273 drive_info_struct *drv;
3274 int i, dir;
5c07a311
DB		 3275 int sg_index = 0;
3276 int chained = 0;
1da177e4 3277
7c832835 3278 queue:
9934c8c0 3279 creq = blk_peek_request(q);
1da177e4
LT		 3280 if (!creq)
3281 goto startio;
3282
5c07a311 3283 BUG_ON(creq->nr_phys_segments > h->maxsgentries);
1da177e4 3284
6b4d96b8
SC		 3285 c = cmd_alloc(h);
3286 if (!c)
1da177e4
LT		 3287 goto full;
3288
9934c8c0 3289 blk_start_request(creq);
1da177e4 3290
5c07a311 3291 tmp_sg = h->scatter_list[c->cmdindex];
1da177e4
LT		 3292 spin_unlock_irq(q->queue_lock);
3293
3294 c->cmd_type = CMD_RWREQ;
3295 c->rq = creq;
7c832835
BH		 3296
3297 /* fill in the request */
1da177e4 3298 drv = creq->rq_disk->private_data;
b028461d 3299 c->Header.ReplyQueue = 0; /* unused in simple mode */
33079b21
MM		 3300 /* got command from pool, so use the command block index instead */
3301 /* for direct lookups. */
3302 /* The first 2 bits are reserved for controller error reporting. */
0c2b3908
MM		 3303 cciss_set_tag_index(&c->Header.Tag.lower, c->cmdindex);
3304 cciss_mark_tag_indexed(&c->Header.Tag.lower);
39ccf9a6 3305 memcpy(&c->Header.LUN, drv->LunID, sizeof(drv->LunID));
b028461d 3306 c->Request.CDBLen = 10; /* 12 byte commands not in FW yet; */
3307 c->Request.Type.Type = TYPE_CMD; /* It is a command. */
7c832835
BH		 3308 c->Request.Type.Attribute = ATTR_SIMPLE;
3309 c->Request.Type.Direction =
a52de245 3310 (rq_data_dir(creq) == READ) ? XFER_READ : XFER_WRITE;
b028461d 3311 c->Request.Timeout = 0; /* Don't time out */
7c832835 3312 c->Request.CDB[0] =
00988a35 3313 (rq_data_dir(creq) == READ) ? h->cciss_read : h->cciss_write;
83096ebf 3314 start_blk = blk_rq_pos(creq);
b2a4a43d 3315 dev_dbg(&h->pdev->dev, "sector =%d nr_sectors=%d\n",
83096ebf 3316 (int)blk_rq_pos(creq), (int)blk_rq_sectors(creq));
5c07a311 3317 sg_init_table(tmp_sg, h->maxsgentries);
1da177e4
LT		 3318 seg = blk_rq_map_sg(q, creq, tmp_sg);
3319
7c832835 3320 /* get the DMA records for the setup */
1da177e4
LT		 3321 if (c->Request.Type.Direction == XFER_READ)
3322 dir = PCI_DMA_FROMDEVICE;
3323 else
3324 dir = PCI_DMA_TODEVICE;
3325
5c07a311
DB		 3326 curr_sg = c->SG;
3327 sg_index = 0;
3328 chained = 0;
3329
7c832835 3330 for (i = 0; i < seg; i++) {
5c07a311
DB		 3331 if (((sg_index+1) == (h->max_cmd_sgentries)) &&
3332 !chained && ((seg - i) > 1)) {
5c07a311 3333 /* Point to next chain block. */
dccc9b56 3334 curr_sg = h->cmd_sg_list[c->cmdindex];
5c07a311
DB		 3335 sg_index = 0;
3336 chained = 1;
3337 }
3338 curr_sg[sg_index].Len = tmp_sg[i].length;
45711f1a 3339 temp64.val = (__u64) pci_map_page(h->pdev, sg_page(&tmp_sg[i]),
5c07a311
DB		 3340 tmp_sg[i].offset,
3341 tmp_sg[i].length, dir);
3342 curr_sg[sg_index].Addr.lower = temp64.val32.lower;
3343 curr_sg[sg_index].Addr.upper = temp64.val32.upper;
3344 curr_sg[sg_index].Ext = 0; /* we are not chaining */
5c07a311 3345 ++sg_index;
1da177e4 3346 }
d45033ef
SC		 3347 if (chained)
3348 cciss_map_sg_chain_block(h, c, h->cmd_sg_list[c->cmdindex],
3349 (seg - (h->max_cmd_sgentries - 1)) *
3350 sizeof(SGDescriptor_struct));
5c07a311 3351
7c832835
BH		 3352 /* track how many SG entries we are using */
3353 if (seg > h->maxSG)
3354 h->maxSG = seg;
1da177e4 3355
b2a4a43d 3356 dev_dbg(&h->pdev->dev, "Submitting %u sectors in %d segments "
5c07a311
DB		 3357 "chained[%d]\n",
3358 blk_rq_sectors(creq), seg, chained);
1da177e4 3359
5e216153
MM		 3360 c->Header.SGTotal = seg + chained;
3361 if (seg <= h->max_cmd_sgentries)
3362 c->Header.SGList = c->Header.SGTotal;
3363 else
5c07a311 3364 c->Header.SGList = h->max_cmd_sgentries;
5e216153 3365 set_performant_mode(h, c);
5c07a311 3366
33659ebb 3367 if (likely(creq->cmd_type == REQ_TYPE_FS)) {
03bbfee5
MMOD		 3368 if(h->cciss_read == CCISS_READ_10) {
3369 c->Request.CDB[1] = 0;
b028461d 3370 c->Request.CDB[2] = (start_blk >> 24) & 0xff; /* MSB */
03bbfee5
MMOD		 3371 c->Request.CDB[3] = (start_blk >> 16) & 0xff;
3372 c->Request.CDB[4] = (start_blk >> 8) & 0xff;
3373 c->Request.CDB[5] = start_blk & 0xff;
b028461d 3374 c->Request.CDB[6] = 0; /* (sect >> 24) & 0xff; MSB */
83096ebf
TH		 3375 c->Request.CDB[7] = (blk_rq_sectors(creq) >> 8) & 0xff;
3376 c->Request.CDB[8] = blk_rq_sectors(creq) & 0xff;
03bbfee5
MMOD		 3377 c->Request.CDB[9] = c->Request.CDB[11] = c->Request.CDB[12] = 0;
3378 } else {
582539e5
RD		 3379 u32 upper32 = upper_32_bits(start_blk);
3380
03bbfee5
MMOD		 3381 c->Request.CDBLen = 16;
3382 c->Request.CDB[1]= 0;
b028461d 3383 c->Request.CDB[2]= (upper32 >> 24) & 0xff; /* MSB */
582539e5
RD		 3384 c->Request.CDB[3]= (upper32 >> 16) & 0xff;
3385 c->Request.CDB[4]= (upper32 >> 8) & 0xff;
3386 c->Request.CDB[5]= upper32 & 0xff;
03bbfee5
MMOD		 3387 c->Request.CDB[6]= (start_blk >> 24) & 0xff;
3388 c->Request.CDB[7]= (start_blk >> 16) & 0xff;
3389 c->Request.CDB[8]= (start_blk >> 8) & 0xff;
3390 c->Request.CDB[9]= start_blk & 0xff;
83096ebf
TH		 3391 c->Request.CDB[10]= (blk_rq_sectors(creq) >> 24) & 0xff;
3392 c->Request.CDB[11]= (blk_rq_sectors(creq) >> 16) & 0xff;
3393 c->Request.CDB[12]= (blk_rq_sectors(creq) >> 8) & 0xff;
3394 c->Request.CDB[13]= blk_rq_sectors(creq) & 0xff;
03bbfee5
MMOD		 3395 c->Request.CDB[14] = c->Request.CDB[15] = 0;
3396 }
33659ebb 3397 } else if (creq->cmd_type == REQ_TYPE_BLOCK_PC) {
03bbfee5
MMOD		 3398 c->Request.CDBLen = creq->cmd_len;
3399 memcpy(c->Request.CDB, creq->cmd, BLK_MAX_CDB);
00988a35 3400 } else {
b2a4a43d
SC		 3401 dev_warn(&h->pdev->dev, "bad request type %d\n",
3402 creq->cmd_type);
03bbfee5 3403 BUG();
00988a35 3404 }
1da177e4
LT		 3405
3406 spin_lock_irq(q->queue_lock);
3407
8a3173de 3408 addQ(&h->reqQ, c);
1da177e4 3409 h->Qdepth++;
7c832835
BH		 3410 if (h->Qdepth > h->maxQsinceinit)
3411 h->maxQsinceinit = h->Qdepth;
1da177e4
LT		 3412
3413 goto queue;
00988a35 3414full:
1da177e4 3415 blk_stop_queue(q);
00988a35 3416startio:
1da177e4
LT		 3417 /* We will already have the driver lock here so not need
3418 * to lock it.
7c832835 3419 */
1da177e4
LT		 3420 start_io(h);
3421}
3422
3da8b713 3423static inline unsigned long get_next_completion(ctlr_info_t *h)
3424{
3da8b713 3425 return h->access.command_completed(h);
3da8b713 3426}
3427
3428static inline int interrupt_pending(ctlr_info_t *h)
3429{
3da8b713 3430 return h->access.intr_pending(h);
3da8b713 3431}
3432
3433static inline long interrupt_not_for_us(ctlr_info_t *h)
3434{
81125860 3435 return ((h->access.intr_pending(h) == 0) ||
2cf3af1c 3436 (h->interrupts_enabled == 0));
3da8b713 3437}
3438
0c2b3908
MM		 3439static inline int bad_tag(ctlr_info_t *h, u32 tag_index,
3440 u32 raw_tag)
1da177e4 3441{
0c2b3908
MM		 3442 if (unlikely(tag_index >= h->nr_cmds)) {
3443 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
3444 return 1;
3445 }
3446 return 0;
3447}
3448
3449static inline void finish_cmd(ctlr_info_t *h, CommandList_struct *c,
3450 u32 raw_tag)
3451{
3452 removeQ(c);
3453 if (likely(c->cmd_type == CMD_RWREQ))
3454 complete_command(h, c, 0);
3455 else if (c->cmd_type == CMD_IOCTL_PEND)
3456 complete(c->waiting);
3457#ifdef CONFIG_CISS_SCSI_TAPE
3458 else if (c->cmd_type == CMD_SCSI)
3459 complete_scsi_command(c, 0, raw_tag);
3460#endif
3461}
3462
29979a71
MM		 3463static inline u32 next_command(ctlr_info_t *h)
3464{
3465 u32 a;
3466
0498cc2a 3467 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
29979a71
MM		 3468 return h->access.command_completed(h);
3469
3470 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
3471 a = *(h->reply_pool_head); /* Next cmd in ring buffer */
3472 (h->reply_pool_head)++;
3473 h->commands_outstanding--;
3474 } else {
3475 a = FIFO_EMPTY;
3476 }
3477 /* Check for wraparound */
3478 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
3479 h->reply_pool_head = h->reply_pool;
3480 h->reply_pool_wraparound ^= 1;
3481 }
3482 return a;
3483}
3484
0c2b3908
MM		 3485/* process completion of an indexed ("direct lookup") command */
3486static inline u32 process_indexed_cmd(ctlr_info_t *h, u32 raw_tag)
3487{
3488 u32 tag_index;
1da177e4 3489 CommandList_struct *c;
0c2b3908
MM		 3490
3491 tag_index = cciss_tag_to_index(raw_tag);
3492 if (bad_tag(h, tag_index, raw_tag))
5e216153 3493 return next_command(h);
0c2b3908
MM		 3494 c = h->cmd_pool + tag_index;
3495 finish_cmd(h, c, raw_tag);
5e216153 3496 return next_command(h);
0c2b3908
MM		 3497}
3498
3499/* process completion of a non-indexed command */
3500static inline u32 process_nonindexed_cmd(ctlr_info_t *h, u32 raw_tag)
3501{
0c2b3908 3502 CommandList_struct *c = NULL;
0c2b3908
MM		 3503 __u32 busaddr_masked, tag_masked;
3504
0498cc2a 3505 tag_masked = cciss_tag_discard_error_bits(h, raw_tag);
e6e1ee93 3506 list_for_each_entry(c, &h->cmpQ, list) {
0498cc2a 3507 busaddr_masked = cciss_tag_discard_error_bits(h, c->busaddr);
0c2b3908
MM		 3508 if (busaddr_masked == tag_masked) {
3509 finish_cmd(h, c, raw_tag);
5e216153 3510 return next_command(h);
0c2b3908
MM		 3511 }
3512 }
3513 bad_tag(h, h->nr_cmds + 1, raw_tag);
5e216153 3514 return next_command(h);
0c2b3908
MM		 3515}
3516
5afe2781
SC		 3517/* Some controllers, like p400, will give us one interrupt
3518 * after a soft reset, even if we turned interrupts off.
3519 * Only need to check for this in the cciss_xxx_discard_completions
3520 * functions.
3521 */
3522static int ignore_bogus_interrupt(ctlr_info_t *h)
3523{
3524 if (likely(!reset_devices))
3525 return 0;
3526
3527 if (likely(h->interrupts_enabled))
3528 return 0;
3529
3530 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
3531 "(known firmware bug.) Ignoring.\n");
3532
3533 return 1;
3534}
3535
3536static irqreturn_t cciss_intx_discard_completions(int irq, void *dev_id)
3537{
3538 ctlr_info_t *h = dev_id;
3539 unsigned long flags;
3540 u32 raw_tag;
3541
3542 if (ignore_bogus_interrupt(h))
3543 return IRQ_NONE;
3544
3545 if (interrupt_not_for_us(h))
3546 return IRQ_NONE;
3547 spin_lock_irqsave(&h->lock, flags);
3548 while (interrupt_pending(h)) {
3549 raw_tag = get_next_completion(h);
3550 while (raw_tag != FIFO_EMPTY)
3551 raw_tag = next_command(h);
3552 }
3553 spin_unlock_irqrestore(&h->lock, flags);
3554 return IRQ_HANDLED;
3555}
3556
3557static irqreturn_t cciss_msix_discard_completions(int irq, void *dev_id)
3558{
3559 ctlr_info_t *h = dev_id;
3560 unsigned long flags;
3561 u32 raw_tag;
3562
3563 if (ignore_bogus_interrupt(h))
3564 return IRQ_NONE;
3565
3566 spin_lock_irqsave(&h->lock, flags);
3567 raw_tag = get_next_completion(h);
3568 while (raw_tag != FIFO_EMPTY)
3569 raw_tag = next_command(h);
3570 spin_unlock_irqrestore(&h->lock, flags);
3571 return IRQ_HANDLED;
3572}
3573
0c2b3908
MM		 3574static irqreturn_t do_cciss_intx(int irq, void *dev_id)
3575{
3576 ctlr_info_t *h = dev_id;
1da177e4 3577 unsigned long flags;
0c2b3908 3578 u32 raw_tag;
1da177e4 3579
3da8b713 3580 if (interrupt_not_for_us(h))
1da177e4 3581 return IRQ_NONE;
f70dba83 3582 spin_lock_irqsave(&h->lock, flags);
3da8b713 3583 while (interrupt_pending(h)) {
0c2b3908
MM		 3584 raw_tag = get_next_completion(h);
3585 while (raw_tag != FIFO_EMPTY) {
3586 if (cciss_tag_contains_index(raw_tag))
3587 raw_tag = process_indexed_cmd(h, raw_tag);
3588 else
3589 raw_tag = process_nonindexed_cmd(h, raw_tag);
1da177e4
LT		 3590 }
3591 }
f70dba83 3592 spin_unlock_irqrestore(&h->lock, flags);
0c2b3908
MM		 3593 return IRQ_HANDLED;
3594}
1da177e4 3595
0c2b3908
MM		 3596/* Add a second interrupt handler for MSI/MSI-X mode. In this mode we never
3597 * check the interrupt pending register because it is not set.
3598 */
3599static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id)
3600{
3601 ctlr_info_t *h = dev_id;
3602 unsigned long flags;
3603 u32 raw_tag;
8a3173de 3604
f70dba83 3605 spin_lock_irqsave(&h->lock, flags);
0c2b3908
MM		 3606 raw_tag = get_next_completion(h);
3607 while (raw_tag != FIFO_EMPTY) {
3608 if (cciss_tag_contains_index(raw_tag))
3609 raw_tag = process_indexed_cmd(h, raw_tag);
3610 else
3611 raw_tag = process_nonindexed_cmd(h, raw_tag);
1da177e4 3612 }
f70dba83 3613 spin_unlock_irqrestore(&h->lock, flags);
1da177e4
LT		 3614 return IRQ_HANDLED;
3615}
7c832835 3616
b368c9dd
AP		 3617/**
3618 * add_to_scan_list() - add controller to rescan queue
3619 * @h: Pointer to the controller.
3620 *
3621 * Adds the controller to the rescan queue if not already on the queue.
3622 *
3623 * returns 1 if added to the queue, 0 if skipped (could be on the
3624 * queue already, or the controller could be initializing or shutting
3625 * down).
3626 **/
3627static int add_to_scan_list(struct ctlr_info *h)
3628{
3629 struct ctlr_info *test_h;
3630 int found = 0;
3631 int ret = 0;
3632
3633 if (h->busy_initializing)
3634 return 0;
3635
3636 if (!mutex_trylock(&h->busy_shutting_down))
3637 return 0;
3638
3639 mutex_lock(&scan_mutex);
3640 list_for_each_entry(test_h, &scan_q, scan_list) {
3641 if (test_h == h) {
3642 found = 1;
3643 break;
3644 }
3645 }
3646 if (!found && !h->busy_scanning) {
3647 INIT_COMPLETION(h->scan_wait);
3648 list_add_tail(&h->scan_list, &scan_q);
3649 ret = 1;
3650 }
3651 mutex_unlock(&scan_mutex);
3652 mutex_unlock(&h->busy_shutting_down);
3653
3654 return ret;
3655}
3656
3657/**
3658 * remove_from_scan_list() - remove controller from rescan queue
3659 * @h: Pointer to the controller.
3660 *
3661 * Removes the controller from the rescan queue if present. Blocks if
fd8489cf
SC		 3662 * the controller is currently conducting a rescan. The controller
3663 * can be in one of three states:
3664 * 1. Doesn't need a scan
3665 * 2. On the scan list, but not scanning yet (we remove it)
3666 * 3. Busy scanning (and not on the list). In this case we want to wait for
3667 * the scan to complete to make sure the scanning thread for this
3668 * controller is completely idle.
b368c9dd
AP		 3669 **/
3670static void remove_from_scan_list(struct ctlr_info *h)
3671{
3672 struct ctlr_info *test_h, *tmp_h;
b368c9dd
AP		 3673
3674 mutex_lock(&scan_mutex);
3675 list_for_each_entry_safe(test_h, tmp_h, &scan_q, scan_list) {
fd8489cf 3676 if (test_h == h) { /* state 2. */
b368c9dd
AP		 3677 list_del(&h->scan_list);
3678 complete_all(&h->scan_wait);
3679 mutex_unlock(&scan_mutex);
3680 return;
3681 }
3682 }
fd8489cf
SC		 3683 if (h->busy_scanning) { /* state 3. */
3684 mutex_unlock(&scan_mutex);
b368c9dd 3685 wait_for_completion(&h->scan_wait);
fd8489cf
SC		 3686 } else { /* state 1, nothing to do. */
3687 mutex_unlock(&scan_mutex);
3688 }
b368c9dd
AP		 3689}
3690
3691/**
3692 * scan_thread() - kernel thread used to rescan controllers
3693 * @data: Ignored.
3694 *
3695 * A kernel thread used scan for drive topology changes on
3696 * controllers. The thread processes only one controller at a time
3697 * using a queue. Controllers are added to the queue using
3698 * add_to_scan_list() and removed from the queue either after done
3699 * processing or using remove_from_scan_list().
3700 *
3701 * returns 0.
3702 **/
0a9279cc
MM		 3703static int scan_thread(void *data)
3704{
b368c9dd 3705 struct ctlr_info *h;
0a9279cc 3706
b368c9dd
AP		 3707 while (1) {
3708 set_current_state(TASK_INTERRUPTIBLE);
3709 schedule();
0a9279cc
MM		 3710 if (kthread_should_stop())
3711 break;
b368c9dd
AP		 3712
3713 while (1) {
3714 mutex_lock(&scan_mutex);
3715 if (list_empty(&scan_q)) {
3716 mutex_unlock(&scan_mutex);
3717 break;
3718 }
3719
3720 h = list_entry(scan_q.next,
3721 struct ctlr_info,
3722 scan_list);
3723 list_del(&h->scan_list);
3724 h->busy_scanning = 1;
3725 mutex_unlock(&scan_mutex);
3726
d06dfbd2
SC		 3727 rebuild_lun_table(h, 0, 0);
3728 complete_all(&h->scan_wait);
3729 mutex_lock(&scan_mutex);
3730 h->busy_scanning = 0;
3731 mutex_unlock(&scan_mutex);
b368c9dd 3732 }
0a9279cc 3733 }
b368c9dd 3734
0a9279cc
MM		 3735 return 0;
3736}
3737
3738static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c)
3739{
3740 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
3741 return 0;
3742
3743 switch (c->err_info->SenseInfo[12]) {
3744 case STATE_CHANGED:
b2a4a43d
SC		 3745 dev_warn(&h->pdev->dev, "a state change "
3746 "detected, command retried\n");
0a9279cc
MM		 3747 return 1;
3748 break;
3749 case LUN_FAILED:
b2a4a43d
SC		 3750 dev_warn(&h->pdev->dev, "LUN failure "
3751 "detected, action required\n");
0a9279cc
MM		 3752 return 1;
3753 break;
3754 case REPORT_LUNS_CHANGED:
b2a4a43d 3755 dev_warn(&h->pdev->dev, "report LUN data changed\n");
da002184
SC		 3756 /*
3757 * Here, we could call add_to_scan_list and wake up the scan thread,
3758 * except that it's quite likely that we will get more than one
3759 * REPORT_LUNS_CHANGED condition in quick succession, which means
3760 * that those which occur after the first one will likely happen
3761 * *during* the scan_thread's rescan. And the rescan code is not
3762 * robust enough to restart in the middle, undoing what it has already
3763 * done, and it's not clear that it's even possible to do this, since
3764 * part of what it does is notify the block layer, which starts
3765 * doing it's own i/o to read partition tables and so on, and the
3766 * driver doesn't have visibility to know what might need undoing.
3767 * In any event, if possible, it is horribly complicated to get right
3768 * so we just don't do it for now.
3769 *
3770 * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
3771 */
0a9279cc
MM		 3772 return 1;
3773 break;
3774 case POWER_OR_RESET:
b2a4a43d
SC		 3775 dev_warn(&h->pdev->dev,
3776 "a power on or device reset detected\n");
0a9279cc
MM		 3777 return 1;
3778 break;
3779 case UNIT_ATTENTION_CLEARED:
b2a4a43d
SC		 3780 dev_warn(&h->pdev->dev,
3781 "unit attention cleared by another initiator\n");
0a9279cc
MM		 3782 return 1;
3783 break;
3784 default:
b2a4a43d
SC		 3785 dev_warn(&h->pdev->dev, "unknown unit attention detected\n");
3786 return 1;
0a9279cc
MM		 3787 }
3788}
3789
7c832835 3790/*
d14c4ab5 3791 * We cannot read the structure directly, for portability we must use
1da177e4 3792 * the io functions.
7c832835 3793 * This is for debug only.
1da177e4 3794 */
b2a4a43d 3795static void print_cfg_table(ctlr_info_t *h)
1da177e4
LT		 3796{
3797 int i;
3798 char temp_name[17];
b2a4a43d 3799 CfgTable_struct *tb = h->cfgtable;
1da177e4 3800
b2a4a43d
SC		 3801 dev_dbg(&h->pdev->dev, "Controller Configuration information\n");
3802 dev_dbg(&h->pdev->dev, "------------------------------------\n");
7c832835 3803 for (i = 0; i < 4; i++)
1da177e4 3804 temp_name[i] = readb(&(tb->Signature[i]));
7c832835 3805 temp_name[4] = '\0';
b2a4a43d
SC		 3806 dev_dbg(&h->pdev->dev, " Signature = %s\n", temp_name);
3807 dev_dbg(&h->pdev->dev, " Spec Number = %d\n",
3808 readl(&(tb->SpecValence)));
3809 dev_dbg(&h->pdev->dev, " Transport methods supported = 0x%x\n",
7c832835 3810 readl(&(tb->TransportSupport)));
b2a4a43d 3811 dev_dbg(&h->pdev->dev, " Transport methods active = 0x%x\n",
7c832835 3812 readl(&(tb->TransportActive)));
b2a4a43d 3813 dev_dbg(&h->pdev->dev, " Requested transport Method = 0x%x\n",
7c832835 3814 readl(&(tb->HostWrite.TransportRequest)));
b2a4a43d 3815 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Delay = 0x%x\n",
7c832835 3816 readl(&(tb->HostWrite.CoalIntDelay)));
b2a4a43d 3817 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Count = 0x%x\n",
7c832835 3818 readl(&(tb->HostWrite.CoalIntCount)));
b2a4a43d 3819 dev_dbg(&h->pdev->dev, " Max outstanding commands = 0x%d\n",
7c832835 3820 readl(&(tb->CmdsOutMax)));
b2a4a43d
SC		 3821 dev_dbg(&h->pdev->dev, " Bus Types = 0x%x\n",
3822 readl(&(tb->BusTypes)));
7c832835 3823 for (i = 0; i < 16; i++)
1da177e4
LT		 3824 temp_name[i] = readb(&(tb->ServerName[i]));
3825 temp_name[16] = '\0';
b2a4a43d
SC		 3826 dev_dbg(&h->pdev->dev, " Server Name = %s\n", temp_name);
3827 dev_dbg(&h->pdev->dev, " Heartbeat Counter = 0x%x\n\n\n",
3828 readl(&(tb->HeartBeat)));
1da177e4 3829}
1da177e4 3830
7c832835 3831static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
1da177e4
LT		 3832{
3833 int i, offset, mem_type, bar_type;
7c832835 3834 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
1da177e4
LT		 3835 return 0;
3836 offset = 0;
7c832835
BH		 3837 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3838 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
1da177e4
LT		 3839 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
3840 offset += 4;
3841 else {
3842 mem_type = pci_resource_flags(pdev, i) &
7c832835 3843 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1da177e4 3844 switch (mem_type) {
7c832835
BH		 3845 case PCI_BASE_ADDRESS_MEM_TYPE_32:
3846 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
3847 offset += 4; /* 32 bit */
3848 break;
3849 case PCI_BASE_ADDRESS_MEM_TYPE_64:
3850 offset += 8;
3851 break;
3852 default: /* reserved in PCI 2.2 */
b2a4a43d 3853 dev_warn(&pdev->dev,
7c832835
BH		 3854 "Base address is invalid\n");
3855 return -1;
1da177e4
LT		 3856 break;
3857 }
3858 }
7c832835
BH		 3859 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
3860 return i + 1;
1da177e4
LT		 3861 }
3862 return -1;
3863}
3864
5e216153
MM		 3865/* Fill in bucket_map[], given nsgs (the max number of
3866 * scatter gather elements supported) and bucket[],
3867 * which is an array of 8 integers. The bucket[] array
3868 * contains 8 different DMA transfer sizes (in 16
3869 * byte increments) which the controller uses to fetch
3870 * commands. This function fills in bucket_map[], which
3871 * maps a given number of scatter gather elements to one of
3872 * the 8 DMA transfer sizes. The point of it is to allow the
3873 * controller to only do as much DMA as needed to fetch the
3874 * command, with the DMA transfer size encoded in the lower
3875 * bits of the command address.
3876 */
3877static void calc_bucket_map(int bucket[], int num_buckets,
3878 int nsgs, int *bucket_map)
3879{
3880 int i, j, b, size;
3881
3882 /* even a command with 0 SGs requires 4 blocks */
3883#define MINIMUM_TRANSFER_BLOCKS 4
3884#define NUM_BUCKETS 8
3885 /* Note, bucket_map must have nsgs+1 entries. */
3886 for (i = 0; i <= nsgs; i++) {
3887 /* Compute size of a command with i SG entries */
3888 size = i + MINIMUM_TRANSFER_BLOCKS;
3889 b = num_buckets; /* Assume the biggest bucket */
3890 /* Find the bucket that is just big enough */
3891 for (j = 0; j < 8; j++) {
3892 if (bucket[j] >= size) {
3893 b = j;
3894 break;
3895 }
3896 }
3897 /* for a command with i SG entries, use bucket b. */
3898 bucket_map[i] = b;
3899 }
3900}
3901
0f8a6a1e
SC		 3902static void __devinit cciss_wait_for_mode_change_ack(ctlr_info_t *h)
3903{
3904 int i;
3905
3906 /* under certain very rare conditions, this can take awhile.
3907 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
3908 * as we enter this code.) */
3909 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
3910 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
3911 break;
332c2f80 3912 usleep_range(10000, 20000);
0f8a6a1e
SC		 3913 }
3914}
3915
0498cc2a
SC		 3916static __devinit void cciss_enter_performant_mode(ctlr_info_t *h,
3917 u32 use_short_tags)
b9933135
SC		 3918{
3919 /* This is a bit complicated. There are 8 registers on
3920 * the controller which we write to to tell it 8 different
3921 * sizes of commands which there may be. It's a way of
3922 * reducing the DMA done to fetch each command. Encoded into
3923 * each command's tag are 3 bits which communicate to the controller
3924 * which of the eight sizes that command fits within. The size of
3925 * each command depends on how many scatter gather entries there are.
3926 * Each SG entry requires 16 bytes. The eight registers are programmed
3927 * with the number of 16-byte blocks a command of that size requires.
3928 * The smallest command possible requires 5 such 16 byte blocks.
3929 * the largest command possible requires MAXSGENTRIES + 4 16-byte
3930 * blocks. Note, this only extends to the SG entries contained
3931 * within the command block, and does not extend to chained blocks
3932 * of SG elements. bft[] contains the eight values we write to
3933 * the registers. They are not evenly distributed, but have more
3934 * sizes for small commands, and fewer sizes for larger commands.
3935 */
5e216153 3936 __u32 trans_offset;
b9933135 3937 int bft[8] = { 5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
5e216153
MM		 3938 /*
3939 * 5 = 1 s/g entry or 4k
3940 * 6 = 2 s/g entry or 8k
3941 * 8 = 4 s/g entry or 16k
3942 * 10 = 6 s/g entry or 24k
3943 */
5e216153 3944 unsigned long register_value;
5e216153
MM		 3945 BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
3946
5e216153
MM		 3947 h->reply_pool_wraparound = 1; /* spec: init to 1 */
3948
3949 /* Controller spec: zero out this buffer. */
3950 memset(h->reply_pool, 0, h->max_commands * sizeof(__u64));
3951 h->reply_pool_head = h->reply_pool;
3952
3953 trans_offset = readl(&(h->cfgtable->TransMethodOffset));
3954 calc_bucket_map(bft, ARRAY_SIZE(bft), h->maxsgentries,
3955 h->blockFetchTable);
3956 writel(bft[0], &h->transtable->BlockFetch0);
3957 writel(bft[1], &h->transtable->BlockFetch1);
3958 writel(bft[2], &h->transtable->BlockFetch2);
3959 writel(bft[3], &h->transtable->BlockFetch3);
3960 writel(bft[4], &h->transtable->BlockFetch4);
3961 writel(bft[5], &h->transtable->BlockFetch5);
3962 writel(bft[6], &h->transtable->BlockFetch6);
3963 writel(bft[7], &h->transtable->BlockFetch7);
3964
3965 /* size of controller ring buffer */
3966 writel(h->max_commands, &h->transtable->RepQSize);
3967 writel(1, &h->transtable->RepQCount);
3968 writel(0, &h->transtable->RepQCtrAddrLow32);
3969 writel(0, &h->transtable->RepQCtrAddrHigh32);
3970 writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
3971 writel(0, &h->transtable->RepQAddr0High32);
0498cc2a 3972 writel(CFGTBL_Trans_Performant | use_short_tags,
5e216153
MM		 3973 &(h->cfgtable->HostWrite.TransportRequest));
3974
5e216153 3975 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
0f8a6a1e 3976 cciss_wait_for_mode_change_ack(h);
5e216153 3977 register_value = readl(&(h->cfgtable->TransportActive));
b9933135 3978 if (!(register_value & CFGTBL_Trans_Performant))
b2a4a43d 3979 dev_warn(&h->pdev->dev, "cciss: unable to get board into"
5e216153 3980 " performant mode\n");
b9933135
SC		 3981}
3982
3983static void __devinit cciss_put_controller_into_performant_mode(ctlr_info_t *h)
3984{
3985 __u32 trans_support;
3986
3987 dev_dbg(&h->pdev->dev, "Trying to put board into Performant mode\n");
3988 /* Attempt to put controller into performant mode if supported */
3989 /* Does board support performant mode? */
3990 trans_support = readl(&(h->cfgtable->TransportSupport));
3991 if (!(trans_support & PERFORMANT_MODE))
3992 return;
3993
b2a4a43d 3994 dev_dbg(&h->pdev->dev, "Placing controller into performant mode\n");
b9933135
SC		 3995 /* Performant mode demands commands on a 32 byte boundary
3996 * pci_alloc_consistent aligns on page boundarys already.
3997 * Just need to check if divisible by 32
3998 */
3999 if ((sizeof(CommandList_struct) % 32) != 0) {
b2a4a43d 4000 dev_warn(&h->pdev->dev, "%s %d %s\n",
b9933135
SC		 4001 "cciss info: command size[",
4002 (int)sizeof(CommandList_struct),
4003 "] not divisible by 32, no performant mode..\n");
5e216153
MM		 4004 return;
4005 }
4006
b9933135
SC		 4007 /* Performant mode ring buffer and supporting data structures */
4008 h->reply_pool = (__u64 *)pci_alloc_consistent(
4009 h->pdev, h->max_commands * sizeof(__u64),
4010 &(h->reply_pool_dhandle));
4011
4012 /* Need a block fetch table for performant mode */
4013 h->blockFetchTable = kmalloc(((h->maxsgentries+1) *
4014 sizeof(__u32)), GFP_KERNEL);
4015
4016 if ((h->reply_pool == NULL) || (h->blockFetchTable == NULL))
4017 goto clean_up;
4018
0498cc2a
SC		 4019 cciss_enter_performant_mode(h,
4020 trans_support & CFGTBL_Trans_use_short_tags);
b9933135 4021
5e216153
MM		 4022 /* Change the access methods to the performant access methods */
4023 h->access = SA5_performant_access;
b9933135 4024 h->transMethod = CFGTBL_Trans_Performant;
5e216153
MM		 4025
4026 return;
4027clean_up:
4028 kfree(h->blockFetchTable);
4029 if (h->reply_pool)
4030 pci_free_consistent(h->pdev,
4031 h->max_commands * sizeof(__u64),
4032 h->reply_pool,
4033 h->reply_pool_dhandle);
4034 return;
4035
4036} /* cciss_put_controller_into_performant_mode */
4037
fb86a35b
MM		 4038/* If MSI/MSI-X is supported by the kernel we will try to enable it on
4039 * controllers that are capable. If not, we use IO-APIC mode.
4040 */
4041
f70dba83 4042static void __devinit cciss_interrupt_mode(ctlr_info_t *h)
fb86a35b
MM		 4043{
4044#ifdef CONFIG_PCI_MSI
7c832835
BH		 4045 int err;
4046 struct msix_entry cciss_msix_entries[4] = { {0, 0}, {0, 1},
4047 {0, 2}, {0, 3}
4048 };
fb86a35b
MM		 4049
4050 /* Some boards advertise MSI but don't really support it */
f70dba83
SC		 4051 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
4052 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
fb86a35b
MM		 4053 goto default_int_mode;
4054
f70dba83
SC		 4055 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
4056 err = pci_enable_msix(h->pdev, cciss_msix_entries, 4);
7c832835 4057 if (!err) {
f70dba83
SC		 4058 h->intr[0] = cciss_msix_entries[0].vector;
4059 h->intr[1] = cciss_msix_entries[1].vector;
4060 h->intr[2] = cciss_msix_entries[2].vector;
4061 h->intr[3] = cciss_msix_entries[3].vector;
4062 h->msix_vector = 1;
7c832835
BH		 4063 return;
4064 }
4065 if (err > 0) {
b2a4a43d
SC		 4066 dev_warn(&h->pdev->dev,
4067 "only %d MSI-X vectors available\n", err);
1ecb9c0f 4068 goto default_int_mode;
7c832835 4069 } else {
b2a4a43d
SC		 4070 dev_warn(&h->pdev->dev,
4071 "MSI-X init failed %d\n", err);
1ecb9c0f 4072 goto default_int_mode;
7c832835
BH		 4073 }
4074 }
f70dba83
SC		 4075 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
4076 if (!pci_enable_msi(h->pdev))
4077 h->msi_vector = 1;
4078 else
b2a4a43d 4079 dev_warn(&h->pdev->dev, "MSI init failed\n");
7c832835 4080 }
1ecb9c0f 4081default_int_mode:
7c832835 4082#endif /* CONFIG_PCI_MSI */
fb86a35b 4083 /* if we get here we're going to use the default interrupt mode */
f70dba83 4084 h->intr[PERF_MODE_INT] = h->pdev->irq;
fb86a35b
MM		 4085 return;
4086}
4087
6539fa9b 4088static int __devinit cciss_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
1da177e4 4089{
6539fa9b
SC		 4090 int i;
4091 u32 subsystem_vendor_id, subsystem_device_id;
2ec24ff1
SC		 4092
4093 subsystem_vendor_id = pdev->subsystem_vendor;
4094 subsystem_device_id = pdev->subsystem_device;
6539fa9b
SC		 4095 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
4096 subsystem_vendor_id;
2ec24ff1 4097
4205df34 4098 for (i = 0; i < ARRAY_SIZE(products); i++)
6539fa9b
SC		 4099 if (*board_id == products[i].board_id)
4100 return i;
6539fa9b
SC		 4101 dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x, ignoring.\n",
4102 *board_id);
4103 return -ENODEV;
4104}
1da177e4 4105
dd9c426e
SC		 4106static inline bool cciss_board_disabled(ctlr_info_t *h)
4107{
4108 u16 command;
1da177e4 4109
dd9c426e
SC		 4110 (void) pci_read_config_word(h->pdev, PCI_COMMAND, &command);
4111 return ((command & PCI_COMMAND_MEMORY) == 0);
4112}
1da177e4 4113
d474830d
SC		 4114static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,
4115 unsigned long *memory_bar)
4116{
4117 int i;
4e570309 4118
d474830d
SC		 4119 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
4120 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4121 /* addressing mode bits already removed */
4122 *memory_bar = pci_resource_start(pdev, i);
4123 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
4124 *memory_bar);
4125 return 0;
4126 }
4127 dev_warn(&pdev->dev, "no memory BAR found\n");
4128 return -ENODEV;
4129}
1da177e4 4130
afa842fa
SC		 4131static int __devinit cciss_wait_for_board_state(struct pci_dev *pdev,
4132 void __iomem *vaddr, int wait_for_ready)
4133#define BOARD_READY 1
4134#define BOARD_NOT_READY 0
e99ba136 4135{
afa842fa 4136 int i, iterations;
e99ba136 4137 u32 scratchpad;
1da177e4 4138
afa842fa
SC		 4139 if (wait_for_ready)
4140 iterations = CCISS_BOARD_READY_ITERATIONS;
4141 else
4142 iterations = CCISS_BOARD_NOT_READY_ITERATIONS;
4143
4144 for (i = 0; i < iterations; i++) {
4145 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
4146 if (wait_for_ready) {
4147 if (scratchpad == CCISS_FIRMWARE_READY)
4148 return 0;
4149 } else {
4150 if (scratchpad != CCISS_FIRMWARE_READY)
4151 return 0;
4152 }
e99ba136 4153 msleep(CCISS_BOARD_READY_POLL_INTERVAL_MSECS);
e1438581 4154 }
afa842fa 4155 dev_warn(&pdev->dev, "board not ready, timed out.\n");
e99ba136
SC		 4156 return -ENODEV;
4157}
e1438581 4158
8e93bf6d
SC		 4159static int __devinit cciss_find_cfg_addrs(struct pci_dev *pdev,
4160 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
4161 u64 *cfg_offset)
4162{
4163 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
4164 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
4165 *cfg_base_addr &= (u32) 0x0000ffff;
4166 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
4167 if (*cfg_base_addr_index == -1) {
4168 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index, "
4169 "*cfg_base_addr = 0x%08x\n", *cfg_base_addr);
4170 return -ENODEV;
4171 }
4172 return 0;
4173}
1da177e4 4174
4809d098
SC		 4175static int __devinit cciss_find_cfgtables(ctlr_info_t *h)
4176{
4177 u64 cfg_offset;
4178 u32 cfg_base_addr;
4179 u64 cfg_base_addr_index;
4180 u32 trans_offset;
8e93bf6d 4181 int rc;
1da177e4 4182
8e93bf6d
SC		 4183 rc = cciss_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
4184 &cfg_base_addr_index, &cfg_offset);
4185 if (rc)
4186 return rc;
4809d098 4187 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
8e93bf6d 4188 cfg_base_addr_index) + cfg_offset, sizeof(h->cfgtable));
4809d098
SC		 4189 if (!h->cfgtable)
4190 return -ENOMEM;
62710ae1
SC		 4191 rc = write_driver_ver_to_cfgtable(h->cfgtable);
4192 if (rc)
4193 return rc;
4809d098 4194 /* Find performant mode table. */
8e93bf6d 4195 trans_offset = readl(&h->cfgtable->TransMethodOffset);
4809d098
SC		 4196 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
4197 cfg_base_addr_index)+cfg_offset+trans_offset,
4198 sizeof(*h->transtable));
4199 if (!h->transtable)
4200 return -ENOMEM;
4201 return 0;
4202}
1da177e4 4203
adfbc1ff
SC		 4204static void __devinit cciss_get_max_perf_mode_cmds(struct ctlr_info *h)
4205{
4206 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
186fb9cf
SC		 4207
4208 /* Limit commands in memory limited kdump scenario. */
4209 if (reset_devices && h->max_commands > 32)
4210 h->max_commands = 32;
4211
adfbc1ff
SC		 4212 if (h->max_commands < 16) {
4213 dev_warn(&h->pdev->dev, "Controller reports "
4214 "max supported commands of %d, an obvious lie. "
4215 "Using 16. Ensure that firmware is up to date.\n",
4216 h->max_commands);
4217 h->max_commands = 16;
1da177e4 4218 }
adfbc1ff 4219}
1da177e4 4220
afadbf4b
SC		 4221/* Interrogate the hardware for some limits:
4222 * max commands, max SG elements without chaining, and with chaining,
4223 * SG chain block size, etc.
4224 */
4225static void __devinit cciss_find_board_params(ctlr_info_t *h)
4226{
adfbc1ff 4227 cciss_get_max_perf_mode_cmds(h);
8a4ec67b 4228 h->nr_cmds = h->max_commands - 4 - cciss_tape_cmds;
afadbf4b 4229 h->maxsgentries = readl(&(h->cfgtable->MaxSGElements));
5c07a311 4230 /*
afadbf4b 4231 * Limit in-command s/g elements to 32 save dma'able memory.
5c07a311
DB		 4232 * Howvever spec says if 0, use 31
4233 */
afadbf4b
SC		 4234 h->max_cmd_sgentries = 31;
4235 if (h->maxsgentries > 512) {
4236 h->max_cmd_sgentries = 32;
4237 h->chainsize = h->maxsgentries - h->max_cmd_sgentries + 1;
4238 h->maxsgentries--; /* save one for chain pointer */
5c07a311 4239 } else {
afadbf4b
SC		 4240 h->maxsgentries = 31; /* default to traditional values */
4241 h->chainsize = 0;
5c07a311 4242 }
afadbf4b 4243}
5c07a311 4244
501b92cd
SC		 4245static inline bool CISS_signature_present(ctlr_info_t *h)
4246{
4247 if ((readb(&h->cfgtable->Signature[0]) != 'C') ||
4248 (readb(&h->cfgtable->Signature[1]) != 'I') ||
4249 (readb(&h->cfgtable->Signature[2]) != 'S') ||
4250 (readb(&h->cfgtable->Signature[3]) != 'S')) {
4251 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
4252 return false;
1da177e4 4253 }
501b92cd
SC		 4254 return true;
4255}
4256
322e304c
SC		 4257/* Need to enable prefetch in the SCSI core for 6400 in x86 */
4258static inline void cciss_enable_scsi_prefetch(ctlr_info_t *h)
4259{
1da177e4 4260#ifdef CONFIG_X86
322e304c
SC		 4261 u32 prefetch;
4262
4263 prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
4264 prefetch |= 0x100;
4265 writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
1da177e4 4266#endif
322e304c 4267}
1da177e4 4268
bfd63ee5
SC		 4269/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
4270 * in a prefetch beyond physical memory.
4271 */
4272static inline void cciss_p600_dma_prefetch_quirk(ctlr_info_t *h)
4273{
4274 u32 dma_prefetch;
4275 __u32 dma_refetch;
4276
4277 if (h->board_id != 0x3225103C)
4278 return;
4279 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
4280 dma_prefetch |= 0x8000;
4281 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
4282 pci_read_config_dword(h->pdev, PCI_COMMAND_PARITY, &dma_refetch);
4283 dma_refetch |= 0x1;
4284 pci_write_config_dword(h->pdev, PCI_COMMAND_PARITY, dma_refetch);
4285}
4286
f70dba83 4287static int __devinit cciss_pci_init(ctlr_info_t *h)
6539fa9b 4288{
4809d098 4289 int prod_index, err;
6539fa9b 4290
f70dba83 4291 prod_index = cciss_lookup_board_id(h->pdev, &h->board_id);
6539fa9b 4292 if (prod_index < 0)
2ec24ff1 4293 return -ENODEV;
f70dba83
SC		 4294 h->product_name = products[prod_index].product_name;
4295 h->access = *(products[prod_index].access);
1da177e4 4296
f70dba83 4297 if (cciss_board_disabled(h)) {
b2a4a43d 4298 dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
c33ac89b 4299 return -ENODEV;
1da177e4 4300 }
f70dba83 4301 err = pci_enable_device(h->pdev);
7c832835 4302 if (err) {
b2a4a43d 4303 dev_warn(&h->pdev->dev, "Unable to Enable PCI device\n");
c33ac89b 4304 return err;
f92e2f5f
MM		 4305 }
4306
f70dba83 4307 err = pci_request_regions(h->pdev, "cciss");
4e570309 4308 if (err) {
b2a4a43d
SC		 4309 dev_warn(&h->pdev->dev,
4310 "Cannot obtain PCI resources, aborting\n");
872225ca 4311 return err;
4e570309 4312 }
1da177e4 4313
b2a4a43d
SC		 4314 dev_dbg(&h->pdev->dev, "irq = %x\n", h->pdev->irq);
4315 dev_dbg(&h->pdev->dev, "board_id = %x\n", h->board_id);
1da177e4 4316
fb86a35b
MM		 4317/* If the kernel supports MSI/MSI-X we will try to enable that functionality,
4318 * else we use the IO-APIC interrupt assigned to us by system ROM.
4319 */
f70dba83
SC		 4320 cciss_interrupt_mode(h);
4321 err = cciss_pci_find_memory_BAR(h->pdev, &h->paddr);
d474830d 4322 if (err)
e1438581 4323 goto err_out_free_res;
f70dba83
SC		 4324 h->vaddr = remap_pci_mem(h->paddr, 0x250);
4325 if (!h->vaddr) {
da550321
SC		 4326 err = -ENOMEM;
4327 goto err_out_free_res;
7c832835 4328 }
afa842fa 4329 err = cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
e99ba136 4330 if (err)
4e570309 4331 goto err_out_free_res;
f70dba83 4332 err = cciss_find_cfgtables(h);
4809d098 4333 if (err)
4e570309 4334 goto err_out_free_res;
b2a4a43d 4335 print_cfg_table(h);
f70dba83 4336 cciss_find_board_params(h);
1da177e4 4337
f70dba83 4338 if (!CISS_signature_present(h)) {
c33ac89b 4339 err = -ENODEV;
4e570309 4340 goto err_out_free_res;
1da177e4 4341 }
f70dba83
SC		 4342 cciss_enable_scsi_prefetch(h);
4343 cciss_p600_dma_prefetch_quirk(h);
4344 cciss_put_controller_into_performant_mode(h);
1da177e4
LT		 4345 return 0;
4346
5faad620 4347err_out_free_res:
872225ca
MM		 4348 /*
4349 * Deliberately omit pci_disable_device(): it does something nasty to
4350 * Smart Array controllers that pci_enable_device does not undo
4351 */
f70dba83
SC		 4352 if (h->transtable)
4353 iounmap(h->transtable);
4354 if (h->cfgtable)
4355 iounmap(h->cfgtable);
4356 if (h->vaddr)
4357 iounmap(h->vaddr);
4358 pci_release_regions(h->pdev);
c33ac89b 4359 return err;
1da177e4
LT		 4360}
4361
6ae5ce8e
MM		 4362/* Function to find the first free pointer into our hba[] array
4363 * Returns -1 if no free entries are left.
7c832835 4364 */
b2a4a43d 4365static int alloc_cciss_hba(struct pci_dev *pdev)
1da177e4 4366{
799202cb 4367 int i;
1da177e4 4368
7c832835 4369 for (i = 0; i < MAX_CTLR; i++) {
1da177e4 4370 if (!hba[i]) {
f70dba83 4371 ctlr_info_t *h;
f2912a12 4372
f70dba83
SC		 4373 h = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL);
4374 if (!h)
1da177e4 4375 goto Enomem;
f70dba83 4376 hba[i] = h;
1da177e4
LT		 4377 return i;
4378 }
4379 }
b2a4a43d 4380 dev_warn(&pdev->dev, "This driver supports a maximum"
7c832835 4381 " of %d controllers.\n", MAX_CTLR);
799202cb
MM		 4382 return -1;
4383Enomem:
b2a4a43d 4384 dev_warn(&pdev->dev, "out of memory.\n");
1da177e4
LT		 4385 return -1;
4386}
4387
f70dba83 4388static void free_hba(ctlr_info_t *h)
1da177e4 4389{
2c935593 4390 int i;
1da177e4 4391
f70dba83 4392 hba[h->ctlr] = NULL;
2c935593
SC		 4393 for (i = 0; i < h->highest_lun + 1; i++)
4394 if (h->gendisk[i] != NULL)
4395 put_disk(h->gendisk[i]);
4396 kfree(h);
1da177e4
LT		 4397}
4398
82eb03cf
CC		 4399/* Send a message CDB to the firmware. */
4400static __devinit int cciss_message(struct pci_dev *pdev, unsigned char opcode, unsigned char type)
4401{
4402 typedef struct {
4403 CommandListHeader_struct CommandHeader;
4404 RequestBlock_struct Request;
4405 ErrDescriptor_struct ErrorDescriptor;
4406 } Command;
4407 static const size_t cmd_sz = sizeof(Command) + sizeof(ErrorInfo_struct);
4408 Command *cmd;
4409 dma_addr_t paddr64;
4410 uint32_t paddr32, tag;
4411 void __iomem *vaddr;
4412 int i, err;
4413
4414 vaddr = ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
4415 if (vaddr == NULL)
4416 return -ENOMEM;
4417
4418 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4419 CCISS commands, so they must be allocated from the lower 4GiB of
4420 memory. */
e930438c 4421 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
82eb03cf
CC		 4422 if (err) {
4423 iounmap(vaddr);
4424 return -ENOMEM;
4425 }
4426
4427 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4428 if (cmd == NULL) {
4429 iounmap(vaddr);
4430 return -ENOMEM;
4431 }
4432
4433 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4434 although there's no guarantee, we assume that the address is at
4435 least 4-byte aligned (most likely, it's page-aligned). */
4436 paddr32 = paddr64;
4437
4438 cmd->CommandHeader.ReplyQueue = 0;
4439 cmd->CommandHeader.SGList = 0;
4440 cmd->CommandHeader.SGTotal = 0;
4441 cmd->CommandHeader.Tag.lower = paddr32;
4442 cmd->CommandHeader.Tag.upper = 0;
4443 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4444
4445 cmd->Request.CDBLen = 16;
4446 cmd->Request.Type.Type = TYPE_MSG;
4447 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4448 cmd->Request.Type.Direction = XFER_NONE;
4449 cmd->Request.Timeout = 0; /* Don't time out */
4450 cmd->Request.CDB[0] = opcode;
4451 cmd->Request.CDB[1] = type;
4452 memset(&cmd->Request.CDB[2], 0, 14); /* the rest of the CDB is reserved */
4453
4454 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(Command);
4455 cmd->ErrorDescriptor.Addr.upper = 0;
4456 cmd->ErrorDescriptor.Len = sizeof(ErrorInfo_struct);
4457
4458 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4459
4460 for (i = 0; i < 10; i++) {
4461 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
4462 if ((tag & ~3) == paddr32)
4463 break;
3e28601f 4464 msleep(CCISS_POST_RESET_NOOP_TIMEOUT_MSECS);
82eb03cf
CC		 4465 }
4466
4467 iounmap(vaddr);
4468
4469 /* we leak the DMA buffer here ... no choice since the controller could
4470 still complete the command. */
4471 if (i == 10) {
b2a4a43d
SC		 4472 dev_err(&pdev->dev,
4473 "controller message %02x:%02x timed out\n",
82eb03cf
CC		 4474 opcode, type);
4475 return -ETIMEDOUT;
4476 }
4477
4478 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4479
4480 if (tag & 2) {
b2a4a43d 4481 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
82eb03cf
CC		 4482 opcode, type);
4483 return -EIO;
4484 }
4485
b2a4a43d 4486 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
82eb03cf
CC		 4487 opcode, type);
4488 return 0;
4489}
4490
82eb03cf
CC		 4491#define cciss_noop(p) cciss_message(p, 3, 0)
4492
a6528d01 4493static int cciss_controller_hard_reset(struct pci_dev *pdev,
bf2e2e6b 4494 void * __iomem vaddr, u32 use_doorbell)
82eb03cf 4495{
a6528d01
SC		 4496 u16 pmcsr;
4497 int pos;
82eb03cf 4498
a6528d01
SC		 4499 if (use_doorbell) {
4500 /* For everything after the P600, the PCI power state method
4501 * of resetting the controller doesn't work, so we have this
4502 * other way using the doorbell register.
4503 */
4504 dev_info(&pdev->dev, "using doorbell to reset controller\n");
bf2e2e6b 4505 writel(use_doorbell, vaddr + SA5_DOORBELL);
a6528d01
SC		 4506 } else { /* Try to do it the PCI power state way */
4507
4508 /* Quoting from the Open CISS Specification: "The Power
4509 * Management Control/Status Register (CSR) controls the power
4510 * state of the device. The normal operating state is D0,
4511 * CSR=00h. The software off state is D3, CSR=03h. To reset
4512 * the controller, place the interface device in D3 then to D0,
4513 * this causes a secondary PCI reset which will reset the
4514 * controller." */
4515
4516 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4517 if (pos == 0) {
4518 dev_err(&pdev->dev,
4519 "cciss_controller_hard_reset: "
4520 "PCI PM not supported\n");
4521 return -ENODEV;
4522 }
4523 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
4524 /* enter the D3hot power management state */
4525 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
4526 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4527 pmcsr |= PCI_D3hot;
4528 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
82eb03cf 4529
a6528d01 4530 msleep(500);
82eb03cf 4531
a6528d01
SC		 4532 /* enter the D0 power management state */
4533 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4534 pmcsr |= PCI_D0;
4535 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
a6528d01
SC		 4536 }
4537 return 0;
4538}
82eb03cf 4539
62710ae1
SC		 4540static __devinit void init_driver_version(char *driver_version, int len)
4541{
4542 memset(driver_version, 0, len);
4543 strncpy(driver_version, "cciss " DRIVER_NAME, len - 1);
4544}
4545
4546static __devinit int write_driver_ver_to_cfgtable(
4547 CfgTable_struct __iomem *cfgtable)
4548{
4549 char *driver_version;
4550 int i, size = sizeof(cfgtable->driver_version);
4551
4552 driver_version = kmalloc(size, GFP_KERNEL);
4553 if (!driver_version)
4554 return -ENOMEM;
4555
4556 init_driver_version(driver_version, size);
4557 for (i = 0; i < size; i++)
4558 writeb(driver_version[i], &cfgtable->driver_version[i]);
4559 kfree(driver_version);
4560 return 0;
4561}
4562
4563static __devinit void read_driver_ver_from_cfgtable(
4564 CfgTable_struct __iomem *cfgtable, unsigned char *driver_ver)
4565{
4566 int i;
4567
4568 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
4569 driver_ver[i] = readb(&cfgtable->driver_version[i]);
4570}
4571
4572static __devinit int controller_reset_failed(
4573 CfgTable_struct __iomem *cfgtable)
4574{
4575
4576 char *driver_ver, *old_driver_ver;
4577 int rc, size = sizeof(cfgtable->driver_version);
4578
4579 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
4580 if (!old_driver_ver)
4581 return -ENOMEM;
4582 driver_ver = old_driver_ver + size;
4583
4584 /* After a reset, the 32 bytes of "driver version" in the cfgtable
4585 * should have been changed, otherwise we know the reset failed.
4586 */
4587 init_driver_version(old_driver_ver, size);
4588 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
4589 rc = !memcmp(driver_ver, old_driver_ver, size);
4590 kfree(old_driver_ver);
4591 return rc;
4592}
4593
a6528d01
SC		 4594/* This does a hard reset of the controller using PCI power management
4595 * states or using the doorbell register. */
4596static __devinit int cciss_kdump_hard_reset_controller(struct pci_dev *pdev)
4597{
a6528d01
SC		 4598 u64 cfg_offset;
4599 u32 cfg_base_addr;
4600 u64 cfg_base_addr_index;
4601 void __iomem *vaddr;
4602 unsigned long paddr;
62710ae1 4603 u32 misc_fw_support;
f442e64b 4604 int rc;
a6528d01 4605 CfgTable_struct __iomem *cfgtable;
bf2e2e6b 4606 u32 use_doorbell;
058a0f9f 4607 u32 board_id;
f442e64b 4608 u16 command_register;
a6528d01
SC		 4609
4610 /* For controllers as old a the p600, this is very nearly
4611 * the same thing as
4612 *
4613 * pci_save_state(pci_dev);
4614 * pci_set_power_state(pci_dev, PCI_D3hot);
4615 * pci_set_power_state(pci_dev, PCI_D0);
4616 * pci_restore_state(pci_dev);
4617 *
a6528d01
SC		 4618 * For controllers newer than the P600, the pci power state
4619 * method of resetting doesn't work so we have another way
4620 * using the doorbell register.
4621 */
82eb03cf 4622
058a0f9f
SC		 4623 /* Exclude 640x boards. These are two pci devices in one slot
4624 * which share a battery backed cache module. One controls the
4625 * cache, the other accesses the cache through the one that controls
4626 * it. If we reset the one controlling the cache, the other will
4627 * likely not be happy. Just forbid resetting this conjoined mess.
4628 */
4629 cciss_lookup_board_id(pdev, &board_id);
ec52d5f1 4630 if (!ctlr_is_resettable(board_id)) {
058a0f9f
SC		 4631 dev_warn(&pdev->dev, "Cannot reset Smart Array 640x "
4632 "due to shared cache module.");
82eb03cf
CC		 4633 return -ENODEV;
4634 }
4635
ec52d5f1
SC		 4636 /* if controller is soft- but not hard resettable... */
4637 if (!ctlr_is_hard_resettable(board_id))
4638 return -ENOTSUPP; /* try soft reset later. */
4639
f442e64b
SC		 4640 /* Save the PCI command register */
4641 pci_read_config_word(pdev, 4, &command_register);
4642 /* Turn the board off. This is so that later pci_restore_state()
4643 * won't turn the board on before the rest of config space is ready.
4644 */
4645 pci_disable_device(pdev);
4646 pci_save_state(pdev);
82eb03cf 4647
a6528d01
SC		 4648 /* find the first memory BAR, so we can find the cfg table */
4649 rc = cciss_pci_find_memory_BAR(pdev, &paddr);
4650 if (rc)
4651 return rc;
4652 vaddr = remap_pci_mem(paddr, 0x250);
4653 if (!vaddr)
4654 return -ENOMEM;
82eb03cf 4655
a6528d01
SC		 4656 /* find cfgtable in order to check if reset via doorbell is supported */
4657 rc = cciss_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
4658 &cfg_base_addr_index, &cfg_offset);
4659 if (rc)
4660 goto unmap_vaddr;
4661 cfgtable = remap_pci_mem(pci_resource_start(pdev,
4662 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
4663 if (!cfgtable) {
4664 rc = -ENOMEM;
4665 goto unmap_vaddr;
4666 }
62710ae1
SC		 4667 rc = write_driver_ver_to_cfgtable(cfgtable);
4668 if (rc)
4669 goto unmap_vaddr;
82eb03cf 4670
bf2e2e6b
SC		 4671 /* If reset via doorbell register is supported, use that.
4672 * There are two such methods. Favor the newest method.
75230ff2 4673 */
bf2e2e6b
SC		 4674 misc_fw_support = readl(&cfgtable->misc_fw_support);
4675 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
4676 if (use_doorbell) {
4677 use_doorbell = DOORBELL_CTLR_RESET2;
4678 } else {
4679 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
063d2cf7
SC		 4680 if (use_doorbell) {
4681 dev_warn(&pdev->dev, "Controller claims that "
4682 "'Bit 2 doorbell reset' is "
4683 "supported, but not 'bit 5 doorbell reset'. "
4684 "Firmware update is recommended.\n");
4685 rc = -ENOTSUPP; /* use the soft reset */
4686 goto unmap_cfgtable;
4687 }
bf2e2e6b 4688 }
75230ff2 4689
a6528d01
SC		 4690 rc = cciss_controller_hard_reset(pdev, vaddr, use_doorbell);
4691 if (rc)
4692 goto unmap_cfgtable;
f442e64b
SC		 4693 pci_restore_state(pdev);
4694 rc = pci_enable_device(pdev);
4695 if (rc) {
4696 dev_warn(&pdev->dev, "failed to enable device.\n");
4697 goto unmap_cfgtable;
82eb03cf 4698 }
f442e64b 4699 pci_write_config_word(pdev, 4, command_register);
82eb03cf 4700
a6528d01
SC		 4701 /* Some devices (notably the HP Smart Array 5i Controller)
4702 need a little pause here */
4703 msleep(CCISS_POST_RESET_PAUSE_MSECS);
4704
afa842fa 4705 /* Wait for board to become not ready, then ready. */
59ec86bb 4706 dev_info(&pdev->dev, "Waiting for board to reset.\n");
afa842fa 4707 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
5afe2781
SC		 4708 if (rc) {
4709 dev_warn(&pdev->dev, "Failed waiting for board to hard reset."
4710 " Will try soft reset.\n");
4711 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
4712 goto unmap_cfgtable;
4713 }
afa842fa
SC		 4714 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_READY);
4715 if (rc) {
4716 dev_warn(&pdev->dev,
5afe2781
SC		 4717 "failed waiting for board to become ready "
4718 "after hard reset\n");
afa842fa
SC		 4719 goto unmap_cfgtable;
4720 }
afa842fa 4721
62710ae1
SC		 4722 rc = controller_reset_failed(vaddr);
4723 if (rc < 0)
4724 goto unmap_cfgtable;
4725 if (rc) {
5afe2781
SC		 4726 dev_warn(&pdev->dev, "Unable to successfully hard reset "
4727 "controller. Will try soft reset.\n");
4728 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
62710ae1 4729 } else {
5afe2781 4730 dev_info(&pdev->dev, "Board ready after hard reset.\n");
a6528d01
SC		 4731 }
4732
4733unmap_cfgtable:
4734 iounmap(cfgtable);
4735
4736unmap_vaddr:
4737 iounmap(vaddr);
4738 return rc;
82eb03cf
CC		 4739}
4740
83123cb1
SC		 4741static __devinit int cciss_init_reset_devices(struct pci_dev *pdev)
4742{
a6528d01 4743 int rc, i;
83123cb1
SC		 4744
4745 if (!reset_devices)
4746 return 0;
4747
a6528d01
SC		 4748 /* Reset the controller with a PCI power-cycle or via doorbell */
4749 rc = cciss_kdump_hard_reset_controller(pdev);
83123cb1 4750
a6528d01
SC		 4751 /* -ENOTSUPP here means we cannot reset the controller
4752 * but it's already (and still) up and running in
058a0f9f
SC		 4753 * "performant mode". Or, it might be 640x, which can't reset
4754 * due to concerns about shared bbwc between 6402/6404 pair.
a6528d01
SC		 4755 */
4756 if (rc == -ENOTSUPP)
5afe2781 4757 return rc; /* just try to do the kdump anyhow. */
a6528d01
SC		 4758 if (rc)
4759 return -ENODEV;
83123cb1
SC		 4760
4761 /* Now try to get the controller to respond to a no-op */
59ec86bb 4762 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
83123cb1
SC		 4763 for (i = 0; i < CCISS_POST_RESET_NOOP_RETRIES; i++) {
4764 if (cciss_noop(pdev) == 0)
4765 break;
4766 else
4767 dev_warn(&pdev->dev, "no-op failed%s\n",
4768 (i < CCISS_POST_RESET_NOOP_RETRIES - 1 ?
4769 "; re-trying" : ""));
4770 msleep(CCISS_POST_RESET_NOOP_INTERVAL_MSECS);
4771 }
82eb03cf
CC		 4772 return 0;
4773}
4774
54dae343
SC		 4775static __devinit int cciss_allocate_cmd_pool(ctlr_info_t *h)
4776{
4777 h->cmd_pool_bits = kmalloc(
4778 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
4779 sizeof(unsigned long), GFP_KERNEL);
4780 h->cmd_pool = pci_alloc_consistent(h->pdev,
4781 h->nr_cmds * sizeof(CommandList_struct),
4782 &(h->cmd_pool_dhandle));
4783 h->errinfo_pool = pci_alloc_consistent(h->pdev,
4784 h->nr_cmds * sizeof(ErrorInfo_struct),
4785 &(h->errinfo_pool_dhandle));
4786 if ((h->cmd_pool_bits == NULL)
4787 || (h->cmd_pool == NULL)
4788 || (h->errinfo_pool == NULL)) {
4789 dev_err(&h->pdev->dev, "out of memory");
4790 return -ENOMEM;
4791 }
4792 return 0;
4793}
4794
abf7966e
SC		 4795static __devinit int cciss_allocate_scatterlists(ctlr_info_t *h)
4796{
4797 int i;
4798
4799 /* zero it, so that on free we need not know how many were alloc'ed */
4800 h->scatter_list = kzalloc(h->max_commands *
4801 sizeof(struct scatterlist *), GFP_KERNEL);
4802 if (!h->scatter_list)
4803 return -ENOMEM;
4804
4805 for (i = 0; i < h->nr_cmds; i++) {
4806 h->scatter_list[i] = kmalloc(sizeof(struct scatterlist) *
4807 h->maxsgentries, GFP_KERNEL);
4808 if (h->scatter_list[i] == NULL) {
4809 dev_err(&h->pdev->dev, "could not allocate "
4810 "s/g lists\n");
4811 return -ENOMEM;
4812 }
4813 }
4814 return 0;
4815}
4816
4817static void cciss_free_scatterlists(ctlr_info_t *h)
4818{
4819 int i;
4820
4821 if (h->scatter_list) {
4822 for (i = 0; i < h->nr_cmds; i++)
4823 kfree(h->scatter_list[i]);
4824 kfree(h->scatter_list);
4825 }
4826}
4827
54dae343
SC		 4828static void cciss_free_cmd_pool(ctlr_info_t *h)
4829{
4830 kfree(h->cmd_pool_bits);
4831 if (h->cmd_pool)
4832 pci_free_consistent(h->pdev,
4833 h->nr_cmds * sizeof(CommandList_struct),
4834 h->cmd_pool, h->cmd_pool_dhandle);
4835 if (h->errinfo_pool)
4836 pci_free_consistent(h->pdev,
4837 h->nr_cmds * sizeof(ErrorInfo_struct),
4838 h->errinfo_pool, h->errinfo_pool_dhandle);
4839}
4840
2b48085f
SC		 4841static int cciss_request_irq(ctlr_info_t *h,
4842 irqreturn_t (*msixhandler)(int, void *),
4843 irqreturn_t (*intxhandler)(int, void *))
4844{
4845 if (h->msix_vector || h->msi_vector) {
4846 if (!request_irq(h->intr[PERF_MODE_INT], msixhandler,
4847 IRQF_DISABLED, h->devname, h))
4848 return 0;
4849 dev_err(&h->pdev->dev, "Unable to get msi irq %d"
4850 " for %s\n", h->intr[PERF_MODE_INT],
4851 h->devname);
4852 return -1;
4853 }
4854
4855 if (!request_irq(h->intr[PERF_MODE_INT], intxhandler,
4856 IRQF_DISABLED, h->devname, h))
4857 return 0;
4858 dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
4859 h->intr[PERF_MODE_INT], h->devname);
4860 return -1;
4861}
4862
5afe2781
SC		 4863static int __devinit cciss_kdump_soft_reset(ctlr_info_t *h)
4864{
4865 if (cciss_send_reset(h, CTLR_LUNID, CCISS_RESET_TYPE_CONTROLLER)) {
4866 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
4867 return -EIO;
4868 }
4869
4870 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
4871 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
4872 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
4873 return -1;
4874 }
4875
4876 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
4877 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
4878 dev_warn(&h->pdev->dev, "Board failed to become ready "
4879 "after soft reset.\n");
4880 return -1;
4881 }
4882
4883 return 0;
4884}
4885
4886static void cciss_undo_allocations_after_kdump_soft_reset(ctlr_info_t *h)
4887{
4888 int ctlr = h->ctlr;
4889
4890 free_irq(h->intr[PERF_MODE_INT], h);
4891#ifdef CONFIG_PCI_MSI
4892 if (h->msix_vector)
4893 pci_disable_msix(h->pdev);
4894 else if (h->msi_vector)
4895 pci_disable_msi(h->pdev);
4896#endif /* CONFIG_PCI_MSI */
4897 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
4898 cciss_free_scatterlists(h);
4899 cciss_free_cmd_pool(h);
4900 kfree(h->blockFetchTable);
4901 if (h->reply_pool)
4902 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
4903 h->reply_pool, h->reply_pool_dhandle);
4904 if (h->transtable)
4905 iounmap(h->transtable);
4906 if (h->cfgtable)
4907 iounmap(h->cfgtable);
4908 if (h->vaddr)
4909 iounmap(h->vaddr);
4910 unregister_blkdev(h->major, h->devname);
4911 cciss_destroy_hba_sysfs_entry(h);
4912 pci_release_regions(h->pdev);
4913 kfree(h);
4914 hba[ctlr] = NULL;
4915}
4916
1da177e4
LT		 4917/*
4918 * This is it. Find all the controllers and register them. I really hate
4919 * stealing all these major device numbers.
4920 * returns the number of block devices registered.
4921 */
4922static int __devinit cciss_init_one(struct pci_dev *pdev,
7c832835 4923 const struct pci_device_id *ent)
1da177e4 4924{
1da177e4 4925 int i;
799202cb 4926 int j = 0;
1da177e4 4927 int rc;
5afe2781 4928 int try_soft_reset = 0;
22bece00 4929 int dac, return_code;
212a5026 4930 InquiryData_struct *inq_buff;
f70dba83 4931 ctlr_info_t *h;
5afe2781 4932 unsigned long flags;
1da177e4 4933
83123cb1 4934 rc = cciss_init_reset_devices(pdev);
5afe2781
SC		 4935 if (rc) {
4936 if (rc != -ENOTSUPP)
4937 return rc;
4938 /* If the reset fails in a particular way (it has no way to do
4939 * a proper hard reset, so returns -ENOTSUPP) we can try to do
4940 * a soft reset once we get the controller configured up to the
4941 * point that it can accept a command.
4942 */
4943 try_soft_reset = 1;
4944 rc = 0;
4945 }
4946
4947reinit_after_soft_reset:
4948
b2a4a43d 4949 i = alloc_cciss_hba(pdev);
7c832835 4950 if (i < 0)
e2019b58 4951 return -1;
1f8ef380 4952
f70dba83
SC		 4953 h = hba[i];
4954 h->pdev = pdev;
4955 h->busy_initializing = 1;
e6e1ee93
JA		 4956 INIT_LIST_HEAD(&h->cmpQ);
4957 INIT_LIST_HEAD(&h->reqQ);
f70dba83 4958 mutex_init(&h->busy_shutting_down);
1f8ef380 4959
f70dba83 4960 if (cciss_pci_init(h) != 0)
2cfa948c 4961 goto clean_no_release_regions;
1da177e4 4962
f70dba83
SC		 4963 sprintf(h->devname, "cciss%d", i);
4964 h->ctlr = i;
1da177e4 4965
8a4ec67b
SC		 4966 if (cciss_tape_cmds < 2)
4967 cciss_tape_cmds = 2;
4968 if (cciss_tape_cmds > 16)
4969 cciss_tape_cmds = 16;
4970
f70dba83 4971 init_completion(&h->scan_wait);
b368c9dd 4972
f70dba83 4973 if (cciss_create_hba_sysfs_entry(h))
7fe06326
AP		 4974 goto clean0;
4975
1da177e4 4976 /* configure PCI DMA stuff */
6a35528a 4977 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
40aabb58 4978 dac = 1;
284901a9 4979 else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
40aabb58 4980 dac = 0;
1da177e4 4981 else {
b2a4a43d 4982 dev_err(&h->pdev->dev, "no suitable DMA available\n");
1da177e4
LT		 4983 goto clean1;
4984 }
4985
4986 /*
4987 * register with the major number, or get a dynamic major number
4988 * by passing 0 as argument. This is done for greater than
4989 * 8 controller support.
4990 */
4991 if (i < MAX_CTLR_ORIG)
f70dba83
SC		 4992 h->major = COMPAQ_CISS_MAJOR + i;
4993 rc = register_blkdev(h->major, h->devname);
7c832835 4994 if (rc == -EBUSY || rc == -EINVAL) {
b2a4a43d
SC		 4995 dev_err(&h->pdev->dev,
4996 "Unable to get major number %d for %s "
f70dba83 4997 "on hba %d\n", h->major, h->devname, i);
1da177e4 4998 goto clean1;
7c832835 4999 } else {
1da177e4 5000 if (i >= MAX_CTLR_ORIG)
f70dba83 5001 h->major = rc;
1da177e4
LT		 5002 }
5003
5004 /* make sure the board interrupts are off */
f70dba83 5005 h->access.set_intr_mask(h, CCISS_INTR_OFF);
2b48085f
SC		 5006 rc = cciss_request_irq(h, do_cciss_msix_intr, do_cciss_intx);
5007 if (rc)
5008 goto clean2;
40aabb58 5009
b2a4a43d 5010 dev_info(&h->pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
f70dba83
SC		 5011 h->devname, pdev->device, pci_name(pdev),
5012 h->intr[PERF_MODE_INT], dac ? "" : " not");
7c832835 5013
54dae343 5014 if (cciss_allocate_cmd_pool(h))
1da177e4 5015 goto clean4;
5c07a311 5016
abf7966e 5017 if (cciss_allocate_scatterlists(h))
4ee69851
DC		 5018 goto clean4;
5019
f70dba83
SC		 5020 h->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,
5021 h->chainsize, h->nr_cmds);
5022 if (!h->cmd_sg_list && h->chainsize > 0)
5c07a311 5023 goto clean4;
5c07a311 5024
f70dba83 5025 spin_lock_init(&h->lock);
1da177e4 5026
7c832835 5027 /* Initialize the pdev driver private data.
f70dba83
SC		 5028 have it point to h. */
5029 pci_set_drvdata(pdev, h);
7c832835
BH		 5030 /* command and error info recs zeroed out before
5031 they are used */
f70dba83
SC		 5032 memset(h->cmd_pool_bits, 0,
5033 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG)
061837bc 5034 * sizeof(unsigned long));
1da177e4 5035
f70dba83
SC		 5036 h->num_luns = 0;
5037 h->highest_lun = -1;
6ae5ce8e 5038 for (j = 0; j < CISS_MAX_LUN; j++) {
f70dba83
SC		 5039 h->drv[j] = NULL;
5040 h->gendisk[j] = NULL;
6ae5ce8e 5041 }
1da177e4 5042
5afe2781
SC		 5043 /* At this point, the controller is ready to take commands.
5044 * Now, if reset_devices and the hard reset didn't work, try
5045 * the soft reset and see if that works.
5046 */
5047 if (try_soft_reset) {
5048
5049 /* This is kind of gross. We may or may not get a completion
5050 * from the soft reset command, and if we do, then the value
5051 * from the fifo may or may not be valid. So, we wait 10 secs
5052 * after the reset throwing away any completions we get during
5053 * that time. Unregister the interrupt handler and register
5054 * fake ones to scoop up any residual completions.
5055 */
5056 spin_lock_irqsave(&h->lock, flags);
5057 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5058 spin_unlock_irqrestore(&h->lock, flags);
5059 free_irq(h->intr[PERF_MODE_INT], h);
5060 rc = cciss_request_irq(h, cciss_msix_discard_completions,
5061 cciss_intx_discard_completions);
5062 if (rc) {
5063 dev_warn(&h->pdev->dev, "Failed to request_irq after "
5064 "soft reset.\n");
5065 goto clean4;
5066 }
5067
5068 rc = cciss_kdump_soft_reset(h);
5069 if (rc) {
5070 dev_warn(&h->pdev->dev, "Soft reset failed.\n");
5071 goto clean4;
5072 }
5073
5074 dev_info(&h->pdev->dev, "Board READY.\n");
5075 dev_info(&h->pdev->dev,
5076 "Waiting for stale completions to drain.\n");
5077 h->access.set_intr_mask(h, CCISS_INTR_ON);
5078 msleep(10000);
5079 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5080
5081 rc = controller_reset_failed(h->cfgtable);
5082 if (rc)
5083 dev_info(&h->pdev->dev,
5084 "Soft reset appears to have failed.\n");
5085
5086 /* since the controller's reset, we have to go back and re-init
5087 * everything. Easiest to just forget what we've done and do it
5088 * all over again.
5089 */
5090 cciss_undo_allocations_after_kdump_soft_reset(h);
5091 try_soft_reset = 0;
5092 if (rc)
5093 /* don't go to clean4, we already unallocated */
5094 return -ENODEV;
5095
5096 goto reinit_after_soft_reset;
5097 }
5098
f70dba83 5099 cciss_scsi_setup(h);
1da177e4
LT		 5100
5101 /* Turn the interrupts on so we can service requests */
f70dba83 5102 h->access.set_intr_mask(h, CCISS_INTR_ON);
1da177e4 5103
22bece00
MM		 5104 /* Get the firmware version */
5105 inq_buff = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
5106 if (inq_buff == NULL) {
b2a4a43d 5107 dev_err(&h->pdev->dev, "out of memory\n");
22bece00
MM		 5108 goto clean4;
5109 }
5110
f70dba83 5111 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
b57695fe 5112 sizeof(InquiryData_struct), 0, CTLR_LUNID, TYPE_CMD);
22bece00 5113 if (return_code == IO_OK) {
f70dba83
SC		 5114 h->firm_ver[0] = inq_buff->data_byte[32];
5115 h->firm_ver[1] = inq_buff->data_byte[33];
5116 h->firm_ver[2] = inq_buff->data_byte[34];
5117 h->firm_ver[3] = inq_buff->data_byte[35];
22bece00 5118 } else { /* send command failed */
b2a4a43d 5119 dev_warn(&h->pdev->dev, "unable to determine firmware"
22bece00
MM		 5120 " version of controller\n");
5121 }
212a5026 5122 kfree(inq_buff);
22bece00 5123
f70dba83 5124 cciss_procinit(h);
92c4231a 5125
f70dba83 5126 h->cciss_max_sectors = 8192;
92c4231a 5127
f70dba83
SC		 5128 rebuild_lun_table(h, 1, 0);
5129 h->busy_initializing = 0;
e2019b58 5130 return 1;
1da177e4 5131
6ae5ce8e 5132clean4:
54dae343 5133 cciss_free_cmd_pool(h);
abf7966e 5134 cciss_free_scatterlists(h);
f70dba83 5135 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
f70dba83 5136 free_irq(h->intr[PERF_MODE_INT], h);
6ae5ce8e 5137clean2:
f70dba83 5138 unregister_blkdev(h->major, h->devname);
6ae5ce8e 5139clean1:
f70dba83 5140 cciss_destroy_hba_sysfs_entry(h);
7fe06326 5141clean0:
2cfa948c
SC		 5142 pci_release_regions(pdev);
5143clean_no_release_regions:
f70dba83 5144 h->busy_initializing = 0;
9cef0d2f 5145
872225ca
MM		 5146 /*
5147 * Deliberately omit pci_disable_device(): it does something nasty to
5148 * Smart Array controllers that pci_enable_device does not undo
5149 */
799202cb 5150 pci_set_drvdata(pdev, NULL);
f70dba83 5151 free_hba(h);
e2019b58 5152 return -1;
1da177e4
LT		 5153}
5154
e9ca75b5 5155static void cciss_shutdown(struct pci_dev *pdev)
1da177e4 5156{
29009a03
SC		 5157 ctlr_info_t *h;
5158 char *flush_buf;
7c832835 5159 int return_code;
1da177e4 5160
29009a03
SC		 5161 h = pci_get_drvdata(pdev);
5162 flush_buf = kzalloc(4, GFP_KERNEL);
5163 if (!flush_buf) {
b2a4a43d 5164 dev_warn(&h->pdev->dev, "cache not flushed, out of memory.\n");
e9ca75b5 5165 return;
e9ca75b5 5166 }
29009a03
SC		 5167 /* write all data in the battery backed cache to disk */
5168 memset(flush_buf, 0, 4);
f70dba83 5169 return_code = sendcmd_withirq(h, CCISS_CACHE_FLUSH, flush_buf,
29009a03
SC		 5170 4, 0, CTLR_LUNID, TYPE_CMD);
5171 kfree(flush_buf);
5172 if (return_code != IO_OK)
b2a4a43d 5173 dev_warn(&h->pdev->dev, "Error flushing cache\n");
29009a03 5174 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5e216153 5175 free_irq(h->intr[PERF_MODE_INT], h);
e9ca75b5
GB		 5176}
5177
5178static void __devexit cciss_remove_one(struct pci_dev *pdev)
5179{
f70dba83 5180 ctlr_info_t *h;
e9ca75b5
GB		 5181 int i, j;
5182
7c832835 5183 if (pci_get_drvdata(pdev) == NULL) {
b2a4a43d 5184 dev_err(&pdev->dev, "Unable to remove device\n");
1da177e4
LT		 5185 return;
5186 }
0a9279cc 5187
f70dba83
SC		 5188 h = pci_get_drvdata(pdev);
5189 i = h->ctlr;
7c832835 5190 if (hba[i] == NULL) {
b2a4a43d 5191 dev_err(&pdev->dev, "device appears to already be removed\n");
1da177e4
LT		 5192 return;
5193 }
b6550777 5194
f70dba83 5195 mutex_lock(&h->busy_shutting_down);
0a9279cc 5196
f70dba83
SC		 5197 remove_from_scan_list(h);
5198 remove_proc_entry(h->devname, proc_cciss);
5199 unregister_blkdev(h->major, h->devname);
b6550777
BH		 5200
5201 /* remove it from the disk list */
5202 for (j = 0; j < CISS_MAX_LUN; j++) {
f70dba83 5203 struct gendisk *disk = h->gendisk[j];
b6550777 5204 if (disk) {
165125e1 5205 struct request_queue *q = disk->queue;
b6550777 5206
097d0264 5207 if (disk->flags & GENHD_FL_UP) {
f70dba83 5208 cciss_destroy_ld_sysfs_entry(h, j, 1);
b6550777 5209 del_gendisk(disk);
097d0264 5210 }
b6550777
BH		 5211 if (q)
5212 blk_cleanup_queue(q);
5213 }
5214 }
5215
ba198efb 5216#ifdef CONFIG_CISS_SCSI_TAPE
f70dba83 5217 cciss_unregister_scsi(h); /* unhook from SCSI subsystem */
ba198efb 5218#endif
b6550777 5219
e9ca75b5 5220 cciss_shutdown(pdev);
fb86a35b
MM		 5221
5222#ifdef CONFIG_PCI_MSI
f70dba83
SC		 5223 if (h->msix_vector)
5224 pci_disable_msix(h->pdev);
5225 else if (h->msi_vector)
5226 pci_disable_msi(h->pdev);
7c832835 5227#endif /* CONFIG_PCI_MSI */
fb86a35b 5228
f70dba83
SC		 5229 iounmap(h->transtable);
5230 iounmap(h->cfgtable);
5231 iounmap(h->vaddr);
1da177e4 5232
54dae343 5233 cciss_free_cmd_pool(h);
5c07a311 5234 /* Free up sg elements */
f70dba83
SC		 5235 for (j = 0; j < h->nr_cmds; j++)
5236 kfree(h->scatter_list[j]);
5237 kfree(h->scatter_list);
5238 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
e363e014
SC		 5239 kfree(h->blockFetchTable);
5240 if (h->reply_pool)
5241 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
5242 h->reply_pool, h->reply_pool_dhandle);
872225ca
MM		 5243 /*
5244 * Deliberately omit pci_disable_device(): it does something nasty to
5245 * Smart Array controllers that pci_enable_device does not undo
5246 */
7c832835 5247 pci_release_regions(pdev);
4e570309 5248 pci_set_drvdata(pdev, NULL);
f70dba83
SC		 5249 cciss_destroy_hba_sysfs_entry(h);
5250 mutex_unlock(&h->busy_shutting_down);
5251 free_hba(h);
7c832835 5252}
1da177e4
LT		 5253
5254static struct pci_driver cciss_pci_driver = {
7c832835
BH		 5255 .name = "cciss",
5256 .probe = cciss_init_one,
5257 .remove = __devexit_p(cciss_remove_one),
5258 .id_table = cciss_pci_device_id, /* id_table */
e9ca75b5 5259 .shutdown = cciss_shutdown,
1da177e4
LT		 5260};
5261
5262/*
5263 * This is it. Register the PCI driver information for the cards we control
7c832835 5264 * the OS will call our registered routines when it finds one of our cards.
1da177e4
LT		 5265 */
5266static int __init cciss_init(void)
5267{
7fe06326
AP		 5268 int err;
5269
10cbda97
JA		 5270 /*
5271 * The hardware requires that commands are aligned on a 64-bit
5272 * boundary. Given that we use pci_alloc_consistent() to allocate an
5273 * array of them, the size must be a multiple of 8 bytes.
5274 */
1b7d0d28 5275 BUILD_BUG_ON(sizeof(CommandList_struct) % COMMANDLIST_ALIGNMENT);
1da177e4
LT		 5276 printk(KERN_INFO DRIVER_NAME "\n");
5277
7fe06326
AP		 5278 err = bus_register(&cciss_bus_type);
5279 if (err)
5280 return err;
5281
b368c9dd
AP		 5282 /* Start the scan thread */
5283 cciss_scan_thread = kthread_run(scan_thread, NULL, "cciss_scan");
5284 if (IS_ERR(cciss_scan_thread)) {
5285 err = PTR_ERR(cciss_scan_thread);
5286 goto err_bus_unregister;
5287 }
5288
1da177e4 5289 /* Register for our PCI devices */
7fe06326
AP		 5290 err = pci_register_driver(&cciss_pci_driver);
5291 if (err)
b368c9dd 5292 goto err_thread_stop;
7fe06326 5293
617e1344 5294 return err;
7fe06326 5295
b368c9dd
AP		 5296err_thread_stop:
5297 kthread_stop(cciss_scan_thread);
5298err_bus_unregister:
7fe06326 5299 bus_unregister(&cciss_bus_type);
b368c9dd 5300
7fe06326 5301 return err;
1da177e4
LT		 5302}
5303
5304static void __exit cciss_cleanup(void)
5305{
5306 int i;
5307
5308 pci_unregister_driver(&cciss_pci_driver);
5309 /* double check that all controller entrys have been removed */
7c832835
BH		 5310 for (i = 0; i < MAX_CTLR; i++) {
5311 if (hba[i] != NULL) {
b2a4a43d
SC		 5312 dev_warn(&hba[i]->pdev->dev,
5313 "had to remove controller\n");
1da177e4
LT		 5314 cciss_remove_one(hba[i]->pdev);
5315 }
5316 }
b368c9dd 5317 kthread_stop(cciss_scan_thread);
90fdb0b9
JA		 5318 if (proc_cciss)
5319 remove_proc_entry("driver/cciss", NULL);
7fe06326 5320 bus_unregister(&cciss_bus_type);
1da177e4
LT		 5321}
5322
5323module_init(cciss_init);
5324module_exit(cciss_cleanup);
Linux kernel - Deliverables
This page took 1.024266 seconds and 5 git commands to generate.