Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef CCISS_H |
2 | #define CCISS_H | |
3 | ||
4 | #include <linux/genhd.h> | |
5 | ||
6 | #include "cciss_cmd.h" | |
7 | ||
8 | ||
1da177e4 LT |
9 | #define NWD_SHIFT 4 |
10 | #define MAX_PART (1 << NWD_SHIFT) | |
11 | ||
12 | #define IO_OK 0 | |
13 | #define IO_ERROR 1 | |
14 | ||
1da177e4 LT |
15 | struct ctlr_info; |
16 | typedef struct ctlr_info ctlr_info_t; | |
17 | ||
18 | struct access_method { | |
19 | void (*submit_command)(ctlr_info_t *h, CommandList_struct *c); | |
20 | void (*set_intr_mask)(ctlr_info_t *h, unsigned long val); | |
21 | unsigned long (*fifo_full)(ctlr_info_t *h); | |
22 | unsigned long (*intr_pending)(ctlr_info_t *h); | |
23 | unsigned long (*command_completed)(ctlr_info_t *h); | |
24 | }; | |
25 | typedef struct _drive_info_struct | |
26 | { | |
27 | __u32 LunID; | |
28 | int usage_count; | |
ad2b9312 | 29 | struct request_queue *queue; |
1da177e4 LT |
30 | sector_t nr_blocks; |
31 | int block_size; | |
32 | int heads; | |
33 | int sectors; | |
34 | int cylinders; | |
ddd47442 MM |
35 | int raid_level; /* set to -1 to indicate that |
36 | * the drive is not in use/configured | |
37 | */ | |
38 | int busy_configuring; /*This is set when the drive is being removed | |
39 | *to prevent it from being opened or it's queue | |
40 | *from being started. | |
41 | */ | |
a72da29b MM |
42 | __u8 serial_no[16]; /* from inquiry page 0x83, */ |
43 | /* not necc. null terminated. */ | |
1da177e4 LT |
44 | } drive_info_struct; |
45 | ||
3da8b713 | 46 | #ifdef CONFIG_CISS_SCSI_TAPE |
47 | ||
48 | struct sendcmd_reject_list { | |
49 | int ncompletions; | |
50 | unsigned long *complete; /* array of NR_CMDS tags */ | |
51 | }; | |
52 | ||
53 | #endif | |
1da177e4 LT |
54 | struct ctlr_info |
55 | { | |
56 | int ctlr; | |
57 | char devname[8]; | |
58 | char *product_name; | |
59 | char firm_ver[4]; // Firmware version | |
60 | struct pci_dev *pdev; | |
61 | __u32 board_id; | |
62 | void __iomem *vaddr; | |
63 | unsigned long paddr; | |
f880632f | 64 | int nr_cmds; /* Number of commands allowed on this controller */ |
1da177e4 | 65 | CfgTable_struct __iomem *cfgtable; |
1da177e4 LT |
66 | int interrupts_enabled; |
67 | int major; | |
68 | int max_commands; | |
69 | int commands_outstanding; | |
70 | int max_outstanding; /* Debug */ | |
71 | int num_luns; | |
72 | int highest_lun; | |
73 | int usage_count; /* number of opens all all minor devices */ | |
fb86a35b MM |
74 | # define DOORBELL_INT 0 |
75 | # define PERF_MODE_INT 1 | |
76 | # define SIMPLE_MODE_INT 2 | |
77 | # define MEMQ_MODE_INT 3 | |
78 | unsigned int intr[4]; | |
79 | unsigned int msix_vector; | |
80 | unsigned int msi_vector; | |
92c4231a | 81 | int cciss_max_sectors; |
00988a35 MMOD |
82 | BYTE cciss_read; |
83 | BYTE cciss_write; | |
84 | BYTE cciss_read_capacity; | |
1da177e4 LT |
85 | |
86 | // information about each logical volume | |
87 | drive_info_struct drv[CISS_MAX_LUN]; | |
88 | ||
89 | struct access_method access; | |
90 | ||
91 | /* queue and queue Info */ | |
92 | CommandList_struct *reqQ; | |
93 | CommandList_struct *cmpQ; | |
94 | unsigned int Qdepth; | |
95 | unsigned int maxQsinceinit; | |
96 | unsigned int maxSG; | |
97 | spinlock_t lock; | |
1da177e4 LT |
98 | |
99 | //* pointers to command and error info pool */ | |
100 | CommandList_struct *cmd_pool; | |
101 | dma_addr_t cmd_pool_dhandle; | |
102 | ErrorInfo_struct *errinfo_pool; | |
103 | dma_addr_t errinfo_pool_dhandle; | |
104 | unsigned long *cmd_pool_bits; | |
105 | int nr_allocs; | |
106 | int nr_frees; | |
107 | int busy_configuring; | |
1f8ef380 | 108 | int busy_initializing; |
1da177e4 LT |
109 | |
110 | /* This element holds the zero based queue number of the last | |
111 | * queue to be started. It is used for fairness. | |
112 | */ | |
113 | int next_to_run; | |
114 | ||
115 | // Disk structures we need to pass back | |
799202cb | 116 | struct gendisk *gendisk[CISS_MAX_LUN]; |
1da177e4 LT |
117 | #ifdef CONFIG_CISS_SCSI_TAPE |
118 | void *scsi_ctlr; /* ptr to structure containing scsi related stuff */ | |
3da8b713 | 119 | /* list of block side commands the scsi error handling sucked up */ |
120 | /* and saved for later processing */ | |
121 | struct sendcmd_reject_list scsi_rejects; | |
1da177e4 | 122 | #endif |
33079b21 | 123 | unsigned char alive; |
1da177e4 LT |
124 | }; |
125 | ||
126 | /* Defining the diffent access_menthods */ | |
127 | /* | |
128 | * Memory mapped FIFO interface (SMART 53xx cards) | |
129 | */ | |
130 | #define SA5_DOORBELL 0x20 | |
131 | #define SA5_REQUEST_PORT_OFFSET 0x40 | |
132 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 | |
133 | #define SA5_REPLY_PORT_OFFSET 0x44 | |
134 | #define SA5_INTR_STATUS 0x30 | |
135 | #define SA5_SCRATCHPAD_OFFSET 0xB0 | |
136 | ||
137 | #define SA5_CTCFG_OFFSET 0xB4 | |
138 | #define SA5_CTMEM_OFFSET 0xB8 | |
139 | ||
140 | #define SA5_INTR_OFF 0x08 | |
141 | #define SA5B_INTR_OFF 0x04 | |
142 | #define SA5_INTR_PENDING 0x08 | |
143 | #define SA5B_INTR_PENDING 0x04 | |
144 | #define FIFO_EMPTY 0xffffffff | |
145 | #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ | |
146 | ||
147 | #define CISS_ERROR_BIT 0x02 | |
148 | ||
149 | #define CCISS_INTR_ON 1 | |
150 | #define CCISS_INTR_OFF 0 | |
151 | /* | |
152 | Send the command to the hardware | |
153 | */ | |
154 | static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c) | |
155 | { | |
156 | #ifdef CCISS_DEBUG | |
157 | printk("Sending %x - down to controller\n", c->busaddr ); | |
158 | #endif /* CCISS_DEBUG */ | |
159 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); | |
160 | h->commands_outstanding++; | |
161 | if ( h->commands_outstanding > h->max_outstanding) | |
162 | h->max_outstanding = h->commands_outstanding; | |
163 | } | |
164 | ||
165 | /* | |
166 | * This card is the opposite of the other cards. | |
167 | * 0 turns interrupts on... | |
168 | * 0x08 turns them off... | |
169 | */ | |
170 | static void SA5_intr_mask(ctlr_info_t *h, unsigned long val) | |
171 | { | |
172 | if (val) | |
173 | { /* Turn interrupts on */ | |
174 | h->interrupts_enabled = 1; | |
175 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
176 | } else /* Turn them off */ | |
177 | { | |
178 | h->interrupts_enabled = 0; | |
179 | writel( SA5_INTR_OFF, | |
180 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
181 | } | |
182 | } | |
183 | /* | |
184 | * This card is the opposite of the other cards. | |
185 | * 0 turns interrupts on... | |
186 | * 0x04 turns them off... | |
187 | */ | |
188 | static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val) | |
189 | { | |
190 | if (val) | |
191 | { /* Turn interrupts on */ | |
192 | h->interrupts_enabled = 1; | |
193 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
194 | } else /* Turn them off */ | |
195 | { | |
196 | h->interrupts_enabled = 0; | |
197 | writel( SA5B_INTR_OFF, | |
198 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
199 | } | |
200 | } | |
201 | /* | |
202 | * Returns true if fifo is full. | |
203 | * | |
204 | */ | |
205 | static unsigned long SA5_fifo_full(ctlr_info_t *h) | |
206 | { | |
207 | if( h->commands_outstanding >= h->max_commands) | |
208 | return(1); | |
209 | else | |
210 | return(0); | |
211 | ||
212 | } | |
213 | /* | |
214 | * returns value read from hardware. | |
215 | * returns FIFO_EMPTY if there is nothing to read | |
216 | */ | |
217 | static unsigned long SA5_completed(ctlr_info_t *h) | |
218 | { | |
219 | unsigned long register_value | |
220 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); | |
221 | if(register_value != FIFO_EMPTY) | |
222 | { | |
223 | h->commands_outstanding--; | |
224 | #ifdef CCISS_DEBUG | |
225 | printk("cciss: Read %lx back from board\n", register_value); | |
226 | #endif /* CCISS_DEBUG */ | |
227 | } | |
228 | #ifdef CCISS_DEBUG | |
229 | else | |
230 | { | |
231 | printk("cciss: FIFO Empty read\n"); | |
232 | } | |
233 | #endif | |
234 | return ( register_value); | |
235 | ||
236 | } | |
237 | /* | |
238 | * Returns true if an interrupt is pending.. | |
239 | */ | |
240 | static unsigned long SA5_intr_pending(ctlr_info_t *h) | |
241 | { | |
242 | unsigned long register_value = | |
243 | readl(h->vaddr + SA5_INTR_STATUS); | |
244 | #ifdef CCISS_DEBUG | |
245 | printk("cciss: intr_pending %lx\n", register_value); | |
246 | #endif /* CCISS_DEBUG */ | |
247 | if( register_value & SA5_INTR_PENDING) | |
248 | return 1; | |
249 | return 0 ; | |
250 | } | |
251 | ||
252 | /* | |
253 | * Returns true if an interrupt is pending.. | |
254 | */ | |
255 | static unsigned long SA5B_intr_pending(ctlr_info_t *h) | |
256 | { | |
257 | unsigned long register_value = | |
258 | readl(h->vaddr + SA5_INTR_STATUS); | |
259 | #ifdef CCISS_DEBUG | |
260 | printk("cciss: intr_pending %lx\n", register_value); | |
261 | #endif /* CCISS_DEBUG */ | |
262 | if( register_value & SA5B_INTR_PENDING) | |
263 | return 1; | |
264 | return 0 ; | |
265 | } | |
266 | ||
267 | ||
268 | static struct access_method SA5_access = { | |
269 | SA5_submit_command, | |
270 | SA5_intr_mask, | |
271 | SA5_fifo_full, | |
272 | SA5_intr_pending, | |
273 | SA5_completed, | |
274 | }; | |
275 | ||
276 | static struct access_method SA5B_access = { | |
277 | SA5_submit_command, | |
278 | SA5B_intr_mask, | |
279 | SA5_fifo_full, | |
280 | SA5B_intr_pending, | |
281 | SA5_completed, | |
282 | }; | |
283 | ||
284 | struct board_type { | |
285 | __u32 board_id; | |
286 | char *product_name; | |
287 | struct access_method *access; | |
f880632f | 288 | int nr_cmds; /* Max cmds this kind of ctlr can handle. */ |
1da177e4 LT |
289 | }; |
290 | ||
ad2b9312 | 291 | #define CCISS_LOCK(i) (&hba[i]->lock) |
1da177e4 LT |
292 | |
293 | #endif /* CCISS_H */ | |
294 |