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1da177e4 LT |
1 | #ifndef CCISS_H |
2 | #define CCISS_H | |
3 | ||
4 | #include <linux/genhd.h> | |
b368c9dd | 5 | #include <linux/mutex.h> |
1da177e4 LT |
6 | |
7 | #include "cciss_cmd.h" | |
8 | ||
9 | ||
1da177e4 LT |
10 | #define NWD_SHIFT 4 |
11 | #define MAX_PART (1 << NWD_SHIFT) | |
12 | ||
13 | #define IO_OK 0 | |
14 | #define IO_ERROR 1 | |
789a424a | 15 | #define IO_NEEDS_RETRY 3 |
1da177e4 | 16 | |
7fe06326 AP |
17 | #define VENDOR_LEN 8 |
18 | #define MODEL_LEN 16 | |
19 | #define REV_LEN 4 | |
20 | ||
1da177e4 LT |
21 | struct ctlr_info; |
22 | typedef struct ctlr_info ctlr_info_t; | |
23 | ||
24 | struct access_method { | |
25 | void (*submit_command)(ctlr_info_t *h, CommandList_struct *c); | |
26 | void (*set_intr_mask)(ctlr_info_t *h, unsigned long val); | |
27 | unsigned long (*fifo_full)(ctlr_info_t *h); | |
28 | unsigned long (*intr_pending)(ctlr_info_t *h); | |
29 | unsigned long (*command_completed)(ctlr_info_t *h); | |
30 | }; | |
31 | typedef struct _drive_info_struct | |
32 | { | |
33 | __u32 LunID; | |
34 | int usage_count; | |
ad2b9312 | 35 | struct request_queue *queue; |
1da177e4 LT |
36 | sector_t nr_blocks; |
37 | int block_size; | |
38 | int heads; | |
39 | int sectors; | |
40 | int cylinders; | |
ddd47442 MM |
41 | int raid_level; /* set to -1 to indicate that |
42 | * the drive is not in use/configured | |
7fe06326 AP |
43 | */ |
44 | int busy_configuring; /* This is set when a drive is being removed | |
45 | * to prevent it from being opened or it's | |
46 | * queue from being started. | |
47 | */ | |
617e1344 | 48 | struct device *dev; |
7fe06326 AP |
49 | __u8 serial_no[16]; /* from inquiry page 0x83, |
50 | * not necc. null terminated. | |
51 | */ | |
52 | char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */ | |
53 | char model[MODEL_LEN + 1]; /* SCSI model string */ | |
54 | char rev[REV_LEN + 1]; /* SCSI revision string */ | |
1da177e4 LT |
55 | } drive_info_struct; |
56 | ||
57 | struct ctlr_info | |
58 | { | |
59 | int ctlr; | |
60 | char devname[8]; | |
61 | char *product_name; | |
62 | char firm_ver[4]; // Firmware version | |
63 | struct pci_dev *pdev; | |
64 | __u32 board_id; | |
65 | void __iomem *vaddr; | |
66 | unsigned long paddr; | |
f880632f | 67 | int nr_cmds; /* Number of commands allowed on this controller */ |
1da177e4 | 68 | CfgTable_struct __iomem *cfgtable; |
1da177e4 LT |
69 | int interrupts_enabled; |
70 | int major; | |
71 | int max_commands; | |
72 | int commands_outstanding; | |
73 | int max_outstanding; /* Debug */ | |
74 | int num_luns; | |
75 | int highest_lun; | |
76 | int usage_count; /* number of opens all all minor devices */ | |
fb86a35b MM |
77 | # define DOORBELL_INT 0 |
78 | # define PERF_MODE_INT 1 | |
79 | # define SIMPLE_MODE_INT 2 | |
80 | # define MEMQ_MODE_INT 3 | |
81 | unsigned int intr[4]; | |
82 | unsigned int msix_vector; | |
83 | unsigned int msi_vector; | |
92c4231a | 84 | int cciss_max_sectors; |
00988a35 MMOD |
85 | BYTE cciss_read; |
86 | BYTE cciss_write; | |
87 | BYTE cciss_read_capacity; | |
1da177e4 LT |
88 | |
89 | // information about each logical volume | |
90 | drive_info_struct drv[CISS_MAX_LUN]; | |
91 | ||
92 | struct access_method access; | |
93 | ||
94 | /* queue and queue Info */ | |
8a3173de JA |
95 | struct hlist_head reqQ; |
96 | struct hlist_head cmpQ; | |
1da177e4 LT |
97 | unsigned int Qdepth; |
98 | unsigned int maxQsinceinit; | |
99 | unsigned int maxSG; | |
100 | spinlock_t lock; | |
1da177e4 LT |
101 | |
102 | //* pointers to command and error info pool */ | |
103 | CommandList_struct *cmd_pool; | |
104 | dma_addr_t cmd_pool_dhandle; | |
105 | ErrorInfo_struct *errinfo_pool; | |
106 | dma_addr_t errinfo_pool_dhandle; | |
107 | unsigned long *cmd_pool_bits; | |
108 | int nr_allocs; | |
109 | int nr_frees; | |
110 | int busy_configuring; | |
1f8ef380 | 111 | int busy_initializing; |
b368c9dd AP |
112 | int busy_scanning; |
113 | struct mutex busy_shutting_down; | |
1da177e4 LT |
114 | |
115 | /* This element holds the zero based queue number of the last | |
116 | * queue to be started. It is used for fairness. | |
117 | */ | |
118 | int next_to_run; | |
119 | ||
120 | // Disk structures we need to pass back | |
799202cb | 121 | struct gendisk *gendisk[CISS_MAX_LUN]; |
1da177e4 LT |
122 | #ifdef CONFIG_CISS_SCSI_TAPE |
123 | void *scsi_ctlr; /* ptr to structure containing scsi related stuff */ | |
3da8b713 | 124 | /* list of block side commands the scsi error handling sucked up */ |
125 | /* and saved for later processing */ | |
1da177e4 | 126 | #endif |
33079b21 | 127 | unsigned char alive; |
b368c9dd AP |
128 | struct list_head scan_list; |
129 | struct completion scan_wait; | |
7fe06326 | 130 | struct device dev; |
1da177e4 LT |
131 | }; |
132 | ||
133 | /* Defining the diffent access_menthods */ | |
134 | /* | |
135 | * Memory mapped FIFO interface (SMART 53xx cards) | |
136 | */ | |
137 | #define SA5_DOORBELL 0x20 | |
138 | #define SA5_REQUEST_PORT_OFFSET 0x40 | |
139 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 | |
140 | #define SA5_REPLY_PORT_OFFSET 0x44 | |
141 | #define SA5_INTR_STATUS 0x30 | |
142 | #define SA5_SCRATCHPAD_OFFSET 0xB0 | |
143 | ||
144 | #define SA5_CTCFG_OFFSET 0xB4 | |
145 | #define SA5_CTMEM_OFFSET 0xB8 | |
146 | ||
147 | #define SA5_INTR_OFF 0x08 | |
148 | #define SA5B_INTR_OFF 0x04 | |
149 | #define SA5_INTR_PENDING 0x08 | |
150 | #define SA5B_INTR_PENDING 0x04 | |
151 | #define FIFO_EMPTY 0xffffffff | |
152 | #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ | |
153 | ||
154 | #define CISS_ERROR_BIT 0x02 | |
155 | ||
156 | #define CCISS_INTR_ON 1 | |
157 | #define CCISS_INTR_OFF 0 | |
158 | /* | |
159 | Send the command to the hardware | |
160 | */ | |
161 | static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c) | |
162 | { | |
163 | #ifdef CCISS_DEBUG | |
164 | printk("Sending %x - down to controller\n", c->busaddr ); | |
165 | #endif /* CCISS_DEBUG */ | |
166 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); | |
167 | h->commands_outstanding++; | |
168 | if ( h->commands_outstanding > h->max_outstanding) | |
169 | h->max_outstanding = h->commands_outstanding; | |
170 | } | |
171 | ||
172 | /* | |
173 | * This card is the opposite of the other cards. | |
174 | * 0 turns interrupts on... | |
175 | * 0x08 turns them off... | |
176 | */ | |
177 | static void SA5_intr_mask(ctlr_info_t *h, unsigned long val) | |
178 | { | |
179 | if (val) | |
180 | { /* Turn interrupts on */ | |
181 | h->interrupts_enabled = 1; | |
182 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
183 | } else /* Turn them off */ | |
184 | { | |
185 | h->interrupts_enabled = 0; | |
186 | writel( SA5_INTR_OFF, | |
187 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
188 | } | |
189 | } | |
190 | /* | |
191 | * This card is the opposite of the other cards. | |
192 | * 0 turns interrupts on... | |
193 | * 0x04 turns them off... | |
194 | */ | |
195 | static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val) | |
196 | { | |
197 | if (val) | |
198 | { /* Turn interrupts on */ | |
199 | h->interrupts_enabled = 1; | |
200 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
201 | } else /* Turn them off */ | |
202 | { | |
203 | h->interrupts_enabled = 0; | |
204 | writel( SA5B_INTR_OFF, | |
205 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
206 | } | |
207 | } | |
208 | /* | |
209 | * Returns true if fifo is full. | |
210 | * | |
211 | */ | |
212 | static unsigned long SA5_fifo_full(ctlr_info_t *h) | |
213 | { | |
214 | if( h->commands_outstanding >= h->max_commands) | |
215 | return(1); | |
216 | else | |
217 | return(0); | |
218 | ||
219 | } | |
220 | /* | |
221 | * returns value read from hardware. | |
222 | * returns FIFO_EMPTY if there is nothing to read | |
223 | */ | |
224 | static unsigned long SA5_completed(ctlr_info_t *h) | |
225 | { | |
226 | unsigned long register_value | |
227 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); | |
228 | if(register_value != FIFO_EMPTY) | |
229 | { | |
230 | h->commands_outstanding--; | |
231 | #ifdef CCISS_DEBUG | |
232 | printk("cciss: Read %lx back from board\n", register_value); | |
233 | #endif /* CCISS_DEBUG */ | |
234 | } | |
235 | #ifdef CCISS_DEBUG | |
236 | else | |
237 | { | |
238 | printk("cciss: FIFO Empty read\n"); | |
239 | } | |
240 | #endif | |
241 | return ( register_value); | |
242 | ||
243 | } | |
244 | /* | |
245 | * Returns true if an interrupt is pending.. | |
246 | */ | |
247 | static unsigned long SA5_intr_pending(ctlr_info_t *h) | |
248 | { | |
249 | unsigned long register_value = | |
250 | readl(h->vaddr + SA5_INTR_STATUS); | |
251 | #ifdef CCISS_DEBUG | |
252 | printk("cciss: intr_pending %lx\n", register_value); | |
253 | #endif /* CCISS_DEBUG */ | |
254 | if( register_value & SA5_INTR_PENDING) | |
255 | return 1; | |
256 | return 0 ; | |
257 | } | |
258 | ||
259 | /* | |
260 | * Returns true if an interrupt is pending.. | |
261 | */ | |
262 | static unsigned long SA5B_intr_pending(ctlr_info_t *h) | |
263 | { | |
264 | unsigned long register_value = | |
265 | readl(h->vaddr + SA5_INTR_STATUS); | |
266 | #ifdef CCISS_DEBUG | |
267 | printk("cciss: intr_pending %lx\n", register_value); | |
268 | #endif /* CCISS_DEBUG */ | |
269 | if( register_value & SA5B_INTR_PENDING) | |
270 | return 1; | |
271 | return 0 ; | |
272 | } | |
273 | ||
274 | ||
275 | static struct access_method SA5_access = { | |
276 | SA5_submit_command, | |
277 | SA5_intr_mask, | |
278 | SA5_fifo_full, | |
279 | SA5_intr_pending, | |
280 | SA5_completed, | |
281 | }; | |
282 | ||
283 | static struct access_method SA5B_access = { | |
284 | SA5_submit_command, | |
285 | SA5B_intr_mask, | |
286 | SA5_fifo_full, | |
287 | SA5B_intr_pending, | |
288 | SA5_completed, | |
289 | }; | |
290 | ||
291 | struct board_type { | |
292 | __u32 board_id; | |
293 | char *product_name; | |
294 | struct access_method *access; | |
f880632f | 295 | int nr_cmds; /* Max cmds this kind of ctlr can handle. */ |
1da177e4 LT |
296 | }; |
297 | ||
ad2b9312 | 298 | #define CCISS_LOCK(i) (&hba[i]->lock) |
1da177e4 LT |
299 | |
300 | #endif /* CCISS_H */ | |
301 |