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NVMe: Remove unused variables
[deliverable/linux.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b3fffdef 45#define NVME_MINORS (1U << MINORBITS)
9d43cf64 46#define NVME_Q_DEPTH 1024
a4aea562 47#define NVME_AQ_DEPTH 64
b60503ba
MW		 48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 50#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 51#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
bd67608a
MW		 57unsigned char nvme_io_timeout = 30;
58module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
2484f407
DM		 61static unsigned char shutdown_timeout = 5;
62module_param(shutdown_timeout, byte, 0644);
63MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
64
b60503ba
MW		 65static int nvme_major;
66module_param(nvme_major, int, 0);
67
b3fffdef
KB		 68static int nvme_char_major;
69module_param(nvme_char_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
1fa6aead 79
b3fffdef
KB		 80static struct class *nvme_class;
81
d4b4ff8e 82static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 83static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 84
4d115420
KB		 85struct async_cmd_info {
86 struct kthread_work work;
87 struct kthread_worker *worker;
a4aea562 88 struct request *req;
4d115420
KB		 89 u32 result;
90 int status;
91 void *ctx;
92};
1fa6aead 93
b60503ba
MW		 94/*
95 * An NVM Express queue. Each device has at least two (one for admin
96 * commands and one for I/O commands).
97 */
98struct nvme_queue {
99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
6222d172 109 s16 cq_vector;
b60503ba
MW		 110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
ac3dd5bd 147 struct nvme_iod iod[0];
e85248e5
MW		 148};
149
ac3dd5bd
JA		 150/*
151 * Max size of iod being embedded in the request payload
152 */
153#define NVME_INT_PAGES 2
154#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
155
156/*
157 * Will slightly overestimate the number of pages needed. This is OK
158 * as it only leads to a small amount of wasted memory for the lifetime of
159 * the I/O.
160 */
161static int nvme_npages(unsigned size, struct nvme_dev *dev)
162{
163 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
164 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
165}
166
167static unsigned int nvme_cmd_size(struct nvme_dev *dev)
168{
169 unsigned int ret = sizeof(struct nvme_cmd_info);
170
171 ret += sizeof(struct nvme_iod);
172 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
173 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
174
175 return ret;
176}
177
a4aea562
MB		 178static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
179 unsigned int hctx_idx)
e85248e5 180{
a4aea562
MB		 181 struct nvme_dev *dev = data;
182 struct nvme_queue *nvmeq = dev->queues[0];
183
184 WARN_ON(nvmeq->hctx);
185 nvmeq->hctx = hctx;
186 hctx->driver_data = nvmeq;
187 return 0;
e85248e5
MW		 188}
189
a4aea562
MB		 190static int nvme_admin_init_request(void *data, struct request *req,
191 unsigned int hctx_idx, unsigned int rq_idx,
192 unsigned int numa_node)
22404274 193{
a4aea562
MB		 194 struct nvme_dev *dev = data;
195 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
196 struct nvme_queue *nvmeq = dev->queues[0];
197
198 BUG_ON(!nvmeq);
199 cmd->nvmeq = nvmeq;
200 return 0;
22404274
KB		 201}
202
2c30540b
JA		 203static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
204{
205 struct nvme_queue *nvmeq = hctx->driver_data;
206
207 nvmeq->hctx = NULL;
208}
209
a4aea562
MB		 210static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
211 unsigned int hctx_idx)
b60503ba 212{
a4aea562
MB		 213 struct nvme_dev *dev = data;
214 struct nvme_queue *nvmeq = dev->queues[
215 (hctx_idx % dev->queue_count) + 1];
b60503ba 216
a4aea562
MB		 217 if (!nvmeq->hctx)
218 nvmeq->hctx = hctx;
219
220 /* nvmeq queues are shared between namespaces. We assume here that
221 * blk-mq map the tags so they match up with the nvme queue tags. */
222 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 223
a4aea562
MB		 224 hctx->driver_data = nvmeq;
225 return 0;
b60503ba
MW		 226}
227
a4aea562
MB		 228static int nvme_init_request(void *data, struct request *req,
229 unsigned int hctx_idx, unsigned int rq_idx,
230 unsigned int numa_node)
b60503ba 231{
a4aea562
MB		 232 struct nvme_dev *dev = data;
233 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
234 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
235
236 BUG_ON(!nvmeq);
237 cmd->nvmeq = nvmeq;
238 return 0;
239}
240
241static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
242 nvme_completion_fn handler)
243{
244 cmd->fn = handler;
245 cmd->ctx = ctx;
246 cmd->aborted = 0;
c917dfe5 247 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 248}
249
ac3dd5bd
JA		 250static void *iod_get_private(struct nvme_iod *iod)
251{
252 return (void *) (iod->private & ~0x1UL);
253}
254
255/*
256 * If bit 0 is set, the iod is embedded in the request payload.
257 */
258static bool iod_should_kfree(struct nvme_iod *iod)
259{
260 return (iod->private & 0x01) == 0;
261}
262
c2f5b650
MW		 263/* Special values must be less than 0x1000 */
264#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 265#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
266#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
267#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 268
edd10d33 269static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 270 struct nvme_completion *cqe)
271{
272 if (ctx == CMD_CTX_CANCELLED)
273 return;
c2f5b650 274 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 275 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 276 "completed id %d twice on queue %d\n",
277 cqe->command_id, le16_to_cpup(&cqe->sq_id));
278 return;
279 }
280 if (ctx == CMD_CTX_INVALID) {
edd10d33 281 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 282 "invalid id %d completed on queue %d\n",
283 cqe->command_id, le16_to_cpup(&cqe->sq_id));
284 return;
285 }
edd10d33 286 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 287}
288
a4aea562 289static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 290{
c2f5b650 291 void *ctx;
b60503ba 292
859361a2 293 if (fn)
a4aea562
MB		 294 *fn = cmd->fn;
295 ctx = cmd->ctx;
296 cmd->fn = special_completion;
297 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 298 return ctx;
b60503ba
MW		 299}
300
a4aea562
MB		 301static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
302 struct nvme_completion *cqe)
3c0cf138 303{
a4aea562 304 struct request *req = ctx;
3c0cf138 305
a4aea562
MB		 306 u32 result = le32_to_cpup(&cqe->result);
307 u16 status = le16_to_cpup(&cqe->status) >> 1;
308
309 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
310 ++nvmeq->dev->event_limit;
311 if (status == NVME_SC_SUCCESS)
312 dev_warn(nvmeq->q_dmadev,
313 "async event result %08x\n", result);
314
9d135bb8 315 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 316}
317
a4aea562
MB		 318static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
319 struct nvme_completion *cqe)
5a92e700 320{
a4aea562
MB		 321 struct request *req = ctx;
322
323 u16 status = le16_to_cpup(&cqe->status) >> 1;
324 u32 result = le32_to_cpup(&cqe->result);
a51afb54 325
9d135bb8 326 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 327
a4aea562
MB		 328 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
329 ++nvmeq->dev->abort_limit;
5a92e700
KB		 330}
331
a4aea562
MB		 332static void async_completion(struct nvme_queue *nvmeq, void *ctx,
333 struct nvme_completion *cqe)
b60503ba 334{
a4aea562
MB		 335 struct async_cmd_info *cmdinfo = ctx;
336 cmdinfo->result = le32_to_cpup(&cqe->result);
337 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
338 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 339 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 340}
341
a4aea562
MB		 342static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
343 unsigned int tag)
b60503ba 344{
a4aea562
MB		 345 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
346 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 347
a4aea562 348 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 349}
350
a4aea562
MB		 351/*
352 * Called with local interrupts disabled and the q_lock held. May not sleep.
353 */
354static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
355 nvme_completion_fn *fn)
4f5099af 356{
a4aea562
MB		 357 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
358 void *ctx;
359 if (tag >= nvmeq->q_depth) {
360 *fn = special_completion;
361 return CMD_CTX_INVALID;
362 }
363 if (fn)
364 *fn = cmd->fn;
365 ctx = cmd->ctx;
366 cmd->fn = special_completion;
367 cmd->ctx = CMD_CTX_COMPLETED;
368 return ctx;
b60503ba
MW		 369}
370
371/**
714a7a22 372 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 373 * @nvmeq: The queue to use
374 * @cmd: The command to send
375 *
376 * Safe to use from interrupt context
377 */
a4aea562 378static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 379{
a4aea562
MB		 380 u16 tail = nvmeq->sq_tail;
381
b60503ba 382 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 383 if (++tail == nvmeq->q_depth)
384 tail = 0;
7547881d 385 writel(tail, nvmeq->q_db);
b60503ba 386 nvmeq->sq_tail = tail;
b60503ba
MW		 387
388 return 0;
389}
390
a4aea562
MB		 391static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
392{
393 unsigned long flags;
394 int ret;
395 spin_lock_irqsave(&nvmeq->q_lock, flags);
396 ret = __nvme_submit_cmd(nvmeq, cmd);
397 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
398 return ret;
399}
400
eca18b23 401static __le64 **iod_list(struct nvme_iod *iod)
e025344c 402{
eca18b23 403 return ((void *)iod) + iod->offset;
e025344c
SMM		 404}
405
ac3dd5bd
JA		 406static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
407 unsigned nseg, unsigned long private)
eca18b23 408{
ac3dd5bd
JA		 409 iod->private = private;
410 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
411 iod->npages = -1;
412 iod->length = nbytes;
413 iod->nents = 0;
eca18b23 414}
b60503ba 415
eca18b23 416static struct nvme_iod *
ac3dd5bd
JA		 417__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
418 unsigned long priv, gfp_t gfp)
b60503ba 419{
eca18b23 420 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 421 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 422 sizeof(struct scatterlist) * nseg, gfp);
423
ac3dd5bd
JA		 424 if (iod)
425 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 426
427 return iod;
b60503ba
MW		 428}
429
ac3dd5bd
JA		 430static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
431 gfp_t gfp)
432{
433 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
434 sizeof(struct nvme_dsm_range);
435 unsigned long mask = 0;
436 struct nvme_iod *iod;
437
438 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
439 size <= NVME_INT_BYTES(dev)) {
440 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
441
442 iod = cmd->iod;
443 mask = 0x01;
444 iod_init(iod, size, rq->nr_phys_segments,
445 (unsigned long) rq | 0x01);
446 return iod;
447 }
448
449 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
450 (unsigned long) rq, gfp);
451}
452
5d0f6131 453void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 454{
1d090624 455 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 456 int i;
457 __le64 **list = iod_list(iod);
458 dma_addr_t prp_dma = iod->first_dma;
459
460 if (iod->npages == 0)
461 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
462 for (i = 0; i < iod->npages; i++) {
463 __le64 *prp_list = list[i];
464 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
465 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
466 prp_dma = next_prp_dma;
467 }
ac3dd5bd
JA		 468
469 if (iod_should_kfree(iod))
470 kfree(iod);
b60503ba
MW		 471}
472
b4ff9c8d
KB		 473static int nvme_error_status(u16 status)
474{
475 switch (status & 0x7ff) {
476 case NVME_SC_SUCCESS:
477 return 0;
478 case NVME_SC_CAP_EXCEEDED:
479 return -ENOSPC;
480 default:
481 return -EIO;
482 }
483}
484
e1e5e564
KB		 485static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
486{
487 if (be32_to_cpu(pi->ref_tag) == v)
488 pi->ref_tag = cpu_to_be32(p);
489}
490
491static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
492{
493 if (be32_to_cpu(pi->ref_tag) == p)
494 pi->ref_tag = cpu_to_be32(v);
495}
496
497/**
498 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
499 *
500 * The virtual start sector is the one that was originally submitted by the
501 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
502 * start sector may be different. Remap protection information to match the
503 * physical LBA on writes, and back to the original seed on reads.
504 *
505 * Type 0 and 3 do not have a ref tag, so no remapping required.
506 */
507static void nvme_dif_remap(struct request *req,
508 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
509{
510 struct nvme_ns *ns = req->rq_disk->private_data;
511 struct bio_integrity_payload *bip;
512 struct t10_pi_tuple *pi;
513 void *p, *pmap;
514 u32 i, nlb, ts, phys, virt;
515
516 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
517 return;
518
519 bip = bio_integrity(req->bio);
520 if (!bip)
521 return;
522
523 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
524 if (!pmap)
525 return;
526
527 p = pmap;
528 virt = bip_get_seed(bip);
529 phys = nvme_block_nr(ns, blk_rq_pos(req));
530 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
531 ts = ns->disk->integrity->tuple_size;
532
533 for (i = 0; i < nlb; i++, virt++, phys++) {
534 pi = (struct t10_pi_tuple *)p;
535 dif_swap(phys, virt, pi);
536 p += ts;
537 }
538 kunmap_atomic(pmap);
539}
540
a4aea562 541static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 542 struct nvme_completion *cqe)
543{
eca18b23 544 struct nvme_iod *iod = ctx;
ac3dd5bd 545 struct request *req = iod_get_private(iod);
a4aea562
MB		 546 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
547
b60503ba
MW		 548 u16 status = le16_to_cpup(&cqe->status) >> 1;
549
edd10d33 550 if (unlikely(status)) {
a4aea562
MB		 551 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
552 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 553 unsigned long flags;
554
a4aea562 555 blk_mq_requeue_request(req);
c9d3bf88
KB		 556 spin_lock_irqsave(req->q->queue_lock, flags);
557 if (!blk_queue_stopped(req->q))
558 blk_mq_kick_requeue_list(req->q);
559 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 560 return;
561 }
a4aea562
MB		 562 req->errors = nvme_error_status(status);
563 } else
564 req->errors = 0;
565
566 if (cmd_rq->aborted)
567 dev_warn(&nvmeq->dev->pci_dev->dev,
568 "completing aborted command with status:%04x\n",
569 status);
570
e1e5e564 571 if (iod->nents) {
a4aea562
MB		 572 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
573 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 574 if (blk_integrity_rq(req)) {
575 if (!rq_data_dir(req))
576 nvme_dif_remap(req, nvme_dif_complete);
577 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1,
578 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
579 }
580 }
edd10d33 581 nvme_free_iod(nvmeq->dev, iod);
3291fa57 582
a4aea562 583 blk_mq_complete_request(req);
b60503ba
MW		 584}
585
184d2944 586/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 587int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
588 gfp_t gfp)
ff22b54f 589{
99802a7a 590 struct dma_pool *pool;
eca18b23
MW		 591 int length = total_len;
592 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 593 int dma_len = sg_dma_len(sg);
594 u64 dma_addr = sg_dma_address(sg);
595 int offset = offset_in_page(dma_addr);
e025344c 596 __le64 *prp_list;
eca18b23 597 __le64 **list = iod_list(iod);
e025344c 598 dma_addr_t prp_dma;
eca18b23 599 int nprps, i;
1d090624 600 u32 page_size = dev->page_size;
ff22b54f 601
1d090624 602 length -= (page_size - offset);
ff22b54f 603 if (length <= 0)
eca18b23 604 return total_len;
ff22b54f 605
1d090624 606 dma_len -= (page_size - offset);
ff22b54f 607 if (dma_len) {
1d090624 608 dma_addr += (page_size - offset);
ff22b54f
MW		 609 } else {
610 sg = sg_next(sg);
611 dma_addr = sg_dma_address(sg);
612 dma_len = sg_dma_len(sg);
613 }
614
1d090624 615 if (length <= page_size) {
edd10d33 616 iod->first_dma = dma_addr;
eca18b23 617 return total_len;
e025344c
SMM		 618 }
619
1d090624 620 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 621 if (nprps <= (256 / 8)) {
622 pool = dev->prp_small_pool;
eca18b23 623 iod->npages = 0;
99802a7a
MW		 624 } else {
625 pool = dev->prp_page_pool;
eca18b23 626 iod->npages = 1;
99802a7a
MW		 627 }
628
b77954cb
MW		 629 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
630 if (!prp_list) {
edd10d33 631 iod->first_dma = dma_addr;
eca18b23 632 iod->npages = -1;
1d090624 633 return (total_len - length) + page_size;
b77954cb 634 }
eca18b23
MW		 635 list[0] = prp_list;
636 iod->first_dma = prp_dma;
e025344c
SMM		 637 i = 0;
638 for (;;) {
1d090624 639 if (i == page_size >> 3) {
e025344c 640 __le64 *old_prp_list = prp_list;
b77954cb 641 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 642 if (!prp_list)
643 return total_len - length;
644 list[iod->npages++] = prp_list;
7523d834
MW		 645 prp_list[0] = old_prp_list[i - 1];
646 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
647 i = 1;
e025344c
SMM		 648 }
649 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 650 dma_len -= page_size;
651 dma_addr += page_size;
652 length -= page_size;
e025344c
SMM		 653 if (length <= 0)
654 break;
655 if (dma_len > 0)
656 continue;
657 BUG_ON(dma_len < 0);
658 sg = sg_next(sg);
659 dma_addr = sg_dma_address(sg);
660 dma_len = sg_dma_len(sg);
ff22b54f
MW		 661 }
662
eca18b23 663 return total_len;
ff22b54f
MW		 664}
665
a4aea562
MB		 666/*
667 * We reuse the small pool to allocate the 16-byte range here as it is not
668 * worth having a special pool for these or additional cases to handle freeing
669 * the iod.
670 */
671static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
672 struct request *req, struct nvme_iod *iod)
0e5e4f0e 673{
edd10d33
KB		 674 struct nvme_dsm_range *range =
675 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 676 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
677
0e5e4f0e 678 range->cattr = cpu_to_le32(0);
a4aea562
MB		 679 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
680 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 681
682 memset(cmnd, 0, sizeof(*cmnd));
683 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 684 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 685 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
686 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
687 cmnd->dsm.nr = 0;
688 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
689
690 if (++nvmeq->sq_tail == nvmeq->q_depth)
691 nvmeq->sq_tail = 0;
692 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 693}
694
a4aea562 695static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 696 int cmdid)
697{
698 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
699
700 memset(cmnd, 0, sizeof(*cmnd));
701 cmnd->common.opcode = nvme_cmd_flush;
702 cmnd->common.command_id = cmdid;
703 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
704
705 if (++nvmeq->sq_tail == nvmeq->q_depth)
706 nvmeq->sq_tail = 0;
707 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 708}
709
a4aea562
MB		 710static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
711 struct nvme_ns *ns)
b60503ba 712{
ac3dd5bd 713 struct request *req = iod_get_private(iod);
ff22b54f 714 struct nvme_command *cmnd;
a4aea562
MB		 715 u16 control = 0;
716 u32 dsmgmt = 0;
00df5cb4 717
a4aea562 718 if (req->cmd_flags & REQ_FUA)
b60503ba 719 control |= NVME_RW_FUA;
a4aea562 720 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 721 control |= NVME_RW_LR;
722
a4aea562 723 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 724 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
725
ff22b54f 726 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 727 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 728
a4aea562
MB		 729 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
730 cmnd->rw.command_id = req->tag;
ff22b54f 731 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 732 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
733 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 734 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
735 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 736
737 if (blk_integrity_rq(req)) {
738 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
739 switch (ns->pi_type) {
740 case NVME_NS_DPS_PI_TYPE3:
741 control |= NVME_RW_PRINFO_PRCHK_GUARD;
742 break;
743 case NVME_NS_DPS_PI_TYPE1:
744 case NVME_NS_DPS_PI_TYPE2:
745 control |= NVME_RW_PRINFO_PRCHK_GUARD |
746 NVME_RW_PRINFO_PRCHK_REF;
747 cmnd->rw.reftag = cpu_to_le32(
748 nvme_block_nr(ns, blk_rq_pos(req)));
749 break;
750 }
751 } else if (ns->ms)
752 control |= NVME_RW_PRINFO_PRACT;
753
ff22b54f
MW		 754 cmnd->rw.control = cpu_to_le16(control);
755 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 756
b60503ba
MW		 757 if (++nvmeq->sq_tail == nvmeq->q_depth)
758 nvmeq->sq_tail = 0;
7547881d 759 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 760
1974b1ae 761 return 0;
edd10d33
KB		 762}
763
a4aea562
MB		 764static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
765 const struct blk_mq_queue_data *bd)
edd10d33 766{
a4aea562
MB		 767 struct nvme_ns *ns = hctx->queue->queuedata;
768 struct nvme_queue *nvmeq = hctx->driver_data;
769 struct request *req = bd->rq;
770 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 771 struct nvme_iod *iod;
a4aea562 772 enum dma_data_direction dma_dir;
edd10d33 773
e1e5e564
KB		 774 /*
775 * If formated with metadata, require the block layer provide a buffer
776 * unless this namespace is formated such that the metadata can be
777 * stripped/generated by the controller with PRACT=1.
778 */
779 if (ns->ms && !blk_integrity_rq(req)) {
780 if (!(ns->pi_type && ns->ms == 8)) {
781 req->errors = -EFAULT;
782 blk_mq_complete_request(req);
783 return BLK_MQ_RQ_QUEUE_OK;
784 }
785 }
786
ac3dd5bd 787 iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
edd10d33 788 if (!iod)
fe54303e 789 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 790
a4aea562 791 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 792 void *range;
793 /*
794 * We reuse the small pool to allocate the 16-byte range here
795 * as it is not worth having a special pool for these or
796 * additional cases to handle freeing the iod.
797 */
798 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
799 GFP_ATOMIC,
800 &iod->first_dma);
a4aea562 801 if (!range)
fe54303e 802 goto retry_cmd;
edd10d33
KB		 803 iod_list(iod)[0] = (__le64 *)range;
804 iod->npages = 0;
ac3dd5bd 805 } else if (req->nr_phys_segments) {
a4aea562
MB		 806 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
807
ac3dd5bd 808 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 809 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 810 if (!iod->nents)
811 goto error_cmd;
a4aea562
MB		 812
813 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 814 goto retry_cmd;
a4aea562 815
fe54303e
JA		 816 if (blk_rq_bytes(req) !=
817 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
818 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
819 iod->nents, dma_dir);
820 goto retry_cmd;
821 }
e1e5e564
KB		 822 if (blk_integrity_rq(req)) {
823 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
824 goto error_cmd;
825
826 sg_init_table(iod->meta_sg, 1);
827 if (blk_rq_map_integrity_sg(
828 req->q, req->bio, iod->meta_sg) != 1)
829 goto error_cmd;
830
831 if (rq_data_dir(req))
832 nvme_dif_remap(req, nvme_dif_prep);
833
834 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
835 goto error_cmd;
836 }
edd10d33 837 }
1974b1ae 838
9af8785a 839 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 840 spin_lock_irq(&nvmeq->q_lock);
841 if (req->cmd_flags & REQ_DISCARD)
842 nvme_submit_discard(nvmeq, ns, req, iod);
843 else if (req->cmd_flags & REQ_FLUSH)
844 nvme_submit_flush(nvmeq, ns, req->tag);
845 else
846 nvme_submit_iod(nvmeq, iod, ns);
847
848 nvme_process_cq(nvmeq);
849 spin_unlock_irq(&nvmeq->q_lock);
850 return BLK_MQ_RQ_QUEUE_OK;
851
fe54303e
JA		 852 error_cmd:
853 nvme_free_iod(nvmeq->dev, iod);
854 return BLK_MQ_RQ_QUEUE_ERROR;
855 retry_cmd:
eca18b23 856 nvme_free_iod(nvmeq->dev, iod);
fe54303e 857 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 858}
859
e9539f47 860static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 861{
82123460 862 u16 head, phase;
b60503ba 863
b60503ba 864 head = nvmeq->cq_head;
82123460 865 phase = nvmeq->cq_phase;
b60503ba
MW		 866
867 for (;;) {
c2f5b650
MW		 868 void *ctx;
869 nvme_completion_fn fn;
b60503ba 870 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 871 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 872 break;
873 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
874 if (++head == nvmeq->q_depth) {
875 head = 0;
82123460 876 phase = !phase;
b60503ba 877 }
a4aea562 878 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 879 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 880 }
881
882 /* If the controller ignores the cq head doorbell and continuously
883 * writes to the queue, it is theoretically possible to wrap around
884 * the queue twice and mistakenly return IRQ_NONE. Linux only
885 * requires that 0.1% of your interrupts are handled, so this isn't
886 * a big problem.
887 */
82123460 888 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 889 return 0;
b60503ba 890
b80d5ccc 891 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 892 nvmeq->cq_head = head;
82123460 893 nvmeq->cq_phase = phase;
b60503ba 894
e9539f47
MW		 895 nvmeq->cqe_seen = 1;
896 return 1;
b60503ba
MW		 897}
898
a4aea562
MB		 899/* Admin queue isn't initialized as a request queue. If at some point this
900 * happens anyway, make sure to notify the user */
901static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
902 const struct blk_mq_queue_data *bd)
7d822457 903{
a4aea562
MB		 904 WARN_ON_ONCE(1);
905 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 906}
907
b60503ba 908static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 909{
910 irqreturn_t result;
911 struct nvme_queue *nvmeq = data;
912 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 913 nvme_process_cq(nvmeq);
914 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
915 nvmeq->cqe_seen = 0;
58ffacb5
MW		 916 spin_unlock(&nvmeq->q_lock);
917 return result;
918}
919
920static irqreturn_t nvme_irq_check(int irq, void *data)
921{
922 struct nvme_queue *nvmeq = data;
923 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
924 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
925 return IRQ_NONE;
926 return IRQ_WAKE_THREAD;
927}
928
a4aea562
MB		 929static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
930 cmd_info)
3c0cf138
MW		 931{
932 spin_lock_irq(&nvmeq->q_lock);
a4aea562 933 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 934 spin_unlock_irq(&nvmeq->q_lock);
935}
936
c2f5b650
MW		 937struct sync_cmd_info {
938 struct task_struct *task;
939 u32 result;
940 int status;
941};
942
edd10d33 943static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 944 struct nvme_completion *cqe)
945{
946 struct sync_cmd_info *cmdinfo = ctx;
947 cmdinfo->result = le32_to_cpup(&cqe->result);
948 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
949 wake_up_process(cmdinfo->task);
950}
951
b60503ba
MW		 952/*
953 * Returns 0 on success. If the result is negative, it's a Linux error code;
954 * if the result is positive, it's an NVM Express status code
955 */
a4aea562 956static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 957 u32 *result, unsigned timeout)
b60503ba 958{
a4aea562 959 int ret;
b60503ba 960 struct sync_cmd_info cmdinfo;
a4aea562
MB		 961 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
962 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 963
964 cmdinfo.task = current;
965 cmdinfo.status = -EINTR;
966
a4aea562
MB		 967 cmd->common.command_id = req->tag;
968
969 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 970
3c0cf138 971 set_current_state(TASK_KILLABLE);
4f5099af
KB		 972 ret = nvme_submit_cmd(nvmeq, cmd);
973 if (ret) {
a4aea562 974 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 975 set_current_state(TASK_RUNNING);
4f5099af 976 }
849c6e77 977 ret = schedule_timeout(timeout);
b60503ba 978
849c6e77
JA		 979 /*
980 * Ensure that sync_completion has either run, or that it will
981 * never run.
982 */
983 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
984
985 /*
986 * We never got the completion
987 */
988 if (cmdinfo.status == -EINTR)
3c0cf138 989 return -EINTR;
3c0cf138 990
b60503ba
MW		 991 if (result)
992 *result = cmdinfo.result;
993
994 return cmdinfo.status;
995}
996
a4aea562
MB		 997static int nvme_submit_async_admin_req(struct nvme_dev *dev)
998{
999 struct nvme_queue *nvmeq = dev->queues[0];
1000 struct nvme_command c;
1001 struct nvme_cmd_info *cmd_info;
1002 struct request *req;
1003
6dcc0cf6 1004 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 1005 if (IS_ERR(req))
1006 return PTR_ERR(req);
a4aea562 1007
c917dfe5 1008 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562
MB		 1009 cmd_info = blk_mq_rq_to_pdu(req);
1010 nvme_set_info(cmd_info, req, async_req_completion);
1011
1012 memset(&c, 0, sizeof(c));
1013 c.common.opcode = nvme_admin_async_event;
1014 c.common.command_id = req->tag;
1015
1016 return __nvme_submit_cmd(nvmeq, &c);
1017}
1018
1019static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1020 struct nvme_command *cmd,
1021 struct async_cmd_info *cmdinfo, unsigned timeout)
1022{
a4aea562
MB		 1023 struct nvme_queue *nvmeq = dev->queues[0];
1024 struct request *req;
1025 struct nvme_cmd_info *cmd_rq;
4d115420 1026
a4aea562 1027 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1028 if (IS_ERR(req))
1029 return PTR_ERR(req);
a4aea562
MB		 1030
1031 req->timeout = timeout;
1032 cmd_rq = blk_mq_rq_to_pdu(req);
1033 cmdinfo->req = req;
1034 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1035 cmdinfo->status = -EINTR;
a4aea562
MB		 1036
1037 cmd->common.command_id = req->tag;
1038
4f5099af 1039 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1040}
1041
a64e6bb4 1042static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 1043 u32 *result, unsigned timeout)
b60503ba 1044{
a4aea562
MB		 1045 int res;
1046 struct request *req;
1047
1048 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 1049 if (IS_ERR(req))
1050 return PTR_ERR(req);
a4aea562 1051 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 1052 blk_mq_free_request(req);
a4aea562 1053 return res;
4f5099af
KB		 1054}
1055
a4aea562 1056int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 1057 u32 *result)
1058{
a4aea562 1059 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 1060}
1061
a4aea562
MB		 1062int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1063 struct nvme_command *cmd, u32 *result)
4d115420 1064{
a4aea562
MB		 1065 int res;
1066 struct request *req;
1067
1068 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
1069 false);
97fe3832
JA		 1070 if (IS_ERR(req))
1071 return PTR_ERR(req);
a4aea562 1072 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 1073 blk_mq_free_request(req);
a4aea562 1074 return res;
4d115420
KB		 1075}
1076
b60503ba
MW		 1077static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1078{
b60503ba
MW		 1079 struct nvme_command c;
1080
1081 memset(&c, 0, sizeof(c));
1082 c.delete_queue.opcode = opcode;
1083 c.delete_queue.qid = cpu_to_le16(id);
1084
a4aea562 1085 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1086}
1087
1088static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1089 struct nvme_queue *nvmeq)
1090{
b60503ba
MW		 1091 struct nvme_command c;
1092 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1093
1094 memset(&c, 0, sizeof(c));
1095 c.create_cq.opcode = nvme_admin_create_cq;
1096 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1097 c.create_cq.cqid = cpu_to_le16(qid);
1098 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1099 c.create_cq.cq_flags = cpu_to_le16(flags);
1100 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1101
a4aea562 1102 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1103}
1104
1105static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1106 struct nvme_queue *nvmeq)
1107{
b60503ba
MW		 1108 struct nvme_command c;
1109 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1110
1111 memset(&c, 0, sizeof(c));
1112 c.create_sq.opcode = nvme_admin_create_sq;
1113 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1114 c.create_sq.sqid = cpu_to_le16(qid);
1115 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1116 c.create_sq.sq_flags = cpu_to_le16(flags);
1117 c.create_sq.cqid = cpu_to_le16(qid);
1118
a4aea562 1119 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 1120}
1121
1122static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1123{
1124 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1125}
1126
1127static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1128{
1129 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1130}
1131
5d0f6131 1132int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1133 dma_addr_t dma_addr)
1134{
1135 struct nvme_command c;
1136
1137 memset(&c, 0, sizeof(c));
1138 c.identify.opcode = nvme_admin_identify;
1139 c.identify.nsid = cpu_to_le32(nsid);
1140 c.identify.prp1 = cpu_to_le64(dma_addr);
1141 c.identify.cns = cpu_to_le32(cns);
1142
1143 return nvme_submit_admin_cmd(dev, &c, NULL);
1144}
1145
5d0f6131 1146int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1147 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1148{
1149 struct nvme_command c;
1150
1151 memset(&c, 0, sizeof(c));
1152 c.features.opcode = nvme_admin_get_features;
a42cecce 1153 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1154 c.features.prp1 = cpu_to_le64(dma_addr);
1155 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1156
08df1e05 1157 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1158}
1159
5d0f6131
VV		 1160int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1161 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1162{
1163 struct nvme_command c;
1164
1165 memset(&c, 0, sizeof(c));
1166 c.features.opcode = nvme_admin_set_features;
1167 c.features.prp1 = cpu_to_le64(dma_addr);
1168 c.features.fid = cpu_to_le32(fid);
1169 c.features.dword11 = cpu_to_le32(dword11);
1170
bc5fc7e4
MW		 1171 return nvme_submit_admin_cmd(dev, &c, result);
1172}
1173
c30341dc 1174/**
a4aea562 1175 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1176 *
1177 * Schedule controller reset if the command was already aborted once before and
1178 * still hasn't been returned to the driver, or if this is the admin queue.
1179 */
a4aea562 1180static void nvme_abort_req(struct request *req)
c30341dc 1181{
a4aea562
MB		 1182 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1183 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1184 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1185 struct request *abort_req;
1186 struct nvme_cmd_info *abort_cmd;
1187 struct nvme_command cmd;
c30341dc 1188
a4aea562 1189 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1190 unsigned long flags;
1191
1192 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1193 if (work_busy(&dev->reset_work))
7a509a6b 1194 goto out;
c30341dc
KB		 1195 list_del_init(&dev->node);
1196 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1197 "I/O %d QID %d timeout, reset controller\n",
1198 req->tag, nvmeq->qid);
9ca97374 1199 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1200 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1201 out:
1202 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1203 return;
1204 }
1205
1206 if (!dev->abort_limit)
1207 return;
1208
a4aea562
MB		 1209 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1210 false);
9f173b33 1211 if (IS_ERR(abort_req))
c30341dc
KB		 1212 return;
1213
a4aea562
MB		 1214 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1215 nvme_set_info(abort_cmd, abort_req, abort_completion);
1216
c30341dc
KB		 1217 memset(&cmd, 0, sizeof(cmd));
1218 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1219 cmd.abort.cid = req->tag;
c30341dc 1220 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1221 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1222
1223 --dev->abort_limit;
a4aea562 1224 cmd_rq->aborted = 1;
c30341dc 1225
a4aea562 1226 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1227 nvmeq->qid);
a4aea562
MB		 1228 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1229 dev_warn(nvmeq->q_dmadev,
1230 "Could not abort I/O %d QID %d",
1231 req->tag, nvmeq->qid);
c87fd540 1232 blk_mq_free_request(abort_req);
a4aea562 1233 }
c30341dc
KB		 1234}
1235
a4aea562
MB		 1236static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1237 struct request *req, void *data, bool reserved)
a09115b2 1238{
a4aea562
MB		 1239 struct nvme_queue *nvmeq = data;
1240 void *ctx;
1241 nvme_completion_fn fn;
1242 struct nvme_cmd_info *cmd;
cef6a948
KB		 1243 struct nvme_completion cqe;
1244
1245 if (!blk_mq_request_started(req))
1246 return;
a09115b2 1247
a4aea562 1248 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1249
a4aea562
MB		 1250 if (cmd->ctx == CMD_CTX_CANCELLED)
1251 return;
1252
cef6a948
KB		 1253 if (blk_queue_dying(req->q))
1254 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1255 else
1256 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1257
1258
a4aea562
MB		 1259 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1260 req->tag, nvmeq->qid);
1261 ctx = cancel_cmd_info(cmd, &fn);
1262 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1263}
1264
a4aea562 1265static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1266{
a4aea562
MB		 1267 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1268 struct nvme_queue *nvmeq = cmd->nvmeq;
1269
1270 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1271 nvmeq->qid);
7a509a6b 1272 spin_lock_irq(&nvmeq->q_lock);
07836e65 1273 nvme_abort_req(req);
7a509a6b 1274 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1275
07836e65
KB		 1276 /*
1277 * The aborted req will be completed on receiving the abort req.
1278 * We enable the timer again. If hit twice, it'll cause a device reset,
1279 * as the device then is in a faulty state.
1280 */
1281 return BLK_EH_RESET_TIMER;
a4aea562 1282}
22404274 1283
a4aea562
MB		 1284static void nvme_free_queue(struct nvme_queue *nvmeq)
1285{
9e866774
MW		 1286 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1287 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1288 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1289 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1290 kfree(nvmeq);
1291}
1292
a1a5ef99 1293static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1294{
1295 int i;
1296
a1a5ef99 1297 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1298 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1299 dev->queue_count--;
a4aea562 1300 dev->queues[i] = NULL;
f435c282 1301 nvme_free_queue(nvmeq);
121c7ad4 1302 }
22404274
KB		 1303}
1304
4d115420
KB		 1305/**
1306 * nvme_suspend_queue - put queue into suspended state
1307 * @nvmeq - queue to suspend
4d115420
KB		 1308 */
1309static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1310{
2b25d981 1311 int vector;
b60503ba 1312
a09115b2 1313 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1314 if (nvmeq->cq_vector == -1) {
1315 spin_unlock_irq(&nvmeq->q_lock);
1316 return 1;
1317 }
1318 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1319 nvmeq->dev->online_queues--;
2b25d981 1320 nvmeq->cq_vector = -1;
a09115b2
MW		 1321 spin_unlock_irq(&nvmeq->q_lock);
1322
aba2080f
MW		 1323 irq_set_affinity_hint(vector, NULL);
1324 free_irq(vector, nvmeq);
b60503ba 1325
4d115420
KB		 1326 return 0;
1327}
b60503ba 1328
4d115420
KB		 1329static void nvme_clear_queue(struct nvme_queue *nvmeq)
1330{
a4aea562
MB		 1331 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1332
22404274 1333 spin_lock_irq(&nvmeq->q_lock);
a4aea562
MB		 1334 if (hctx && hctx->tags)
1335 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1336 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1337}
1338
4d115420
KB		 1339static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1340{
a4aea562 1341 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1342
1343 if (!nvmeq)
1344 return;
1345 if (nvme_suspend_queue(nvmeq))
1346 return;
1347
0e53d180
KB		 1348 /* Don't tell the adapter to delete the admin queue.
1349 * Don't tell a removed adapter to delete IO queues. */
1350 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1351 adapter_delete_sq(dev, qid);
1352 adapter_delete_cq(dev, qid);
1353 }
0fb59cbc
KB		 1354 if (!qid && dev->admin_q)
1355 blk_mq_freeze_queue_start(dev->admin_q);
07836e65
KB		 1356
1357 spin_lock_irq(&nvmeq->q_lock);
1358 nvme_process_cq(nvmeq);
1359 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1360}
1361
1362static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1363 int depth)
b60503ba
MW		 1364{
1365 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1366 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1367 if (!nvmeq)
1368 return NULL;
1369
4d51abf9
JP		 1370 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1371 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1372 if (!nvmeq->cqes)
1373 goto free_nvmeq;
b60503ba
MW		 1374
1375 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1376 &nvmeq->sq_dma_addr, GFP_KERNEL);
1377 if (!nvmeq->sq_cmds)
1378 goto free_cqdma;
1379
1380 nvmeq->q_dmadev = dmadev;
091b6092 1381 nvmeq->dev = dev;
3193f07b
MW		 1382 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1383 dev->instance, qid);
b60503ba
MW		 1384 spin_lock_init(&nvmeq->q_lock);
1385 nvmeq->cq_head = 0;
82123460 1386 nvmeq->cq_phase = 1;
b80d5ccc 1387 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1388 nvmeq->q_depth = depth;
c30341dc 1389 nvmeq->qid = qid;
22404274 1390 dev->queue_count++;
a4aea562 1391 dev->queues[qid] = nvmeq;
b60503ba
MW		 1392
1393 return nvmeq;
1394
1395 free_cqdma:
68b8eca5 1396 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1397 nvmeq->cq_dma_addr);
1398 free_nvmeq:
1399 kfree(nvmeq);
1400 return NULL;
1401}
1402
3001082c
MW		 1403static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1404 const char *name)
1405{
58ffacb5
MW		 1406 if (use_threaded_interrupts)
1407 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1408 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1409 name, nvmeq);
3001082c 1410 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1411 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1412}
1413
22404274 1414static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1415{
22404274 1416 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1417
7be50e93 1418 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1419 nvmeq->sq_tail = 0;
1420 nvmeq->cq_head = 0;
1421 nvmeq->cq_phase = 1;
b80d5ccc 1422 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1423 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1424 dev->online_queues++;
7be50e93 1425 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1426}
1427
1428static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1429{
1430 struct nvme_dev *dev = nvmeq->dev;
1431 int result;
3f85d50b 1432
2b25d981 1433 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1434 result = adapter_alloc_cq(dev, qid, nvmeq);
1435 if (result < 0)
22404274 1436 return result;
b60503ba
MW		 1437
1438 result = adapter_alloc_sq(dev, qid, nvmeq);
1439 if (result < 0)
1440 goto release_cq;
1441
3193f07b 1442 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1443 if (result < 0)
1444 goto release_sq;
1445
22404274 1446 nvme_init_queue(nvmeq, qid);
22404274 1447 return result;
b60503ba
MW		 1448
1449 release_sq:
1450 adapter_delete_sq(dev, qid);
1451 release_cq:
1452 adapter_delete_cq(dev, qid);
22404274 1453 return result;
b60503ba
MW		 1454}
1455
ba47e386
MW		 1456static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1457{
1458 unsigned long timeout;
1459 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1460
1461 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1462
1463 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1464 msleep(100);
1465 if (fatal_signal_pending(current))
1466 return -EINTR;
1467 if (time_after(jiffies, timeout)) {
1468 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1469 "Device not ready; aborting %s\n", enabled ?
1470 "initialisation" : "reset");
ba47e386
MW		 1471 return -ENODEV;
1472 }
1473 }
1474
1475 return 0;
1476}
1477
1478/*
1479 * If the device has been passed off to us in an enabled state, just clear
1480 * the enabled bit. The spec says we should set the 'shutdown notification
1481 * bits', but doing so may cause the device to complete commands to the
1482 * admin queue ... and we don't know what memory that might be pointing at!
1483 */
1484static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1485{
01079522
DM		 1486 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1487 dev->ctrl_config &= ~NVME_CC_ENABLE;
1488 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1489
ba47e386
MW		 1490 return nvme_wait_ready(dev, cap, false);
1491}
1492
1493static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1494{
01079522
DM		 1495 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1496 dev->ctrl_config |= NVME_CC_ENABLE;
1497 writel(dev->ctrl_config, &dev->bar->cc);
1498
ba47e386
MW		 1499 return nvme_wait_ready(dev, cap, true);
1500}
1501
1894d8f1
KB		 1502static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1503{
1504 unsigned long timeout;
1894d8f1 1505
01079522
DM		 1506 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1507 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1508
1509 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1510
2484f407 1511 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1512 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1513 NVME_CSTS_SHST_CMPLT) {
1514 msleep(100);
1515 if (fatal_signal_pending(current))
1516 return -EINTR;
1517 if (time_after(jiffies, timeout)) {
1518 dev_err(&dev->pci_dev->dev,
1519 "Device shutdown incomplete; abort shutdown\n");
1520 return -ENODEV;
1521 }
1522 }
1523
1524 return 0;
1525}
1526
a4aea562
MB		 1527static struct blk_mq_ops nvme_mq_admin_ops = {
1528 .queue_rq = nvme_admin_queue_rq,
1529 .map_queue = blk_mq_map_queue,
1530 .init_hctx = nvme_admin_init_hctx,
2c30540b 1531 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1532 .init_request = nvme_admin_init_request,
1533 .timeout = nvme_timeout,
1534};
1535
1536static struct blk_mq_ops nvme_mq_ops = {
1537 .queue_rq = nvme_queue_rq,
1538 .map_queue = blk_mq_map_queue,
1539 .init_hctx = nvme_init_hctx,
2c30540b 1540 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1541 .init_request = nvme_init_request,
1542 .timeout = nvme_timeout,
1543};
1544
ea191d2f
KB		 1545static void nvme_dev_remove_admin(struct nvme_dev *dev)
1546{
1547 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1548 blk_cleanup_queue(dev->admin_q);
1549 blk_mq_free_tag_set(&dev->admin_tagset);
1550 }
1551}
1552
a4aea562
MB		 1553static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1554{
1555 if (!dev->admin_q) {
1556 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1557 dev->admin_tagset.nr_hw_queues = 1;
1558 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1559 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1560 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
ac3dd5bd 1561 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1562 dev->admin_tagset.driver_data = dev;
1563
1564 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1565 return -ENOMEM;
1566
1567 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1568 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1569 blk_mq_free_tag_set(&dev->admin_tagset);
1570 return -ENOMEM;
1571 }
ea191d2f
KB		 1572 if (!blk_get_queue(dev->admin_q)) {
1573 nvme_dev_remove_admin(dev);
1574 return -ENODEV;
1575 }
0fb59cbc
KB		 1576 } else
1577 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1578
1579 return 0;
1580}
1581
8d85fce7 1582static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1583{
ba47e386 1584 int result;
b60503ba 1585 u32 aqa;
ba47e386 1586 u64 cap = readq(&dev->bar->cap);
b60503ba 1587 struct nvme_queue *nvmeq;
1d090624
KB		 1588 unsigned page_shift = PAGE_SHIFT;
1589 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1590 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1591
1592 if (page_shift < dev_page_min) {
1593 dev_err(&dev->pci_dev->dev,
1594 "Minimum device page size (%u) too large for "
1595 "host (%u)\n", 1 << dev_page_min,
1596 1 << page_shift);
1597 return -ENODEV;
1598 }
1599 if (page_shift > dev_page_max) {
1600 dev_info(&dev->pci_dev->dev,
1601 "Device maximum page size (%u) smaller than "
1602 "host (%u); enabling work-around\n",
1603 1 << dev_page_max, 1 << page_shift);
1604 page_shift = dev_page_max;
1605 }
b60503ba 1606
ba47e386
MW		 1607 result = nvme_disable_ctrl(dev, cap);
1608 if (result < 0)
1609 return result;
b60503ba 1610
a4aea562 1611 nvmeq = dev->queues[0];
cd638946 1612 if (!nvmeq) {
2b25d981 1613 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1614 if (!nvmeq)
1615 return -ENOMEM;
cd638946 1616 }
b60503ba
MW		 1617
1618 aqa = nvmeq->q_depth - 1;
1619 aqa |= aqa << 16;
1620
1d090624
KB		 1621 dev->page_size = 1 << page_shift;
1622
01079522 1623 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1624 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1625 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1626 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1627
1628 writel(aqa, &dev->bar->aqa);
1629 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1630 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1631
ba47e386 1632 result = nvme_enable_ctrl(dev, cap);
025c557a 1633 if (result)
a4aea562
MB		 1634 goto free_nvmeq;
1635
2b25d981 1636 nvmeq->cq_vector = 0;
3193f07b 1637 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1638 if (result)
0fb59cbc 1639 goto free_nvmeq;
025c557a 1640
b60503ba 1641 return result;
a4aea562 1642
a4aea562
MB		 1643 free_nvmeq:
1644 nvme_free_queues(dev, 0);
1645 return result;
b60503ba
MW		 1646}
1647
5d0f6131 1648struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1649 unsigned long addr, unsigned length)
b60503ba 1650{
36c14ed9 1651 int i, err, count, nents, offset;
7fc3cdab
MW		 1652 struct scatterlist *sg;
1653 struct page **pages;
eca18b23 1654 struct nvme_iod *iod;
36c14ed9
MW		 1655
1656 if (addr & 3)
eca18b23 1657 return ERR_PTR(-EINVAL);
5460fc03 1658 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1659 return ERR_PTR(-EINVAL);
7fc3cdab 1660
36c14ed9 1661 offset = offset_in_page(addr);
7fc3cdab
MW		 1662 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1663 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1664 if (!pages)
1665 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1666
1667 err = get_user_pages_fast(addr, count, 1, pages);
1668 if (err < count) {
1669 count = err;
1670 err = -EFAULT;
1671 goto put_pages;
1672 }
7fc3cdab 1673
6808c5fb 1674 err = -ENOMEM;
ac3dd5bd 1675 iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
6808c5fb
S		 1676 if (!iod)
1677 goto put_pages;
1678
eca18b23 1679 sg = iod->sg;
36c14ed9 1680 sg_init_table(sg, count);
d0ba1e49
MW		 1681 for (i = 0; i < count; i++) {
1682 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1683 min_t(unsigned, length, PAGE_SIZE - offset),
1684 offset);
d0ba1e49
MW		 1685 length -= (PAGE_SIZE - offset);
1686 offset = 0;
7fc3cdab 1687 }
fe304c43 1688 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1689 iod->nents = count;
7fc3cdab 1690
7fc3cdab
MW		 1691 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1692 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1693 if (!nents)
eca18b23 1694 goto free_iod;
b60503ba 1695
7fc3cdab 1696 kfree(pages);
eca18b23 1697 return iod;
b60503ba 1698
eca18b23
MW		 1699 free_iod:
1700 kfree(iod);
7fc3cdab
MW		 1701 put_pages:
1702 for (i = 0; i < count; i++)
1703 put_page(pages[i]);
1704 kfree(pages);
eca18b23 1705 return ERR_PTR(err);
7fc3cdab 1706}
b60503ba 1707
5d0f6131 1708void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1709 struct nvme_iod *iod)
7fc3cdab 1710{
1c2ad9fa 1711 int i;
b60503ba 1712
1c2ad9fa
MW		 1713 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1714 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1715
1c2ad9fa
MW		 1716 for (i = 0; i < iod->nents; i++)
1717 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1718}
b60503ba 1719
a53295b6
MW		 1720static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1721{
1722 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1723 struct nvme_user_io io;
1724 struct nvme_command c;
f410c680
KB		 1725 unsigned length, meta_len;
1726 int status, i;
1727 struct nvme_iod *iod, *meta_iod = NULL;
1728 dma_addr_t meta_dma_addr;
1729 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1730
1731 if (copy_from_user(&io, uio, sizeof(io)))
1732 return -EFAULT;
6c7d4945 1733 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1734 meta_len = (io.nblocks + 1) * ns->ms;
1735
1736 if (meta_len && ((io.metadata & 3) || !io.metadata))
1737 return -EINVAL;
6c7d4945
MW		 1738
1739 switch (io.opcode) {
1740 case nvme_cmd_write:
1741 case nvme_cmd_read:
6bbf1acd 1742 case nvme_cmd_compare:
eca18b23 1743 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1744 break;
6c7d4945 1745 default:
6bbf1acd 1746 return -EINVAL;
6c7d4945
MW		 1747 }
1748
eca18b23
MW		 1749 if (IS_ERR(iod))
1750 return PTR_ERR(iod);
a53295b6
MW		 1751
1752 memset(&c, 0, sizeof(c));
1753 c.rw.opcode = io.opcode;
1754 c.rw.flags = io.flags;
6c7d4945 1755 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1756 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1757 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1758 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1759 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1760 c.rw.reftag = cpu_to_le32(io.reftag);
1761 c.rw.apptag = cpu_to_le16(io.apptag);
1762 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1763
1764 if (meta_len) {
1b56749e
KB		 1765 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1766 meta_len);
f410c680
KB		 1767 if (IS_ERR(meta_iod)) {
1768 status = PTR_ERR(meta_iod);
1769 meta_iod = NULL;
1770 goto unmap;
1771 }
1772
1773 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1774 &meta_dma_addr, GFP_KERNEL);
1775 if (!meta_mem) {
1776 status = -ENOMEM;
1777 goto unmap;
1778 }
1779
1780 if (io.opcode & 1) {
1781 int meta_offset = 0;
1782
1783 for (i = 0; i < meta_iod->nents; i++) {
1784 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1785 meta_iod->sg[i].offset;
1786 memcpy(meta_mem + meta_offset, meta,
1787 meta_iod->sg[i].length);
1788 kunmap_atomic(meta);
1789 meta_offset += meta_iod->sg[i].length;
1790 }
1791 }
1792
1793 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1794 }
1795
edd10d33
KB		 1796 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1797 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1798 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1799
b77954cb
MW		 1800 if (length != (io.nblocks + 1) << ns->lba_shift)
1801 status = -ENOMEM;
1802 else
a4aea562 1803 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1804
f410c680
KB		 1805 if (meta_len) {
1806 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1807 int meta_offset = 0;
1808
1809 for (i = 0; i < meta_iod->nents; i++) {
1810 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1811 meta_iod->sg[i].offset;
1812 memcpy(meta, meta_mem + meta_offset,
1813 meta_iod->sg[i].length);
1814 kunmap_atomic(meta);
1815 meta_offset += meta_iod->sg[i].length;
1816 }
1817 }
1818
1819 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1820 meta_dma_addr);
1821 }
1822
1823 unmap:
1c2ad9fa 1824 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1825 nvme_free_iod(dev, iod);
f410c680
KB		 1826
1827 if (meta_iod) {
1828 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1829 nvme_free_iod(dev, meta_iod);
1830 }
1831
a53295b6
MW		 1832 return status;
1833}
1834
a4aea562
MB		 1835static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1836 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1837{
7963e521 1838 struct nvme_passthru_cmd cmd;
6ee44cdc 1839 struct nvme_command c;
eca18b23 1840 int status, length;
c7d36ab8 1841 struct nvme_iod *uninitialized_var(iod);
94f370ca 1842 unsigned timeout;
6ee44cdc 1843
6bbf1acd
MW		 1844 if (!capable(CAP_SYS_ADMIN))
1845 return -EACCES;
1846 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1847 return -EFAULT;
6ee44cdc
MW		 1848
1849 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1850 c.common.opcode = cmd.opcode;
1851 c.common.flags = cmd.flags;
1852 c.common.nsid = cpu_to_le32(cmd.nsid);
1853 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1854 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1855 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1856 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1857 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1858 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1859 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1860 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1861
1862 length = cmd.data_len;
1863 if (cmd.data_len) {
49742188
MW		 1864 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1865 length);
eca18b23
MW		 1866 if (IS_ERR(iod))
1867 return PTR_ERR(iod);
edd10d33
KB		 1868 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1869 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1870 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1871 }
1872
94f370ca
KB		 1873 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1874 ADMIN_TIMEOUT;
a4aea562 1875
6bbf1acd 1876 if (length != cmd.data_len)
b77954cb 1877 status = -ENOMEM;
a4aea562
MB		 1878 else if (ns) {
1879 struct request *req;
1880
1881 req = blk_mq_alloc_request(ns->queue, WRITE,
1882 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1883 if (IS_ERR(req))
1884 status = PTR_ERR(req);
a4aea562
MB		 1885 else {
1886 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1887 timeout);
9d135bb8 1888 blk_mq_free_request(req);
a4aea562
MB		 1889 }
1890 } else
1891 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1892
6bbf1acd 1893 if (cmd.data_len) {
1c2ad9fa 1894 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1895 nvme_free_iod(dev, iod);
6bbf1acd 1896 }
f4f117f6 1897
cf90bc48 1898 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1899 sizeof(cmd.result)))
1900 status = -EFAULT;
1901
6ee44cdc
MW		 1902 return status;
1903}
1904
b60503ba
MW		 1905static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1906 unsigned long arg)
1907{
1908 struct nvme_ns *ns = bdev->bd_disk->private_data;
1909
1910 switch (cmd) {
6bbf1acd 1911 case NVME_IOCTL_ID:
c3bfe717 1912 force_successful_syscall_return();
6bbf1acd
MW		 1913 return ns->ns_id;
1914 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1915 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1916 case NVME_IOCTL_IO_CMD:
a4aea562 1917 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1918 case NVME_IOCTL_SUBMIT_IO:
1919 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1920 case SG_GET_VERSION_NUM:
1921 return nvme_sg_get_version_num((void __user *)arg);
1922 case SG_IO:
1923 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1924 default:
1925 return -ENOTTY;
1926 }
1927}
1928
320a3827
KB		 1929#ifdef CONFIG_COMPAT
1930static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1931 unsigned int cmd, unsigned long arg)
1932{
320a3827
KB		 1933 switch (cmd) {
1934 case SG_IO:
e179729a 1935 return -ENOIOCTLCMD;
320a3827
KB		 1936 }
1937 return nvme_ioctl(bdev, mode, cmd, arg);
1938}
1939#else
1940#define nvme_compat_ioctl NULL
1941#endif
1942
9ac27090
KB		 1943static int nvme_open(struct block_device *bdev, fmode_t mode)
1944{
9e60352c
KB		 1945 int ret = 0;
1946 struct nvme_ns *ns;
9ac27090 1947
9e60352c
KB		 1948 spin_lock(&dev_list_lock);
1949 ns = bdev->bd_disk->private_data;
1950 if (!ns)
1951 ret = -ENXIO;
1952 else if (!kref_get_unless_zero(&ns->dev->kref))
1953 ret = -ENXIO;
1954 spin_unlock(&dev_list_lock);
1955
1956 return ret;
9ac27090
KB		 1957}
1958
1959static void nvme_free_dev(struct kref *kref);
1960
1961static void nvme_release(struct gendisk *disk, fmode_t mode)
1962{
1963 struct nvme_ns *ns = disk->private_data;
1964 struct nvme_dev *dev = ns->dev;
1965
1966 kref_put(&dev->kref, nvme_free_dev);
1967}
1968
4cc09e2d
KB		 1969static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1970{
1971 /* some standard values */
1972 geo->heads = 1 << 6;
1973 geo->sectors = 1 << 5;
1974 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1975 return 0;
1976}
1977
e1e5e564
KB		 1978static void nvme_config_discard(struct nvme_ns *ns)
1979{
1980 u32 logical_block_size = queue_logical_block_size(ns->queue);
1981 ns->queue->limits.discard_zeroes_data = 0;
1982 ns->queue->limits.discard_alignment = logical_block_size;
1983 ns->queue->limits.discard_granularity = logical_block_size;
1984 ns->queue->limits.max_discard_sectors = 0xffffffff;
1985 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1986}
1987
1988static int nvme_noop_verify(struct blk_integrity_iter *iter)
1989{
1990 return 0;
1991}
1992
1993static int nvme_noop_generate(struct blk_integrity_iter *iter)
1994{
1995 return 0;
1996}
1997
1998struct blk_integrity nvme_meta_noop = {
1999 .name = "NVME_META_NOOP",
2000 .generate_fn = nvme_noop_generate,
2001 .verify_fn = nvme_noop_verify,
2002};
2003
2004static void nvme_init_integrity(struct nvme_ns *ns)
2005{
2006 struct blk_integrity integrity;
2007
2008 switch (ns->pi_type) {
2009 case NVME_NS_DPS_PI_TYPE3:
2010 integrity = t10_pi_type3_crc;
2011 break;
2012 case NVME_NS_DPS_PI_TYPE1:
2013 case NVME_NS_DPS_PI_TYPE2:
2014 integrity = t10_pi_type1_crc;
2015 break;
2016 default:
2017 integrity = nvme_meta_noop;
2018 break;
2019 }
2020 integrity.tuple_size = ns->ms;
2021 blk_integrity_register(ns->disk, &integrity);
2022 blk_queue_max_integrity_segments(ns->queue, 1);
2023}
2024
1b9dbf7f
KB		 2025static int nvme_revalidate_disk(struct gendisk *disk)
2026{
2027 struct nvme_ns *ns = disk->private_data;
2028 struct nvme_dev *dev = ns->dev;
2029 struct nvme_id_ns *id;
2030 dma_addr_t dma_addr;
e1e5e564
KB		 2031 int lbaf, pi_type, old_ms;
2032 unsigned short bs;
1b9dbf7f
KB		 2033
2034 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
2035 GFP_KERNEL);
2036 if (!id) {
2037 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
2038 __func__);
2039 return 0;
2040 }
e1e5e564
KB		 2041 if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) {
2042 dev_warn(&dev->pci_dev->dev,
2043 "identify failed ns:%d, setting capacity to 0\n",
2044 ns->ns_id);
2045 memset(id, 0, sizeof(*id));
2046 }
1b9dbf7f 2047
e1e5e564
KB		 2048 old_ms = ns->ms;
2049 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2050 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564
KB		 2051 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2052
2053 /*
2054 * If identify namespace failed, use default 512 byte block size so
2055 * block layer can use before failing read/write for 0 capacity.
2056 */
2057 if (ns->lba_shift == 0)
2058 ns->lba_shift = 9;
2059 bs = 1 << ns->lba_shift;
2060
2061 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2062 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2063 id->dps & NVME_NS_DPS_PI_MASK : 0;
2064
2065 if (disk->integrity && (ns->pi_type != pi_type || ns->ms != old_ms ||
2066 bs != queue_logical_block_size(disk->queue) ||
2067 (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT)))
2068 blk_integrity_unregister(disk);
2069
2070 ns->pi_type = pi_type;
2071 blk_queue_logical_block_size(ns->queue, bs);
2072
2073 if (ns->ms && !disk->integrity && (disk->flags & GENHD_FL_UP) &&
2074 !(id->flbas & NVME_NS_FLBAS_META_EXT))
2075 nvme_init_integrity(ns);
2076
2077 if (id->ncap == 0 || (ns->ms && !disk->integrity))
2078 set_capacity(disk, 0);
2079 else
2080 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2081
2082 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2083 nvme_config_discard(ns);
1b9dbf7f 2084
1b9dbf7f
KB		 2085 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
2086 return 0;
2087}
2088
b60503ba
MW		 2089static const struct block_device_operations nvme_fops = {
2090 .owner = THIS_MODULE,
2091 .ioctl = nvme_ioctl,
320a3827 2092 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2093 .open = nvme_open,
2094 .release = nvme_release,
4cc09e2d 2095 .getgeo = nvme_getgeo,
1b9dbf7f 2096 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 2097};
2098
1fa6aead
MW		 2099static int nvme_kthread(void *data)
2100{
d4b4ff8e 2101 struct nvme_dev *dev, *next;
1fa6aead
MW		 2102
2103 while (!kthread_should_stop()) {
564a232c 2104 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2105 spin_lock(&dev_list_lock);
d4b4ff8e 2106 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2107 int i;
07836e65 2108 if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
d4b4ff8e
KB		 2109 if (work_busy(&dev->reset_work))
2110 continue;
2111 list_del_init(&dev->node);
2112 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 2113 "Failed status: %x, reset controller\n",
2114 readl(&dev->bar->csts));
9ca97374 2115 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 2116 queue_work(nvme_workq, &dev->reset_work);
2117 continue;
2118 }
1fa6aead 2119 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2120 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2121 if (!nvmeq)
2122 continue;
1fa6aead 2123 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2124 nvme_process_cq(nvmeq);
6fccf938
KB		 2125
2126 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2127 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2128 break;
2129 dev->event_limit--;
2130 }
1fa6aead
MW		 2131 spin_unlock_irq(&nvmeq->q_lock);
2132 }
2133 }
2134 spin_unlock(&dev_list_lock);
acb7aa0d 2135 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2136 }
2137 return 0;
2138}
2139
e1e5e564 2140static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2141{
2142 struct nvme_ns *ns;
2143 struct gendisk *disk;
a4aea562 2144 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba 2145
a4aea562 2146 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2147 if (!ns)
e1e5e564
KB		 2148 return;
2149
a4aea562 2150 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2151 if (IS_ERR(ns->queue))
b60503ba 2152 goto out_free_ns;
4eeb9215
MW		 2153 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2154 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2155 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2156 ns->dev = dev;
2157 ns->queue->queuedata = ns;
2158
a4aea562 2159 disk = alloc_disk_node(0, node);
b60503ba
MW		 2160 if (!disk)
2161 goto out_free_queue;
a4aea562 2162
5aff9382 2163 ns->ns_id = nsid;
b60503ba 2164 ns->disk = disk;
e1e5e564
KB		 2165 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2166 list_add_tail(&ns->list, &dev->namespaces);
2167
e9ef4636 2168 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2169 if (dev->max_hw_sectors)
2170 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2171 if (dev->stripe_size)
2172 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2173 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2174 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2175
2176 disk->major = nvme_major;
469071a3 2177 disk->first_minor = 0;
b60503ba
MW		 2178 disk->fops = &nvme_fops;
2179 disk->private_data = ns;
2180 disk->queue = ns->queue;
b3fffdef 2181 disk->driverfs_dev = dev->device;
469071a3 2182 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2183 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2184
e1e5e564
KB		 2185 /*
2186 * Initialize capacity to 0 until we establish the namespace format and
2187 * setup integrity extentions if necessary. The revalidate_disk after
2188 * add_disk allows the driver to register with integrity if the format
2189 * requires it.
2190 */
2191 set_capacity(disk, 0);
2192 nvme_revalidate_disk(ns->disk);
2193 add_disk(ns->disk);
2194 if (ns->ms)
2195 revalidate_disk(ns->disk);
2196 return;
b60503ba
MW		 2197 out_free_queue:
2198 blk_cleanup_queue(ns->queue);
2199 out_free_ns:
2200 kfree(ns);
b60503ba
MW		 2201}
2202
42f61420
KB		 2203static void nvme_create_io_queues(struct nvme_dev *dev)
2204{
a4aea562 2205 unsigned i;
42f61420 2206
a4aea562 2207 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2208 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2209 break;
2210
a4aea562
MB		 2211 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2212 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2213 break;
2214}
2215
b3b06812 2216static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2217{
2218 int status;
2219 u32 result;
b3b06812 2220 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2221
df348139 2222 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2223 &result);
27e8166c
MW		 2224 if (status < 0)
2225 return status;
2226 if (status > 0) {
2227 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2228 status);
badc34d4 2229 return 0;
27e8166c 2230 }
b60503ba
MW		 2231 return min(result & 0xffff, result >> 16) + 1;
2232}
2233
9d713c2b
KB		 2234static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2235{
b80d5ccc 2236 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2237}
2238
8d85fce7 2239static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2240{
a4aea562 2241 struct nvme_queue *adminq = dev->queues[0];
fa08a396 2242 struct pci_dev *pdev = dev->pci_dev;
42f61420 2243 int result, i, vecs, nr_io_queues, size;
b60503ba 2244
42f61420 2245 nr_io_queues = num_possible_cpus();
b348b7d5 2246 result = set_queue_count(dev, nr_io_queues);
badc34d4 2247 if (result <= 0)
1b23484b 2248 return result;
b348b7d5
MW		 2249 if (result < nr_io_queues)
2250 nr_io_queues = result;
b60503ba 2251
9d713c2b
KB		 2252 size = db_bar_size(dev, nr_io_queues);
2253 if (size > 8192) {
f1938f6e 2254 iounmap(dev->bar);
9d713c2b
KB		 2255 do {
2256 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2257 if (dev->bar)
2258 break;
2259 if (!--nr_io_queues)
2260 return -ENOMEM;
2261 size = db_bar_size(dev, nr_io_queues);
2262 } while (1);
f1938f6e 2263 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2264 adminq->q_db = dev->dbs;
f1938f6e
MW		 2265 }
2266
9d713c2b 2267 /* Deregister the admin queue's interrupt */
3193f07b 2268 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2269
e32efbfc
JA		 2270 /*
2271 * If we enable msix early due to not intx, disable it again before
2272 * setting up the full range we need.
2273 */
2274 if (!pdev->irq)
2275 pci_disable_msix(pdev);
2276
be577fab 2277 for (i = 0; i < nr_io_queues; i++)
1b23484b 2278 dev->entry[i].entry = i;
be577fab
AG		 2279 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2280 if (vecs < 0) {
2281 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2282 if (vecs < 0) {
2283 vecs = 1;
2284 } else {
2285 for (i = 0; i < vecs; i++)
2286 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2287 }
2288 }
2289
063a8096
MW		 2290 /*
2291 * Should investigate if there's a performance win from allocating
2292 * more queues than interrupt vectors; it might allow the submission
2293 * path to scale better, even if the receive path is limited by the
2294 * number of interrupts.
2295 */
2296 nr_io_queues = vecs;
42f61420 2297 dev->max_qid = nr_io_queues;
063a8096 2298
3193f07b 2299 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2300 if (result)
22404274 2301 goto free_queues;
1b23484b 2302
cd638946 2303 /* Free previously allocated queues that are no longer usable */
42f61420 2304 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2305 nvme_create_io_queues(dev);
9ecdc946 2306
22404274 2307 return 0;
b60503ba 2308
22404274 2309 free_queues:
a1a5ef99 2310 nvme_free_queues(dev, 1);
22404274 2311 return result;
b60503ba
MW		 2312}
2313
422ef0c7
MW		 2314/*
2315 * Return: error value if an error occurred setting up the queues or calling
2316 * Identify Device. 0 if these succeeded, even if adding some of the
2317 * namespaces failed. At the moment, these failures are silent. TBD which
2318 * failures should be reported.
2319 */
8d85fce7 2320static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2321{
68608c26 2322 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2323 int res;
2324 unsigned nn, i;
51814232 2325 struct nvme_id_ctrl *ctrl;
bc5fc7e4 2326 void *mem;
b60503ba 2327 dma_addr_t dma_addr;
159b67d7 2328 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2329
e1e5e564 2330 mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2331 if (!mem)
2332 return -ENOMEM;
b60503ba 2333
bc5fc7e4 2334 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2335 if (res) {
27e8166c 2336 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564
KB		 2337 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2338 return -EIO;
b60503ba
MW		 2339 }
2340
bc5fc7e4 2341 ctrl = mem;
51814232 2342 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2343 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2344 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2345 dev->vwc = ctrl->vwc;
6fccf938 2346 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2347 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2348 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2349 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2350 if (ctrl->mdts)
8fc23e03 2351 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2352 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2353 (pdev->device == 0x0953) && ctrl->vs[3]) {
2354 unsigned int max_hw_sectors;
2355
159b67d7 2356 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2357 max_hw_sectors = dev->stripe_size >> (shift - 9);
2358 if (dev->max_hw_sectors) {
2359 dev->max_hw_sectors = min(max_hw_sectors,
2360 dev->max_hw_sectors);
2361 } else
2362 dev->max_hw_sectors = max_hw_sectors;
2363 }
e1e5e564 2364 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
a4aea562
MB		 2365
2366 dev->tagset.ops = &nvme_mq_ops;
2367 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2368 dev->tagset.timeout = NVME_IO_TIMEOUT;
2369 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2370 dev->tagset.queue_depth =
2371 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ac3dd5bd 2372 dev->tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 2373 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2374 dev->tagset.driver_data = dev;
2375
2376 if (blk_mq_alloc_tag_set(&dev->tagset))
e1e5e564 2377 return 0;
b60503ba 2378
e1e5e564
KB		 2379 for (i = 1; i <= nn; i++)
2380 nvme_alloc_ns(dev, i);
b60503ba 2381
e1e5e564 2382 return 0;
b60503ba
MW		 2383}
2384
0877cb0d
KB		 2385static int nvme_dev_map(struct nvme_dev *dev)
2386{
42f61420 2387 u64 cap;
0877cb0d
KB		 2388 int bars, result = -ENOMEM;
2389 struct pci_dev *pdev = dev->pci_dev;
2390
2391 if (pci_enable_device_mem(pdev))
2392 return result;
2393
2394 dev->entry[0].vector = pdev->irq;
2395 pci_set_master(pdev);
2396 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2397 if (!bars)
2398 goto disable_pci;
2399
0877cb0d
KB		 2400 if (pci_request_selected_regions(pdev, bars, "nvme"))
2401 goto disable_pci;
2402
052d0efa
RK		 2403 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2404 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2405 goto disable;
0877cb0d 2406
0877cb0d
KB		 2407 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2408 if (!dev->bar)
2409 goto disable;
e32efbfc 2410
0e53d180
KB		 2411 if (readl(&dev->bar->csts) == -1) {
2412 result = -ENODEV;
2413 goto unmap;
2414 }
e32efbfc
JA		 2415
2416 /*
2417 * Some devices don't advertse INTx interrupts, pre-enable a single
2418 * MSIX vec for setup. We'll adjust this later.
2419 */
2420 if (!pdev->irq) {
2421 result = pci_enable_msix(pdev, dev->entry, 1);
2422 if (result < 0)
2423 goto unmap;
2424 }
2425
42f61420
KB		 2426 cap = readq(&dev->bar->cap);
2427 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2428 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2429 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2430
2431 return 0;
2432
0e53d180
KB		 2433 unmap:
2434 iounmap(dev->bar);
2435 dev->bar = NULL;
0877cb0d
KB		 2436 disable:
2437 pci_release_regions(pdev);
2438 disable_pci:
2439 pci_disable_device(pdev);
2440 return result;
2441}
2442
2443static void nvme_dev_unmap(struct nvme_dev *dev)
2444{
2445 if (dev->pci_dev->msi_enabled)
2446 pci_disable_msi(dev->pci_dev);
2447 else if (dev->pci_dev->msix_enabled)
2448 pci_disable_msix(dev->pci_dev);
2449
2450 if (dev->bar) {
2451 iounmap(dev->bar);
2452 dev->bar = NULL;
9a6b9458 2453 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2454 }
2455
0877cb0d
KB		 2456 if (pci_is_enabled(dev->pci_dev))
2457 pci_disable_device(dev->pci_dev);
2458}
2459
4d115420
KB		 2460struct nvme_delq_ctx {
2461 struct task_struct *waiter;
2462 struct kthread_worker *worker;
2463 atomic_t refcount;
2464};
2465
2466static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2467{
2468 dq->waiter = current;
2469 mb();
2470
2471 for (;;) {
2472 set_current_state(TASK_KILLABLE);
2473 if (!atomic_read(&dq->refcount))
2474 break;
2475 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2476 fatal_signal_pending(current)) {
0fb59cbc
KB		 2477 /*
2478 * Disable the controller first since we can't trust it
2479 * at this point, but leave the admin queue enabled
2480 * until all queue deletion requests are flushed.
2481 * FIXME: This may take a while if there are more h/w
2482 * queues than admin tags.
2483 */
4d115420 2484 set_current_state(TASK_RUNNING);
4d115420 2485 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2486 nvme_clear_queue(dev->queues[0]);
4d115420 2487 flush_kthread_worker(dq->worker);
0fb59cbc 2488 nvme_disable_queue(dev, 0);
4d115420
KB		 2489 return;
2490 }
2491 }
2492 set_current_state(TASK_RUNNING);
2493}
2494
2495static void nvme_put_dq(struct nvme_delq_ctx *dq)
2496{
2497 atomic_dec(&dq->refcount);
2498 if (dq->waiter)
2499 wake_up_process(dq->waiter);
2500}
2501
2502static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2503{
2504 atomic_inc(&dq->refcount);
2505 return dq;
2506}
2507
2508static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2509{
2510 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2511 nvme_put_dq(dq);
2512}
2513
2514static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2515 kthread_work_func_t fn)
2516{
2517 struct nvme_command c;
2518
2519 memset(&c, 0, sizeof(c));
2520 c.delete_queue.opcode = opcode;
2521 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2522
2523 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2524 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2525 ADMIN_TIMEOUT);
4d115420
KB		 2526}
2527
2528static void nvme_del_cq_work_handler(struct kthread_work *work)
2529{
2530 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2531 cmdinfo.work);
2532 nvme_del_queue_end(nvmeq);
2533}
2534
2535static int nvme_delete_cq(struct nvme_queue *nvmeq)
2536{
2537 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2538 nvme_del_cq_work_handler);
2539}
2540
2541static void nvme_del_sq_work_handler(struct kthread_work *work)
2542{
2543 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2544 cmdinfo.work);
2545 int status = nvmeq->cmdinfo.status;
2546
2547 if (!status)
2548 status = nvme_delete_cq(nvmeq);
2549 if (status)
2550 nvme_del_queue_end(nvmeq);
2551}
2552
2553static int nvme_delete_sq(struct nvme_queue *nvmeq)
2554{
2555 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2556 nvme_del_sq_work_handler);
2557}
2558
2559static void nvme_del_queue_start(struct kthread_work *work)
2560{
2561 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2562 cmdinfo.work);
4d115420
KB		 2563 if (nvme_delete_sq(nvmeq))
2564 nvme_del_queue_end(nvmeq);
2565}
2566
2567static void nvme_disable_io_queues(struct nvme_dev *dev)
2568{
2569 int i;
2570 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2571 struct nvme_delq_ctx dq;
2572 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2573 &worker, "nvme%d", dev->instance);
2574
2575 if (IS_ERR(kworker_task)) {
2576 dev_err(&dev->pci_dev->dev,
2577 "Failed to create queue del task\n");
2578 for (i = dev->queue_count - 1; i > 0; i--)
2579 nvme_disable_queue(dev, i);
2580 return;
2581 }
2582
2583 dq.waiter = NULL;
2584 atomic_set(&dq.refcount, 0);
2585 dq.worker = &worker;
2586 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2587 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2588
2589 if (nvme_suspend_queue(nvmeq))
2590 continue;
2591 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2592 nvmeq->cmdinfo.worker = dq.worker;
2593 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2594 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2595 }
2596 nvme_wait_dq(&dq, dev);
2597 kthread_stop(kworker_task);
2598}
2599
b9afca3e
DM		 2600/*
2601* Remove the node from the device list and check
2602* for whether or not we need to stop the nvme_thread.
2603*/
2604static void nvme_dev_list_remove(struct nvme_dev *dev)
2605{
2606 struct task_struct *tmp = NULL;
2607
2608 spin_lock(&dev_list_lock);
2609 list_del_init(&dev->node);
2610 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2611 tmp = nvme_thread;
2612 nvme_thread = NULL;
2613 }
2614 spin_unlock(&dev_list_lock);
2615
2616 if (tmp)
2617 kthread_stop(tmp);
2618}
2619
c9d3bf88
KB		 2620static void nvme_freeze_queues(struct nvme_dev *dev)
2621{
2622 struct nvme_ns *ns;
2623
2624 list_for_each_entry(ns, &dev->namespaces, list) {
2625 blk_mq_freeze_queue_start(ns->queue);
2626
2627 spin_lock(ns->queue->queue_lock);
2628 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2629 spin_unlock(ns->queue->queue_lock);
2630
2631 blk_mq_cancel_requeue_work(ns->queue);
2632 blk_mq_stop_hw_queues(ns->queue);
2633 }
2634}
2635
2636static void nvme_unfreeze_queues(struct nvme_dev *dev)
2637{
2638 struct nvme_ns *ns;
2639
2640 list_for_each_entry(ns, &dev->namespaces, list) {
2641 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2642 blk_mq_unfreeze_queue(ns->queue);
2643 blk_mq_start_stopped_hw_queues(ns->queue, true);
2644 blk_mq_kick_requeue_list(ns->queue);
2645 }
2646}
2647
f0b50732 2648static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2649{
22404274 2650 int i;
7c1b2450 2651 u32 csts = -1;
22404274 2652
b9afca3e 2653 nvme_dev_list_remove(dev);
1fa6aead 2654
c9d3bf88
KB		 2655 if (dev->bar) {
2656 nvme_freeze_queues(dev);
7c1b2450 2657 csts = readl(&dev->bar->csts);
c9d3bf88 2658 }
7c1b2450 2659 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2660 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2661 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2662 nvme_suspend_queue(nvmeq);
4d115420
KB		 2663 }
2664 } else {
2665 nvme_disable_io_queues(dev);
1894d8f1 2666 nvme_shutdown_ctrl(dev);
4d115420
KB		 2667 nvme_disable_queue(dev, 0);
2668 }
f0b50732 2669 nvme_dev_unmap(dev);
07836e65
KB		 2670
2671 for (i = dev->queue_count - 1; i >= 0; i--)
2672 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2673}
2674
2675static void nvme_dev_remove(struct nvme_dev *dev)
2676{
9ac27090 2677 struct nvme_ns *ns;
f0b50732 2678
9ac27090 2679 list_for_each_entry(ns, &dev->namespaces, list) {
e1e5e564
KB		 2680 if (ns->disk->flags & GENHD_FL_UP) {
2681 if (ns->disk->integrity)
2682 blk_integrity_unregister(ns->disk);
9ac27090 2683 del_gendisk(ns->disk);
e1e5e564 2684 }
cef6a948
KB		 2685 if (!blk_queue_dying(ns->queue)) {
2686 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2687 blk_cleanup_queue(ns->queue);
cef6a948 2688 }
b60503ba 2689 }
b60503ba
MW		 2690}
2691
091b6092
MW		 2692static int nvme_setup_prp_pools(struct nvme_dev *dev)
2693{
2694 struct device *dmadev = &dev->pci_dev->dev;
2695 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2696 PAGE_SIZE, PAGE_SIZE, 0);
2697 if (!dev->prp_page_pool)
2698 return -ENOMEM;
2699
99802a7a
MW		 2700 /* Optimisation for I/Os between 4k and 128k */
2701 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2702 256, 256, 0);
2703 if (!dev->prp_small_pool) {
2704 dma_pool_destroy(dev->prp_page_pool);
2705 return -ENOMEM;
2706 }
091b6092
MW		 2707 return 0;
2708}
2709
2710static void nvme_release_prp_pools(struct nvme_dev *dev)
2711{
2712 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2713 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2714}
2715
cd58ad7d
QSA		 2716static DEFINE_IDA(nvme_instance_ida);
2717
2718static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2719{
cd58ad7d
QSA		 2720 int instance, error;
2721
2722 do {
2723 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2724 return -ENODEV;
2725
2726 spin_lock(&dev_list_lock);
2727 error = ida_get_new(&nvme_instance_ida, &instance);
2728 spin_unlock(&dev_list_lock);
2729 } while (error == -EAGAIN);
2730
2731 if (error)
2732 return -ENODEV;
2733
2734 dev->instance = instance;
2735 return 0;
b60503ba
MW		 2736}
2737
2738static void nvme_release_instance(struct nvme_dev *dev)
2739{
cd58ad7d
QSA		 2740 spin_lock(&dev_list_lock);
2741 ida_remove(&nvme_instance_ida, dev->instance);
2742 spin_unlock(&dev_list_lock);
b60503ba
MW		 2743}
2744
9ac27090
KB		 2745static void nvme_free_namespaces(struct nvme_dev *dev)
2746{
2747 struct nvme_ns *ns, *next;
2748
2749 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2750 list_del(&ns->list);
9e60352c
KB		 2751
2752 spin_lock(&dev_list_lock);
2753 ns->disk->private_data = NULL;
2754 spin_unlock(&dev_list_lock);
2755
9ac27090
KB		 2756 put_disk(ns->disk);
2757 kfree(ns);
2758 }
2759}
2760
5e82e952
KB		 2761static void nvme_free_dev(struct kref *kref)
2762{
2763 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2764
a96d4f5c 2765 pci_dev_put(dev->pci_dev);
b3fffdef 2766 put_device(dev->device);
9ac27090 2767 nvme_free_namespaces(dev);
285dffc9 2768 nvme_release_instance(dev);
a4aea562 2769 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2770 blk_put_queue(dev->admin_q);
5e82e952
KB		 2771 kfree(dev->queues);
2772 kfree(dev->entry);
2773 kfree(dev);
2774}
2775
2776static int nvme_dev_open(struct inode *inode, struct file *f)
2777{
b3fffdef
KB		 2778 struct nvme_dev *dev;
2779 int instance = iminor(inode);
2780 int ret = -ENODEV;
2781
2782 spin_lock(&dev_list_lock);
2783 list_for_each_entry(dev, &dev_list, node) {
2784 if (dev->instance == instance) {
2e1d8448
KB		 2785 if (!dev->admin_q) {
2786 ret = -EWOULDBLOCK;
2787 break;
2788 }
b3fffdef
KB		 2789 if (!kref_get_unless_zero(&dev->kref))
2790 break;
2791 f->private_data = dev;
2792 ret = 0;
2793 break;
2794 }
2795 }
2796 spin_unlock(&dev_list_lock);
2797
2798 return ret;
5e82e952
KB		 2799}
2800
2801static int nvme_dev_release(struct inode *inode, struct file *f)
2802{
2803 struct nvme_dev *dev = f->private_data;
2804 kref_put(&dev->kref, nvme_free_dev);
2805 return 0;
2806}
2807
2808static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2809{
2810 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2811 struct nvme_ns *ns;
2812
5e82e952
KB		 2813 switch (cmd) {
2814 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2815 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2816 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2817 if (list_empty(&dev->namespaces))
2818 return -ENOTTY;
2819 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2820 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2821 default:
2822 return -ENOTTY;
2823 }
2824}
2825
2826static const struct file_operations nvme_dev_fops = {
2827 .owner = THIS_MODULE,
2828 .open = nvme_dev_open,
2829 .release = nvme_dev_release,
2830 .unlocked_ioctl = nvme_dev_ioctl,
2831 .compat_ioctl = nvme_dev_ioctl,
2832};
2833
a4aea562
MB		 2834static void nvme_set_irq_hints(struct nvme_dev *dev)
2835{
2836 struct nvme_queue *nvmeq;
2837 int i;
2838
2839 for (i = 0; i < dev->online_queues; i++) {
2840 nvmeq = dev->queues[i];
2841
2842 if (!nvmeq->hctx)
2843 continue;
2844
2845 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2846 nvmeq->hctx->cpumask);
2847 }
2848}
2849
f0b50732
KB		 2850static int nvme_dev_start(struct nvme_dev *dev)
2851{
2852 int result;
b9afca3e 2853 bool start_thread = false;
f0b50732
KB		 2854
2855 result = nvme_dev_map(dev);
2856 if (result)
2857 return result;
2858
2859 result = nvme_configure_admin_queue(dev);
2860 if (result)
2861 goto unmap;
2862
2863 spin_lock(&dev_list_lock);
b9afca3e
DM		 2864 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2865 start_thread = true;
2866 nvme_thread = NULL;
2867 }
f0b50732
KB		 2868 list_add(&dev->node, &dev_list);
2869 spin_unlock(&dev_list_lock);
2870
b9afca3e
DM		 2871 if (start_thread) {
2872 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2873 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2874 } else
2875 wait_event_killable(nvme_kthread_wait, nvme_thread);
2876
2877 if (IS_ERR_OR_NULL(nvme_thread)) {
2878 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2879 goto disable;
2880 }
a4aea562
MB		 2881
2882 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2883 result = nvme_alloc_admin_tags(dev);
2884 if (result)
2885 goto disable;
b9afca3e 2886
f0b50732 2887 result = nvme_setup_io_queues(dev);
badc34d4 2888 if (result)
0fb59cbc 2889 goto free_tags;
f0b50732 2890
a4aea562
MB		 2891 nvme_set_irq_hints(dev);
2892
d82e8bfd 2893 return result;
f0b50732 2894
0fb59cbc
KB		 2895 free_tags:
2896 nvme_dev_remove_admin(dev);
f0b50732 2897 disable:
a1a5ef99 2898 nvme_disable_queue(dev, 0);
b9afca3e 2899 nvme_dev_list_remove(dev);
f0b50732
KB		 2900 unmap:
2901 nvme_dev_unmap(dev);
2902 return result;
2903}
2904
9a6b9458
KB		 2905static int nvme_remove_dead_ctrl(void *arg)
2906{
2907 struct nvme_dev *dev = (struct nvme_dev *)arg;
2908 struct pci_dev *pdev = dev->pci_dev;
2909
2910 if (pci_get_drvdata(pdev))
c81f4975 2911 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2912 kref_put(&dev->kref, nvme_free_dev);
2913 return 0;
2914}
2915
2916static void nvme_remove_disks(struct work_struct *ws)
2917{
9a6b9458
KB		 2918 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2919
5a92e700 2920 nvme_free_queues(dev, 1);
302c6727 2921 nvme_dev_remove(dev);
9a6b9458
KB		 2922}
2923
2924static int nvme_dev_resume(struct nvme_dev *dev)
2925{
2926 int ret;
2927
2928 ret = nvme_dev_start(dev);
badc34d4 2929 if (ret)
9a6b9458 2930 return ret;
badc34d4 2931 if (dev->online_queues < 2) {
9a6b9458 2932 spin_lock(&dev_list_lock);
9ca97374 2933 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2934 queue_work(nvme_workq, &dev->reset_work);
2935 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2936 } else {
2937 nvme_unfreeze_queues(dev);
2938 nvme_set_irq_hints(dev);
9a6b9458
KB		 2939 }
2940 return 0;
2941}
2942
2943static void nvme_dev_reset(struct nvme_dev *dev)
2944{
2945 nvme_dev_shutdown(dev);
2946 if (nvme_dev_resume(dev)) {
a4aea562 2947 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2948 kref_get(&dev->kref);
2949 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2950 dev->instance))) {
2951 dev_err(&dev->pci_dev->dev,
2952 "Failed to start controller remove task\n");
2953 kref_put(&dev->kref, nvme_free_dev);
2954 }
2955 }
2956}
2957
2958static void nvme_reset_failed_dev(struct work_struct *ws)
2959{
2960 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2961 nvme_dev_reset(dev);
2962}
2963
9ca97374
TH		 2964static void nvme_reset_workfn(struct work_struct *work)
2965{
2966 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2967 dev->reset_workfn(work);
2968}
2969
2e1d8448 2970static void nvme_async_probe(struct work_struct *work);
8d85fce7 2971static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2972{
a4aea562 2973 int node, result = -ENOMEM;
b60503ba
MW		 2974 struct nvme_dev *dev;
2975
a4aea562
MB		 2976 node = dev_to_node(&pdev->dev);
2977 if (node == NUMA_NO_NODE)
2978 set_dev_node(&pdev->dev, 0);
2979
2980 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2981 if (!dev)
2982 return -ENOMEM;
a4aea562
MB		 2983 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2984 GFP_KERNEL, node);
b60503ba
MW		 2985 if (!dev->entry)
2986 goto free;
a4aea562
MB		 2987 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2988 GFP_KERNEL, node);
b60503ba
MW		 2989 if (!dev->queues)
2990 goto free;
2991
2992 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2993 dev->reset_workfn = nvme_reset_failed_dev;
2994 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2995 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2996 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2997 result = nvme_set_instance(dev);
2998 if (result)
a96d4f5c 2999 goto put_pci;
b60503ba 3000
091b6092
MW		 3001 result = nvme_setup_prp_pools(dev);
3002 if (result)
0877cb0d 3003 goto release;
091b6092 3004
fb35e914 3005 kref_init(&dev->kref);
b3fffdef
KB		 3006 dev->device = device_create(nvme_class, &pdev->dev,
3007 MKDEV(nvme_char_major, dev->instance),
3008 dev, "nvme%d", dev->instance);
3009 if (IS_ERR(dev->device)) {
3010 result = PTR_ERR(dev->device);
2e1d8448 3011 goto release_pools;
b3fffdef
KB		 3012 }
3013 get_device(dev->device);
740216fc 3014
2e1d8448
KB		 3015 INIT_WORK(&dev->probe_work, nvme_async_probe);
3016 schedule_work(&dev->probe_work);
b60503ba
MW		 3017 return 0;
3018
0877cb0d 3019 release_pools:
091b6092 3020 nvme_release_prp_pools(dev);
0877cb0d
KB		 3021 release:
3022 nvme_release_instance(dev);
a96d4f5c
KB		 3023 put_pci:
3024 pci_dev_put(dev->pci_dev);
b60503ba
MW		 3025 free:
3026 kfree(dev->queues);
3027 kfree(dev->entry);
3028 kfree(dev);
3029 return result;
3030}
3031
2e1d8448
KB		 3032static void nvme_async_probe(struct work_struct *work)
3033{
3034 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3035 int result;
3036
3037 result = nvme_dev_start(dev);
3038 if (result)
3039 goto reset;
3040
3041 if (dev->online_queues > 1)
3042 result = nvme_dev_add(dev);
3043 if (result)
3044 goto reset;
3045
3046 nvme_set_irq_hints(dev);
2e1d8448
KB		 3047 return;
3048 reset:
07836e65
KB		 3049 if (!work_busy(&dev->reset_work)) {
3050 dev->reset_workfn = nvme_reset_failed_dev;
3051 queue_work(nvme_workq, &dev->reset_work);
3052 }
2e1d8448
KB		 3053}
3054
f0d54a54
KB		 3055static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3056{
a6739479 3057 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3058
a6739479
KB		 3059 if (prepare)
3060 nvme_dev_shutdown(dev);
3061 else
3062 nvme_dev_resume(dev);
f0d54a54
KB		 3063}
3064
09ece142
KB		 3065static void nvme_shutdown(struct pci_dev *pdev)
3066{
3067 struct nvme_dev *dev = pci_get_drvdata(pdev);
3068 nvme_dev_shutdown(dev);
3069}
3070
8d85fce7 3071static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3072{
3073 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3074
3075 spin_lock(&dev_list_lock);
3076 list_del_init(&dev->node);
3077 spin_unlock(&dev_list_lock);
3078
3079 pci_set_drvdata(pdev, NULL);
2e1d8448 3080 flush_work(&dev->probe_work);
9a6b9458 3081 flush_work(&dev->reset_work);
9a6b9458 3082 nvme_dev_shutdown(dev);
c9d3bf88 3083 nvme_dev_remove(dev);
a4aea562 3084 nvme_dev_remove_admin(dev);
b3fffdef 3085 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3086 nvme_free_queues(dev, 0);
9a6b9458 3087 nvme_release_prp_pools(dev);
5e82e952 3088 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3089}
3090
3091/* These functions are yet to be implemented */
3092#define nvme_error_detected NULL
3093#define nvme_dump_registers NULL
3094#define nvme_link_reset NULL
3095#define nvme_slot_reset NULL
3096#define nvme_error_resume NULL
cd638946 3097
671a6018 3098#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3099static int nvme_suspend(struct device *dev)
3100{
3101 struct pci_dev *pdev = to_pci_dev(dev);
3102 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3103
3104 nvme_dev_shutdown(ndev);
3105 return 0;
3106}
3107
3108static int nvme_resume(struct device *dev)
3109{
3110 struct pci_dev *pdev = to_pci_dev(dev);
3111 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3112
9a6b9458 3113 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3114 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3115 queue_work(nvme_workq, &ndev->reset_work);
3116 }
3117 return 0;
cd638946 3118}
671a6018 3119#endif
cd638946
KB		 3120
3121static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3122
1d352035 3123static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3124 .error_detected = nvme_error_detected,
3125 .mmio_enabled = nvme_dump_registers,
3126 .link_reset = nvme_link_reset,
3127 .slot_reset = nvme_slot_reset,
3128 .resume = nvme_error_resume,
f0d54a54 3129 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3130};
3131
3132/* Move to pci_ids.h later */
3133#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3134
6eb0d698 3135static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3136 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3137 { 0, }
3138};
3139MODULE_DEVICE_TABLE(pci, nvme_id_table);
3140
3141static struct pci_driver nvme_driver = {
3142 .name = "nvme",
3143 .id_table = nvme_id_table,
3144 .probe = nvme_probe,
8d85fce7 3145 .remove = nvme_remove,
09ece142 3146 .shutdown = nvme_shutdown,
cd638946
KB		 3147 .driver = {
3148 .pm = &nvme_dev_pm_ops,
3149 },
b60503ba
MW		 3150 .err_handler = &nvme_err_handler,
3151};
3152
3153static int __init nvme_init(void)
3154{
0ac13140 3155 int result;
1fa6aead 3156
b9afca3e 3157 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3158
9a6b9458
KB		 3159 nvme_workq = create_singlethread_workqueue("nvme");
3160 if (!nvme_workq)
b9afca3e 3161 return -ENOMEM;
9a6b9458 3162
5c42ea16
KB		 3163 result = register_blkdev(nvme_major, "nvme");
3164 if (result < 0)
9a6b9458 3165 goto kill_workq;
5c42ea16 3166 else if (result > 0)
0ac13140 3167 nvme_major = result;
b60503ba 3168
b3fffdef
KB		 3169 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3170 &nvme_dev_fops);
3171 if (result < 0)
3172 goto unregister_blkdev;
3173 else if (result > 0)
3174 nvme_char_major = result;
3175
3176 nvme_class = class_create(THIS_MODULE, "nvme");
3177 if (!nvme_class)
3178 goto unregister_chrdev;
3179
f3db22fe
KB		 3180 result = pci_register_driver(&nvme_driver);
3181 if (result)
b3fffdef 3182 goto destroy_class;
1fa6aead 3183 return 0;
b60503ba 3184
b3fffdef
KB		 3185 destroy_class:
3186 class_destroy(nvme_class);
3187 unregister_chrdev:
3188 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3189 unregister_blkdev:
b60503ba 3190 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3191 kill_workq:
3192 destroy_workqueue(nvme_workq);
b60503ba
MW		 3193 return result;
3194}
3195
3196static void __exit nvme_exit(void)
3197{
3198 pci_unregister_driver(&nvme_driver);
3199 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3200 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3201 class_destroy(nvme_class);
3202 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3203 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3204 _nvme_check_size();
b60503ba
MW		 3205}
3206
3207MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3208MODULE_LICENSE("GPL");
c78b4713 3209MODULE_VERSION("1.0");
b60503ba
MW		 3210module_init(nvme_init);
3211module_exit(nvme_exit);
Linux kernel - Deliverables
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