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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
15 | #include <linux/nvme.h> | |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba MW |
31 | #include <linux/kernel.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/pci.h> | |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
b60503ba | 41 | #include <linux/types.h> |
5d0f6131 | 42 | #include <scsi/sg.h> |
797a796a HM |
43 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
44 | ||
b3fffdef | 45 | #define NVME_MINORS (1U << MINORBITS) |
9d43cf64 | 46 | #define NVME_Q_DEPTH 1024 |
a4aea562 | 47 | #define NVME_AQ_DEPTH 64 |
b60503ba MW |
48 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
49 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
9d43cf64 | 50 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
2484f407 | 51 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) |
9d43cf64 KB |
52 | |
53 | static unsigned char admin_timeout = 60; | |
54 | module_param(admin_timeout, byte, 0644); | |
55 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 56 | |
bd67608a MW |
57 | unsigned char nvme_io_timeout = 30; |
58 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 59 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 60 | |
2484f407 DM |
61 | static unsigned char shutdown_timeout = 5; |
62 | module_param(shutdown_timeout, byte, 0644); | |
63 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
64 | ||
b60503ba MW |
65 | static int nvme_major; |
66 | module_param(nvme_major, int, 0); | |
67 | ||
b3fffdef KB |
68 | static int nvme_char_major; |
69 | module_param(nvme_char_major, int, 0); | |
70 | ||
58ffacb5 MW |
71 | static int use_threaded_interrupts; |
72 | module_param(use_threaded_interrupts, int, 0); | |
73 | ||
1fa6aead MW |
74 | static DEFINE_SPINLOCK(dev_list_lock); |
75 | static LIST_HEAD(dev_list); | |
76 | static struct task_struct *nvme_thread; | |
9a6b9458 | 77 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 78 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 79 | |
b3fffdef KB |
80 | static struct class *nvme_class; |
81 | ||
d4b4ff8e | 82 | static void nvme_reset_failed_dev(struct work_struct *ws); |
a4aea562 | 83 | static int nvme_process_cq(struct nvme_queue *nvmeq); |
d4b4ff8e | 84 | |
4d115420 KB |
85 | struct async_cmd_info { |
86 | struct kthread_work work; | |
87 | struct kthread_worker *worker; | |
a4aea562 | 88 | struct request *req; |
4d115420 KB |
89 | u32 result; |
90 | int status; | |
91 | void *ctx; | |
92 | }; | |
1fa6aead | 93 | |
b60503ba MW |
94 | /* |
95 | * An NVM Express queue. Each device has at least two (one for admin | |
96 | * commands and one for I/O commands). | |
97 | */ | |
98 | struct nvme_queue { | |
99 | struct device *q_dmadev; | |
091b6092 | 100 | struct nvme_dev *dev; |
3193f07b | 101 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
102 | spinlock_t q_lock; |
103 | struct nvme_command *sq_cmds; | |
104 | volatile struct nvme_completion *cqes; | |
105 | dma_addr_t sq_dma_addr; | |
106 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
107 | u32 __iomem *q_db; |
108 | u16 q_depth; | |
6222d172 | 109 | s16 cq_vector; |
b60503ba MW |
110 | u16 sq_head; |
111 | u16 sq_tail; | |
112 | u16 cq_head; | |
c30341dc | 113 | u16 qid; |
e9539f47 MW |
114 | u8 cq_phase; |
115 | u8 cqe_seen; | |
4d115420 | 116 | struct async_cmd_info cmdinfo; |
a4aea562 | 117 | struct blk_mq_hw_ctx *hctx; |
b60503ba MW |
118 | }; |
119 | ||
120 | /* | |
121 | * Check we didin't inadvertently grow the command struct | |
122 | */ | |
123 | static inline void _nvme_check_size(void) | |
124 | { | |
125 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
126 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
127 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
128 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
129 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 130 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 131 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
132 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
133 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
134 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
135 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 136 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
137 | } |
138 | ||
edd10d33 | 139 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
140 | struct nvme_completion *); |
141 | ||
e85248e5 | 142 | struct nvme_cmd_info { |
c2f5b650 MW |
143 | nvme_completion_fn fn; |
144 | void *ctx; | |
c30341dc | 145 | int aborted; |
a4aea562 | 146 | struct nvme_queue *nvmeq; |
ac3dd5bd | 147 | struct nvme_iod iod[0]; |
e85248e5 MW |
148 | }; |
149 | ||
ac3dd5bd JA |
150 | /* |
151 | * Max size of iod being embedded in the request payload | |
152 | */ | |
153 | #define NVME_INT_PAGES 2 | |
154 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size) | |
155 | ||
156 | /* | |
157 | * Will slightly overestimate the number of pages needed. This is OK | |
158 | * as it only leads to a small amount of wasted memory for the lifetime of | |
159 | * the I/O. | |
160 | */ | |
161 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
162 | { | |
163 | unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size); | |
164 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
165 | } | |
166 | ||
167 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
168 | { | |
169 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
170 | ||
171 | ret += sizeof(struct nvme_iod); | |
172 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
173 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
174 | ||
175 | return ret; | |
176 | } | |
177 | ||
a4aea562 MB |
178 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
179 | unsigned int hctx_idx) | |
e85248e5 | 180 | { |
a4aea562 MB |
181 | struct nvme_dev *dev = data; |
182 | struct nvme_queue *nvmeq = dev->queues[0]; | |
183 | ||
184 | WARN_ON(nvmeq->hctx); | |
185 | nvmeq->hctx = hctx; | |
186 | hctx->driver_data = nvmeq; | |
187 | return 0; | |
e85248e5 MW |
188 | } |
189 | ||
a4aea562 MB |
190 | static int nvme_admin_init_request(void *data, struct request *req, |
191 | unsigned int hctx_idx, unsigned int rq_idx, | |
192 | unsigned int numa_node) | |
22404274 | 193 | { |
a4aea562 MB |
194 | struct nvme_dev *dev = data; |
195 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
196 | struct nvme_queue *nvmeq = dev->queues[0]; | |
197 | ||
198 | BUG_ON(!nvmeq); | |
199 | cmd->nvmeq = nvmeq; | |
200 | return 0; | |
22404274 KB |
201 | } |
202 | ||
2c30540b JA |
203 | static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
204 | { | |
205 | struct nvme_queue *nvmeq = hctx->driver_data; | |
206 | ||
207 | nvmeq->hctx = NULL; | |
208 | } | |
209 | ||
a4aea562 MB |
210 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
211 | unsigned int hctx_idx) | |
b60503ba | 212 | { |
a4aea562 MB |
213 | struct nvme_dev *dev = data; |
214 | struct nvme_queue *nvmeq = dev->queues[ | |
215 | (hctx_idx % dev->queue_count) + 1]; | |
b60503ba | 216 | |
a4aea562 MB |
217 | if (!nvmeq->hctx) |
218 | nvmeq->hctx = hctx; | |
219 | ||
220 | /* nvmeq queues are shared between namespaces. We assume here that | |
221 | * blk-mq map the tags so they match up with the nvme queue tags. */ | |
222 | WARN_ON(nvmeq->hctx->tags != hctx->tags); | |
b60503ba | 223 | |
a4aea562 MB |
224 | hctx->driver_data = nvmeq; |
225 | return 0; | |
b60503ba MW |
226 | } |
227 | ||
a4aea562 MB |
228 | static int nvme_init_request(void *data, struct request *req, |
229 | unsigned int hctx_idx, unsigned int rq_idx, | |
230 | unsigned int numa_node) | |
b60503ba | 231 | { |
a4aea562 MB |
232 | struct nvme_dev *dev = data; |
233 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
234 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
235 | ||
236 | BUG_ON(!nvmeq); | |
237 | cmd->nvmeq = nvmeq; | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
242 | nvme_completion_fn handler) | |
243 | { | |
244 | cmd->fn = handler; | |
245 | cmd->ctx = ctx; | |
246 | cmd->aborted = 0; | |
c917dfe5 | 247 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
248 | } |
249 | ||
ac3dd5bd JA |
250 | static void *iod_get_private(struct nvme_iod *iod) |
251 | { | |
252 | return (void *) (iod->private & ~0x1UL); | |
253 | } | |
254 | ||
255 | /* | |
256 | * If bit 0 is set, the iod is embedded in the request payload. | |
257 | */ | |
258 | static bool iod_should_kfree(struct nvme_iod *iod) | |
259 | { | |
260 | return (iod->private & 0x01) == 0; | |
261 | } | |
262 | ||
c2f5b650 MW |
263 | /* Special values must be less than 0x1000 */ |
264 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
265 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
266 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
267 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 268 | |
edd10d33 | 269 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
270 | struct nvme_completion *cqe) |
271 | { | |
272 | if (ctx == CMD_CTX_CANCELLED) | |
273 | return; | |
c2f5b650 | 274 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 275 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
276 | "completed id %d twice on queue %d\n", |
277 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
278 | return; | |
279 | } | |
280 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 281 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
282 | "invalid id %d completed on queue %d\n", |
283 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
284 | return; | |
285 | } | |
edd10d33 | 286 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
287 | } |
288 | ||
a4aea562 | 289 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 290 | { |
c2f5b650 | 291 | void *ctx; |
b60503ba | 292 | |
859361a2 | 293 | if (fn) |
a4aea562 MB |
294 | *fn = cmd->fn; |
295 | ctx = cmd->ctx; | |
296 | cmd->fn = special_completion; | |
297 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 298 | return ctx; |
b60503ba MW |
299 | } |
300 | ||
a4aea562 MB |
301 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
302 | struct nvme_completion *cqe) | |
3c0cf138 | 303 | { |
a4aea562 | 304 | struct request *req = ctx; |
3c0cf138 | 305 | |
a4aea562 MB |
306 | u32 result = le32_to_cpup(&cqe->result); |
307 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
308 | ||
309 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
310 | ++nvmeq->dev->event_limit; | |
311 | if (status == NVME_SC_SUCCESS) | |
312 | dev_warn(nvmeq->q_dmadev, | |
313 | "async event result %08x\n", result); | |
314 | ||
9d135bb8 | 315 | blk_mq_free_hctx_request(nvmeq->hctx, req); |
b60503ba MW |
316 | } |
317 | ||
a4aea562 MB |
318 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
319 | struct nvme_completion *cqe) | |
5a92e700 | 320 | { |
a4aea562 MB |
321 | struct request *req = ctx; |
322 | ||
323 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
324 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 325 | |
9d135bb8 | 326 | blk_mq_free_hctx_request(nvmeq->hctx, req); |
a51afb54 | 327 | |
a4aea562 MB |
328 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
329 | ++nvmeq->dev->abort_limit; | |
5a92e700 KB |
330 | } |
331 | ||
a4aea562 MB |
332 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
333 | struct nvme_completion *cqe) | |
b60503ba | 334 | { |
a4aea562 MB |
335 | struct async_cmd_info *cmdinfo = ctx; |
336 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
337 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
338 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
9d135bb8 | 339 | blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req); |
b60503ba MW |
340 | } |
341 | ||
a4aea562 MB |
342 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
343 | unsigned int tag) | |
b60503ba | 344 | { |
a4aea562 MB |
345 | struct blk_mq_hw_ctx *hctx = nvmeq->hctx; |
346 | struct request *req = blk_mq_tag_to_rq(hctx->tags, tag); | |
a51afb54 | 347 | |
a4aea562 | 348 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
349 | } |
350 | ||
a4aea562 MB |
351 | /* |
352 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
353 | */ | |
354 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
355 | nvme_completion_fn *fn) | |
4f5099af | 356 | { |
a4aea562 MB |
357 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
358 | void *ctx; | |
359 | if (tag >= nvmeq->q_depth) { | |
360 | *fn = special_completion; | |
361 | return CMD_CTX_INVALID; | |
362 | } | |
363 | if (fn) | |
364 | *fn = cmd->fn; | |
365 | ctx = cmd->ctx; | |
366 | cmd->fn = special_completion; | |
367 | cmd->ctx = CMD_CTX_COMPLETED; | |
368 | return ctx; | |
b60503ba MW |
369 | } |
370 | ||
371 | /** | |
714a7a22 | 372 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
373 | * @nvmeq: The queue to use |
374 | * @cmd: The command to send | |
375 | * | |
376 | * Safe to use from interrupt context | |
377 | */ | |
a4aea562 | 378 | static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
b60503ba | 379 | { |
a4aea562 MB |
380 | u16 tail = nvmeq->sq_tail; |
381 | ||
b60503ba | 382 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); |
b60503ba MW |
383 | if (++tail == nvmeq->q_depth) |
384 | tail = 0; | |
7547881d | 385 | writel(tail, nvmeq->q_db); |
b60503ba | 386 | nvmeq->sq_tail = tail; |
b60503ba MW |
387 | |
388 | return 0; | |
389 | } | |
390 | ||
a4aea562 MB |
391 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
392 | { | |
393 | unsigned long flags; | |
394 | int ret; | |
395 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
396 | ret = __nvme_submit_cmd(nvmeq, cmd); | |
397 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
398 | return ret; | |
399 | } | |
400 | ||
eca18b23 | 401 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 402 | { |
eca18b23 | 403 | return ((void *)iod) + iod->offset; |
e025344c SMM |
404 | } |
405 | ||
ac3dd5bd JA |
406 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
407 | unsigned nseg, unsigned long private) | |
eca18b23 | 408 | { |
ac3dd5bd JA |
409 | iod->private = private; |
410 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
411 | iod->npages = -1; | |
412 | iod->length = nbytes; | |
413 | iod->nents = 0; | |
eca18b23 | 414 | } |
b60503ba | 415 | |
eca18b23 | 416 | static struct nvme_iod * |
ac3dd5bd JA |
417 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
418 | unsigned long priv, gfp_t gfp) | |
b60503ba | 419 | { |
eca18b23 | 420 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 421 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
422 | sizeof(struct scatterlist) * nseg, gfp); |
423 | ||
ac3dd5bd JA |
424 | if (iod) |
425 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
426 | |
427 | return iod; | |
b60503ba MW |
428 | } |
429 | ||
ac3dd5bd JA |
430 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
431 | gfp_t gfp) | |
432 | { | |
433 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
434 | sizeof(struct nvme_dsm_range); | |
435 | unsigned long mask = 0; | |
436 | struct nvme_iod *iod; | |
437 | ||
438 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
439 | size <= NVME_INT_BYTES(dev)) { | |
440 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
441 | ||
442 | iod = cmd->iod; | |
443 | mask = 0x01; | |
444 | iod_init(iod, size, rq->nr_phys_segments, | |
445 | (unsigned long) rq | 0x01); | |
446 | return iod; | |
447 | } | |
448 | ||
449 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
450 | (unsigned long) rq, gfp); | |
451 | } | |
452 | ||
5d0f6131 | 453 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 454 | { |
1d090624 | 455 | const int last_prp = dev->page_size / 8 - 1; |
eca18b23 MW |
456 | int i; |
457 | __le64 **list = iod_list(iod); | |
458 | dma_addr_t prp_dma = iod->first_dma; | |
459 | ||
460 | if (iod->npages == 0) | |
461 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
462 | for (i = 0; i < iod->npages; i++) { | |
463 | __le64 *prp_list = list[i]; | |
464 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
465 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
466 | prp_dma = next_prp_dma; | |
467 | } | |
ac3dd5bd JA |
468 | |
469 | if (iod_should_kfree(iod)) | |
470 | kfree(iod); | |
b60503ba MW |
471 | } |
472 | ||
b4ff9c8d KB |
473 | static int nvme_error_status(u16 status) |
474 | { | |
475 | switch (status & 0x7ff) { | |
476 | case NVME_SC_SUCCESS: | |
477 | return 0; | |
478 | case NVME_SC_CAP_EXCEEDED: | |
479 | return -ENOSPC; | |
480 | default: | |
481 | return -EIO; | |
482 | } | |
483 | } | |
484 | ||
52b68d7e | 485 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
486 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
487 | { | |
488 | if (be32_to_cpu(pi->ref_tag) == v) | |
489 | pi->ref_tag = cpu_to_be32(p); | |
490 | } | |
491 | ||
492 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
493 | { | |
494 | if (be32_to_cpu(pi->ref_tag) == p) | |
495 | pi->ref_tag = cpu_to_be32(v); | |
496 | } | |
497 | ||
498 | /** | |
499 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
500 | * | |
501 | * The virtual start sector is the one that was originally submitted by the | |
502 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
503 | * start sector may be different. Remap protection information to match the | |
504 | * physical LBA on writes, and back to the original seed on reads. | |
505 | * | |
506 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
507 | */ | |
508 | static void nvme_dif_remap(struct request *req, | |
509 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
510 | { | |
511 | struct nvme_ns *ns = req->rq_disk->private_data; | |
512 | struct bio_integrity_payload *bip; | |
513 | struct t10_pi_tuple *pi; | |
514 | void *p, *pmap; | |
515 | u32 i, nlb, ts, phys, virt; | |
516 | ||
517 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
518 | return; | |
519 | ||
520 | bip = bio_integrity(req->bio); | |
521 | if (!bip) | |
522 | return; | |
523 | ||
524 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
525 | if (!pmap) | |
526 | return; | |
527 | ||
528 | p = pmap; | |
529 | virt = bip_get_seed(bip); | |
530 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
531 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
532 | ts = ns->disk->integrity->tuple_size; | |
533 | ||
534 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
535 | pi = (struct t10_pi_tuple *)p; | |
536 | dif_swap(phys, virt, pi); | |
537 | p += ts; | |
538 | } | |
539 | kunmap_atomic(pmap); | |
540 | } | |
541 | ||
52b68d7e KB |
542 | static int nvme_noop_verify(struct blk_integrity_iter *iter) |
543 | { | |
544 | return 0; | |
545 | } | |
546 | ||
547 | static int nvme_noop_generate(struct blk_integrity_iter *iter) | |
548 | { | |
549 | return 0; | |
550 | } | |
551 | ||
552 | struct blk_integrity nvme_meta_noop = { | |
553 | .name = "NVME_META_NOOP", | |
554 | .generate_fn = nvme_noop_generate, | |
555 | .verify_fn = nvme_noop_verify, | |
556 | }; | |
557 | ||
558 | static void nvme_init_integrity(struct nvme_ns *ns) | |
559 | { | |
560 | struct blk_integrity integrity; | |
561 | ||
562 | switch (ns->pi_type) { | |
563 | case NVME_NS_DPS_PI_TYPE3: | |
564 | integrity = t10_pi_type3_crc; | |
565 | break; | |
566 | case NVME_NS_DPS_PI_TYPE1: | |
567 | case NVME_NS_DPS_PI_TYPE2: | |
568 | integrity = t10_pi_type1_crc; | |
569 | break; | |
570 | default: | |
571 | integrity = nvme_meta_noop; | |
572 | break; | |
573 | } | |
574 | integrity.tuple_size = ns->ms; | |
575 | blk_integrity_register(ns->disk, &integrity); | |
576 | blk_queue_max_integrity_segments(ns->queue, 1); | |
577 | } | |
578 | #else /* CONFIG_BLK_DEV_INTEGRITY */ | |
579 | static void nvme_dif_remap(struct request *req, | |
580 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
581 | { | |
582 | } | |
583 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
584 | { | |
585 | } | |
586 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
587 | { | |
588 | } | |
589 | static void nvme_init_integrity(struct nvme_ns *ns) | |
590 | { | |
591 | } | |
592 | #endif | |
593 | ||
a4aea562 | 594 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
595 | struct nvme_completion *cqe) |
596 | { | |
eca18b23 | 597 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 598 | struct request *req = iod_get_private(iod); |
a4aea562 MB |
599 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
600 | ||
b60503ba MW |
601 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
602 | ||
edd10d33 | 603 | if (unlikely(status)) { |
a4aea562 MB |
604 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
605 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
606 | unsigned long flags; |
607 | ||
a4aea562 | 608 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
609 | spin_lock_irqsave(req->q->queue_lock, flags); |
610 | if (!blk_queue_stopped(req->q)) | |
611 | blk_mq_kick_requeue_list(req->q); | |
612 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
edd10d33 KB |
613 | return; |
614 | } | |
a4aea562 MB |
615 | req->errors = nvme_error_status(status); |
616 | } else | |
617 | req->errors = 0; | |
618 | ||
619 | if (cmd_rq->aborted) | |
620 | dev_warn(&nvmeq->dev->pci_dev->dev, | |
621 | "completing aborted command with status:%04x\n", | |
622 | status); | |
623 | ||
e1e5e564 | 624 | if (iod->nents) { |
a4aea562 MB |
625 | dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents, |
626 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
e1e5e564 KB |
627 | if (blk_integrity_rq(req)) { |
628 | if (!rq_data_dir(req)) | |
629 | nvme_dif_remap(req, nvme_dif_complete); | |
630 | dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1, | |
631 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
632 | } | |
633 | } | |
edd10d33 | 634 | nvme_free_iod(nvmeq->dev, iod); |
3291fa57 | 635 | |
a4aea562 | 636 | blk_mq_complete_request(req); |
b60503ba MW |
637 | } |
638 | ||
184d2944 | 639 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
edd10d33 KB |
640 | int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len, |
641 | gfp_t gfp) | |
ff22b54f | 642 | { |
99802a7a | 643 | struct dma_pool *pool; |
eca18b23 MW |
644 | int length = total_len; |
645 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
646 | int dma_len = sg_dma_len(sg); |
647 | u64 dma_addr = sg_dma_address(sg); | |
648 | int offset = offset_in_page(dma_addr); | |
e025344c | 649 | __le64 *prp_list; |
eca18b23 | 650 | __le64 **list = iod_list(iod); |
e025344c | 651 | dma_addr_t prp_dma; |
eca18b23 | 652 | int nprps, i; |
1d090624 | 653 | u32 page_size = dev->page_size; |
ff22b54f | 654 | |
1d090624 | 655 | length -= (page_size - offset); |
ff22b54f | 656 | if (length <= 0) |
eca18b23 | 657 | return total_len; |
ff22b54f | 658 | |
1d090624 | 659 | dma_len -= (page_size - offset); |
ff22b54f | 660 | if (dma_len) { |
1d090624 | 661 | dma_addr += (page_size - offset); |
ff22b54f MW |
662 | } else { |
663 | sg = sg_next(sg); | |
664 | dma_addr = sg_dma_address(sg); | |
665 | dma_len = sg_dma_len(sg); | |
666 | } | |
667 | ||
1d090624 | 668 | if (length <= page_size) { |
edd10d33 | 669 | iod->first_dma = dma_addr; |
eca18b23 | 670 | return total_len; |
e025344c SMM |
671 | } |
672 | ||
1d090624 | 673 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
674 | if (nprps <= (256 / 8)) { |
675 | pool = dev->prp_small_pool; | |
eca18b23 | 676 | iod->npages = 0; |
99802a7a MW |
677 | } else { |
678 | pool = dev->prp_page_pool; | |
eca18b23 | 679 | iod->npages = 1; |
99802a7a MW |
680 | } |
681 | ||
b77954cb MW |
682 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
683 | if (!prp_list) { | |
edd10d33 | 684 | iod->first_dma = dma_addr; |
eca18b23 | 685 | iod->npages = -1; |
1d090624 | 686 | return (total_len - length) + page_size; |
b77954cb | 687 | } |
eca18b23 MW |
688 | list[0] = prp_list; |
689 | iod->first_dma = prp_dma; | |
e025344c SMM |
690 | i = 0; |
691 | for (;;) { | |
1d090624 | 692 | if (i == page_size >> 3) { |
e025344c | 693 | __le64 *old_prp_list = prp_list; |
b77954cb | 694 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
695 | if (!prp_list) |
696 | return total_len - length; | |
697 | list[iod->npages++] = prp_list; | |
7523d834 MW |
698 | prp_list[0] = old_prp_list[i - 1]; |
699 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
700 | i = 1; | |
e025344c SMM |
701 | } |
702 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
703 | dma_len -= page_size; |
704 | dma_addr += page_size; | |
705 | length -= page_size; | |
e025344c SMM |
706 | if (length <= 0) |
707 | break; | |
708 | if (dma_len > 0) | |
709 | continue; | |
710 | BUG_ON(dma_len < 0); | |
711 | sg = sg_next(sg); | |
712 | dma_addr = sg_dma_address(sg); | |
713 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
714 | } |
715 | ||
eca18b23 | 716 | return total_len; |
ff22b54f MW |
717 | } |
718 | ||
a4aea562 MB |
719 | /* |
720 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
721 | * worth having a special pool for these or additional cases to handle freeing | |
722 | * the iod. | |
723 | */ | |
724 | static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
725 | struct request *req, struct nvme_iod *iod) | |
0e5e4f0e | 726 | { |
edd10d33 KB |
727 | struct nvme_dsm_range *range = |
728 | (struct nvme_dsm_range *)iod_list(iod)[0]; | |
0e5e4f0e KB |
729 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
730 | ||
0e5e4f0e | 731 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
732 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
733 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e KB |
734 | |
735 | memset(cmnd, 0, sizeof(*cmnd)); | |
736 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
a4aea562 | 737 | cmnd->dsm.command_id = req->tag; |
0e5e4f0e KB |
738 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); |
739 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
740 | cmnd->dsm.nr = 0; | |
741 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
742 | ||
743 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
744 | nvmeq->sq_tail = 0; | |
745 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
0e5e4f0e KB |
746 | } |
747 | ||
a4aea562 | 748 | static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
00df5cb4 MW |
749 | int cmdid) |
750 | { | |
751 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
752 | ||
753 | memset(cmnd, 0, sizeof(*cmnd)); | |
754 | cmnd->common.opcode = nvme_cmd_flush; | |
755 | cmnd->common.command_id = cmdid; | |
756 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
757 | ||
758 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
759 | nvmeq->sq_tail = 0; | |
760 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
00df5cb4 MW |
761 | } |
762 | ||
a4aea562 MB |
763 | static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
764 | struct nvme_ns *ns) | |
b60503ba | 765 | { |
ac3dd5bd | 766 | struct request *req = iod_get_private(iod); |
ff22b54f | 767 | struct nvme_command *cmnd; |
a4aea562 MB |
768 | u16 control = 0; |
769 | u32 dsmgmt = 0; | |
00df5cb4 | 770 | |
a4aea562 | 771 | if (req->cmd_flags & REQ_FUA) |
b60503ba | 772 | control |= NVME_RW_FUA; |
a4aea562 | 773 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) |
b60503ba MW |
774 | control |= NVME_RW_LR; |
775 | ||
a4aea562 | 776 | if (req->cmd_flags & REQ_RAHEAD) |
b60503ba MW |
777 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; |
778 | ||
ff22b54f | 779 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b8deb62c | 780 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 781 | |
a4aea562 MB |
782 | cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); |
783 | cmnd->rw.command_id = req->tag; | |
ff22b54f | 784 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); |
edd10d33 KB |
785 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
786 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
a4aea562 MB |
787 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); |
788 | cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
e1e5e564 KB |
789 | |
790 | if (blk_integrity_rq(req)) { | |
791 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
792 | switch (ns->pi_type) { | |
793 | case NVME_NS_DPS_PI_TYPE3: | |
794 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
795 | break; | |
796 | case NVME_NS_DPS_PI_TYPE1: | |
797 | case NVME_NS_DPS_PI_TYPE2: | |
798 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
799 | NVME_RW_PRINFO_PRCHK_REF; | |
800 | cmnd->rw.reftag = cpu_to_le32( | |
801 | nvme_block_nr(ns, blk_rq_pos(req))); | |
802 | break; | |
803 | } | |
804 | } else if (ns->ms) | |
805 | control |= NVME_RW_PRINFO_PRACT; | |
806 | ||
ff22b54f MW |
807 | cmnd->rw.control = cpu_to_le16(control); |
808 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 809 | |
b60503ba MW |
810 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
811 | nvmeq->sq_tail = 0; | |
7547881d | 812 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 813 | |
1974b1ae | 814 | return 0; |
edd10d33 KB |
815 | } |
816 | ||
a4aea562 MB |
817 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
818 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 819 | { |
a4aea562 MB |
820 | struct nvme_ns *ns = hctx->queue->queuedata; |
821 | struct nvme_queue *nvmeq = hctx->driver_data; | |
822 | struct request *req = bd->rq; | |
823 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 824 | struct nvme_iod *iod; |
a4aea562 | 825 | enum dma_data_direction dma_dir; |
edd10d33 | 826 | |
e1e5e564 KB |
827 | /* |
828 | * If formated with metadata, require the block layer provide a buffer | |
829 | * unless this namespace is formated such that the metadata can be | |
830 | * stripped/generated by the controller with PRACT=1. | |
831 | */ | |
832 | if (ns->ms && !blk_integrity_rq(req)) { | |
833 | if (!(ns->pi_type && ns->ms == 8)) { | |
834 | req->errors = -EFAULT; | |
835 | blk_mq_complete_request(req); | |
836 | return BLK_MQ_RQ_QUEUE_OK; | |
837 | } | |
838 | } | |
839 | ||
ac3dd5bd | 840 | iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC); |
edd10d33 | 841 | if (!iod) |
fe54303e | 842 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 843 | |
a4aea562 | 844 | if (req->cmd_flags & REQ_DISCARD) { |
edd10d33 KB |
845 | void *range; |
846 | /* | |
847 | * We reuse the small pool to allocate the 16-byte range here | |
848 | * as it is not worth having a special pool for these or | |
849 | * additional cases to handle freeing the iod. | |
850 | */ | |
851 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, | |
852 | GFP_ATOMIC, | |
853 | &iod->first_dma); | |
a4aea562 | 854 | if (!range) |
fe54303e | 855 | goto retry_cmd; |
edd10d33 KB |
856 | iod_list(iod)[0] = (__le64 *)range; |
857 | iod->npages = 0; | |
ac3dd5bd | 858 | } else if (req->nr_phys_segments) { |
a4aea562 MB |
859 | dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; |
860 | ||
ac3dd5bd | 861 | sg_init_table(iod->sg, req->nr_phys_segments); |
a4aea562 | 862 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
fe54303e JA |
863 | if (!iod->nents) |
864 | goto error_cmd; | |
a4aea562 MB |
865 | |
866 | if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir)) | |
fe54303e | 867 | goto retry_cmd; |
a4aea562 | 868 | |
fe54303e JA |
869 | if (blk_rq_bytes(req) != |
870 | nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) { | |
871 | dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, | |
872 | iod->nents, dma_dir); | |
873 | goto retry_cmd; | |
874 | } | |
e1e5e564 KB |
875 | if (blk_integrity_rq(req)) { |
876 | if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) | |
877 | goto error_cmd; | |
878 | ||
879 | sg_init_table(iod->meta_sg, 1); | |
880 | if (blk_rq_map_integrity_sg( | |
881 | req->q, req->bio, iod->meta_sg) != 1) | |
882 | goto error_cmd; | |
883 | ||
884 | if (rq_data_dir(req)) | |
885 | nvme_dif_remap(req, nvme_dif_prep); | |
886 | ||
887 | if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) | |
888 | goto error_cmd; | |
889 | } | |
edd10d33 | 890 | } |
1974b1ae | 891 | |
9af8785a | 892 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 MB |
893 | spin_lock_irq(&nvmeq->q_lock); |
894 | if (req->cmd_flags & REQ_DISCARD) | |
895 | nvme_submit_discard(nvmeq, ns, req, iod); | |
896 | else if (req->cmd_flags & REQ_FLUSH) | |
897 | nvme_submit_flush(nvmeq, ns, req->tag); | |
898 | else | |
899 | nvme_submit_iod(nvmeq, iod, ns); | |
900 | ||
901 | nvme_process_cq(nvmeq); | |
902 | spin_unlock_irq(&nvmeq->q_lock); | |
903 | return BLK_MQ_RQ_QUEUE_OK; | |
904 | ||
fe54303e JA |
905 | error_cmd: |
906 | nvme_free_iod(nvmeq->dev, iod); | |
907 | return BLK_MQ_RQ_QUEUE_ERROR; | |
908 | retry_cmd: | |
eca18b23 | 909 | nvme_free_iod(nvmeq->dev, iod); |
fe54303e | 910 | return BLK_MQ_RQ_QUEUE_BUSY; |
b60503ba MW |
911 | } |
912 | ||
e9539f47 | 913 | static int nvme_process_cq(struct nvme_queue *nvmeq) |
b60503ba | 914 | { |
82123460 | 915 | u16 head, phase; |
b60503ba | 916 | |
b60503ba | 917 | head = nvmeq->cq_head; |
82123460 | 918 | phase = nvmeq->cq_phase; |
b60503ba MW |
919 | |
920 | for (;;) { | |
c2f5b650 MW |
921 | void *ctx; |
922 | nvme_completion_fn fn; | |
b60503ba | 923 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 924 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
925 | break; |
926 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
927 | if (++head == nvmeq->q_depth) { | |
928 | head = 0; | |
82123460 | 929 | phase = !phase; |
b60503ba | 930 | } |
a4aea562 | 931 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 932 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
933 | } |
934 | ||
935 | /* If the controller ignores the cq head doorbell and continuously | |
936 | * writes to the queue, it is theoretically possible to wrap around | |
937 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
938 | * requires that 0.1% of your interrupts are handled, so this isn't | |
939 | * a big problem. | |
940 | */ | |
82123460 | 941 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
e9539f47 | 942 | return 0; |
b60503ba | 943 | |
b80d5ccc | 944 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
b60503ba | 945 | nvmeq->cq_head = head; |
82123460 | 946 | nvmeq->cq_phase = phase; |
b60503ba | 947 | |
e9539f47 MW |
948 | nvmeq->cqe_seen = 1; |
949 | return 1; | |
b60503ba MW |
950 | } |
951 | ||
a4aea562 MB |
952 | /* Admin queue isn't initialized as a request queue. If at some point this |
953 | * happens anyway, make sure to notify the user */ | |
954 | static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx, | |
955 | const struct blk_mq_queue_data *bd) | |
7d822457 | 956 | { |
a4aea562 MB |
957 | WARN_ON_ONCE(1); |
958 | return BLK_MQ_RQ_QUEUE_ERROR; | |
7d822457 MW |
959 | } |
960 | ||
b60503ba | 961 | static irqreturn_t nvme_irq(int irq, void *data) |
58ffacb5 MW |
962 | { |
963 | irqreturn_t result; | |
964 | struct nvme_queue *nvmeq = data; | |
965 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
966 | nvme_process_cq(nvmeq); |
967 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
968 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
969 | spin_unlock(&nvmeq->q_lock); |
970 | return result; | |
971 | } | |
972 | ||
973 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
974 | { | |
975 | struct nvme_queue *nvmeq = data; | |
976 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
977 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
978 | return IRQ_NONE; | |
979 | return IRQ_WAKE_THREAD; | |
980 | } | |
981 | ||
c2f5b650 MW |
982 | struct sync_cmd_info { |
983 | struct task_struct *task; | |
984 | u32 result; | |
985 | int status; | |
986 | }; | |
987 | ||
edd10d33 | 988 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
989 | struct nvme_completion *cqe) |
990 | { | |
991 | struct sync_cmd_info *cmdinfo = ctx; | |
992 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
993 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
994 | wake_up_process(cmdinfo->task); | |
995 | } | |
996 | ||
b60503ba MW |
997 | /* |
998 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
999 | * if the result is positive, it's an NVM Express status code | |
1000 | */ | |
a4aea562 | 1001 | static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd, |
5d0f6131 | 1002 | u32 *result, unsigned timeout) |
b60503ba | 1003 | { |
b60503ba | 1004 | struct sync_cmd_info cmdinfo; |
a4aea562 MB |
1005 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1006 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
b60503ba MW |
1007 | |
1008 | cmdinfo.task = current; | |
1009 | cmdinfo.status = -EINTR; | |
1010 | ||
a4aea562 MB |
1011 | cmd->common.command_id = req->tag; |
1012 | ||
1013 | nvme_set_info(cmd_rq, &cmdinfo, sync_completion); | |
b60503ba | 1014 | |
0c0f9b95 KB |
1015 | set_current_state(TASK_UNINTERRUPTIBLE); |
1016 | nvme_submit_cmd(nvmeq, cmd); | |
1017 | schedule(); | |
3c0cf138 | 1018 | |
b60503ba MW |
1019 | if (result) |
1020 | *result = cmdinfo.result; | |
b60503ba MW |
1021 | return cmdinfo.status; |
1022 | } | |
1023 | ||
a4aea562 MB |
1024 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
1025 | { | |
1026 | struct nvme_queue *nvmeq = dev->queues[0]; | |
1027 | struct nvme_command c; | |
1028 | struct nvme_cmd_info *cmd_info; | |
1029 | struct request *req; | |
1030 | ||
6dcc0cf6 | 1031 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false); |
9f173b33 DC |
1032 | if (IS_ERR(req)) |
1033 | return PTR_ERR(req); | |
a4aea562 | 1034 | |
c917dfe5 | 1035 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 MB |
1036 | cmd_info = blk_mq_rq_to_pdu(req); |
1037 | nvme_set_info(cmd_info, req, async_req_completion); | |
1038 | ||
1039 | memset(&c, 0, sizeof(c)); | |
1040 | c.common.opcode = nvme_admin_async_event; | |
1041 | c.common.command_id = req->tag; | |
1042 | ||
1043 | return __nvme_submit_cmd(nvmeq, &c); | |
1044 | } | |
1045 | ||
1046 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
1047 | struct nvme_command *cmd, |
1048 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
1049 | { | |
a4aea562 MB |
1050 | struct nvme_queue *nvmeq = dev->queues[0]; |
1051 | struct request *req; | |
1052 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1053 | |
a4aea562 | 1054 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false); |
9f173b33 DC |
1055 | if (IS_ERR(req)) |
1056 | return PTR_ERR(req); | |
a4aea562 MB |
1057 | |
1058 | req->timeout = timeout; | |
1059 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1060 | cmdinfo->req = req; | |
1061 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1062 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1063 | |
1064 | cmd->common.command_id = req->tag; | |
1065 | ||
4f5099af | 1066 | return nvme_submit_cmd(nvmeq, cmd); |
4d115420 KB |
1067 | } |
1068 | ||
a64e6bb4 | 1069 | static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
a4aea562 | 1070 | u32 *result, unsigned timeout) |
b60503ba | 1071 | { |
a4aea562 MB |
1072 | int res; |
1073 | struct request *req; | |
1074 | ||
1075 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false); | |
97fe3832 JA |
1076 | if (IS_ERR(req)) |
1077 | return PTR_ERR(req); | |
a4aea562 | 1078 | res = nvme_submit_sync_cmd(req, cmd, result, timeout); |
9d135bb8 | 1079 | blk_mq_free_request(req); |
a4aea562 | 1080 | return res; |
4f5099af KB |
1081 | } |
1082 | ||
a4aea562 | 1083 | int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
4f5099af KB |
1084 | u32 *result) |
1085 | { | |
a4aea562 | 1086 | return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
1087 | } |
1088 | ||
a4aea562 MB |
1089 | int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns, |
1090 | struct nvme_command *cmd, u32 *result) | |
4d115420 | 1091 | { |
a4aea562 MB |
1092 | int res; |
1093 | struct request *req; | |
1094 | ||
1095 | req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT), | |
1096 | false); | |
97fe3832 JA |
1097 | if (IS_ERR(req)) |
1098 | return PTR_ERR(req); | |
a4aea562 | 1099 | res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT); |
9d135bb8 | 1100 | blk_mq_free_request(req); |
a4aea562 | 1101 | return res; |
4d115420 KB |
1102 | } |
1103 | ||
b60503ba MW |
1104 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1105 | { | |
b60503ba MW |
1106 | struct nvme_command c; |
1107 | ||
1108 | memset(&c, 0, sizeof(c)); | |
1109 | c.delete_queue.opcode = opcode; | |
1110 | c.delete_queue.qid = cpu_to_le16(id); | |
1111 | ||
a4aea562 | 1112 | return nvme_submit_admin_cmd(dev, &c, NULL); |
b60503ba MW |
1113 | } |
1114 | ||
1115 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1116 | struct nvme_queue *nvmeq) | |
1117 | { | |
b60503ba MW |
1118 | struct nvme_command c; |
1119 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1120 | ||
1121 | memset(&c, 0, sizeof(c)); | |
1122 | c.create_cq.opcode = nvme_admin_create_cq; | |
1123 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1124 | c.create_cq.cqid = cpu_to_le16(qid); | |
1125 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1126 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1127 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1128 | ||
a4aea562 | 1129 | return nvme_submit_admin_cmd(dev, &c, NULL); |
b60503ba MW |
1130 | } |
1131 | ||
1132 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1133 | struct nvme_queue *nvmeq) | |
1134 | { | |
b60503ba MW |
1135 | struct nvme_command c; |
1136 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1137 | ||
1138 | memset(&c, 0, sizeof(c)); | |
1139 | c.create_sq.opcode = nvme_admin_create_sq; | |
1140 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1141 | c.create_sq.sqid = cpu_to_le16(qid); | |
1142 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1143 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1144 | c.create_sq.cqid = cpu_to_le16(qid); | |
1145 | ||
a4aea562 | 1146 | return nvme_submit_admin_cmd(dev, &c, NULL); |
b60503ba MW |
1147 | } |
1148 | ||
1149 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1150 | { | |
1151 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1152 | } | |
1153 | ||
1154 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1155 | { | |
1156 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1157 | } | |
1158 | ||
5d0f6131 | 1159 | int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
bc5fc7e4 MW |
1160 | dma_addr_t dma_addr) |
1161 | { | |
1162 | struct nvme_command c; | |
1163 | ||
1164 | memset(&c, 0, sizeof(c)); | |
1165 | c.identify.opcode = nvme_admin_identify; | |
1166 | c.identify.nsid = cpu_to_le32(nsid); | |
1167 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
1168 | c.identify.cns = cpu_to_le32(cns); | |
1169 | ||
1170 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
1171 | } | |
1172 | ||
5d0f6131 | 1173 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 1174 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
1175 | { |
1176 | struct nvme_command c; | |
1177 | ||
1178 | memset(&c, 0, sizeof(c)); | |
1179 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 1180 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
1181 | c.features.prp1 = cpu_to_le64(dma_addr); |
1182 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 1183 | |
08df1e05 | 1184 | return nvme_submit_admin_cmd(dev, &c, result); |
df348139 MW |
1185 | } |
1186 | ||
5d0f6131 VV |
1187 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
1188 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
1189 | { |
1190 | struct nvme_command c; | |
1191 | ||
1192 | memset(&c, 0, sizeof(c)); | |
1193 | c.features.opcode = nvme_admin_set_features; | |
1194 | c.features.prp1 = cpu_to_le64(dma_addr); | |
1195 | c.features.fid = cpu_to_le32(fid); | |
1196 | c.features.dword11 = cpu_to_le32(dword11); | |
1197 | ||
bc5fc7e4 MW |
1198 | return nvme_submit_admin_cmd(dev, &c, result); |
1199 | } | |
1200 | ||
c30341dc | 1201 | /** |
a4aea562 | 1202 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1203 | * |
1204 | * Schedule controller reset if the command was already aborted once before and | |
1205 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1206 | */ | |
a4aea562 | 1207 | static void nvme_abort_req(struct request *req) |
c30341dc | 1208 | { |
a4aea562 MB |
1209 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1210 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1211 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1212 | struct request *abort_req; |
1213 | struct nvme_cmd_info *abort_cmd; | |
1214 | struct nvme_command cmd; | |
c30341dc | 1215 | |
a4aea562 | 1216 | if (!nvmeq->qid || cmd_rq->aborted) { |
7a509a6b KB |
1217 | unsigned long flags; |
1218 | ||
1219 | spin_lock_irqsave(&dev_list_lock, flags); | |
c30341dc | 1220 | if (work_busy(&dev->reset_work)) |
7a509a6b | 1221 | goto out; |
c30341dc KB |
1222 | list_del_init(&dev->node); |
1223 | dev_warn(&dev->pci_dev->dev, | |
a4aea562 MB |
1224 | "I/O %d QID %d timeout, reset controller\n", |
1225 | req->tag, nvmeq->qid); | |
9ca97374 | 1226 | dev->reset_workfn = nvme_reset_failed_dev; |
c30341dc | 1227 | queue_work(nvme_workq, &dev->reset_work); |
7a509a6b KB |
1228 | out: |
1229 | spin_unlock_irqrestore(&dev_list_lock, flags); | |
c30341dc KB |
1230 | return; |
1231 | } | |
1232 | ||
1233 | if (!dev->abort_limit) | |
1234 | return; | |
1235 | ||
a4aea562 MB |
1236 | abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, |
1237 | false); | |
9f173b33 | 1238 | if (IS_ERR(abort_req)) |
c30341dc KB |
1239 | return; |
1240 | ||
a4aea562 MB |
1241 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1242 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1243 | ||
c30341dc KB |
1244 | memset(&cmd, 0, sizeof(cmd)); |
1245 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1246 | cmd.abort.cid = req->tag; |
c30341dc | 1247 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1248 | cmd.abort.command_id = abort_req->tag; |
c30341dc KB |
1249 | |
1250 | --dev->abort_limit; | |
a4aea562 | 1251 | cmd_rq->aborted = 1; |
c30341dc | 1252 | |
a4aea562 | 1253 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1254 | nvmeq->qid); |
a4aea562 MB |
1255 | if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) { |
1256 | dev_warn(nvmeq->q_dmadev, | |
1257 | "Could not abort I/O %d QID %d", | |
1258 | req->tag, nvmeq->qid); | |
c87fd540 | 1259 | blk_mq_free_request(abort_req); |
a4aea562 | 1260 | } |
c30341dc KB |
1261 | } |
1262 | ||
a4aea562 MB |
1263 | static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx, |
1264 | struct request *req, void *data, bool reserved) | |
a09115b2 | 1265 | { |
a4aea562 MB |
1266 | struct nvme_queue *nvmeq = data; |
1267 | void *ctx; | |
1268 | nvme_completion_fn fn; | |
1269 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1270 | struct nvme_completion cqe; |
1271 | ||
1272 | if (!blk_mq_request_started(req)) | |
1273 | return; | |
a09115b2 | 1274 | |
a4aea562 | 1275 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1276 | |
a4aea562 MB |
1277 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1278 | return; | |
1279 | ||
cef6a948 KB |
1280 | if (blk_queue_dying(req->q)) |
1281 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1282 | else | |
1283 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1284 | ||
1285 | ||
a4aea562 MB |
1286 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1287 | req->tag, nvmeq->qid); | |
1288 | ctx = cancel_cmd_info(cmd, &fn); | |
1289 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1290 | } |
1291 | ||
a4aea562 | 1292 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1293 | { |
a4aea562 MB |
1294 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1295 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1296 | ||
1297 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1298 | nvmeq->qid); | |
7a509a6b | 1299 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1300 | nvme_abort_req(req); |
7a509a6b | 1301 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1302 | |
07836e65 KB |
1303 | /* |
1304 | * The aborted req will be completed on receiving the abort req. | |
1305 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1306 | * as the device then is in a faulty state. | |
1307 | */ | |
1308 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1309 | } |
22404274 | 1310 | |
a4aea562 MB |
1311 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1312 | { | |
9e866774 MW |
1313 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1314 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1315 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1316 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1317 | kfree(nvmeq); | |
1318 | } | |
1319 | ||
a1a5ef99 | 1320 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1321 | { |
1322 | int i; | |
1323 | ||
a1a5ef99 | 1324 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1325 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1326 | dev->queue_count--; |
a4aea562 | 1327 | dev->queues[i] = NULL; |
f435c282 | 1328 | nvme_free_queue(nvmeq); |
121c7ad4 | 1329 | } |
22404274 KB |
1330 | } |
1331 | ||
4d115420 KB |
1332 | /** |
1333 | * nvme_suspend_queue - put queue into suspended state | |
1334 | * @nvmeq - queue to suspend | |
4d115420 KB |
1335 | */ |
1336 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1337 | { |
2b25d981 | 1338 | int vector; |
b60503ba | 1339 | |
a09115b2 | 1340 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1341 | if (nvmeq->cq_vector == -1) { |
1342 | spin_unlock_irq(&nvmeq->q_lock); | |
1343 | return 1; | |
1344 | } | |
1345 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1346 | nvmeq->dev->online_queues--; |
2b25d981 | 1347 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1348 | spin_unlock_irq(&nvmeq->q_lock); |
1349 | ||
aba2080f MW |
1350 | irq_set_affinity_hint(vector, NULL); |
1351 | free_irq(vector, nvmeq); | |
b60503ba | 1352 | |
4d115420 KB |
1353 | return 0; |
1354 | } | |
b60503ba | 1355 | |
4d115420 KB |
1356 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1357 | { | |
a4aea562 MB |
1358 | struct blk_mq_hw_ctx *hctx = nvmeq->hctx; |
1359 | ||
22404274 | 1360 | spin_lock_irq(&nvmeq->q_lock); |
a4aea562 MB |
1361 | if (hctx && hctx->tags) |
1362 | blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1363 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1364 | } |
1365 | ||
4d115420 KB |
1366 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1367 | { | |
a4aea562 | 1368 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1369 | |
1370 | if (!nvmeq) | |
1371 | return; | |
1372 | if (nvme_suspend_queue(nvmeq)) | |
1373 | return; | |
1374 | ||
0e53d180 KB |
1375 | /* Don't tell the adapter to delete the admin queue. |
1376 | * Don't tell a removed adapter to delete IO queues. */ | |
1377 | if (qid && readl(&dev->bar->csts) != -1) { | |
b60503ba MW |
1378 | adapter_delete_sq(dev, qid); |
1379 | adapter_delete_cq(dev, qid); | |
1380 | } | |
0fb59cbc KB |
1381 | if (!qid && dev->admin_q) |
1382 | blk_mq_freeze_queue_start(dev->admin_q); | |
07836e65 KB |
1383 | |
1384 | spin_lock_irq(&nvmeq->q_lock); | |
1385 | nvme_process_cq(nvmeq); | |
1386 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1387 | } |
1388 | ||
1389 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
2b25d981 | 1390 | int depth) |
b60503ba MW |
1391 | { |
1392 | struct device *dmadev = &dev->pci_dev->dev; | |
a4aea562 | 1393 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1394 | if (!nvmeq) |
1395 | return NULL; | |
1396 | ||
4d51abf9 JP |
1397 | nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth), |
1398 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
b60503ba MW |
1399 | if (!nvmeq->cqes) |
1400 | goto free_nvmeq; | |
b60503ba MW |
1401 | |
1402 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
1403 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1404 | if (!nvmeq->sq_cmds) | |
1405 | goto free_cqdma; | |
1406 | ||
1407 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 1408 | nvmeq->dev = dev; |
3193f07b MW |
1409 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1410 | dev->instance, qid); | |
b60503ba MW |
1411 | spin_lock_init(&nvmeq->q_lock); |
1412 | nvmeq->cq_head = 0; | |
82123460 | 1413 | nvmeq->cq_phase = 1; |
b80d5ccc | 1414 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1415 | nvmeq->q_depth = depth; |
c30341dc | 1416 | nvmeq->qid = qid; |
22404274 | 1417 | dev->queue_count++; |
a4aea562 | 1418 | dev->queues[qid] = nvmeq; |
b60503ba MW |
1419 | |
1420 | return nvmeq; | |
1421 | ||
1422 | free_cqdma: | |
68b8eca5 | 1423 | dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1424 | nvmeq->cq_dma_addr); |
1425 | free_nvmeq: | |
1426 | kfree(nvmeq); | |
1427 | return NULL; | |
1428 | } | |
1429 | ||
3001082c MW |
1430 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1431 | const char *name) | |
1432 | { | |
58ffacb5 MW |
1433 | if (use_threaded_interrupts) |
1434 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1435 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1436 | name, nvmeq); |
3001082c | 1437 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1438 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1439 | } |
1440 | ||
22404274 | 1441 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1442 | { |
22404274 | 1443 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1444 | |
7be50e93 | 1445 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1446 | nvmeq->sq_tail = 0; |
1447 | nvmeq->cq_head = 0; | |
1448 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1449 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1450 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1451 | dev->online_queues++; |
7be50e93 | 1452 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1453 | } |
1454 | ||
1455 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1456 | { | |
1457 | struct nvme_dev *dev = nvmeq->dev; | |
1458 | int result; | |
3f85d50b | 1459 | |
2b25d981 | 1460 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1461 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1462 | if (result < 0) | |
22404274 | 1463 | return result; |
b60503ba MW |
1464 | |
1465 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1466 | if (result < 0) | |
1467 | goto release_cq; | |
1468 | ||
3193f07b | 1469 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1470 | if (result < 0) |
1471 | goto release_sq; | |
1472 | ||
22404274 | 1473 | nvme_init_queue(nvmeq, qid); |
22404274 | 1474 | return result; |
b60503ba MW |
1475 | |
1476 | release_sq: | |
1477 | adapter_delete_sq(dev, qid); | |
1478 | release_cq: | |
1479 | adapter_delete_cq(dev, qid); | |
22404274 | 1480 | return result; |
b60503ba MW |
1481 | } |
1482 | ||
ba47e386 MW |
1483 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1484 | { | |
1485 | unsigned long timeout; | |
1486 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1487 | ||
1488 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1489 | ||
1490 | while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) { | |
1491 | msleep(100); | |
1492 | if (fatal_signal_pending(current)) | |
1493 | return -EINTR; | |
1494 | if (time_after(jiffies, timeout)) { | |
1495 | dev_err(&dev->pci_dev->dev, | |
27e8166c MW |
1496 | "Device not ready; aborting %s\n", enabled ? |
1497 | "initialisation" : "reset"); | |
ba47e386 MW |
1498 | return -ENODEV; |
1499 | } | |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | /* | |
1506 | * If the device has been passed off to us in an enabled state, just clear | |
1507 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1508 | * bits', but doing so may cause the device to complete commands to the | |
1509 | * admin queue ... and we don't know what memory that might be pointing at! | |
1510 | */ | |
1511 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1512 | { | |
01079522 DM |
1513 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1514 | dev->ctrl_config &= ~NVME_CC_ENABLE; | |
1515 | writel(dev->ctrl_config, &dev->bar->cc); | |
44af146a | 1516 | |
ba47e386 MW |
1517 | return nvme_wait_ready(dev, cap, false); |
1518 | } | |
1519 | ||
1520 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1521 | { | |
01079522 DM |
1522 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1523 | dev->ctrl_config |= NVME_CC_ENABLE; | |
1524 | writel(dev->ctrl_config, &dev->bar->cc); | |
1525 | ||
ba47e386 MW |
1526 | return nvme_wait_ready(dev, cap, true); |
1527 | } | |
1528 | ||
1894d8f1 KB |
1529 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1530 | { | |
1531 | unsigned long timeout; | |
1894d8f1 | 1532 | |
01079522 DM |
1533 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1534 | dev->ctrl_config |= NVME_CC_SHN_NORMAL; | |
1535 | ||
1536 | writel(dev->ctrl_config, &dev->bar->cc); | |
1894d8f1 | 1537 | |
2484f407 | 1538 | timeout = SHUTDOWN_TIMEOUT + jiffies; |
1894d8f1 KB |
1539 | while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) != |
1540 | NVME_CSTS_SHST_CMPLT) { | |
1541 | msleep(100); | |
1542 | if (fatal_signal_pending(current)) | |
1543 | return -EINTR; | |
1544 | if (time_after(jiffies, timeout)) { | |
1545 | dev_err(&dev->pci_dev->dev, | |
1546 | "Device shutdown incomplete; abort shutdown\n"); | |
1547 | return -ENODEV; | |
1548 | } | |
1549 | } | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
a4aea562 MB |
1554 | static struct blk_mq_ops nvme_mq_admin_ops = { |
1555 | .queue_rq = nvme_admin_queue_rq, | |
1556 | .map_queue = blk_mq_map_queue, | |
1557 | .init_hctx = nvme_admin_init_hctx, | |
2c30540b | 1558 | .exit_hctx = nvme_exit_hctx, |
a4aea562 MB |
1559 | .init_request = nvme_admin_init_request, |
1560 | .timeout = nvme_timeout, | |
1561 | }; | |
1562 | ||
1563 | static struct blk_mq_ops nvme_mq_ops = { | |
1564 | .queue_rq = nvme_queue_rq, | |
1565 | .map_queue = blk_mq_map_queue, | |
1566 | .init_hctx = nvme_init_hctx, | |
2c30540b | 1567 | .exit_hctx = nvme_exit_hctx, |
a4aea562 MB |
1568 | .init_request = nvme_init_request, |
1569 | .timeout = nvme_timeout, | |
1570 | }; | |
1571 | ||
ea191d2f KB |
1572 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1573 | { | |
1574 | if (dev->admin_q && !blk_queue_dying(dev->admin_q)) { | |
1575 | blk_cleanup_queue(dev->admin_q); | |
1576 | blk_mq_free_tag_set(&dev->admin_tagset); | |
1577 | } | |
1578 | } | |
1579 | ||
a4aea562 MB |
1580 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1581 | { | |
1582 | if (!dev->admin_q) { | |
1583 | dev->admin_tagset.ops = &nvme_mq_admin_ops; | |
1584 | dev->admin_tagset.nr_hw_queues = 1; | |
1585 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1586 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; | |
1587 | dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev); | |
ac3dd5bd | 1588 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1589 | dev->admin_tagset.driver_data = dev; |
1590 | ||
1591 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1592 | return -ENOMEM; | |
1593 | ||
1594 | dev->admin_q = blk_mq_init_queue(&dev->admin_tagset); | |
35b489d3 | 1595 | if (IS_ERR(dev->admin_q)) { |
a4aea562 MB |
1596 | blk_mq_free_tag_set(&dev->admin_tagset); |
1597 | return -ENOMEM; | |
1598 | } | |
ea191d2f KB |
1599 | if (!blk_get_queue(dev->admin_q)) { |
1600 | nvme_dev_remove_admin(dev); | |
1601 | return -ENODEV; | |
1602 | } | |
0fb59cbc KB |
1603 | } else |
1604 | blk_mq_unfreeze_queue(dev->admin_q); | |
a4aea562 MB |
1605 | |
1606 | return 0; | |
1607 | } | |
1608 | ||
8d85fce7 | 1609 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1610 | { |
ba47e386 | 1611 | int result; |
b60503ba | 1612 | u32 aqa; |
ba47e386 | 1613 | u64 cap = readq(&dev->bar->cap); |
b60503ba | 1614 | struct nvme_queue *nvmeq; |
1d090624 KB |
1615 | unsigned page_shift = PAGE_SHIFT; |
1616 | unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12; | |
1617 | unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12; | |
1618 | ||
1619 | if (page_shift < dev_page_min) { | |
1620 | dev_err(&dev->pci_dev->dev, | |
1621 | "Minimum device page size (%u) too large for " | |
1622 | "host (%u)\n", 1 << dev_page_min, | |
1623 | 1 << page_shift); | |
1624 | return -ENODEV; | |
1625 | } | |
1626 | if (page_shift > dev_page_max) { | |
1627 | dev_info(&dev->pci_dev->dev, | |
1628 | "Device maximum page size (%u) smaller than " | |
1629 | "host (%u); enabling work-around\n", | |
1630 | 1 << dev_page_max, 1 << page_shift); | |
1631 | page_shift = dev_page_max; | |
1632 | } | |
b60503ba | 1633 | |
ba47e386 MW |
1634 | result = nvme_disable_ctrl(dev, cap); |
1635 | if (result < 0) | |
1636 | return result; | |
b60503ba | 1637 | |
a4aea562 | 1638 | nvmeq = dev->queues[0]; |
cd638946 | 1639 | if (!nvmeq) { |
2b25d981 | 1640 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1641 | if (!nvmeq) |
1642 | return -ENOMEM; | |
cd638946 | 1643 | } |
b60503ba MW |
1644 | |
1645 | aqa = nvmeq->q_depth - 1; | |
1646 | aqa |= aqa << 16; | |
1647 | ||
1d090624 KB |
1648 | dev->page_size = 1 << page_shift; |
1649 | ||
01079522 | 1650 | dev->ctrl_config = NVME_CC_CSS_NVM; |
1d090624 | 1651 | dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT; |
b60503ba | 1652 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; |
7f53f9d2 | 1653 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba MW |
1654 | |
1655 | writel(aqa, &dev->bar->aqa); | |
1656 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1657 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
b60503ba | 1658 | |
ba47e386 | 1659 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1660 | if (result) |
a4aea562 MB |
1661 | goto free_nvmeq; |
1662 | ||
2b25d981 | 1663 | nvmeq->cq_vector = 0; |
3193f07b | 1664 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
025c557a | 1665 | if (result) |
0fb59cbc | 1666 | goto free_nvmeq; |
025c557a | 1667 | |
b60503ba | 1668 | return result; |
a4aea562 | 1669 | |
a4aea562 MB |
1670 | free_nvmeq: |
1671 | nvme_free_queues(dev, 0); | |
1672 | return result; | |
b60503ba MW |
1673 | } |
1674 | ||
5d0f6131 | 1675 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
eca18b23 | 1676 | unsigned long addr, unsigned length) |
b60503ba | 1677 | { |
36c14ed9 | 1678 | int i, err, count, nents, offset; |
7fc3cdab MW |
1679 | struct scatterlist *sg; |
1680 | struct page **pages; | |
eca18b23 | 1681 | struct nvme_iod *iod; |
36c14ed9 MW |
1682 | |
1683 | if (addr & 3) | |
eca18b23 | 1684 | return ERR_PTR(-EINVAL); |
5460fc03 | 1685 | if (!length || length > INT_MAX - PAGE_SIZE) |
eca18b23 | 1686 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1687 | |
36c14ed9 | 1688 | offset = offset_in_page(addr); |
7fc3cdab MW |
1689 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1690 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
22fff826 DC |
1691 | if (!pages) |
1692 | return ERR_PTR(-ENOMEM); | |
36c14ed9 MW |
1693 | |
1694 | err = get_user_pages_fast(addr, count, 1, pages); | |
1695 | if (err < count) { | |
1696 | count = err; | |
1697 | err = -EFAULT; | |
1698 | goto put_pages; | |
1699 | } | |
7fc3cdab | 1700 | |
6808c5fb | 1701 | err = -ENOMEM; |
ac3dd5bd | 1702 | iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL); |
6808c5fb S |
1703 | if (!iod) |
1704 | goto put_pages; | |
1705 | ||
eca18b23 | 1706 | sg = iod->sg; |
36c14ed9 | 1707 | sg_init_table(sg, count); |
d0ba1e49 MW |
1708 | for (i = 0; i < count; i++) { |
1709 | sg_set_page(&sg[i], pages[i], | |
5460fc03 DC |
1710 | min_t(unsigned, length, PAGE_SIZE - offset), |
1711 | offset); | |
d0ba1e49 MW |
1712 | length -= (PAGE_SIZE - offset); |
1713 | offset = 0; | |
7fc3cdab | 1714 | } |
fe304c43 | 1715 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1716 | iod->nents = count; |
7fc3cdab | 1717 | |
7fc3cdab MW |
1718 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, |
1719 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1720 | if (!nents) |
eca18b23 | 1721 | goto free_iod; |
b60503ba | 1722 | |
7fc3cdab | 1723 | kfree(pages); |
eca18b23 | 1724 | return iod; |
b60503ba | 1725 | |
eca18b23 MW |
1726 | free_iod: |
1727 | kfree(iod); | |
7fc3cdab MW |
1728 | put_pages: |
1729 | for (i = 0; i < count; i++) | |
1730 | put_page(pages[i]); | |
1731 | kfree(pages); | |
eca18b23 | 1732 | return ERR_PTR(err); |
7fc3cdab | 1733 | } |
b60503ba | 1734 | |
5d0f6131 | 1735 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1736 | struct nvme_iod *iod) |
7fc3cdab | 1737 | { |
1c2ad9fa | 1738 | int i; |
b60503ba | 1739 | |
1c2ad9fa MW |
1740 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1741 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1742 | |
1c2ad9fa MW |
1743 | for (i = 0; i < iod->nents; i++) |
1744 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1745 | } |
b60503ba | 1746 | |
a53295b6 MW |
1747 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1748 | { | |
1749 | struct nvme_dev *dev = ns->dev; | |
a53295b6 MW |
1750 | struct nvme_user_io io; |
1751 | struct nvme_command c; | |
f410c680 KB |
1752 | unsigned length, meta_len; |
1753 | int status, i; | |
1754 | struct nvme_iod *iod, *meta_iod = NULL; | |
1755 | dma_addr_t meta_dma_addr; | |
1756 | void *meta, *uninitialized_var(meta_mem); | |
a53295b6 MW |
1757 | |
1758 | if (copy_from_user(&io, uio, sizeof(io))) | |
1759 | return -EFAULT; | |
6c7d4945 | 1760 | length = (io.nblocks + 1) << ns->lba_shift; |
f410c680 KB |
1761 | meta_len = (io.nblocks + 1) * ns->ms; |
1762 | ||
1763 | if (meta_len && ((io.metadata & 3) || !io.metadata)) | |
1764 | return -EINVAL; | |
6c7d4945 MW |
1765 | |
1766 | switch (io.opcode) { | |
1767 | case nvme_cmd_write: | |
1768 | case nvme_cmd_read: | |
6bbf1acd | 1769 | case nvme_cmd_compare: |
eca18b23 | 1770 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1771 | break; |
6c7d4945 | 1772 | default: |
6bbf1acd | 1773 | return -EINVAL; |
6c7d4945 MW |
1774 | } |
1775 | ||
eca18b23 MW |
1776 | if (IS_ERR(iod)) |
1777 | return PTR_ERR(iod); | |
a53295b6 MW |
1778 | |
1779 | memset(&c, 0, sizeof(c)); | |
1780 | c.rw.opcode = io.opcode; | |
1781 | c.rw.flags = io.flags; | |
6c7d4945 | 1782 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1783 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1784 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1785 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1786 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1787 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1788 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1789 | c.rw.appmask = cpu_to_le16(io.appmask); | |
f410c680 KB |
1790 | |
1791 | if (meta_len) { | |
1b56749e KB |
1792 | meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata, |
1793 | meta_len); | |
f410c680 KB |
1794 | if (IS_ERR(meta_iod)) { |
1795 | status = PTR_ERR(meta_iod); | |
1796 | meta_iod = NULL; | |
1797 | goto unmap; | |
1798 | } | |
1799 | ||
1800 | meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len, | |
1801 | &meta_dma_addr, GFP_KERNEL); | |
1802 | if (!meta_mem) { | |
1803 | status = -ENOMEM; | |
1804 | goto unmap; | |
1805 | } | |
1806 | ||
1807 | if (io.opcode & 1) { | |
1808 | int meta_offset = 0; | |
1809 | ||
1810 | for (i = 0; i < meta_iod->nents; i++) { | |
1811 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1812 | meta_iod->sg[i].offset; | |
1813 | memcpy(meta_mem + meta_offset, meta, | |
1814 | meta_iod->sg[i].length); | |
1815 | kunmap_atomic(meta); | |
1816 | meta_offset += meta_iod->sg[i].length; | |
1817 | } | |
1818 | } | |
1819 | ||
1820 | c.rw.metadata = cpu_to_le64(meta_dma_addr); | |
1821 | } | |
1822 | ||
edd10d33 KB |
1823 | length = nvme_setup_prps(dev, iod, length, GFP_KERNEL); |
1824 | c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
1825 | c.rw.prp2 = cpu_to_le64(iod->first_dma); | |
a53295b6 | 1826 | |
b77954cb MW |
1827 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1828 | status = -ENOMEM; | |
1829 | else | |
a4aea562 | 1830 | status = nvme_submit_io_cmd(dev, ns, &c, NULL); |
a53295b6 | 1831 | |
f410c680 KB |
1832 | if (meta_len) { |
1833 | if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) { | |
1834 | int meta_offset = 0; | |
1835 | ||
1836 | for (i = 0; i < meta_iod->nents; i++) { | |
1837 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1838 | meta_iod->sg[i].offset; | |
1839 | memcpy(meta, meta_mem + meta_offset, | |
1840 | meta_iod->sg[i].length); | |
1841 | kunmap_atomic(meta); | |
1842 | meta_offset += meta_iod->sg[i].length; | |
1843 | } | |
1844 | } | |
1845 | ||
1846 | dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem, | |
1847 | meta_dma_addr); | |
1848 | } | |
1849 | ||
1850 | unmap: | |
1c2ad9fa | 1851 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1852 | nvme_free_iod(dev, iod); |
f410c680 KB |
1853 | |
1854 | if (meta_iod) { | |
1855 | nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod); | |
1856 | nvme_free_iod(dev, meta_iod); | |
1857 | } | |
1858 | ||
a53295b6 MW |
1859 | return status; |
1860 | } | |
1861 | ||
a4aea562 MB |
1862 | static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns, |
1863 | struct nvme_passthru_cmd __user *ucmd) | |
6ee44cdc | 1864 | { |
7963e521 | 1865 | struct nvme_passthru_cmd cmd; |
6ee44cdc | 1866 | struct nvme_command c; |
eca18b23 | 1867 | int status, length; |
c7d36ab8 | 1868 | struct nvme_iod *uninitialized_var(iod); |
94f370ca | 1869 | unsigned timeout; |
6ee44cdc | 1870 | |
6bbf1acd MW |
1871 | if (!capable(CAP_SYS_ADMIN)) |
1872 | return -EACCES; | |
1873 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1874 | return -EFAULT; |
6ee44cdc MW |
1875 | |
1876 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1877 | c.common.opcode = cmd.opcode; |
1878 | c.common.flags = cmd.flags; | |
1879 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1880 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1881 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1882 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1883 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1884 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1885 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1886 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1887 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1888 | ||
1889 | length = cmd.data_len; | |
1890 | if (cmd.data_len) { | |
49742188 MW |
1891 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1892 | length); | |
eca18b23 MW |
1893 | if (IS_ERR(iod)) |
1894 | return PTR_ERR(iod); | |
edd10d33 KB |
1895 | length = nvme_setup_prps(dev, iod, length, GFP_KERNEL); |
1896 | c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
1897 | c.common.prp2 = cpu_to_le64(iod->first_dma); | |
6bbf1acd MW |
1898 | } |
1899 | ||
94f370ca KB |
1900 | timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) : |
1901 | ADMIN_TIMEOUT; | |
a4aea562 | 1902 | |
6bbf1acd | 1903 | if (length != cmd.data_len) |
b77954cb | 1904 | status = -ENOMEM; |
a4aea562 MB |
1905 | else if (ns) { |
1906 | struct request *req; | |
1907 | ||
1908 | req = blk_mq_alloc_request(ns->queue, WRITE, | |
1909 | (GFP_KERNEL|__GFP_WAIT), false); | |
97fe3832 JA |
1910 | if (IS_ERR(req)) |
1911 | status = PTR_ERR(req); | |
a4aea562 MB |
1912 | else { |
1913 | status = nvme_submit_sync_cmd(req, &c, &cmd.result, | |
1914 | timeout); | |
9d135bb8 | 1915 | blk_mq_free_request(req); |
a4aea562 MB |
1916 | } |
1917 | } else | |
1918 | status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout); | |
eca18b23 | 1919 | |
6bbf1acd | 1920 | if (cmd.data_len) { |
1c2ad9fa | 1921 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1922 | nvme_free_iod(dev, iod); |
6bbf1acd | 1923 | } |
f4f117f6 | 1924 | |
cf90bc48 | 1925 | if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result, |
f4f117f6 KB |
1926 | sizeof(cmd.result))) |
1927 | status = -EFAULT; | |
1928 | ||
6ee44cdc MW |
1929 | return status; |
1930 | } | |
1931 | ||
b60503ba MW |
1932 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1933 | unsigned long arg) | |
1934 | { | |
1935 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1936 | ||
1937 | switch (cmd) { | |
6bbf1acd | 1938 | case NVME_IOCTL_ID: |
c3bfe717 | 1939 | force_successful_syscall_return(); |
6bbf1acd MW |
1940 | return ns->ns_id; |
1941 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 1942 | return nvme_user_cmd(ns->dev, NULL, (void __user *)arg); |
7963e521 | 1943 | case NVME_IOCTL_IO_CMD: |
a4aea562 | 1944 | return nvme_user_cmd(ns->dev, ns, (void __user *)arg); |
a53295b6 MW |
1945 | case NVME_IOCTL_SUBMIT_IO: |
1946 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1947 | case SG_GET_VERSION_NUM: |
1948 | return nvme_sg_get_version_num((void __user *)arg); | |
1949 | case SG_IO: | |
1950 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1951 | default: |
1952 | return -ENOTTY; | |
1953 | } | |
1954 | } | |
1955 | ||
320a3827 KB |
1956 | #ifdef CONFIG_COMPAT |
1957 | static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode, | |
1958 | unsigned int cmd, unsigned long arg) | |
1959 | { | |
320a3827 KB |
1960 | switch (cmd) { |
1961 | case SG_IO: | |
e179729a | 1962 | return -ENOIOCTLCMD; |
320a3827 KB |
1963 | } |
1964 | return nvme_ioctl(bdev, mode, cmd, arg); | |
1965 | } | |
1966 | #else | |
1967 | #define nvme_compat_ioctl NULL | |
1968 | #endif | |
1969 | ||
9ac27090 KB |
1970 | static int nvme_open(struct block_device *bdev, fmode_t mode) |
1971 | { | |
9e60352c KB |
1972 | int ret = 0; |
1973 | struct nvme_ns *ns; | |
9ac27090 | 1974 | |
9e60352c KB |
1975 | spin_lock(&dev_list_lock); |
1976 | ns = bdev->bd_disk->private_data; | |
1977 | if (!ns) | |
1978 | ret = -ENXIO; | |
1979 | else if (!kref_get_unless_zero(&ns->dev->kref)) | |
1980 | ret = -ENXIO; | |
1981 | spin_unlock(&dev_list_lock); | |
1982 | ||
1983 | return ret; | |
9ac27090 KB |
1984 | } |
1985 | ||
1986 | static void nvme_free_dev(struct kref *kref); | |
1987 | ||
1988 | static void nvme_release(struct gendisk *disk, fmode_t mode) | |
1989 | { | |
1990 | struct nvme_ns *ns = disk->private_data; | |
1991 | struct nvme_dev *dev = ns->dev; | |
1992 | ||
1993 | kref_put(&dev->kref, nvme_free_dev); | |
1994 | } | |
1995 | ||
4cc09e2d KB |
1996 | static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo) |
1997 | { | |
1998 | /* some standard values */ | |
1999 | geo->heads = 1 << 6; | |
2000 | geo->sectors = 1 << 5; | |
2001 | geo->cylinders = get_capacity(bd->bd_disk) >> 11; | |
2002 | return 0; | |
2003 | } | |
2004 | ||
e1e5e564 KB |
2005 | static void nvme_config_discard(struct nvme_ns *ns) |
2006 | { | |
2007 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
2008 | ns->queue->limits.discard_zeroes_data = 0; | |
2009 | ns->queue->limits.discard_alignment = logical_block_size; | |
2010 | ns->queue->limits.discard_granularity = logical_block_size; | |
2011 | ns->queue->limits.max_discard_sectors = 0xffffffff; | |
2012 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); | |
2013 | } | |
2014 | ||
1b9dbf7f KB |
2015 | static int nvme_revalidate_disk(struct gendisk *disk) |
2016 | { | |
2017 | struct nvme_ns *ns = disk->private_data; | |
2018 | struct nvme_dev *dev = ns->dev; | |
2019 | struct nvme_id_ns *id; | |
2020 | dma_addr_t dma_addr; | |
e1e5e564 KB |
2021 | int lbaf, pi_type, old_ms; |
2022 | unsigned short bs; | |
1b9dbf7f KB |
2023 | |
2024 | id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr, | |
2025 | GFP_KERNEL); | |
2026 | if (!id) { | |
2027 | dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n", | |
2028 | __func__); | |
2029 | return 0; | |
2030 | } | |
e1e5e564 KB |
2031 | if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) { |
2032 | dev_warn(&dev->pci_dev->dev, | |
2033 | "identify failed ns:%d, setting capacity to 0\n", | |
2034 | ns->ns_id); | |
2035 | memset(id, 0, sizeof(*id)); | |
2036 | } | |
1b9dbf7f | 2037 | |
e1e5e564 KB |
2038 | old_ms = ns->ms; |
2039 | lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK; | |
1b9dbf7f | 2040 | ns->lba_shift = id->lbaf[lbaf].ds; |
e1e5e564 KB |
2041 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
2042 | ||
2043 | /* | |
2044 | * If identify namespace failed, use default 512 byte block size so | |
2045 | * block layer can use before failing read/write for 0 capacity. | |
2046 | */ | |
2047 | if (ns->lba_shift == 0) | |
2048 | ns->lba_shift = 9; | |
2049 | bs = 1 << ns->lba_shift; | |
2050 | ||
2051 | /* XXX: PI implementation requires metadata equal t10 pi tuple size */ | |
2052 | pi_type = ns->ms == sizeof(struct t10_pi_tuple) ? | |
2053 | id->dps & NVME_NS_DPS_PI_MASK : 0; | |
2054 | ||
52b68d7e KB |
2055 | if (blk_get_integrity(disk) && (ns->pi_type != pi_type || |
2056 | ns->ms != old_ms || | |
e1e5e564 KB |
2057 | bs != queue_logical_block_size(disk->queue) || |
2058 | (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT))) | |
2059 | blk_integrity_unregister(disk); | |
2060 | ||
2061 | ns->pi_type = pi_type; | |
2062 | blk_queue_logical_block_size(ns->queue, bs); | |
2063 | ||
52b68d7e | 2064 | if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) && |
e1e5e564 KB |
2065 | !(id->flbas & NVME_NS_FLBAS_META_EXT)) |
2066 | nvme_init_integrity(ns); | |
2067 | ||
52b68d7e | 2068 | if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk))) |
e1e5e564 KB |
2069 | set_capacity(disk, 0); |
2070 | else | |
2071 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
2072 | ||
2073 | if (dev->oncs & NVME_CTRL_ONCS_DSM) | |
2074 | nvme_config_discard(ns); | |
1b9dbf7f | 2075 | |
1b9dbf7f KB |
2076 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); |
2077 | return 0; | |
2078 | } | |
2079 | ||
b60503ba MW |
2080 | static const struct block_device_operations nvme_fops = { |
2081 | .owner = THIS_MODULE, | |
2082 | .ioctl = nvme_ioctl, | |
320a3827 | 2083 | .compat_ioctl = nvme_compat_ioctl, |
9ac27090 KB |
2084 | .open = nvme_open, |
2085 | .release = nvme_release, | |
4cc09e2d | 2086 | .getgeo = nvme_getgeo, |
1b9dbf7f | 2087 | .revalidate_disk= nvme_revalidate_disk, |
b60503ba MW |
2088 | }; |
2089 | ||
1fa6aead MW |
2090 | static int nvme_kthread(void *data) |
2091 | { | |
d4b4ff8e | 2092 | struct nvme_dev *dev, *next; |
1fa6aead MW |
2093 | |
2094 | while (!kthread_should_stop()) { | |
564a232c | 2095 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 2096 | spin_lock(&dev_list_lock); |
d4b4ff8e | 2097 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 2098 | int i; |
07836e65 | 2099 | if (readl(&dev->bar->csts) & NVME_CSTS_CFS) { |
d4b4ff8e KB |
2100 | if (work_busy(&dev->reset_work)) |
2101 | continue; | |
2102 | list_del_init(&dev->node); | |
2103 | dev_warn(&dev->pci_dev->dev, | |
a4aea562 MB |
2104 | "Failed status: %x, reset controller\n", |
2105 | readl(&dev->bar->csts)); | |
9ca97374 | 2106 | dev->reset_workfn = nvme_reset_failed_dev; |
d4b4ff8e KB |
2107 | queue_work(nvme_workq, &dev->reset_work); |
2108 | continue; | |
2109 | } | |
1fa6aead | 2110 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 2111 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
2112 | if (!nvmeq) |
2113 | continue; | |
1fa6aead | 2114 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 2115 | nvme_process_cq(nvmeq); |
6fccf938 KB |
2116 | |
2117 | while ((i == 0) && (dev->event_limit > 0)) { | |
a4aea562 | 2118 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 KB |
2119 | break; |
2120 | dev->event_limit--; | |
2121 | } | |
1fa6aead MW |
2122 | spin_unlock_irq(&nvmeq->q_lock); |
2123 | } | |
2124 | } | |
2125 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 2126 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
2127 | } |
2128 | return 0; | |
2129 | } | |
2130 | ||
e1e5e564 | 2131 | static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid) |
b60503ba MW |
2132 | { |
2133 | struct nvme_ns *ns; | |
2134 | struct gendisk *disk; | |
a4aea562 | 2135 | int node = dev_to_node(&dev->pci_dev->dev); |
b60503ba | 2136 | |
a4aea562 | 2137 | ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); |
b60503ba | 2138 | if (!ns) |
e1e5e564 KB |
2139 | return; |
2140 | ||
a4aea562 | 2141 | ns->queue = blk_mq_init_queue(&dev->tagset); |
9f173b33 | 2142 | if (IS_ERR(ns->queue)) |
b60503ba | 2143 | goto out_free_ns; |
4eeb9215 MW |
2144 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); |
2145 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
a4aea562 | 2146 | queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue); |
b60503ba MW |
2147 | ns->dev = dev; |
2148 | ns->queue->queuedata = ns; | |
2149 | ||
a4aea562 | 2150 | disk = alloc_disk_node(0, node); |
b60503ba MW |
2151 | if (!disk) |
2152 | goto out_free_queue; | |
a4aea562 | 2153 | |
5aff9382 | 2154 | ns->ns_id = nsid; |
b60503ba | 2155 | ns->disk = disk; |
e1e5e564 KB |
2156 | ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */ |
2157 | list_add_tail(&ns->list, &dev->namespaces); | |
2158 | ||
e9ef4636 | 2159 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
2160 | if (dev->max_hw_sectors) |
2161 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
a4aea562 MB |
2162 | if (dev->stripe_size) |
2163 | blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9); | |
a7d2ce28 KB |
2164 | if (dev->vwc & NVME_CTRL_VWC_PRESENT) |
2165 | blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA); | |
b60503ba MW |
2166 | |
2167 | disk->major = nvme_major; | |
469071a3 | 2168 | disk->first_minor = 0; |
b60503ba MW |
2169 | disk->fops = &nvme_fops; |
2170 | disk->private_data = ns; | |
2171 | disk->queue = ns->queue; | |
b3fffdef | 2172 | disk->driverfs_dev = dev->device; |
469071a3 | 2173 | disk->flags = GENHD_FL_EXT_DEVT; |
5aff9382 | 2174 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba | 2175 | |
e1e5e564 KB |
2176 | /* |
2177 | * Initialize capacity to 0 until we establish the namespace format and | |
2178 | * setup integrity extentions if necessary. The revalidate_disk after | |
2179 | * add_disk allows the driver to register with integrity if the format | |
2180 | * requires it. | |
2181 | */ | |
2182 | set_capacity(disk, 0); | |
2183 | nvme_revalidate_disk(ns->disk); | |
2184 | add_disk(ns->disk); | |
2185 | if (ns->ms) | |
2186 | revalidate_disk(ns->disk); | |
2187 | return; | |
b60503ba MW |
2188 | out_free_queue: |
2189 | blk_cleanup_queue(ns->queue); | |
2190 | out_free_ns: | |
2191 | kfree(ns); | |
b60503ba MW |
2192 | } |
2193 | ||
42f61420 KB |
2194 | static void nvme_create_io_queues(struct nvme_dev *dev) |
2195 | { | |
a4aea562 | 2196 | unsigned i; |
42f61420 | 2197 | |
a4aea562 | 2198 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 2199 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
2200 | break; |
2201 | ||
a4aea562 MB |
2202 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2203 | if (nvme_create_queue(dev->queues[i], i)) | |
42f61420 KB |
2204 | break; |
2205 | } | |
2206 | ||
b3b06812 | 2207 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
2208 | { |
2209 | int status; | |
2210 | u32 result; | |
b3b06812 | 2211 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 2212 | |
df348139 | 2213 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 2214 | &result); |
27e8166c MW |
2215 | if (status < 0) |
2216 | return status; | |
2217 | if (status > 0) { | |
2218 | dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n", | |
2219 | status); | |
badc34d4 | 2220 | return 0; |
27e8166c | 2221 | } |
b60503ba MW |
2222 | return min(result & 0xffff, result >> 16) + 1; |
2223 | } | |
2224 | ||
9d713c2b KB |
2225 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
2226 | { | |
b80d5ccc | 2227 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
2228 | } |
2229 | ||
8d85fce7 | 2230 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2231 | { |
a4aea562 | 2232 | struct nvme_queue *adminq = dev->queues[0]; |
fa08a396 | 2233 | struct pci_dev *pdev = dev->pci_dev; |
42f61420 | 2234 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 2235 | |
42f61420 | 2236 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 2237 | result = set_queue_count(dev, nr_io_queues); |
badc34d4 | 2238 | if (result <= 0) |
1b23484b | 2239 | return result; |
b348b7d5 MW |
2240 | if (result < nr_io_queues) |
2241 | nr_io_queues = result; | |
b60503ba | 2242 | |
9d713c2b KB |
2243 | size = db_bar_size(dev, nr_io_queues); |
2244 | if (size > 8192) { | |
f1938f6e | 2245 | iounmap(dev->bar); |
9d713c2b KB |
2246 | do { |
2247 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
2248 | if (dev->bar) | |
2249 | break; | |
2250 | if (!--nr_io_queues) | |
2251 | return -ENOMEM; | |
2252 | size = db_bar_size(dev, nr_io_queues); | |
2253 | } while (1); | |
f1938f6e | 2254 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
5a92e700 | 2255 | adminq->q_db = dev->dbs; |
f1938f6e MW |
2256 | } |
2257 | ||
9d713c2b | 2258 | /* Deregister the admin queue's interrupt */ |
3193f07b | 2259 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 2260 | |
e32efbfc JA |
2261 | /* |
2262 | * If we enable msix early due to not intx, disable it again before | |
2263 | * setting up the full range we need. | |
2264 | */ | |
2265 | if (!pdev->irq) | |
2266 | pci_disable_msix(pdev); | |
2267 | ||
be577fab | 2268 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 2269 | dev->entry[i].entry = i; |
be577fab AG |
2270 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
2271 | if (vecs < 0) { | |
2272 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
2273 | if (vecs < 0) { | |
2274 | vecs = 1; | |
2275 | } else { | |
2276 | for (i = 0; i < vecs; i++) | |
2277 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
2278 | } |
2279 | } | |
2280 | ||
063a8096 MW |
2281 | /* |
2282 | * Should investigate if there's a performance win from allocating | |
2283 | * more queues than interrupt vectors; it might allow the submission | |
2284 | * path to scale better, even if the receive path is limited by the | |
2285 | * number of interrupts. | |
2286 | */ | |
2287 | nr_io_queues = vecs; | |
42f61420 | 2288 | dev->max_qid = nr_io_queues; |
063a8096 | 2289 | |
3193f07b | 2290 | result = queue_request_irq(dev, adminq, adminq->irqname); |
a4aea562 | 2291 | if (result) |
22404274 | 2292 | goto free_queues; |
1b23484b | 2293 | |
cd638946 | 2294 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 2295 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 2296 | nvme_create_io_queues(dev); |
9ecdc946 | 2297 | |
22404274 | 2298 | return 0; |
b60503ba | 2299 | |
22404274 | 2300 | free_queues: |
a1a5ef99 | 2301 | nvme_free_queues(dev, 1); |
22404274 | 2302 | return result; |
b60503ba MW |
2303 | } |
2304 | ||
422ef0c7 MW |
2305 | /* |
2306 | * Return: error value if an error occurred setting up the queues or calling | |
2307 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2308 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2309 | * failures should be reported. | |
2310 | */ | |
8d85fce7 | 2311 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2312 | { |
68608c26 | 2313 | struct pci_dev *pdev = dev->pci_dev; |
c3bfe717 MW |
2314 | int res; |
2315 | unsigned nn, i; | |
51814232 | 2316 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 | 2317 | void *mem; |
b60503ba | 2318 | dma_addr_t dma_addr; |
159b67d7 | 2319 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; |
b60503ba | 2320 | |
e1e5e564 | 2321 | mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL); |
a9ef4343 KB |
2322 | if (!mem) |
2323 | return -ENOMEM; | |
b60503ba | 2324 | |
bc5fc7e4 | 2325 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba | 2326 | if (res) { |
27e8166c | 2327 | dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res); |
e1e5e564 KB |
2328 | dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr); |
2329 | return -EIO; | |
b60503ba MW |
2330 | } |
2331 | ||
bc5fc7e4 | 2332 | ctrl = mem; |
51814232 | 2333 | nn = le32_to_cpup(&ctrl->nn); |
0e5e4f0e | 2334 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
c30341dc | 2335 | dev->abort_limit = ctrl->acl + 1; |
a7d2ce28 | 2336 | dev->vwc = ctrl->vwc; |
6fccf938 | 2337 | dev->event_limit = min(ctrl->aerl + 1, 8); |
51814232 MW |
2338 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
2339 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
2340 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 2341 | if (ctrl->mdts) |
8fc23e03 | 2342 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
68608c26 | 2343 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL) && |
a4aea562 MB |
2344 | (pdev->device == 0x0953) && ctrl->vs[3]) { |
2345 | unsigned int max_hw_sectors; | |
2346 | ||
159b67d7 | 2347 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); |
a4aea562 MB |
2348 | max_hw_sectors = dev->stripe_size >> (shift - 9); |
2349 | if (dev->max_hw_sectors) { | |
2350 | dev->max_hw_sectors = min(max_hw_sectors, | |
2351 | dev->max_hw_sectors); | |
2352 | } else | |
2353 | dev->max_hw_sectors = max_hw_sectors; | |
2354 | } | |
e1e5e564 | 2355 | dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr); |
a4aea562 MB |
2356 | |
2357 | dev->tagset.ops = &nvme_mq_ops; | |
2358 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2359 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
2360 | dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev); | |
2361 | dev->tagset.queue_depth = | |
2362 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; | |
ac3dd5bd | 2363 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
2364 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
2365 | dev->tagset.driver_data = dev; | |
2366 | ||
2367 | if (blk_mq_alloc_tag_set(&dev->tagset)) | |
e1e5e564 | 2368 | return 0; |
b60503ba | 2369 | |
e1e5e564 KB |
2370 | for (i = 1; i <= nn; i++) |
2371 | nvme_alloc_ns(dev, i); | |
b60503ba | 2372 | |
e1e5e564 | 2373 | return 0; |
b60503ba MW |
2374 | } |
2375 | ||
0877cb0d KB |
2376 | static int nvme_dev_map(struct nvme_dev *dev) |
2377 | { | |
42f61420 | 2378 | u64 cap; |
0877cb0d KB |
2379 | int bars, result = -ENOMEM; |
2380 | struct pci_dev *pdev = dev->pci_dev; | |
2381 | ||
2382 | if (pci_enable_device_mem(pdev)) | |
2383 | return result; | |
2384 | ||
2385 | dev->entry[0].vector = pdev->irq; | |
2386 | pci_set_master(pdev); | |
2387 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
2388 | if (!bars) |
2389 | goto disable_pci; | |
2390 | ||
0877cb0d KB |
2391 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
2392 | goto disable_pci; | |
2393 | ||
052d0efa RK |
2394 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) && |
2395 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) | |
2396 | goto disable; | |
0877cb0d | 2397 | |
0877cb0d KB |
2398 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2399 | if (!dev->bar) | |
2400 | goto disable; | |
e32efbfc | 2401 | |
0e53d180 KB |
2402 | if (readl(&dev->bar->csts) == -1) { |
2403 | result = -ENODEV; | |
2404 | goto unmap; | |
2405 | } | |
e32efbfc JA |
2406 | |
2407 | /* | |
2408 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
2409 | * MSIX vec for setup. We'll adjust this later. | |
2410 | */ | |
2411 | if (!pdev->irq) { | |
2412 | result = pci_enable_msix(pdev, dev->entry, 1); | |
2413 | if (result < 0) | |
2414 | goto unmap; | |
2415 | } | |
2416 | ||
42f61420 KB |
2417 | cap = readq(&dev->bar->cap); |
2418 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); | |
2419 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
0877cb0d KB |
2420 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
2421 | ||
2422 | return 0; | |
2423 | ||
0e53d180 KB |
2424 | unmap: |
2425 | iounmap(dev->bar); | |
2426 | dev->bar = NULL; | |
0877cb0d KB |
2427 | disable: |
2428 | pci_release_regions(pdev); | |
2429 | disable_pci: | |
2430 | pci_disable_device(pdev); | |
2431 | return result; | |
2432 | } | |
2433 | ||
2434 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
2435 | { | |
2436 | if (dev->pci_dev->msi_enabled) | |
2437 | pci_disable_msi(dev->pci_dev); | |
2438 | else if (dev->pci_dev->msix_enabled) | |
2439 | pci_disable_msix(dev->pci_dev); | |
2440 | ||
2441 | if (dev->bar) { | |
2442 | iounmap(dev->bar); | |
2443 | dev->bar = NULL; | |
9a6b9458 | 2444 | pci_release_regions(dev->pci_dev); |
0877cb0d KB |
2445 | } |
2446 | ||
0877cb0d KB |
2447 | if (pci_is_enabled(dev->pci_dev)) |
2448 | pci_disable_device(dev->pci_dev); | |
2449 | } | |
2450 | ||
4d115420 KB |
2451 | struct nvme_delq_ctx { |
2452 | struct task_struct *waiter; | |
2453 | struct kthread_worker *worker; | |
2454 | atomic_t refcount; | |
2455 | }; | |
2456 | ||
2457 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
2458 | { | |
2459 | dq->waiter = current; | |
2460 | mb(); | |
2461 | ||
2462 | for (;;) { | |
2463 | set_current_state(TASK_KILLABLE); | |
2464 | if (!atomic_read(&dq->refcount)) | |
2465 | break; | |
2466 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
2467 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
2468 | /* |
2469 | * Disable the controller first since we can't trust it | |
2470 | * at this point, but leave the admin queue enabled | |
2471 | * until all queue deletion requests are flushed. | |
2472 | * FIXME: This may take a while if there are more h/w | |
2473 | * queues than admin tags. | |
2474 | */ | |
4d115420 | 2475 | set_current_state(TASK_RUNNING); |
4d115420 | 2476 | nvme_disable_ctrl(dev, readq(&dev->bar->cap)); |
0fb59cbc | 2477 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 2478 | flush_kthread_worker(dq->worker); |
0fb59cbc | 2479 | nvme_disable_queue(dev, 0); |
4d115420 KB |
2480 | return; |
2481 | } | |
2482 | } | |
2483 | set_current_state(TASK_RUNNING); | |
2484 | } | |
2485 | ||
2486 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
2487 | { | |
2488 | atomic_dec(&dq->refcount); | |
2489 | if (dq->waiter) | |
2490 | wake_up_process(dq->waiter); | |
2491 | } | |
2492 | ||
2493 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
2494 | { | |
2495 | atomic_inc(&dq->refcount); | |
2496 | return dq; | |
2497 | } | |
2498 | ||
2499 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
2500 | { | |
2501 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 KB |
2502 | nvme_put_dq(dq); |
2503 | } | |
2504 | ||
2505 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
2506 | kthread_work_func_t fn) | |
2507 | { | |
2508 | struct nvme_command c; | |
2509 | ||
2510 | memset(&c, 0, sizeof(c)); | |
2511 | c.delete_queue.opcode = opcode; | |
2512 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
2513 | ||
2514 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
2515 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
2516 | ADMIN_TIMEOUT); | |
4d115420 KB |
2517 | } |
2518 | ||
2519 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
2520 | { | |
2521 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2522 | cmdinfo.work); | |
2523 | nvme_del_queue_end(nvmeq); | |
2524 | } | |
2525 | ||
2526 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
2527 | { | |
2528 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
2529 | nvme_del_cq_work_handler); | |
2530 | } | |
2531 | ||
2532 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
2533 | { | |
2534 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2535 | cmdinfo.work); | |
2536 | int status = nvmeq->cmdinfo.status; | |
2537 | ||
2538 | if (!status) | |
2539 | status = nvme_delete_cq(nvmeq); | |
2540 | if (status) | |
2541 | nvme_del_queue_end(nvmeq); | |
2542 | } | |
2543 | ||
2544 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
2545 | { | |
2546 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
2547 | nvme_del_sq_work_handler); | |
2548 | } | |
2549 | ||
2550 | static void nvme_del_queue_start(struct kthread_work *work) | |
2551 | { | |
2552 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2553 | cmdinfo.work); | |
4d115420 KB |
2554 | if (nvme_delete_sq(nvmeq)) |
2555 | nvme_del_queue_end(nvmeq); | |
2556 | } | |
2557 | ||
2558 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
2559 | { | |
2560 | int i; | |
2561 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
2562 | struct nvme_delq_ctx dq; | |
2563 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
2564 | &worker, "nvme%d", dev->instance); | |
2565 | ||
2566 | if (IS_ERR(kworker_task)) { | |
2567 | dev_err(&dev->pci_dev->dev, | |
2568 | "Failed to create queue del task\n"); | |
2569 | for (i = dev->queue_count - 1; i > 0; i--) | |
2570 | nvme_disable_queue(dev, i); | |
2571 | return; | |
2572 | } | |
2573 | ||
2574 | dq.waiter = NULL; | |
2575 | atomic_set(&dq.refcount, 0); | |
2576 | dq.worker = &worker; | |
2577 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 2578 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
2579 | |
2580 | if (nvme_suspend_queue(nvmeq)) | |
2581 | continue; | |
2582 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2583 | nvmeq->cmdinfo.worker = dq.worker; | |
2584 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2585 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2586 | } | |
2587 | nvme_wait_dq(&dq, dev); | |
2588 | kthread_stop(kworker_task); | |
2589 | } | |
2590 | ||
b9afca3e DM |
2591 | /* |
2592 | * Remove the node from the device list and check | |
2593 | * for whether or not we need to stop the nvme_thread. | |
2594 | */ | |
2595 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2596 | { | |
2597 | struct task_struct *tmp = NULL; | |
2598 | ||
2599 | spin_lock(&dev_list_lock); | |
2600 | list_del_init(&dev->node); | |
2601 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2602 | tmp = nvme_thread; | |
2603 | nvme_thread = NULL; | |
2604 | } | |
2605 | spin_unlock(&dev_list_lock); | |
2606 | ||
2607 | if (tmp) | |
2608 | kthread_stop(tmp); | |
2609 | } | |
2610 | ||
c9d3bf88 KB |
2611 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2612 | { | |
2613 | struct nvme_ns *ns; | |
2614 | ||
2615 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2616 | blk_mq_freeze_queue_start(ns->queue); | |
2617 | ||
2618 | spin_lock(ns->queue->queue_lock); | |
2619 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); | |
2620 | spin_unlock(ns->queue->queue_lock); | |
2621 | ||
2622 | blk_mq_cancel_requeue_work(ns->queue); | |
2623 | blk_mq_stop_hw_queues(ns->queue); | |
2624 | } | |
2625 | } | |
2626 | ||
2627 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2628 | { | |
2629 | struct nvme_ns *ns; | |
2630 | ||
2631 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2632 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); | |
2633 | blk_mq_unfreeze_queue(ns->queue); | |
2634 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2635 | blk_mq_kick_requeue_list(ns->queue); | |
2636 | } | |
2637 | } | |
2638 | ||
f0b50732 | 2639 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2640 | { |
22404274 | 2641 | int i; |
7c1b2450 | 2642 | u32 csts = -1; |
22404274 | 2643 | |
b9afca3e | 2644 | nvme_dev_list_remove(dev); |
1fa6aead | 2645 | |
c9d3bf88 KB |
2646 | if (dev->bar) { |
2647 | nvme_freeze_queues(dev); | |
7c1b2450 | 2648 | csts = readl(&dev->bar->csts); |
c9d3bf88 | 2649 | } |
7c1b2450 | 2650 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2651 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2652 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2653 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2654 | } |
2655 | } else { | |
2656 | nvme_disable_io_queues(dev); | |
1894d8f1 | 2657 | nvme_shutdown_ctrl(dev); |
4d115420 KB |
2658 | nvme_disable_queue(dev, 0); |
2659 | } | |
f0b50732 | 2660 | nvme_dev_unmap(dev); |
07836e65 KB |
2661 | |
2662 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2663 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2664 | } |
2665 | ||
2666 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2667 | { | |
9ac27090 | 2668 | struct nvme_ns *ns; |
f0b50732 | 2669 | |
9ac27090 | 2670 | list_for_each_entry(ns, &dev->namespaces, list) { |
e1e5e564 | 2671 | if (ns->disk->flags & GENHD_FL_UP) { |
52b68d7e | 2672 | if (blk_get_integrity(ns->disk)) |
e1e5e564 | 2673 | blk_integrity_unregister(ns->disk); |
9ac27090 | 2674 | del_gendisk(ns->disk); |
e1e5e564 | 2675 | } |
cef6a948 KB |
2676 | if (!blk_queue_dying(ns->queue)) { |
2677 | blk_mq_abort_requeue_list(ns->queue); | |
9ac27090 | 2678 | blk_cleanup_queue(ns->queue); |
cef6a948 | 2679 | } |
b60503ba | 2680 | } |
b60503ba MW |
2681 | } |
2682 | ||
091b6092 MW |
2683 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2684 | { | |
2685 | struct device *dmadev = &dev->pci_dev->dev; | |
2686 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
2687 | PAGE_SIZE, PAGE_SIZE, 0); | |
2688 | if (!dev->prp_page_pool) | |
2689 | return -ENOMEM; | |
2690 | ||
99802a7a MW |
2691 | /* Optimisation for I/Os between 4k and 128k */ |
2692 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
2693 | 256, 256, 0); | |
2694 | if (!dev->prp_small_pool) { | |
2695 | dma_pool_destroy(dev->prp_page_pool); | |
2696 | return -ENOMEM; | |
2697 | } | |
091b6092 MW |
2698 | return 0; |
2699 | } | |
2700 | ||
2701 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2702 | { | |
2703 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2704 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2705 | } |
2706 | ||
cd58ad7d QSA |
2707 | static DEFINE_IDA(nvme_instance_ida); |
2708 | ||
2709 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2710 | { |
cd58ad7d QSA |
2711 | int instance, error; |
2712 | ||
2713 | do { | |
2714 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2715 | return -ENODEV; | |
2716 | ||
2717 | spin_lock(&dev_list_lock); | |
2718 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2719 | spin_unlock(&dev_list_lock); | |
2720 | } while (error == -EAGAIN); | |
2721 | ||
2722 | if (error) | |
2723 | return -ENODEV; | |
2724 | ||
2725 | dev->instance = instance; | |
2726 | return 0; | |
b60503ba MW |
2727 | } |
2728 | ||
2729 | static void nvme_release_instance(struct nvme_dev *dev) | |
2730 | { | |
cd58ad7d QSA |
2731 | spin_lock(&dev_list_lock); |
2732 | ida_remove(&nvme_instance_ida, dev->instance); | |
2733 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
2734 | } |
2735 | ||
9ac27090 KB |
2736 | static void nvme_free_namespaces(struct nvme_dev *dev) |
2737 | { | |
2738 | struct nvme_ns *ns, *next; | |
2739 | ||
2740 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
2741 | list_del(&ns->list); | |
9e60352c KB |
2742 | |
2743 | spin_lock(&dev_list_lock); | |
2744 | ns->disk->private_data = NULL; | |
2745 | spin_unlock(&dev_list_lock); | |
2746 | ||
9ac27090 KB |
2747 | put_disk(ns->disk); |
2748 | kfree(ns); | |
2749 | } | |
2750 | } | |
2751 | ||
5e82e952 KB |
2752 | static void nvme_free_dev(struct kref *kref) |
2753 | { | |
2754 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
9ac27090 | 2755 | |
a96d4f5c | 2756 | pci_dev_put(dev->pci_dev); |
b3fffdef | 2757 | put_device(dev->device); |
9ac27090 | 2758 | nvme_free_namespaces(dev); |
285dffc9 | 2759 | nvme_release_instance(dev); |
a4aea562 | 2760 | blk_mq_free_tag_set(&dev->tagset); |
ea191d2f | 2761 | blk_put_queue(dev->admin_q); |
5e82e952 KB |
2762 | kfree(dev->queues); |
2763 | kfree(dev->entry); | |
2764 | kfree(dev); | |
2765 | } | |
2766 | ||
2767 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2768 | { | |
b3fffdef KB |
2769 | struct nvme_dev *dev; |
2770 | int instance = iminor(inode); | |
2771 | int ret = -ENODEV; | |
2772 | ||
2773 | spin_lock(&dev_list_lock); | |
2774 | list_for_each_entry(dev, &dev_list, node) { | |
2775 | if (dev->instance == instance) { | |
2e1d8448 KB |
2776 | if (!dev->admin_q) { |
2777 | ret = -EWOULDBLOCK; | |
2778 | break; | |
2779 | } | |
b3fffdef KB |
2780 | if (!kref_get_unless_zero(&dev->kref)) |
2781 | break; | |
2782 | f->private_data = dev; | |
2783 | ret = 0; | |
2784 | break; | |
2785 | } | |
2786 | } | |
2787 | spin_unlock(&dev_list_lock); | |
2788 | ||
2789 | return ret; | |
5e82e952 KB |
2790 | } |
2791 | ||
2792 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2793 | { | |
2794 | struct nvme_dev *dev = f->private_data; | |
2795 | kref_put(&dev->kref, nvme_free_dev); | |
2796 | return 0; | |
2797 | } | |
2798 | ||
2799 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2800 | { | |
2801 | struct nvme_dev *dev = f->private_data; | |
a4aea562 MB |
2802 | struct nvme_ns *ns; |
2803 | ||
5e82e952 KB |
2804 | switch (cmd) { |
2805 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 2806 | return nvme_user_cmd(dev, NULL, (void __user *)arg); |
7963e521 | 2807 | case NVME_IOCTL_IO_CMD: |
a4aea562 MB |
2808 | if (list_empty(&dev->namespaces)) |
2809 | return -ENOTTY; | |
2810 | ns = list_first_entry(&dev->namespaces, struct nvme_ns, list); | |
2811 | return nvme_user_cmd(dev, ns, (void __user *)arg); | |
5e82e952 KB |
2812 | default: |
2813 | return -ENOTTY; | |
2814 | } | |
2815 | } | |
2816 | ||
2817 | static const struct file_operations nvme_dev_fops = { | |
2818 | .owner = THIS_MODULE, | |
2819 | .open = nvme_dev_open, | |
2820 | .release = nvme_dev_release, | |
2821 | .unlocked_ioctl = nvme_dev_ioctl, | |
2822 | .compat_ioctl = nvme_dev_ioctl, | |
2823 | }; | |
2824 | ||
a4aea562 MB |
2825 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
2826 | { | |
2827 | struct nvme_queue *nvmeq; | |
2828 | int i; | |
2829 | ||
2830 | for (i = 0; i < dev->online_queues; i++) { | |
2831 | nvmeq = dev->queues[i]; | |
2832 | ||
2833 | if (!nvmeq->hctx) | |
2834 | continue; | |
2835 | ||
2836 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
2837 | nvmeq->hctx->cpumask); | |
2838 | } | |
2839 | } | |
2840 | ||
f0b50732 KB |
2841 | static int nvme_dev_start(struct nvme_dev *dev) |
2842 | { | |
2843 | int result; | |
b9afca3e | 2844 | bool start_thread = false; |
f0b50732 KB |
2845 | |
2846 | result = nvme_dev_map(dev); | |
2847 | if (result) | |
2848 | return result; | |
2849 | ||
2850 | result = nvme_configure_admin_queue(dev); | |
2851 | if (result) | |
2852 | goto unmap; | |
2853 | ||
2854 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
2855 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
2856 | start_thread = true; | |
2857 | nvme_thread = NULL; | |
2858 | } | |
f0b50732 KB |
2859 | list_add(&dev->node, &dev_list); |
2860 | spin_unlock(&dev_list_lock); | |
2861 | ||
b9afca3e DM |
2862 | if (start_thread) { |
2863 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 2864 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
2865 | } else |
2866 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
2867 | ||
2868 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
2869 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
2870 | goto disable; | |
2871 | } | |
a4aea562 MB |
2872 | |
2873 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
2874 | result = nvme_alloc_admin_tags(dev); |
2875 | if (result) | |
2876 | goto disable; | |
b9afca3e | 2877 | |
f0b50732 | 2878 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2879 | if (result) |
0fb59cbc | 2880 | goto free_tags; |
f0b50732 | 2881 | |
a4aea562 MB |
2882 | nvme_set_irq_hints(dev); |
2883 | ||
d82e8bfd | 2884 | return result; |
f0b50732 | 2885 | |
0fb59cbc KB |
2886 | free_tags: |
2887 | nvme_dev_remove_admin(dev); | |
f0b50732 | 2888 | disable: |
a1a5ef99 | 2889 | nvme_disable_queue(dev, 0); |
b9afca3e | 2890 | nvme_dev_list_remove(dev); |
f0b50732 KB |
2891 | unmap: |
2892 | nvme_dev_unmap(dev); | |
2893 | return result; | |
2894 | } | |
2895 | ||
9a6b9458 KB |
2896 | static int nvme_remove_dead_ctrl(void *arg) |
2897 | { | |
2898 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
2899 | struct pci_dev *pdev = dev->pci_dev; | |
2900 | ||
2901 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2902 | pci_stop_and_remove_bus_device_locked(pdev); |
9a6b9458 KB |
2903 | kref_put(&dev->kref, nvme_free_dev); |
2904 | return 0; | |
2905 | } | |
2906 | ||
2907 | static void nvme_remove_disks(struct work_struct *ws) | |
2908 | { | |
9a6b9458 KB |
2909 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
2910 | ||
5a92e700 | 2911 | nvme_free_queues(dev, 1); |
302c6727 | 2912 | nvme_dev_remove(dev); |
9a6b9458 KB |
2913 | } |
2914 | ||
2915 | static int nvme_dev_resume(struct nvme_dev *dev) | |
2916 | { | |
2917 | int ret; | |
2918 | ||
2919 | ret = nvme_dev_start(dev); | |
badc34d4 | 2920 | if (ret) |
9a6b9458 | 2921 | return ret; |
badc34d4 | 2922 | if (dev->online_queues < 2) { |
9a6b9458 | 2923 | spin_lock(&dev_list_lock); |
9ca97374 | 2924 | dev->reset_workfn = nvme_remove_disks; |
9a6b9458 KB |
2925 | queue_work(nvme_workq, &dev->reset_work); |
2926 | spin_unlock(&dev_list_lock); | |
c9d3bf88 KB |
2927 | } else { |
2928 | nvme_unfreeze_queues(dev); | |
2929 | nvme_set_irq_hints(dev); | |
9a6b9458 KB |
2930 | } |
2931 | return 0; | |
2932 | } | |
2933 | ||
2934 | static void nvme_dev_reset(struct nvme_dev *dev) | |
2935 | { | |
2936 | nvme_dev_shutdown(dev); | |
2937 | if (nvme_dev_resume(dev)) { | |
a4aea562 | 2938 | dev_warn(&dev->pci_dev->dev, "Device failed to resume\n"); |
9a6b9458 KB |
2939 | kref_get(&dev->kref); |
2940 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", | |
2941 | dev->instance))) { | |
2942 | dev_err(&dev->pci_dev->dev, | |
2943 | "Failed to start controller remove task\n"); | |
2944 | kref_put(&dev->kref, nvme_free_dev); | |
2945 | } | |
2946 | } | |
2947 | } | |
2948 | ||
2949 | static void nvme_reset_failed_dev(struct work_struct *ws) | |
2950 | { | |
2951 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); | |
2952 | nvme_dev_reset(dev); | |
2953 | } | |
2954 | ||
9ca97374 TH |
2955 | static void nvme_reset_workfn(struct work_struct *work) |
2956 | { | |
2957 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); | |
2958 | dev->reset_workfn(work); | |
2959 | } | |
2960 | ||
2e1d8448 | 2961 | static void nvme_async_probe(struct work_struct *work); |
8d85fce7 | 2962 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2963 | { |
a4aea562 | 2964 | int node, result = -ENOMEM; |
b60503ba MW |
2965 | struct nvme_dev *dev; |
2966 | ||
a4aea562 MB |
2967 | node = dev_to_node(&pdev->dev); |
2968 | if (node == NUMA_NO_NODE) | |
2969 | set_dev_node(&pdev->dev, 0); | |
2970 | ||
2971 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2972 | if (!dev) |
2973 | return -ENOMEM; | |
a4aea562 MB |
2974 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2975 | GFP_KERNEL, node); | |
b60503ba MW |
2976 | if (!dev->entry) |
2977 | goto free; | |
a4aea562 MB |
2978 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2979 | GFP_KERNEL, node); | |
b60503ba MW |
2980 | if (!dev->queues) |
2981 | goto free; | |
2982 | ||
2983 | INIT_LIST_HEAD(&dev->namespaces); | |
9ca97374 TH |
2984 | dev->reset_workfn = nvme_reset_failed_dev; |
2985 | INIT_WORK(&dev->reset_work, nvme_reset_workfn); | |
a96d4f5c | 2986 | dev->pci_dev = pci_dev_get(pdev); |
9a6b9458 | 2987 | pci_set_drvdata(pdev, dev); |
cd58ad7d QSA |
2988 | result = nvme_set_instance(dev); |
2989 | if (result) | |
a96d4f5c | 2990 | goto put_pci; |
b60503ba | 2991 | |
091b6092 MW |
2992 | result = nvme_setup_prp_pools(dev); |
2993 | if (result) | |
0877cb0d | 2994 | goto release; |
091b6092 | 2995 | |
fb35e914 | 2996 | kref_init(&dev->kref); |
b3fffdef KB |
2997 | dev->device = device_create(nvme_class, &pdev->dev, |
2998 | MKDEV(nvme_char_major, dev->instance), | |
2999 | dev, "nvme%d", dev->instance); | |
3000 | if (IS_ERR(dev->device)) { | |
3001 | result = PTR_ERR(dev->device); | |
2e1d8448 | 3002 | goto release_pools; |
b3fffdef KB |
3003 | } |
3004 | get_device(dev->device); | |
740216fc | 3005 | |
2e1d8448 KB |
3006 | INIT_WORK(&dev->probe_work, nvme_async_probe); |
3007 | schedule_work(&dev->probe_work); | |
b60503ba MW |
3008 | return 0; |
3009 | ||
0877cb0d | 3010 | release_pools: |
091b6092 | 3011 | nvme_release_prp_pools(dev); |
0877cb0d KB |
3012 | release: |
3013 | nvme_release_instance(dev); | |
a96d4f5c KB |
3014 | put_pci: |
3015 | pci_dev_put(dev->pci_dev); | |
b60503ba MW |
3016 | free: |
3017 | kfree(dev->queues); | |
3018 | kfree(dev->entry); | |
3019 | kfree(dev); | |
3020 | return result; | |
3021 | } | |
3022 | ||
2e1d8448 KB |
3023 | static void nvme_async_probe(struct work_struct *work) |
3024 | { | |
3025 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); | |
3026 | int result; | |
3027 | ||
3028 | result = nvme_dev_start(dev); | |
3029 | if (result) | |
3030 | goto reset; | |
3031 | ||
3032 | if (dev->online_queues > 1) | |
3033 | result = nvme_dev_add(dev); | |
3034 | if (result) | |
3035 | goto reset; | |
3036 | ||
3037 | nvme_set_irq_hints(dev); | |
2e1d8448 KB |
3038 | return; |
3039 | reset: | |
07836e65 KB |
3040 | if (!work_busy(&dev->reset_work)) { |
3041 | dev->reset_workfn = nvme_reset_failed_dev; | |
3042 | queue_work(nvme_workq, &dev->reset_work); | |
3043 | } | |
2e1d8448 KB |
3044 | } |
3045 | ||
f0d54a54 KB |
3046 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
3047 | { | |
a6739479 | 3048 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 3049 | |
a6739479 KB |
3050 | if (prepare) |
3051 | nvme_dev_shutdown(dev); | |
3052 | else | |
3053 | nvme_dev_resume(dev); | |
f0d54a54 KB |
3054 | } |
3055 | ||
09ece142 KB |
3056 | static void nvme_shutdown(struct pci_dev *pdev) |
3057 | { | |
3058 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3059 | nvme_dev_shutdown(dev); | |
3060 | } | |
3061 | ||
8d85fce7 | 3062 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3063 | { |
3064 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
3065 | |
3066 | spin_lock(&dev_list_lock); | |
3067 | list_del_init(&dev->node); | |
3068 | spin_unlock(&dev_list_lock); | |
3069 | ||
3070 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 3071 | flush_work(&dev->probe_work); |
9a6b9458 | 3072 | flush_work(&dev->reset_work); |
9a6b9458 | 3073 | nvme_dev_shutdown(dev); |
c9d3bf88 | 3074 | nvme_dev_remove(dev); |
a4aea562 | 3075 | nvme_dev_remove_admin(dev); |
b3fffdef | 3076 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance)); |
a1a5ef99 | 3077 | nvme_free_queues(dev, 0); |
9a6b9458 | 3078 | nvme_release_prp_pools(dev); |
5e82e952 | 3079 | kref_put(&dev->kref, nvme_free_dev); |
b60503ba MW |
3080 | } |
3081 | ||
3082 | /* These functions are yet to be implemented */ | |
3083 | #define nvme_error_detected NULL | |
3084 | #define nvme_dump_registers NULL | |
3085 | #define nvme_link_reset NULL | |
3086 | #define nvme_slot_reset NULL | |
3087 | #define nvme_error_resume NULL | |
cd638946 | 3088 | |
671a6018 | 3089 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3090 | static int nvme_suspend(struct device *dev) |
3091 | { | |
3092 | struct pci_dev *pdev = to_pci_dev(dev); | |
3093 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
3094 | ||
3095 | nvme_dev_shutdown(ndev); | |
3096 | return 0; | |
3097 | } | |
3098 | ||
3099 | static int nvme_resume(struct device *dev) | |
3100 | { | |
3101 | struct pci_dev *pdev = to_pci_dev(dev); | |
3102 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3103 | |
9a6b9458 | 3104 | if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) { |
9ca97374 | 3105 | ndev->reset_workfn = nvme_reset_failed_dev; |
9a6b9458 KB |
3106 | queue_work(nvme_workq, &ndev->reset_work); |
3107 | } | |
3108 | return 0; | |
cd638946 | 3109 | } |
671a6018 | 3110 | #endif |
cd638946 KB |
3111 | |
3112 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 3113 | |
1d352035 | 3114 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
3115 | .error_detected = nvme_error_detected, |
3116 | .mmio_enabled = nvme_dump_registers, | |
3117 | .link_reset = nvme_link_reset, | |
3118 | .slot_reset = nvme_slot_reset, | |
3119 | .resume = nvme_error_resume, | |
f0d54a54 | 3120 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
3121 | }; |
3122 | ||
3123 | /* Move to pci_ids.h later */ | |
3124 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
3125 | ||
6eb0d698 | 3126 | static const struct pci_device_id nvme_id_table[] = { |
b60503ba MW |
3127 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
3128 | { 0, } | |
3129 | }; | |
3130 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3131 | ||
3132 | static struct pci_driver nvme_driver = { | |
3133 | .name = "nvme", | |
3134 | .id_table = nvme_id_table, | |
3135 | .probe = nvme_probe, | |
8d85fce7 | 3136 | .remove = nvme_remove, |
09ece142 | 3137 | .shutdown = nvme_shutdown, |
cd638946 KB |
3138 | .driver = { |
3139 | .pm = &nvme_dev_pm_ops, | |
3140 | }, | |
b60503ba MW |
3141 | .err_handler = &nvme_err_handler, |
3142 | }; | |
3143 | ||
3144 | static int __init nvme_init(void) | |
3145 | { | |
0ac13140 | 3146 | int result; |
1fa6aead | 3147 | |
b9afca3e | 3148 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 3149 | |
9a6b9458 KB |
3150 | nvme_workq = create_singlethread_workqueue("nvme"); |
3151 | if (!nvme_workq) | |
b9afca3e | 3152 | return -ENOMEM; |
9a6b9458 | 3153 | |
5c42ea16 KB |
3154 | result = register_blkdev(nvme_major, "nvme"); |
3155 | if (result < 0) | |
9a6b9458 | 3156 | goto kill_workq; |
5c42ea16 | 3157 | else if (result > 0) |
0ac13140 | 3158 | nvme_major = result; |
b60503ba | 3159 | |
b3fffdef KB |
3160 | result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme", |
3161 | &nvme_dev_fops); | |
3162 | if (result < 0) | |
3163 | goto unregister_blkdev; | |
3164 | else if (result > 0) | |
3165 | nvme_char_major = result; | |
3166 | ||
3167 | nvme_class = class_create(THIS_MODULE, "nvme"); | |
3168 | if (!nvme_class) | |
3169 | goto unregister_chrdev; | |
3170 | ||
f3db22fe KB |
3171 | result = pci_register_driver(&nvme_driver); |
3172 | if (result) | |
b3fffdef | 3173 | goto destroy_class; |
1fa6aead | 3174 | return 0; |
b60503ba | 3175 | |
b3fffdef KB |
3176 | destroy_class: |
3177 | class_destroy(nvme_class); | |
3178 | unregister_chrdev: | |
3179 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
1fa6aead | 3180 | unregister_blkdev: |
b60503ba | 3181 | unregister_blkdev(nvme_major, "nvme"); |
9a6b9458 KB |
3182 | kill_workq: |
3183 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
3184 | return result; |
3185 | } | |
3186 | ||
3187 | static void __exit nvme_exit(void) | |
3188 | { | |
3189 | pci_unregister_driver(&nvme_driver); | |
3190 | unregister_blkdev(nvme_major, "nvme"); | |
9a6b9458 | 3191 | destroy_workqueue(nvme_workq); |
b3fffdef KB |
3192 | class_destroy(nvme_class); |
3193 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
b9afca3e | 3194 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 3195 | _nvme_check_size(); |
b60503ba MW |
3196 | } |
3197 | ||
3198 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3199 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3200 | MODULE_VERSION("1.0"); |
b60503ba MW |
3201 | module_init(nvme_init); |
3202 | module_exit(nvme_exit); |