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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
fd63e9ce | 23 | #include <linux/delay.h> |
b60503ba MW |
24 | #include <linux/errno.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/genhd.h> | |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
1fa6aead | 32 | #include <linux/kthread.h> |
b60503ba MW |
33 | #include <linux/kernel.h> |
34 | #include <linux/mm.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/pci.h> | |
be7b6275 | 38 | #include <linux/poison.h> |
c3bfe717 | 39 | #include <linux/ptrace.h> |
b60503ba MW |
40 | #include <linux/sched.h> |
41 | #include <linux/slab.h> | |
42 | #include <linux/types.h> | |
5d0f6131 | 43 | #include <scsi/sg.h> |
797a796a HM |
44 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
45 | ||
b60503ba MW |
46 | #define NVME_Q_DEPTH 1024 |
47 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
48 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
49 | #define NVME_MINORS 64 | |
e85248e5 | 50 | #define ADMIN_TIMEOUT (60 * HZ) |
b60503ba MW |
51 | |
52 | static int nvme_major; | |
53 | module_param(nvme_major, int, 0); | |
54 | ||
58ffacb5 MW |
55 | static int use_threaded_interrupts; |
56 | module_param(use_threaded_interrupts, int, 0); | |
57 | ||
1fa6aead MW |
58 | static DEFINE_SPINLOCK(dev_list_lock); |
59 | static LIST_HEAD(dev_list); | |
60 | static struct task_struct *nvme_thread; | |
61 | ||
b60503ba MW |
62 | /* |
63 | * An NVM Express queue. Each device has at least two (one for admin | |
64 | * commands and one for I/O commands). | |
65 | */ | |
66 | struct nvme_queue { | |
67 | struct device *q_dmadev; | |
091b6092 | 68 | struct nvme_dev *dev; |
b60503ba MW |
69 | spinlock_t q_lock; |
70 | struct nvme_command *sq_cmds; | |
71 | volatile struct nvme_completion *cqes; | |
72 | dma_addr_t sq_dma_addr; | |
73 | dma_addr_t cq_dma_addr; | |
74 | wait_queue_head_t sq_full; | |
1fa6aead | 75 | wait_queue_t sq_cong_wait; |
b60503ba MW |
76 | struct bio_list sq_cong; |
77 | u32 __iomem *q_db; | |
78 | u16 q_depth; | |
79 | u16 cq_vector; | |
80 | u16 sq_head; | |
81 | u16 sq_tail; | |
82 | u16 cq_head; | |
e9539f47 MW |
83 | u8 cq_phase; |
84 | u8 cqe_seen; | |
22404274 | 85 | u8 q_suspended; |
b60503ba MW |
86 | unsigned long cmdid_data[]; |
87 | }; | |
88 | ||
89 | /* | |
90 | * Check we didin't inadvertently grow the command struct | |
91 | */ | |
92 | static inline void _nvme_check_size(void) | |
93 | { | |
94 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
95 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
96 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
97 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
98 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 99 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
b60503ba MW |
100 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
101 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
102 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
103 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 104 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
105 | } |
106 | ||
5c1281a3 | 107 | typedef void (*nvme_completion_fn)(struct nvme_dev *, void *, |
c2f5b650 MW |
108 | struct nvme_completion *); |
109 | ||
e85248e5 | 110 | struct nvme_cmd_info { |
c2f5b650 MW |
111 | nvme_completion_fn fn; |
112 | void *ctx; | |
e85248e5 MW |
113 | unsigned long timeout; |
114 | }; | |
115 | ||
116 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
117 | { | |
118 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
119 | } | |
120 | ||
22404274 KB |
121 | static unsigned nvme_queue_extra(int depth) |
122 | { | |
123 | return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info)); | |
124 | } | |
125 | ||
b60503ba | 126 | /** |
714a7a22 MW |
127 | * alloc_cmdid() - Allocate a Command ID |
128 | * @nvmeq: The queue that will be used for this command | |
129 | * @ctx: A pointer that will be passed to the handler | |
c2f5b650 | 130 | * @handler: The function to call on completion |
b60503ba MW |
131 | * |
132 | * Allocate a Command ID for a queue. The data passed in will | |
133 | * be passed to the completion handler. This is implemented by using | |
134 | * the bottom two bits of the ctx pointer to store the handler ID. | |
135 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
136 | * We can change this if it becomes a problem. | |
184d2944 MW |
137 | * |
138 | * May be called with local interrupts disabled and the q_lock held, | |
139 | * or with interrupts enabled and no locks held. | |
b60503ba | 140 | */ |
c2f5b650 MW |
141 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, |
142 | nvme_completion_fn handler, unsigned timeout) | |
b60503ba | 143 | { |
e6d15f79 | 144 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 145 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
146 | int cmdid; |
147 | ||
b60503ba MW |
148 | do { |
149 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
150 | if (cmdid >= depth) | |
151 | return -EBUSY; | |
152 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
153 | ||
c2f5b650 MW |
154 | info[cmdid].fn = handler; |
155 | info[cmdid].ctx = ctx; | |
e85248e5 | 156 | info[cmdid].timeout = jiffies + timeout; |
b60503ba MW |
157 | return cmdid; |
158 | } | |
159 | ||
160 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
c2f5b650 | 161 | nvme_completion_fn handler, unsigned timeout) |
b60503ba MW |
162 | { |
163 | int cmdid; | |
164 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 165 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
166 | return (cmdid < 0) ? -EINTR : cmdid; |
167 | } | |
168 | ||
c2f5b650 MW |
169 | /* Special values must be less than 0x1000 */ |
170 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
171 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
172 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
173 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 174 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
be7b6275 | 175 | |
5c1281a3 | 176 | static void special_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
177 | struct nvme_completion *cqe) |
178 | { | |
179 | if (ctx == CMD_CTX_CANCELLED) | |
180 | return; | |
181 | if (ctx == CMD_CTX_FLUSH) | |
182 | return; | |
183 | if (ctx == CMD_CTX_COMPLETED) { | |
5c1281a3 | 184 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
185 | "completed id %d twice on queue %d\n", |
186 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
187 | return; | |
188 | } | |
189 | if (ctx == CMD_CTX_INVALID) { | |
5c1281a3 | 190 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
191 | "invalid id %d completed on queue %d\n", |
192 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
193 | return; | |
194 | } | |
195 | ||
5c1281a3 | 196 | dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
197 | } |
198 | ||
184d2944 MW |
199 | /* |
200 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
201 | */ | |
c2f5b650 MW |
202 | static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid, |
203 | nvme_completion_fn *fn) | |
b60503ba | 204 | { |
c2f5b650 | 205 | void *ctx; |
e85248e5 | 206 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 207 | |
c2f5b650 MW |
208 | if (cmdid >= nvmeq->q_depth) { |
209 | *fn = special_completion; | |
48e3d398 | 210 | return CMD_CTX_INVALID; |
c2f5b650 | 211 | } |
859361a2 KB |
212 | if (fn) |
213 | *fn = info[cmdid].fn; | |
c2f5b650 MW |
214 | ctx = info[cmdid].ctx; |
215 | info[cmdid].fn = special_completion; | |
e85248e5 | 216 | info[cmdid].ctx = CMD_CTX_COMPLETED; |
b60503ba MW |
217 | clear_bit(cmdid, nvmeq->cmdid_data); |
218 | wake_up(&nvmeq->sq_full); | |
c2f5b650 | 219 | return ctx; |
b60503ba MW |
220 | } |
221 | ||
c2f5b650 MW |
222 | static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid, |
223 | nvme_completion_fn *fn) | |
3c0cf138 | 224 | { |
c2f5b650 | 225 | void *ctx; |
e85248e5 | 226 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
c2f5b650 MW |
227 | if (fn) |
228 | *fn = info[cmdid].fn; | |
229 | ctx = info[cmdid].ctx; | |
230 | info[cmdid].fn = special_completion; | |
e85248e5 | 231 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
c2f5b650 | 232 | return ctx; |
3c0cf138 MW |
233 | } |
234 | ||
5d0f6131 | 235 | struct nvme_queue *get_nvmeq(struct nvme_dev *dev) |
b60503ba | 236 | { |
040a93b5 | 237 | return dev->queues[get_cpu() + 1]; |
b60503ba MW |
238 | } |
239 | ||
5d0f6131 | 240 | void put_nvmeq(struct nvme_queue *nvmeq) |
b60503ba | 241 | { |
1b23484b | 242 | put_cpu(); |
b60503ba MW |
243 | } |
244 | ||
245 | /** | |
714a7a22 | 246 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
247 | * @nvmeq: The queue to use |
248 | * @cmd: The command to send | |
249 | * | |
250 | * Safe to use from interrupt context | |
251 | */ | |
252 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
253 | { | |
254 | unsigned long flags; | |
255 | u16 tail; | |
b60503ba MW |
256 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
257 | tail = nvmeq->sq_tail; | |
258 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
259 | if (++tail == nvmeq->q_depth) |
260 | tail = 0; | |
7547881d | 261 | writel(tail, nvmeq->q_db); |
b60503ba MW |
262 | nvmeq->sq_tail = tail; |
263 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
eca18b23 | 268 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 269 | { |
eca18b23 | 270 | return ((void *)iod) + iod->offset; |
e025344c SMM |
271 | } |
272 | ||
eca18b23 MW |
273 | /* |
274 | * Will slightly overestimate the number of pages needed. This is OK | |
275 | * as it only leads to a small amount of wasted memory for the lifetime of | |
276 | * the I/O. | |
277 | */ | |
278 | static int nvme_npages(unsigned size) | |
279 | { | |
280 | unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE); | |
281 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
282 | } | |
b60503ba | 283 | |
eca18b23 MW |
284 | static struct nvme_iod * |
285 | nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp) | |
b60503ba | 286 | { |
eca18b23 MW |
287 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
288 | sizeof(__le64 *) * nvme_npages(nbytes) + | |
289 | sizeof(struct scatterlist) * nseg, gfp); | |
290 | ||
291 | if (iod) { | |
292 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
293 | iod->npages = -1; | |
294 | iod->length = nbytes; | |
2b196034 | 295 | iod->nents = 0; |
6198221f | 296 | iod->start_time = jiffies; |
eca18b23 MW |
297 | } |
298 | ||
299 | return iod; | |
b60503ba MW |
300 | } |
301 | ||
5d0f6131 | 302 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 303 | { |
eca18b23 MW |
304 | const int last_prp = PAGE_SIZE / 8 - 1; |
305 | int i; | |
306 | __le64 **list = iod_list(iod); | |
307 | dma_addr_t prp_dma = iod->first_dma; | |
308 | ||
309 | if (iod->npages == 0) | |
310 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
311 | for (i = 0; i < iod->npages; i++) { | |
312 | __le64 *prp_list = list[i]; | |
313 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
314 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
315 | prp_dma = next_prp_dma; | |
316 | } | |
317 | kfree(iod); | |
b60503ba MW |
318 | } |
319 | ||
6198221f KB |
320 | static void nvme_start_io_acct(struct bio *bio) |
321 | { | |
322 | struct gendisk *disk = bio->bi_bdev->bd_disk; | |
323 | const int rw = bio_data_dir(bio); | |
324 | int cpu = part_stat_lock(); | |
325 | part_round_stats(cpu, &disk->part0); | |
326 | part_stat_inc(cpu, &disk->part0, ios[rw]); | |
327 | part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio)); | |
328 | part_inc_in_flight(&disk->part0, rw); | |
329 | part_stat_unlock(); | |
330 | } | |
331 | ||
332 | static void nvme_end_io_acct(struct bio *bio, unsigned long start_time) | |
333 | { | |
334 | struct gendisk *disk = bio->bi_bdev->bd_disk; | |
335 | const int rw = bio_data_dir(bio); | |
336 | unsigned long duration = jiffies - start_time; | |
337 | int cpu = part_stat_lock(); | |
338 | part_stat_add(cpu, &disk->part0, ticks[rw], duration); | |
339 | part_round_stats(cpu, &disk->part0); | |
340 | part_dec_in_flight(&disk->part0, rw); | |
341 | part_stat_unlock(); | |
342 | } | |
343 | ||
5c1281a3 | 344 | static void bio_completion(struct nvme_dev *dev, void *ctx, |
b60503ba MW |
345 | struct nvme_completion *cqe) |
346 | { | |
eca18b23 MW |
347 | struct nvme_iod *iod = ctx; |
348 | struct bio *bio = iod->private; | |
b60503ba MW |
349 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
350 | ||
9e59d091 | 351 | if (iod->nents) { |
2b196034 | 352 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
b60503ba | 353 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
9e59d091 KB |
354 | nvme_end_io_acct(bio, iod->start_time); |
355 | } | |
eca18b23 | 356 | nvme_free_iod(dev, iod); |
427e9708 | 357 | if (status) |
1ad2f893 | 358 | bio_endio(bio, -EIO); |
427e9708 | 359 | else |
1ad2f893 | 360 | bio_endio(bio, 0); |
b60503ba MW |
361 | } |
362 | ||
184d2944 | 363 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
5d0f6131 VV |
364 | int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd, |
365 | struct nvme_iod *iod, int total_len, gfp_t gfp) | |
ff22b54f | 366 | { |
99802a7a | 367 | struct dma_pool *pool; |
eca18b23 MW |
368 | int length = total_len; |
369 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
370 | int dma_len = sg_dma_len(sg); |
371 | u64 dma_addr = sg_dma_address(sg); | |
372 | int offset = offset_in_page(dma_addr); | |
e025344c | 373 | __le64 *prp_list; |
eca18b23 | 374 | __le64 **list = iod_list(iod); |
e025344c | 375 | dma_addr_t prp_dma; |
eca18b23 | 376 | int nprps, i; |
ff22b54f MW |
377 | |
378 | cmd->prp1 = cpu_to_le64(dma_addr); | |
379 | length -= (PAGE_SIZE - offset); | |
380 | if (length <= 0) | |
eca18b23 | 381 | return total_len; |
ff22b54f MW |
382 | |
383 | dma_len -= (PAGE_SIZE - offset); | |
384 | if (dma_len) { | |
385 | dma_addr += (PAGE_SIZE - offset); | |
386 | } else { | |
387 | sg = sg_next(sg); | |
388 | dma_addr = sg_dma_address(sg); | |
389 | dma_len = sg_dma_len(sg); | |
390 | } | |
391 | ||
392 | if (length <= PAGE_SIZE) { | |
393 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 | 394 | return total_len; |
e025344c SMM |
395 | } |
396 | ||
397 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
99802a7a MW |
398 | if (nprps <= (256 / 8)) { |
399 | pool = dev->prp_small_pool; | |
eca18b23 | 400 | iod->npages = 0; |
99802a7a MW |
401 | } else { |
402 | pool = dev->prp_page_pool; | |
eca18b23 | 403 | iod->npages = 1; |
99802a7a MW |
404 | } |
405 | ||
b77954cb MW |
406 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
407 | if (!prp_list) { | |
408 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 MW |
409 | iod->npages = -1; |
410 | return (total_len - length) + PAGE_SIZE; | |
b77954cb | 411 | } |
eca18b23 MW |
412 | list[0] = prp_list; |
413 | iod->first_dma = prp_dma; | |
e025344c SMM |
414 | cmd->prp2 = cpu_to_le64(prp_dma); |
415 | i = 0; | |
416 | for (;;) { | |
7523d834 | 417 | if (i == PAGE_SIZE / 8) { |
e025344c | 418 | __le64 *old_prp_list = prp_list; |
b77954cb | 419 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
420 | if (!prp_list) |
421 | return total_len - length; | |
422 | list[iod->npages++] = prp_list; | |
7523d834 MW |
423 | prp_list[0] = old_prp_list[i - 1]; |
424 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
425 | i = 1; | |
e025344c SMM |
426 | } |
427 | prp_list[i++] = cpu_to_le64(dma_addr); | |
428 | dma_len -= PAGE_SIZE; | |
429 | dma_addr += PAGE_SIZE; | |
430 | length -= PAGE_SIZE; | |
431 | if (length <= 0) | |
432 | break; | |
433 | if (dma_len > 0) | |
434 | continue; | |
435 | BUG_ON(dma_len < 0); | |
436 | sg = sg_next(sg); | |
437 | dma_addr = sg_dma_address(sg); | |
438 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
439 | } |
440 | ||
eca18b23 | 441 | return total_len; |
ff22b54f MW |
442 | } |
443 | ||
427e9708 KB |
444 | struct nvme_bio_pair { |
445 | struct bio b1, b2, *parent; | |
446 | struct bio_vec *bv1, *bv2; | |
447 | int err; | |
448 | atomic_t cnt; | |
449 | }; | |
450 | ||
451 | static void nvme_bio_pair_endio(struct bio *bio, int err) | |
452 | { | |
453 | struct nvme_bio_pair *bp = bio->bi_private; | |
454 | ||
455 | if (err) | |
456 | bp->err = err; | |
457 | ||
458 | if (atomic_dec_and_test(&bp->cnt)) { | |
459 | bio_endio(bp->parent, bp->err); | |
1b56749e KB |
460 | kfree(bp->bv1); |
461 | kfree(bp->bv2); | |
427e9708 KB |
462 | kfree(bp); |
463 | } | |
464 | } | |
465 | ||
466 | static struct nvme_bio_pair *nvme_bio_split(struct bio *bio, int idx, | |
467 | int len, int offset) | |
468 | { | |
469 | struct nvme_bio_pair *bp; | |
470 | ||
4f024f37 | 471 | BUG_ON(len > bio->bi_iter.bi_size); |
427e9708 KB |
472 | BUG_ON(idx > bio->bi_vcnt); |
473 | ||
474 | bp = kmalloc(sizeof(*bp), GFP_ATOMIC); | |
475 | if (!bp) | |
476 | return NULL; | |
477 | bp->err = 0; | |
478 | ||
479 | bp->b1 = *bio; | |
480 | bp->b2 = *bio; | |
481 | ||
4f024f37 KO |
482 | bp->b1.bi_iter.bi_size = len; |
483 | bp->b2.bi_iter.bi_size -= len; | |
427e9708 | 484 | bp->b1.bi_vcnt = idx; |
4f024f37 KO |
485 | bp->b2.bi_iter.bi_idx = idx; |
486 | bp->b2.bi_iter.bi_sector += len >> 9; | |
427e9708 KB |
487 | |
488 | if (offset) { | |
489 | bp->bv1 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec), | |
490 | GFP_ATOMIC); | |
491 | if (!bp->bv1) | |
492 | goto split_fail_1; | |
493 | ||
494 | bp->bv2 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec), | |
495 | GFP_ATOMIC); | |
496 | if (!bp->bv2) | |
497 | goto split_fail_2; | |
498 | ||
499 | memcpy(bp->bv1, bio->bi_io_vec, | |
500 | bio->bi_max_vecs * sizeof(struct bio_vec)); | |
501 | memcpy(bp->bv2, bio->bi_io_vec, | |
502 | bio->bi_max_vecs * sizeof(struct bio_vec)); | |
503 | ||
504 | bp->b1.bi_io_vec = bp->bv1; | |
505 | bp->b2.bi_io_vec = bp->bv2; | |
506 | bp->b2.bi_io_vec[idx].bv_offset += offset; | |
507 | bp->b2.bi_io_vec[idx].bv_len -= offset; | |
508 | bp->b1.bi_io_vec[idx].bv_len = offset; | |
509 | bp->b1.bi_vcnt++; | |
510 | } else | |
511 | bp->bv1 = bp->bv2 = NULL; | |
512 | ||
513 | bp->b1.bi_private = bp; | |
514 | bp->b2.bi_private = bp; | |
515 | ||
516 | bp->b1.bi_end_io = nvme_bio_pair_endio; | |
517 | bp->b2.bi_end_io = nvme_bio_pair_endio; | |
518 | ||
519 | bp->parent = bio; | |
520 | atomic_set(&bp->cnt, 2); | |
521 | ||
522 | return bp; | |
523 | ||
524 | split_fail_2: | |
525 | kfree(bp->bv1); | |
526 | split_fail_1: | |
527 | kfree(bp); | |
528 | return NULL; | |
529 | } | |
530 | ||
531 | static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq, | |
532 | int idx, int len, int offset) | |
533 | { | |
534 | struct nvme_bio_pair *bp = nvme_bio_split(bio, idx, len, offset); | |
535 | if (!bp) | |
536 | return -ENOMEM; | |
537 | ||
538 | if (bio_list_empty(&nvmeq->sq_cong)) | |
539 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
540 | bio_list_add(&nvmeq->sq_cong, &bp->b1); | |
541 | bio_list_add(&nvmeq->sq_cong, &bp->b2); | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
1ad2f893 MW |
546 | /* NVMe scatterlists require no holes in the virtual address */ |
547 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
548 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
549 | ||
427e9708 | 550 | static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
b60503ba MW |
551 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
552 | { | |
76830840 MW |
553 | struct bio_vec *bvec, *bvprv = NULL; |
554 | struct scatterlist *sg = NULL; | |
4f024f37 | 555 | int i, length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size; |
159b67d7 KB |
556 | |
557 | if (nvmeq->dev->stripe_size) | |
558 | split_len = nvmeq->dev->stripe_size - | |
4f024f37 KO |
559 | ((bio->bi_iter.bi_sector << 9) & |
560 | (nvmeq->dev->stripe_size - 1)); | |
b60503ba | 561 | |
eca18b23 | 562 | sg_init_table(iod->sg, psegs); |
b60503ba | 563 | bio_for_each_segment(bvec, bio, i) { |
76830840 MW |
564 | if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { |
565 | sg->length += bvec->bv_len; | |
566 | } else { | |
1ad2f893 | 567 | if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec)) |
427e9708 KB |
568 | return nvme_split_and_submit(bio, nvmeq, i, |
569 | length, 0); | |
570 | ||
eca18b23 | 571 | sg = sg ? sg + 1 : iod->sg; |
76830840 MW |
572 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, |
573 | bvec->bv_offset); | |
574 | nsegs++; | |
575 | } | |
159b67d7 KB |
576 | |
577 | if (split_len - length < bvec->bv_len) | |
578 | return nvme_split_and_submit(bio, nvmeq, i, split_len, | |
579 | split_len - length); | |
1ad2f893 | 580 | length += bvec->bv_len; |
76830840 | 581 | bvprv = bvec; |
b60503ba | 582 | } |
eca18b23 | 583 | iod->nents = nsegs; |
76830840 | 584 | sg_mark_end(sg); |
427e9708 | 585 | if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0) |
1ad2f893 | 586 | return -ENOMEM; |
427e9708 | 587 | |
4f024f37 | 588 | BUG_ON(length != bio->bi_iter.bi_size); |
1ad2f893 | 589 | return length; |
b60503ba MW |
590 | } |
591 | ||
0e5e4f0e KB |
592 | /* |
593 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
594 | * worth having a special pool for these or additional cases to handle freeing | |
595 | * the iod. | |
596 | */ | |
597 | static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
598 | struct bio *bio, struct nvme_iod *iod, int cmdid) | |
599 | { | |
600 | struct nvme_dsm_range *range; | |
601 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
602 | ||
603 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
604 | &iod->first_dma); | |
605 | if (!range) | |
606 | return -ENOMEM; | |
607 | ||
608 | iod_list(iod)[0] = (__le64 *)range; | |
609 | iod->npages = 0; | |
610 | ||
611 | range->cattr = cpu_to_le32(0); | |
4f024f37 KO |
612 | range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift); |
613 | range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector)); | |
0e5e4f0e KB |
614 | |
615 | memset(cmnd, 0, sizeof(*cmnd)); | |
616 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
617 | cmnd->dsm.command_id = cmdid; | |
618 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
619 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
620 | cmnd->dsm.nr = 0; | |
621 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
622 | ||
623 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
624 | nvmeq->sq_tail = 0; | |
625 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
00df5cb4 MW |
630 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
631 | int cmdid) | |
632 | { | |
633 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
634 | ||
635 | memset(cmnd, 0, sizeof(*cmnd)); | |
636 | cmnd->common.opcode = nvme_cmd_flush; | |
637 | cmnd->common.command_id = cmdid; | |
638 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
639 | ||
640 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
641 | nvmeq->sq_tail = 0; | |
642 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
5d0f6131 | 647 | int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) |
00df5cb4 MW |
648 | { |
649 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
ff976d72 | 650 | special_completion, NVME_IO_TIMEOUT); |
00df5cb4 MW |
651 | if (unlikely(cmdid < 0)) |
652 | return cmdid; | |
653 | ||
654 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
655 | } | |
656 | ||
184d2944 MW |
657 | /* |
658 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
659 | */ | |
b60503ba MW |
660 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
661 | struct bio *bio) | |
662 | { | |
ff22b54f | 663 | struct nvme_command *cmnd; |
eca18b23 | 664 | struct nvme_iod *iod; |
b60503ba | 665 | enum dma_data_direction dma_dir; |
1287dabd | 666 | int cmdid, length, result; |
b60503ba MW |
667 | u16 control; |
668 | u32 dsmgmt; | |
b60503ba MW |
669 | int psegs = bio_phys_segments(ns->queue, bio); |
670 | ||
00df5cb4 MW |
671 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
672 | result = nvme_submit_flush_data(nvmeq, ns); | |
673 | if (result) | |
674 | return result; | |
675 | } | |
676 | ||
1287dabd | 677 | result = -ENOMEM; |
4f024f37 | 678 | iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC); |
eca18b23 | 679 | if (!iod) |
eeee3226 | 680 | goto nomem; |
eca18b23 | 681 | iod->private = bio; |
b60503ba | 682 | |
eeee3226 | 683 | result = -EBUSY; |
ff976d72 | 684 | cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT); |
b60503ba | 685 | if (unlikely(cmdid < 0)) |
eca18b23 | 686 | goto free_iod; |
b60503ba | 687 | |
0e5e4f0e KB |
688 | if (bio->bi_rw & REQ_DISCARD) { |
689 | result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid); | |
690 | if (result) | |
691 | goto free_cmdid; | |
692 | return result; | |
693 | } | |
00df5cb4 MW |
694 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
695 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
696 | ||
b60503ba MW |
697 | control = 0; |
698 | if (bio->bi_rw & REQ_FUA) | |
699 | control |= NVME_RW_FUA; | |
700 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
701 | control |= NVME_RW_LR; | |
702 | ||
703 | dsmgmt = 0; | |
704 | if (bio->bi_rw & REQ_RAHEAD) | |
705 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
706 | ||
ff22b54f | 707 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 708 | |
b8deb62c | 709 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 710 | if (bio_data_dir(bio)) { |
ff22b54f | 711 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
712 | dma_dir = DMA_TO_DEVICE; |
713 | } else { | |
ff22b54f | 714 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
715 | dma_dir = DMA_FROM_DEVICE; |
716 | } | |
717 | ||
427e9708 KB |
718 | result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs); |
719 | if (result <= 0) | |
859361a2 | 720 | goto free_cmdid; |
1ad2f893 | 721 | length = result; |
b60503ba | 722 | |
ff22b54f MW |
723 | cmnd->rw.command_id = cmdid; |
724 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
eca18b23 MW |
725 | length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length, |
726 | GFP_ATOMIC); | |
4f024f37 | 727 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector)); |
1ad2f893 | 728 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
729 | cmnd->rw.control = cpu_to_le16(control); |
730 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 731 | |
6198221f | 732 | nvme_start_io_acct(bio); |
b60503ba MW |
733 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
734 | nvmeq->sq_tail = 0; | |
7547881d | 735 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 736 | |
1974b1ae MW |
737 | return 0; |
738 | ||
859361a2 KB |
739 | free_cmdid: |
740 | free_cmdid(nvmeq, cmdid, NULL); | |
eca18b23 MW |
741 | free_iod: |
742 | nvme_free_iod(nvmeq->dev, iod); | |
eeee3226 MW |
743 | nomem: |
744 | return result; | |
b60503ba MW |
745 | } |
746 | ||
e9539f47 | 747 | static int nvme_process_cq(struct nvme_queue *nvmeq) |
b60503ba | 748 | { |
82123460 | 749 | u16 head, phase; |
b60503ba | 750 | |
b60503ba | 751 | head = nvmeq->cq_head; |
82123460 | 752 | phase = nvmeq->cq_phase; |
b60503ba MW |
753 | |
754 | for (;;) { | |
c2f5b650 MW |
755 | void *ctx; |
756 | nvme_completion_fn fn; | |
b60503ba | 757 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 758 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
759 | break; |
760 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
761 | if (++head == nvmeq->q_depth) { | |
762 | head = 0; | |
82123460 | 763 | phase = !phase; |
b60503ba MW |
764 | } |
765 | ||
c2f5b650 | 766 | ctx = free_cmdid(nvmeq, cqe.command_id, &fn); |
5c1281a3 | 767 | fn(nvmeq->dev, ctx, &cqe); |
b60503ba MW |
768 | } |
769 | ||
770 | /* If the controller ignores the cq head doorbell and continuously | |
771 | * writes to the queue, it is theoretically possible to wrap around | |
772 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
773 | * requires that 0.1% of your interrupts are handled, so this isn't | |
774 | * a big problem. | |
775 | */ | |
82123460 | 776 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
e9539f47 | 777 | return 0; |
b60503ba | 778 | |
f1938f6e | 779 | writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride)); |
b60503ba | 780 | nvmeq->cq_head = head; |
82123460 | 781 | nvmeq->cq_phase = phase; |
b60503ba | 782 | |
e9539f47 MW |
783 | nvmeq->cqe_seen = 1; |
784 | return 1; | |
b60503ba MW |
785 | } |
786 | ||
7d822457 MW |
787 | static void nvme_make_request(struct request_queue *q, struct bio *bio) |
788 | { | |
789 | struct nvme_ns *ns = q->queuedata; | |
790 | struct nvme_queue *nvmeq = get_nvmeq(ns->dev); | |
791 | int result = -EBUSY; | |
792 | ||
cd638946 KB |
793 | if (!nvmeq) { |
794 | put_nvmeq(NULL); | |
795 | bio_endio(bio, -EIO); | |
796 | return; | |
797 | } | |
798 | ||
7d822457 | 799 | spin_lock_irq(&nvmeq->q_lock); |
22404274 | 800 | if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong)) |
7d822457 MW |
801 | result = nvme_submit_bio_queue(nvmeq, ns, bio); |
802 | if (unlikely(result)) { | |
803 | if (bio_list_empty(&nvmeq->sq_cong)) | |
804 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
805 | bio_list_add(&nvmeq->sq_cong, bio); | |
806 | } | |
807 | ||
808 | nvme_process_cq(nvmeq); | |
809 | spin_unlock_irq(&nvmeq->q_lock); | |
810 | put_nvmeq(nvmeq); | |
811 | } | |
812 | ||
b60503ba | 813 | static irqreturn_t nvme_irq(int irq, void *data) |
58ffacb5 MW |
814 | { |
815 | irqreturn_t result; | |
816 | struct nvme_queue *nvmeq = data; | |
817 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
818 | nvme_process_cq(nvmeq); |
819 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
820 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
821 | spin_unlock(&nvmeq->q_lock); |
822 | return result; | |
823 | } | |
824 | ||
825 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
826 | { | |
827 | struct nvme_queue *nvmeq = data; | |
828 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
829 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
830 | return IRQ_NONE; | |
831 | return IRQ_WAKE_THREAD; | |
832 | } | |
833 | ||
3c0cf138 MW |
834 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
835 | { | |
836 | spin_lock_irq(&nvmeq->q_lock); | |
c2f5b650 | 837 | cancel_cmdid(nvmeq, cmdid, NULL); |
3c0cf138 MW |
838 | spin_unlock_irq(&nvmeq->q_lock); |
839 | } | |
840 | ||
c2f5b650 MW |
841 | struct sync_cmd_info { |
842 | struct task_struct *task; | |
843 | u32 result; | |
844 | int status; | |
845 | }; | |
846 | ||
5c1281a3 | 847 | static void sync_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
848 | struct nvme_completion *cqe) |
849 | { | |
850 | struct sync_cmd_info *cmdinfo = ctx; | |
851 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
852 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
853 | wake_up_process(cmdinfo->task); | |
854 | } | |
855 | ||
b60503ba MW |
856 | /* |
857 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
858 | * if the result is positive, it's an NVM Express status code | |
859 | */ | |
5d0f6131 VV |
860 | int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, |
861 | u32 *result, unsigned timeout) | |
b60503ba MW |
862 | { |
863 | int cmdid; | |
864 | struct sync_cmd_info cmdinfo; | |
865 | ||
866 | cmdinfo.task = current; | |
867 | cmdinfo.status = -EINTR; | |
868 | ||
c2f5b650 | 869 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion, |
e85248e5 | 870 | timeout); |
b60503ba MW |
871 | if (cmdid < 0) |
872 | return cmdid; | |
873 | cmd->common.command_id = cmdid; | |
874 | ||
3c0cf138 MW |
875 | set_current_state(TASK_KILLABLE); |
876 | nvme_submit_cmd(nvmeq, cmd); | |
78f8d257 | 877 | schedule_timeout(timeout); |
b60503ba | 878 | |
3c0cf138 MW |
879 | if (cmdinfo.status == -EINTR) { |
880 | nvme_abort_command(nvmeq, cmdid); | |
881 | return -EINTR; | |
882 | } | |
883 | ||
b60503ba MW |
884 | if (result) |
885 | *result = cmdinfo.result; | |
886 | ||
887 | return cmdinfo.status; | |
888 | } | |
889 | ||
5d0f6131 | 890 | int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
b60503ba MW |
891 | u32 *result) |
892 | { | |
e85248e5 | 893 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
894 | } |
895 | ||
896 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
897 | { | |
898 | int status; | |
899 | struct nvme_command c; | |
900 | ||
901 | memset(&c, 0, sizeof(c)); | |
902 | c.delete_queue.opcode = opcode; | |
903 | c.delete_queue.qid = cpu_to_le16(id); | |
904 | ||
905 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
906 | if (status) | |
907 | return -EIO; | |
908 | return 0; | |
909 | } | |
910 | ||
911 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
912 | struct nvme_queue *nvmeq) | |
913 | { | |
914 | int status; | |
915 | struct nvme_command c; | |
916 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
917 | ||
918 | memset(&c, 0, sizeof(c)); | |
919 | c.create_cq.opcode = nvme_admin_create_cq; | |
920 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
921 | c.create_cq.cqid = cpu_to_le16(qid); | |
922 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
923 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
924 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
925 | ||
926 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
927 | if (status) | |
928 | return -EIO; | |
929 | return 0; | |
930 | } | |
931 | ||
932 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
933 | struct nvme_queue *nvmeq) | |
934 | { | |
935 | int status; | |
936 | struct nvme_command c; | |
937 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
938 | ||
939 | memset(&c, 0, sizeof(c)); | |
940 | c.create_sq.opcode = nvme_admin_create_sq; | |
941 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
942 | c.create_sq.sqid = cpu_to_le16(qid); | |
943 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
944 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
945 | c.create_sq.cqid = cpu_to_le16(qid); | |
946 | ||
947 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
948 | if (status) | |
949 | return -EIO; | |
950 | return 0; | |
951 | } | |
952 | ||
953 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
954 | { | |
955 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
956 | } | |
957 | ||
958 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
959 | { | |
960 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
961 | } | |
962 | ||
5d0f6131 | 963 | int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
bc5fc7e4 MW |
964 | dma_addr_t dma_addr) |
965 | { | |
966 | struct nvme_command c; | |
967 | ||
968 | memset(&c, 0, sizeof(c)); | |
969 | c.identify.opcode = nvme_admin_identify; | |
970 | c.identify.nsid = cpu_to_le32(nsid); | |
971 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
972 | c.identify.cns = cpu_to_le32(cns); | |
973 | ||
974 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
975 | } | |
976 | ||
5d0f6131 | 977 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 978 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
979 | { |
980 | struct nvme_command c; | |
981 | ||
982 | memset(&c, 0, sizeof(c)); | |
983 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 984 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
985 | c.features.prp1 = cpu_to_le64(dma_addr); |
986 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 987 | |
08df1e05 | 988 | return nvme_submit_admin_cmd(dev, &c, result); |
df348139 MW |
989 | } |
990 | ||
5d0f6131 VV |
991 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
992 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
993 | { |
994 | struct nvme_command c; | |
995 | ||
996 | memset(&c, 0, sizeof(c)); | |
997 | c.features.opcode = nvme_admin_set_features; | |
998 | c.features.prp1 = cpu_to_le64(dma_addr); | |
999 | c.features.fid = cpu_to_le32(fid); | |
1000 | c.features.dword11 = cpu_to_le32(dword11); | |
1001 | ||
bc5fc7e4 MW |
1002 | return nvme_submit_admin_cmd(dev, &c, result); |
1003 | } | |
1004 | ||
a09115b2 MW |
1005 | /** |
1006 | * nvme_cancel_ios - Cancel outstanding I/Os | |
1007 | * @queue: The queue to cancel I/Os on | |
1008 | * @timeout: True to only cancel I/Os which have timed out | |
1009 | */ | |
1010 | static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout) | |
1011 | { | |
1012 | int depth = nvmeq->q_depth - 1; | |
1013 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
1014 | unsigned long now = jiffies; | |
1015 | int cmdid; | |
1016 | ||
1017 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
1018 | void *ctx; | |
1019 | nvme_completion_fn fn; | |
1020 | static struct nvme_completion cqe = { | |
af2d9ca7 | 1021 | .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1), |
a09115b2 MW |
1022 | }; |
1023 | ||
1024 | if (timeout && !time_after(now, info[cmdid].timeout)) | |
1025 | continue; | |
053ab702 KB |
1026 | if (info[cmdid].ctx == CMD_CTX_CANCELLED) |
1027 | continue; | |
a09115b2 MW |
1028 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid); |
1029 | ctx = cancel_cmdid(nvmeq, cmdid, &fn); | |
1030 | fn(nvmeq->dev, ctx, &cqe); | |
1031 | } | |
1032 | } | |
1033 | ||
22404274 | 1034 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
9e866774 | 1035 | { |
22404274 KB |
1036 | spin_lock_irq(&nvmeq->q_lock); |
1037 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1038 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1039 | bio_endio(bio, -EIO); | |
1040 | } | |
1041 | spin_unlock_irq(&nvmeq->q_lock); | |
1042 | ||
9e866774 MW |
1043 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1044 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1045 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1046 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1047 | kfree(nvmeq); | |
1048 | } | |
1049 | ||
22404274 KB |
1050 | static void nvme_free_queues(struct nvme_dev *dev) |
1051 | { | |
1052 | int i; | |
1053 | ||
1054 | for (i = dev->queue_count - 1; i >= 0; i--) { | |
1055 | nvme_free_queue(dev->queues[i]); | |
1056 | dev->queue_count--; | |
1057 | dev->queues[i] = NULL; | |
1058 | } | |
1059 | } | |
1060 | ||
1061 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) | |
b60503ba MW |
1062 | { |
1063 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
aba2080f | 1064 | int vector = dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 1065 | |
a09115b2 | 1066 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1067 | if (nvmeq->q_suspended) { |
1068 | spin_unlock_irq(&nvmeq->q_lock); | |
1069 | return; | |
3295874b | 1070 | } |
22404274 | 1071 | nvmeq->q_suspended = 1; |
a09115b2 MW |
1072 | spin_unlock_irq(&nvmeq->q_lock); |
1073 | ||
aba2080f MW |
1074 | irq_set_affinity_hint(vector, NULL); |
1075 | free_irq(vector, nvmeq); | |
b60503ba MW |
1076 | |
1077 | /* Don't tell the adapter to delete the admin queue */ | |
1078 | if (qid) { | |
1079 | adapter_delete_sq(dev, qid); | |
1080 | adapter_delete_cq(dev, qid); | |
1081 | } | |
1082 | ||
22404274 KB |
1083 | spin_lock_irq(&nvmeq->q_lock); |
1084 | nvme_process_cq(nvmeq); | |
1085 | nvme_cancel_ios(nvmeq, false); | |
1086 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1087 | } |
1088 | ||
1089 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
1090 | int depth, int vector) | |
1091 | { | |
1092 | struct device *dmadev = &dev->pci_dev->dev; | |
22404274 | 1093 | unsigned extra = nvme_queue_extra(depth); |
b60503ba MW |
1094 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
1095 | if (!nvmeq) | |
1096 | return NULL; | |
1097 | ||
1098 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
1099 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
1100 | if (!nvmeq->cqes) | |
1101 | goto free_nvmeq; | |
1102 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
1103 | ||
1104 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
1105 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1106 | if (!nvmeq->sq_cmds) | |
1107 | goto free_cqdma; | |
1108 | ||
1109 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 1110 | nvmeq->dev = dev; |
b60503ba MW |
1111 | spin_lock_init(&nvmeq->q_lock); |
1112 | nvmeq->cq_head = 0; | |
82123460 | 1113 | nvmeq->cq_phase = 1; |
b60503ba | 1114 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 1115 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba | 1116 | bio_list_init(&nvmeq->sq_cong); |
f1938f6e | 1117 | nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)]; |
b60503ba MW |
1118 | nvmeq->q_depth = depth; |
1119 | nvmeq->cq_vector = vector; | |
22404274 KB |
1120 | nvmeq->q_suspended = 1; |
1121 | dev->queue_count++; | |
b60503ba MW |
1122 | |
1123 | return nvmeq; | |
1124 | ||
1125 | free_cqdma: | |
68b8eca5 | 1126 | dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1127 | nvmeq->cq_dma_addr); |
1128 | free_nvmeq: | |
1129 | kfree(nvmeq); | |
1130 | return NULL; | |
1131 | } | |
1132 | ||
3001082c MW |
1133 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1134 | const char *name) | |
1135 | { | |
58ffacb5 MW |
1136 | if (use_threaded_interrupts) |
1137 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 1138 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
1139 | IRQF_DISABLED | IRQF_SHARED, |
1140 | name, nvmeq); | |
3001082c MW |
1141 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
1142 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
1143 | } | |
1144 | ||
22404274 | 1145 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1146 | { |
22404274 KB |
1147 | struct nvme_dev *dev = nvmeq->dev; |
1148 | unsigned extra = nvme_queue_extra(nvmeq->q_depth); | |
b60503ba | 1149 | |
22404274 KB |
1150 | nvmeq->sq_tail = 0; |
1151 | nvmeq->cq_head = 0; | |
1152 | nvmeq->cq_phase = 1; | |
1153 | nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)]; | |
1154 | memset(nvmeq->cmdid_data, 0, extra); | |
1155 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); | |
1156 | nvme_cancel_ios(nvmeq, false); | |
1157 | nvmeq->q_suspended = 0; | |
1158 | } | |
1159 | ||
1160 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1161 | { | |
1162 | struct nvme_dev *dev = nvmeq->dev; | |
1163 | int result; | |
3f85d50b | 1164 | |
b60503ba MW |
1165 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1166 | if (result < 0) | |
22404274 | 1167 | return result; |
b60503ba MW |
1168 | |
1169 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1170 | if (result < 0) | |
1171 | goto release_cq; | |
1172 | ||
3001082c | 1173 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
1174 | if (result < 0) |
1175 | goto release_sq; | |
1176 | ||
22404274 KB |
1177 | spin_lock(&nvmeq->q_lock); |
1178 | nvme_init_queue(nvmeq, qid); | |
1179 | spin_unlock(&nvmeq->q_lock); | |
1180 | ||
1181 | return result; | |
b60503ba MW |
1182 | |
1183 | release_sq: | |
1184 | adapter_delete_sq(dev, qid); | |
1185 | release_cq: | |
1186 | adapter_delete_cq(dev, qid); | |
22404274 | 1187 | return result; |
b60503ba MW |
1188 | } |
1189 | ||
ba47e386 MW |
1190 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1191 | { | |
1192 | unsigned long timeout; | |
1193 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1194 | ||
1195 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1196 | ||
1197 | while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) { | |
1198 | msleep(100); | |
1199 | if (fatal_signal_pending(current)) | |
1200 | return -EINTR; | |
1201 | if (time_after(jiffies, timeout)) { | |
1202 | dev_err(&dev->pci_dev->dev, | |
1203 | "Device not ready; aborting initialisation\n"); | |
1204 | return -ENODEV; | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * If the device has been passed off to us in an enabled state, just clear | |
1213 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1214 | * bits', but doing so may cause the device to complete commands to the | |
1215 | * admin queue ... and we don't know what memory that might be pointing at! | |
1216 | */ | |
1217 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1218 | { | |
44af146a MW |
1219 | u32 cc = readl(&dev->bar->cc); |
1220 | ||
1221 | if (cc & NVME_CC_ENABLE) | |
1222 | writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc); | |
ba47e386 MW |
1223 | return nvme_wait_ready(dev, cap, false); |
1224 | } | |
1225 | ||
1226 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1227 | { | |
1228 | return nvme_wait_ready(dev, cap, true); | |
1229 | } | |
1230 | ||
1894d8f1 KB |
1231 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1232 | { | |
1233 | unsigned long timeout; | |
1234 | u32 cc; | |
1235 | ||
1236 | cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL; | |
1237 | writel(cc, &dev->bar->cc); | |
1238 | ||
1239 | timeout = 2 * HZ + jiffies; | |
1240 | while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) != | |
1241 | NVME_CSTS_SHST_CMPLT) { | |
1242 | msleep(100); | |
1243 | if (fatal_signal_pending(current)) | |
1244 | return -EINTR; | |
1245 | if (time_after(jiffies, timeout)) { | |
1246 | dev_err(&dev->pci_dev->dev, | |
1247 | "Device shutdown incomplete; abort shutdown\n"); | |
1248 | return -ENODEV; | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
8d85fce7 | 1255 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1256 | { |
ba47e386 | 1257 | int result; |
b60503ba | 1258 | u32 aqa; |
ba47e386 | 1259 | u64 cap = readq(&dev->bar->cap); |
b60503ba MW |
1260 | struct nvme_queue *nvmeq; |
1261 | ||
ba47e386 MW |
1262 | result = nvme_disable_ctrl(dev, cap); |
1263 | if (result < 0) | |
1264 | return result; | |
b60503ba | 1265 | |
cd638946 KB |
1266 | nvmeq = dev->queues[0]; |
1267 | if (!nvmeq) { | |
1268 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
1269 | if (!nvmeq) | |
1270 | return -ENOMEM; | |
1271 | dev->queues[0] = nvmeq; | |
1272 | } | |
b60503ba MW |
1273 | |
1274 | aqa = nvmeq->q_depth - 1; | |
1275 | aqa |= aqa << 16; | |
1276 | ||
1277 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
1278 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
1279 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 1280 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba MW |
1281 | |
1282 | writel(aqa, &dev->bar->aqa); | |
1283 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1284 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
1285 | writel(dev->ctrl_config, &dev->bar->cc); | |
1286 | ||
ba47e386 | 1287 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1288 | if (result) |
cd638946 | 1289 | return result; |
9e866774 | 1290 | |
3001082c | 1291 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
025c557a | 1292 | if (result) |
cd638946 | 1293 | return result; |
025c557a | 1294 | |
22404274 KB |
1295 | spin_lock(&nvmeq->q_lock); |
1296 | nvme_init_queue(nvmeq, 0); | |
1297 | spin_unlock(&nvmeq->q_lock); | |
b60503ba MW |
1298 | return result; |
1299 | } | |
1300 | ||
5d0f6131 | 1301 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
eca18b23 | 1302 | unsigned long addr, unsigned length) |
b60503ba | 1303 | { |
36c14ed9 | 1304 | int i, err, count, nents, offset; |
7fc3cdab MW |
1305 | struct scatterlist *sg; |
1306 | struct page **pages; | |
eca18b23 | 1307 | struct nvme_iod *iod; |
36c14ed9 MW |
1308 | |
1309 | if (addr & 3) | |
eca18b23 | 1310 | return ERR_PTR(-EINVAL); |
5460fc03 | 1311 | if (!length || length > INT_MAX - PAGE_SIZE) |
eca18b23 | 1312 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1313 | |
36c14ed9 | 1314 | offset = offset_in_page(addr); |
7fc3cdab MW |
1315 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1316 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
22fff826 DC |
1317 | if (!pages) |
1318 | return ERR_PTR(-ENOMEM); | |
36c14ed9 MW |
1319 | |
1320 | err = get_user_pages_fast(addr, count, 1, pages); | |
1321 | if (err < count) { | |
1322 | count = err; | |
1323 | err = -EFAULT; | |
1324 | goto put_pages; | |
1325 | } | |
7fc3cdab | 1326 | |
eca18b23 MW |
1327 | iod = nvme_alloc_iod(count, length, GFP_KERNEL); |
1328 | sg = iod->sg; | |
36c14ed9 | 1329 | sg_init_table(sg, count); |
d0ba1e49 MW |
1330 | for (i = 0; i < count; i++) { |
1331 | sg_set_page(&sg[i], pages[i], | |
5460fc03 DC |
1332 | min_t(unsigned, length, PAGE_SIZE - offset), |
1333 | offset); | |
d0ba1e49 MW |
1334 | length -= (PAGE_SIZE - offset); |
1335 | offset = 0; | |
7fc3cdab | 1336 | } |
fe304c43 | 1337 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1338 | iod->nents = count; |
7fc3cdab MW |
1339 | |
1340 | err = -ENOMEM; | |
1341 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1342 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1343 | if (!nents) |
eca18b23 | 1344 | goto free_iod; |
b60503ba | 1345 | |
7fc3cdab | 1346 | kfree(pages); |
eca18b23 | 1347 | return iod; |
b60503ba | 1348 | |
eca18b23 MW |
1349 | free_iod: |
1350 | kfree(iod); | |
7fc3cdab MW |
1351 | put_pages: |
1352 | for (i = 0; i < count; i++) | |
1353 | put_page(pages[i]); | |
1354 | kfree(pages); | |
eca18b23 | 1355 | return ERR_PTR(err); |
7fc3cdab | 1356 | } |
b60503ba | 1357 | |
5d0f6131 | 1358 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1359 | struct nvme_iod *iod) |
7fc3cdab | 1360 | { |
1c2ad9fa | 1361 | int i; |
b60503ba | 1362 | |
1c2ad9fa MW |
1363 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1364 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1365 | |
1c2ad9fa MW |
1366 | for (i = 0; i < iod->nents; i++) |
1367 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1368 | } |
b60503ba | 1369 | |
a53295b6 MW |
1370 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1371 | { | |
1372 | struct nvme_dev *dev = ns->dev; | |
1373 | struct nvme_queue *nvmeq; | |
1374 | struct nvme_user_io io; | |
1375 | struct nvme_command c; | |
f410c680 KB |
1376 | unsigned length, meta_len; |
1377 | int status, i; | |
1378 | struct nvme_iod *iod, *meta_iod = NULL; | |
1379 | dma_addr_t meta_dma_addr; | |
1380 | void *meta, *uninitialized_var(meta_mem); | |
a53295b6 MW |
1381 | |
1382 | if (copy_from_user(&io, uio, sizeof(io))) | |
1383 | return -EFAULT; | |
6c7d4945 | 1384 | length = (io.nblocks + 1) << ns->lba_shift; |
f410c680 KB |
1385 | meta_len = (io.nblocks + 1) * ns->ms; |
1386 | ||
1387 | if (meta_len && ((io.metadata & 3) || !io.metadata)) | |
1388 | return -EINVAL; | |
6c7d4945 MW |
1389 | |
1390 | switch (io.opcode) { | |
1391 | case nvme_cmd_write: | |
1392 | case nvme_cmd_read: | |
6bbf1acd | 1393 | case nvme_cmd_compare: |
eca18b23 | 1394 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1395 | break; |
6c7d4945 | 1396 | default: |
6bbf1acd | 1397 | return -EINVAL; |
6c7d4945 MW |
1398 | } |
1399 | ||
eca18b23 MW |
1400 | if (IS_ERR(iod)) |
1401 | return PTR_ERR(iod); | |
a53295b6 MW |
1402 | |
1403 | memset(&c, 0, sizeof(c)); | |
1404 | c.rw.opcode = io.opcode; | |
1405 | c.rw.flags = io.flags; | |
6c7d4945 | 1406 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1407 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1408 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1409 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1410 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1411 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1412 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1413 | c.rw.appmask = cpu_to_le16(io.appmask); | |
f410c680 KB |
1414 | |
1415 | if (meta_len) { | |
1b56749e KB |
1416 | meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata, |
1417 | meta_len); | |
f410c680 KB |
1418 | if (IS_ERR(meta_iod)) { |
1419 | status = PTR_ERR(meta_iod); | |
1420 | meta_iod = NULL; | |
1421 | goto unmap; | |
1422 | } | |
1423 | ||
1424 | meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len, | |
1425 | &meta_dma_addr, GFP_KERNEL); | |
1426 | if (!meta_mem) { | |
1427 | status = -ENOMEM; | |
1428 | goto unmap; | |
1429 | } | |
1430 | ||
1431 | if (io.opcode & 1) { | |
1432 | int meta_offset = 0; | |
1433 | ||
1434 | for (i = 0; i < meta_iod->nents; i++) { | |
1435 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1436 | meta_iod->sg[i].offset; | |
1437 | memcpy(meta_mem + meta_offset, meta, | |
1438 | meta_iod->sg[i].length); | |
1439 | kunmap_atomic(meta); | |
1440 | meta_offset += meta_iod->sg[i].length; | |
1441 | } | |
1442 | } | |
1443 | ||
1444 | c.rw.metadata = cpu_to_le64(meta_dma_addr); | |
1445 | } | |
1446 | ||
eca18b23 | 1447 | length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL); |
a53295b6 | 1448 | |
040a93b5 | 1449 | nvmeq = get_nvmeq(dev); |
fa922821 MW |
1450 | /* |
1451 | * Since nvme_submit_sync_cmd sleeps, we can't keep preemption | |
b1ad37ef MW |
1452 | * disabled. We may be preempted at any point, and be rescheduled |
1453 | * to a different CPU. That will cause cacheline bouncing, but no | |
1454 | * additional races since q_lock already protects against other CPUs. | |
1455 | */ | |
a53295b6 | 1456 | put_nvmeq(nvmeq); |
b77954cb MW |
1457 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1458 | status = -ENOMEM; | |
22404274 KB |
1459 | else if (!nvmeq || nvmeq->q_suspended) |
1460 | status = -EBUSY; | |
b77954cb | 1461 | else |
ff976d72 | 1462 | status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT); |
a53295b6 | 1463 | |
f410c680 KB |
1464 | if (meta_len) { |
1465 | if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) { | |
1466 | int meta_offset = 0; | |
1467 | ||
1468 | for (i = 0; i < meta_iod->nents; i++) { | |
1469 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1470 | meta_iod->sg[i].offset; | |
1471 | memcpy(meta, meta_mem + meta_offset, | |
1472 | meta_iod->sg[i].length); | |
1473 | kunmap_atomic(meta); | |
1474 | meta_offset += meta_iod->sg[i].length; | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem, | |
1479 | meta_dma_addr); | |
1480 | } | |
1481 | ||
1482 | unmap: | |
1c2ad9fa | 1483 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1484 | nvme_free_iod(dev, iod); |
f410c680 KB |
1485 | |
1486 | if (meta_iod) { | |
1487 | nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod); | |
1488 | nvme_free_iod(dev, meta_iod); | |
1489 | } | |
1490 | ||
a53295b6 MW |
1491 | return status; |
1492 | } | |
1493 | ||
50af8bae | 1494 | static int nvme_user_admin_cmd(struct nvme_dev *dev, |
6bbf1acd | 1495 | struct nvme_admin_cmd __user *ucmd) |
6ee44cdc | 1496 | { |
6bbf1acd | 1497 | struct nvme_admin_cmd cmd; |
6ee44cdc | 1498 | struct nvme_command c; |
eca18b23 | 1499 | int status, length; |
c7d36ab8 | 1500 | struct nvme_iod *uninitialized_var(iod); |
94f370ca | 1501 | unsigned timeout; |
6ee44cdc | 1502 | |
6bbf1acd MW |
1503 | if (!capable(CAP_SYS_ADMIN)) |
1504 | return -EACCES; | |
1505 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1506 | return -EFAULT; |
6ee44cdc MW |
1507 | |
1508 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1509 | c.common.opcode = cmd.opcode; |
1510 | c.common.flags = cmd.flags; | |
1511 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1512 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1513 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1514 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1515 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1516 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1517 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1518 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1519 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1520 | ||
1521 | length = cmd.data_len; | |
1522 | if (cmd.data_len) { | |
49742188 MW |
1523 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1524 | length); | |
eca18b23 MW |
1525 | if (IS_ERR(iod)) |
1526 | return PTR_ERR(iod); | |
1527 | length = nvme_setup_prps(dev, &c.common, iod, length, | |
1528 | GFP_KERNEL); | |
6bbf1acd MW |
1529 | } |
1530 | ||
94f370ca KB |
1531 | timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) : |
1532 | ADMIN_TIMEOUT; | |
6bbf1acd | 1533 | if (length != cmd.data_len) |
b77954cb MW |
1534 | status = -ENOMEM; |
1535 | else | |
94f370ca KB |
1536 | status = nvme_submit_sync_cmd(dev->queues[0], &c, &cmd.result, |
1537 | timeout); | |
eca18b23 | 1538 | |
6bbf1acd | 1539 | if (cmd.data_len) { |
1c2ad9fa | 1540 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1541 | nvme_free_iod(dev, iod); |
6bbf1acd | 1542 | } |
f4f117f6 | 1543 | |
cf90bc48 | 1544 | if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result, |
f4f117f6 KB |
1545 | sizeof(cmd.result))) |
1546 | status = -EFAULT; | |
1547 | ||
6ee44cdc MW |
1548 | return status; |
1549 | } | |
1550 | ||
b60503ba MW |
1551 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1552 | unsigned long arg) | |
1553 | { | |
1554 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1555 | ||
1556 | switch (cmd) { | |
6bbf1acd | 1557 | case NVME_IOCTL_ID: |
c3bfe717 | 1558 | force_successful_syscall_return(); |
6bbf1acd MW |
1559 | return ns->ns_id; |
1560 | case NVME_IOCTL_ADMIN_CMD: | |
50af8bae | 1561 | return nvme_user_admin_cmd(ns->dev, (void __user *)arg); |
a53295b6 MW |
1562 | case NVME_IOCTL_SUBMIT_IO: |
1563 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1564 | case SG_GET_VERSION_NUM: |
1565 | return nvme_sg_get_version_num((void __user *)arg); | |
1566 | case SG_IO: | |
1567 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1568 | default: |
1569 | return -ENOTTY; | |
1570 | } | |
1571 | } | |
1572 | ||
1573 | static const struct block_device_operations nvme_fops = { | |
1574 | .owner = THIS_MODULE, | |
1575 | .ioctl = nvme_ioctl, | |
49481682 | 1576 | .compat_ioctl = nvme_ioctl, |
b60503ba MW |
1577 | }; |
1578 | ||
1fa6aead MW |
1579 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1580 | { | |
1581 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1582 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1583 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
427e9708 KB |
1584 | |
1585 | if (bio_list_empty(&nvmeq->sq_cong)) | |
1586 | remove_wait_queue(&nvmeq->sq_full, | |
1587 | &nvmeq->sq_cong_wait); | |
1fa6aead | 1588 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { |
427e9708 KB |
1589 | if (bio_list_empty(&nvmeq->sq_cong)) |
1590 | add_wait_queue(&nvmeq->sq_full, | |
1591 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1592 | bio_list_add_head(&nvmeq->sq_cong, bio); |
1593 | break; | |
1594 | } | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | static int nvme_kthread(void *data) | |
1599 | { | |
1600 | struct nvme_dev *dev; | |
1601 | ||
1602 | while (!kthread_should_stop()) { | |
564a232c | 1603 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead MW |
1604 | spin_lock(&dev_list_lock); |
1605 | list_for_each_entry(dev, &dev_list, node) { | |
1606 | int i; | |
1607 | for (i = 0; i < dev->queue_count; i++) { | |
1608 | struct nvme_queue *nvmeq = dev->queues[i]; | |
740216fc MW |
1609 | if (!nvmeq) |
1610 | continue; | |
1fa6aead | 1611 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1612 | if (nvmeq->q_suspended) |
1613 | goto unlock; | |
bc57a0f7 | 1614 | nvme_process_cq(nvmeq); |
a09115b2 | 1615 | nvme_cancel_ios(nvmeq, true); |
1fa6aead | 1616 | nvme_resubmit_bios(nvmeq); |
22404274 | 1617 | unlock: |
1fa6aead MW |
1618 | spin_unlock_irq(&nvmeq->q_lock); |
1619 | } | |
1620 | } | |
1621 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1622 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1623 | } |
1624 | return 0; | |
1625 | } | |
1626 | ||
5aff9382 MW |
1627 | static DEFINE_IDA(nvme_index_ida); |
1628 | ||
1629 | static int nvme_get_ns_idx(void) | |
1630 | { | |
1631 | int index, error; | |
1632 | ||
1633 | do { | |
1634 | if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL)) | |
1635 | return -1; | |
1636 | ||
1637 | spin_lock(&dev_list_lock); | |
1638 | error = ida_get_new(&nvme_index_ida, &index); | |
1639 | spin_unlock(&dev_list_lock); | |
1640 | } while (error == -EAGAIN); | |
1641 | ||
1642 | if (error) | |
1643 | index = -1; | |
1644 | return index; | |
1645 | } | |
1646 | ||
1647 | static void nvme_put_ns_idx(int index) | |
1648 | { | |
1649 | spin_lock(&dev_list_lock); | |
1650 | ida_remove(&nvme_index_ida, index); | |
1651 | spin_unlock(&dev_list_lock); | |
1652 | } | |
1653 | ||
0e5e4f0e KB |
1654 | static void nvme_config_discard(struct nvme_ns *ns) |
1655 | { | |
1656 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1657 | ns->queue->limits.discard_zeroes_data = 0; | |
1658 | ns->queue->limits.discard_alignment = logical_block_size; | |
1659 | ns->queue->limits.discard_granularity = logical_block_size; | |
1660 | ns->queue->limits.max_discard_sectors = 0xffffffff; | |
1661 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); | |
1662 | } | |
1663 | ||
c3bfe717 | 1664 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid, |
b60503ba MW |
1665 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1666 | { | |
1667 | struct nvme_ns *ns; | |
1668 | struct gendisk *disk; | |
1669 | int lbaf; | |
1670 | ||
1671 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1672 | return NULL; | |
1673 | ||
1674 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1675 | if (!ns) | |
1676 | return NULL; | |
1677 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1678 | if (!ns->queue) | |
1679 | goto out_free_ns; | |
4eeb9215 MW |
1680 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT; |
1681 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); | |
1682 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
b60503ba MW |
1683 | blk_queue_make_request(ns->queue, nvme_make_request); |
1684 | ns->dev = dev; | |
1685 | ns->queue->queuedata = ns; | |
1686 | ||
1687 | disk = alloc_disk(NVME_MINORS); | |
1688 | if (!disk) | |
1689 | goto out_free_queue; | |
5aff9382 | 1690 | ns->ns_id = nsid; |
b60503ba MW |
1691 | ns->disk = disk; |
1692 | lbaf = id->flbas & 0xf; | |
1693 | ns->lba_shift = id->lbaf[lbaf].ds; | |
f410c680 | 1694 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
e9ef4636 | 1695 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
1696 | if (dev->max_hw_sectors) |
1697 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
b60503ba MW |
1698 | |
1699 | disk->major = nvme_major; | |
1700 | disk->minors = NVME_MINORS; | |
5aff9382 | 1701 | disk->first_minor = NVME_MINORS * nvme_get_ns_idx(); |
b60503ba MW |
1702 | disk->fops = &nvme_fops; |
1703 | disk->private_data = ns; | |
1704 | disk->queue = ns->queue; | |
388f037f | 1705 | disk->driverfs_dev = &dev->pci_dev->dev; |
5aff9382 | 1706 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1707 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1708 | ||
0e5e4f0e KB |
1709 | if (dev->oncs & NVME_CTRL_ONCS_DSM) |
1710 | nvme_config_discard(ns); | |
1711 | ||
b60503ba MW |
1712 | return ns; |
1713 | ||
1714 | out_free_queue: | |
1715 | blk_cleanup_queue(ns->queue); | |
1716 | out_free_ns: | |
1717 | kfree(ns); | |
1718 | return NULL; | |
1719 | } | |
1720 | ||
1721 | static void nvme_ns_free(struct nvme_ns *ns) | |
1722 | { | |
5aff9382 | 1723 | int index = ns->disk->first_minor / NVME_MINORS; |
b60503ba | 1724 | put_disk(ns->disk); |
5aff9382 | 1725 | nvme_put_ns_idx(index); |
b60503ba MW |
1726 | blk_cleanup_queue(ns->queue); |
1727 | kfree(ns); | |
1728 | } | |
1729 | ||
b3b06812 | 1730 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1731 | { |
1732 | int status; | |
1733 | u32 result; | |
b3b06812 | 1734 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1735 | |
df348139 | 1736 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 1737 | &result); |
b60503ba | 1738 | if (status) |
7e03b124 | 1739 | return status < 0 ? -EIO : -EBUSY; |
b60503ba MW |
1740 | return min(result & 0xffff, result >> 16) + 1; |
1741 | } | |
1742 | ||
9d713c2b KB |
1743 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1744 | { | |
1745 | return 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3)); | |
1746 | } | |
1747 | ||
8d85fce7 | 1748 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1749 | { |
fa08a396 | 1750 | struct pci_dev *pdev = dev->pci_dev; |
9d713c2b | 1751 | int result, cpu, i, vecs, nr_io_queues, size, q_depth; |
b60503ba | 1752 | |
b348b7d5 MW |
1753 | nr_io_queues = num_online_cpus(); |
1754 | result = set_queue_count(dev, nr_io_queues); | |
1b23484b MW |
1755 | if (result < 0) |
1756 | return result; | |
b348b7d5 MW |
1757 | if (result < nr_io_queues) |
1758 | nr_io_queues = result; | |
b60503ba | 1759 | |
9d713c2b KB |
1760 | size = db_bar_size(dev, nr_io_queues); |
1761 | if (size > 8192) { | |
f1938f6e | 1762 | iounmap(dev->bar); |
9d713c2b KB |
1763 | do { |
1764 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1765 | if (dev->bar) | |
1766 | break; | |
1767 | if (!--nr_io_queues) | |
1768 | return -ENOMEM; | |
1769 | size = db_bar_size(dev, nr_io_queues); | |
1770 | } while (1); | |
f1938f6e MW |
1771 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
1772 | dev->queues[0]->q_db = dev->dbs; | |
1773 | } | |
1774 | ||
9d713c2b KB |
1775 | /* Deregister the admin queue's interrupt */ |
1776 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1777 | ||
063a8096 MW |
1778 | vecs = nr_io_queues; |
1779 | for (i = 0; i < vecs; i++) | |
1b23484b MW |
1780 | dev->entry[i].entry = i; |
1781 | for (;;) { | |
063a8096 MW |
1782 | result = pci_enable_msix(pdev, dev->entry, vecs); |
1783 | if (result <= 0) | |
1b23484b | 1784 | break; |
063a8096 | 1785 | vecs = result; |
1b23484b MW |
1786 | } |
1787 | ||
063a8096 MW |
1788 | if (result < 0) { |
1789 | vecs = nr_io_queues; | |
1790 | if (vecs > 32) | |
1791 | vecs = 32; | |
fa08a396 | 1792 | for (;;) { |
063a8096 | 1793 | result = pci_enable_msi_block(pdev, vecs); |
fa08a396 | 1794 | if (result == 0) { |
063a8096 | 1795 | for (i = 0; i < vecs; i++) |
fa08a396 RRG |
1796 | dev->entry[i].vector = i + pdev->irq; |
1797 | break; | |
063a8096 MW |
1798 | } else if (result < 0) { |
1799 | vecs = 1; | |
fa08a396 RRG |
1800 | break; |
1801 | } | |
063a8096 | 1802 | vecs = result; |
fa08a396 RRG |
1803 | } |
1804 | } | |
1805 | ||
063a8096 MW |
1806 | /* |
1807 | * Should investigate if there's a performance win from allocating | |
1808 | * more queues than interrupt vectors; it might allow the submission | |
1809 | * path to scale better, even if the receive path is limited by the | |
1810 | * number of interrupts. | |
1811 | */ | |
1812 | nr_io_queues = vecs; | |
1813 | ||
1b23484b | 1814 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); |
9d713c2b KB |
1815 | if (result) { |
1816 | dev->queues[0]->q_suspended = 1; | |
22404274 | 1817 | goto free_queues; |
9d713c2b | 1818 | } |
1b23484b | 1819 | |
cd638946 KB |
1820 | /* Free previously allocated queues that are no longer usable */ |
1821 | spin_lock(&dev_list_lock); | |
1822 | for (i = dev->queue_count - 1; i > nr_io_queues; i--) { | |
1823 | struct nvme_queue *nvmeq = dev->queues[i]; | |
1824 | ||
1825 | spin_lock(&nvmeq->q_lock); | |
1826 | nvme_cancel_ios(nvmeq, false); | |
1827 | spin_unlock(&nvmeq->q_lock); | |
1828 | ||
1829 | nvme_free_queue(nvmeq); | |
1830 | dev->queue_count--; | |
1831 | dev->queues[i] = NULL; | |
1832 | } | |
1833 | spin_unlock(&dev_list_lock); | |
1834 | ||
1b23484b | 1835 | cpu = cpumask_first(cpu_online_mask); |
b348b7d5 | 1836 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1837 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); |
1838 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1839 | } | |
1840 | ||
a0cadb85 KB |
1841 | q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1, |
1842 | NVME_Q_DEPTH); | |
cd638946 | 1843 | for (i = dev->queue_count - 1; i < nr_io_queues; i++) { |
22404274 KB |
1844 | dev->queues[i + 1] = nvme_alloc_queue(dev, i + 1, q_depth, i); |
1845 | if (!dev->queues[i + 1]) { | |
1846 | result = -ENOMEM; | |
1847 | goto free_queues; | |
1848 | } | |
1b23484b | 1849 | } |
b60503ba | 1850 | |
9ecdc946 MW |
1851 | for (; i < num_possible_cpus(); i++) { |
1852 | int target = i % rounddown_pow_of_two(dev->queue_count - 1); | |
1853 | dev->queues[i + 1] = dev->queues[target + 1]; | |
1854 | } | |
1855 | ||
22404274 KB |
1856 | for (i = 1; i < dev->queue_count; i++) { |
1857 | result = nvme_create_queue(dev->queues[i], i); | |
1858 | if (result) { | |
1859 | for (--i; i > 0; i--) | |
1860 | nvme_disable_queue(dev, i); | |
1861 | goto free_queues; | |
1862 | } | |
1863 | } | |
b60503ba | 1864 | |
22404274 | 1865 | return 0; |
b60503ba | 1866 | |
22404274 KB |
1867 | free_queues: |
1868 | nvme_free_queues(dev); | |
1869 | return result; | |
b60503ba MW |
1870 | } |
1871 | ||
422ef0c7 MW |
1872 | /* |
1873 | * Return: error value if an error occurred setting up the queues or calling | |
1874 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1875 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1876 | * failures should be reported. | |
1877 | */ | |
8d85fce7 | 1878 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1879 | { |
c3bfe717 MW |
1880 | int res; |
1881 | unsigned nn, i; | |
cbb6218f | 1882 | struct nvme_ns *ns; |
51814232 | 1883 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 MW |
1884 | struct nvme_id_ns *id_ns; |
1885 | void *mem; | |
b60503ba | 1886 | dma_addr_t dma_addr; |
159b67d7 | 1887 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; |
b60503ba | 1888 | |
bc5fc7e4 | 1889 | mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, |
b60503ba | 1890 | GFP_KERNEL); |
a9ef4343 KB |
1891 | if (!mem) |
1892 | return -ENOMEM; | |
b60503ba | 1893 | |
bc5fc7e4 | 1894 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba MW |
1895 | if (res) { |
1896 | res = -EIO; | |
cbb6218f | 1897 | goto out; |
b60503ba MW |
1898 | } |
1899 | ||
bc5fc7e4 | 1900 | ctrl = mem; |
51814232 | 1901 | nn = le32_to_cpup(&ctrl->nn); |
0e5e4f0e | 1902 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
51814232 MW |
1903 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
1904 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1905 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 1906 | if (ctrl->mdts) |
8fc23e03 | 1907 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
159b67d7 KB |
1908 | if ((dev->pci_dev->vendor == PCI_VENDOR_ID_INTEL) && |
1909 | (dev->pci_dev->device == 0x0953) && ctrl->vs[3]) | |
1910 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); | |
b60503ba | 1911 | |
bc5fc7e4 | 1912 | id_ns = mem; |
2b2c1896 | 1913 | for (i = 1; i <= nn; i++) { |
bc5fc7e4 | 1914 | res = nvme_identify(dev, i, 0, dma_addr); |
b60503ba MW |
1915 | if (res) |
1916 | continue; | |
1917 | ||
bc5fc7e4 | 1918 | if (id_ns->ncap == 0) |
b60503ba MW |
1919 | continue; |
1920 | ||
bc5fc7e4 | 1921 | res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i, |
08df1e05 | 1922 | dma_addr + 4096, NULL); |
b60503ba | 1923 | if (res) |
12209036 | 1924 | memset(mem + 4096, 0, 4096); |
b60503ba | 1925 | |
bc5fc7e4 | 1926 | ns = nvme_alloc_ns(dev, i, mem, mem + 4096); |
b60503ba MW |
1927 | if (ns) |
1928 | list_add_tail(&ns->list, &dev->namespaces); | |
1929 | } | |
1930 | list_for_each_entry(ns, &dev->namespaces, list) | |
1931 | add_disk(ns->disk); | |
422ef0c7 | 1932 | res = 0; |
b60503ba | 1933 | |
bc5fc7e4 | 1934 | out: |
684f5c20 | 1935 | dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr); |
b60503ba MW |
1936 | return res; |
1937 | } | |
1938 | ||
0877cb0d KB |
1939 | static int nvme_dev_map(struct nvme_dev *dev) |
1940 | { | |
1941 | int bars, result = -ENOMEM; | |
1942 | struct pci_dev *pdev = dev->pci_dev; | |
1943 | ||
1944 | if (pci_enable_device_mem(pdev)) | |
1945 | return result; | |
1946 | ||
1947 | dev->entry[0].vector = pdev->irq; | |
1948 | pci_set_master(pdev); | |
1949 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
1950 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1951 | goto disable_pci; | |
1952 | ||
052d0efa RK |
1953 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) && |
1954 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) | |
1955 | goto disable; | |
0877cb0d KB |
1956 | |
1957 | pci_set_drvdata(pdev, dev); | |
1958 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1959 | if (!dev->bar) | |
1960 | goto disable; | |
1961 | ||
1962 | dev->db_stride = NVME_CAP_STRIDE(readq(&dev->bar->cap)); | |
1963 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
1964 | ||
1965 | return 0; | |
1966 | ||
1967 | disable: | |
1968 | pci_release_regions(pdev); | |
1969 | disable_pci: | |
1970 | pci_disable_device(pdev); | |
1971 | return result; | |
1972 | } | |
1973 | ||
1974 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1975 | { | |
1976 | if (dev->pci_dev->msi_enabled) | |
1977 | pci_disable_msi(dev->pci_dev); | |
1978 | else if (dev->pci_dev->msix_enabled) | |
1979 | pci_disable_msix(dev->pci_dev); | |
1980 | ||
1981 | if (dev->bar) { | |
1982 | iounmap(dev->bar); | |
1983 | dev->bar = NULL; | |
1984 | } | |
1985 | ||
1986 | pci_release_regions(dev->pci_dev); | |
1987 | if (pci_is_enabled(dev->pci_dev)) | |
1988 | pci_disable_device(dev->pci_dev); | |
1989 | } | |
1990 | ||
f0b50732 | 1991 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 1992 | { |
22404274 KB |
1993 | int i; |
1994 | ||
1995 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1996 | nvme_disable_queue(dev, i); | |
b60503ba | 1997 | |
1fa6aead | 1998 | spin_lock(&dev_list_lock); |
f0b50732 | 1999 | list_del_init(&dev->node); |
1fa6aead MW |
2000 | spin_unlock(&dev_list_lock); |
2001 | ||
1894d8f1 KB |
2002 | if (dev->bar) |
2003 | nvme_shutdown_ctrl(dev); | |
f0b50732 KB |
2004 | nvme_dev_unmap(dev); |
2005 | } | |
2006 | ||
2007 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2008 | { | |
2009 | struct nvme_ns *ns, *next; | |
2010 | ||
b60503ba MW |
2011 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { |
2012 | list_del(&ns->list); | |
2013 | del_gendisk(ns->disk); | |
2014 | nvme_ns_free(ns); | |
2015 | } | |
b60503ba MW |
2016 | } |
2017 | ||
091b6092 MW |
2018 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2019 | { | |
2020 | struct device *dmadev = &dev->pci_dev->dev; | |
2021 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
2022 | PAGE_SIZE, PAGE_SIZE, 0); | |
2023 | if (!dev->prp_page_pool) | |
2024 | return -ENOMEM; | |
2025 | ||
99802a7a MW |
2026 | /* Optimisation for I/Os between 4k and 128k */ |
2027 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
2028 | 256, 256, 0); | |
2029 | if (!dev->prp_small_pool) { | |
2030 | dma_pool_destroy(dev->prp_page_pool); | |
2031 | return -ENOMEM; | |
2032 | } | |
091b6092 MW |
2033 | return 0; |
2034 | } | |
2035 | ||
2036 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2037 | { | |
2038 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2039 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2040 | } |
2041 | ||
cd58ad7d QSA |
2042 | static DEFINE_IDA(nvme_instance_ida); |
2043 | ||
2044 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2045 | { |
cd58ad7d QSA |
2046 | int instance, error; |
2047 | ||
2048 | do { | |
2049 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2050 | return -ENODEV; | |
2051 | ||
2052 | spin_lock(&dev_list_lock); | |
2053 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2054 | spin_unlock(&dev_list_lock); | |
2055 | } while (error == -EAGAIN); | |
2056 | ||
2057 | if (error) | |
2058 | return -ENODEV; | |
2059 | ||
2060 | dev->instance = instance; | |
2061 | return 0; | |
b60503ba MW |
2062 | } |
2063 | ||
2064 | static void nvme_release_instance(struct nvme_dev *dev) | |
2065 | { | |
cd58ad7d QSA |
2066 | spin_lock(&dev_list_lock); |
2067 | ida_remove(&nvme_instance_ida, dev->instance); | |
2068 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
2069 | } |
2070 | ||
5e82e952 KB |
2071 | static void nvme_free_dev(struct kref *kref) |
2072 | { | |
2073 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
2074 | nvme_dev_remove(dev); | |
f0b50732 KB |
2075 | nvme_dev_shutdown(dev); |
2076 | nvme_free_queues(dev); | |
5e82e952 KB |
2077 | nvme_release_instance(dev); |
2078 | nvme_release_prp_pools(dev); | |
5e82e952 KB |
2079 | kfree(dev->queues); |
2080 | kfree(dev->entry); | |
2081 | kfree(dev); | |
2082 | } | |
2083 | ||
2084 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2085 | { | |
2086 | struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev, | |
2087 | miscdev); | |
2088 | kref_get(&dev->kref); | |
2089 | f->private_data = dev; | |
2090 | return 0; | |
2091 | } | |
2092 | ||
2093 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2094 | { | |
2095 | struct nvme_dev *dev = f->private_data; | |
2096 | kref_put(&dev->kref, nvme_free_dev); | |
2097 | return 0; | |
2098 | } | |
2099 | ||
2100 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2101 | { | |
2102 | struct nvme_dev *dev = f->private_data; | |
2103 | switch (cmd) { | |
2104 | case NVME_IOCTL_ADMIN_CMD: | |
2105 | return nvme_user_admin_cmd(dev, (void __user *)arg); | |
2106 | default: | |
2107 | return -ENOTTY; | |
2108 | } | |
2109 | } | |
2110 | ||
2111 | static const struct file_operations nvme_dev_fops = { | |
2112 | .owner = THIS_MODULE, | |
2113 | .open = nvme_dev_open, | |
2114 | .release = nvme_dev_release, | |
2115 | .unlocked_ioctl = nvme_dev_ioctl, | |
2116 | .compat_ioctl = nvme_dev_ioctl, | |
2117 | }; | |
2118 | ||
f0b50732 KB |
2119 | static int nvme_dev_start(struct nvme_dev *dev) |
2120 | { | |
2121 | int result; | |
2122 | ||
2123 | result = nvme_dev_map(dev); | |
2124 | if (result) | |
2125 | return result; | |
2126 | ||
2127 | result = nvme_configure_admin_queue(dev); | |
2128 | if (result) | |
2129 | goto unmap; | |
2130 | ||
2131 | spin_lock(&dev_list_lock); | |
2132 | list_add(&dev->node, &dev_list); | |
2133 | spin_unlock(&dev_list_lock); | |
2134 | ||
2135 | result = nvme_setup_io_queues(dev); | |
d82e8bfd | 2136 | if (result && result != -EBUSY) |
f0b50732 KB |
2137 | goto disable; |
2138 | ||
d82e8bfd | 2139 | return result; |
f0b50732 KB |
2140 | |
2141 | disable: | |
2142 | spin_lock(&dev_list_lock); | |
2143 | list_del_init(&dev->node); | |
2144 | spin_unlock(&dev_list_lock); | |
2145 | unmap: | |
2146 | nvme_dev_unmap(dev); | |
2147 | return result; | |
2148 | } | |
2149 | ||
8d85fce7 | 2150 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2151 | { |
0877cb0d | 2152 | int result = -ENOMEM; |
b60503ba MW |
2153 | struct nvme_dev *dev; |
2154 | ||
2155 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
2156 | if (!dev) | |
2157 | return -ENOMEM; | |
2158 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
2159 | GFP_KERNEL); | |
2160 | if (!dev->entry) | |
2161 | goto free; | |
1b23484b MW |
2162 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
2163 | GFP_KERNEL); | |
b60503ba MW |
2164 | if (!dev->queues) |
2165 | goto free; | |
2166 | ||
2167 | INIT_LIST_HEAD(&dev->namespaces); | |
2168 | dev->pci_dev = pdev; | |
052d0efa | 2169 | |
cd58ad7d QSA |
2170 | result = nvme_set_instance(dev); |
2171 | if (result) | |
0877cb0d | 2172 | goto free; |
b60503ba | 2173 | |
091b6092 MW |
2174 | result = nvme_setup_prp_pools(dev); |
2175 | if (result) | |
0877cb0d | 2176 | goto release; |
091b6092 | 2177 | |
f0b50732 | 2178 | result = nvme_dev_start(dev); |
d82e8bfd KB |
2179 | if (result) { |
2180 | if (result == -EBUSY) | |
2181 | goto create_cdev; | |
0877cb0d | 2182 | goto release_pools; |
d82e8bfd | 2183 | } |
b60503ba | 2184 | |
740216fc | 2185 | result = nvme_dev_add(dev); |
d82e8bfd | 2186 | if (result) |
f0b50732 | 2187 | goto shutdown; |
740216fc | 2188 | |
d82e8bfd | 2189 | create_cdev: |
5e82e952 KB |
2190 | scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance); |
2191 | dev->miscdev.minor = MISC_DYNAMIC_MINOR; | |
2192 | dev->miscdev.parent = &pdev->dev; | |
2193 | dev->miscdev.name = dev->name; | |
2194 | dev->miscdev.fops = &nvme_dev_fops; | |
2195 | result = misc_register(&dev->miscdev); | |
2196 | if (result) | |
2197 | goto remove; | |
2198 | ||
2199 | kref_init(&dev->kref); | |
b60503ba MW |
2200 | return 0; |
2201 | ||
5e82e952 KB |
2202 | remove: |
2203 | nvme_dev_remove(dev); | |
f0b50732 KB |
2204 | shutdown: |
2205 | nvme_dev_shutdown(dev); | |
0877cb0d | 2206 | release_pools: |
f0b50732 | 2207 | nvme_free_queues(dev); |
091b6092 | 2208 | nvme_release_prp_pools(dev); |
0877cb0d KB |
2209 | release: |
2210 | nvme_release_instance(dev); | |
b60503ba MW |
2211 | free: |
2212 | kfree(dev->queues); | |
2213 | kfree(dev->entry); | |
2214 | kfree(dev); | |
2215 | return result; | |
2216 | } | |
2217 | ||
8d85fce7 | 2218 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2219 | { |
2220 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
5e82e952 KB |
2221 | misc_deregister(&dev->miscdev); |
2222 | kref_put(&dev->kref, nvme_free_dev); | |
b60503ba MW |
2223 | } |
2224 | ||
2225 | /* These functions are yet to be implemented */ | |
2226 | #define nvme_error_detected NULL | |
2227 | #define nvme_dump_registers NULL | |
2228 | #define nvme_link_reset NULL | |
2229 | #define nvme_slot_reset NULL | |
2230 | #define nvme_error_resume NULL | |
cd638946 KB |
2231 | |
2232 | static int nvme_suspend(struct device *dev) | |
2233 | { | |
2234 | struct pci_dev *pdev = to_pci_dev(dev); | |
2235 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2236 | ||
2237 | nvme_dev_shutdown(ndev); | |
2238 | return 0; | |
2239 | } | |
2240 | ||
2241 | static int nvme_resume(struct device *dev) | |
2242 | { | |
2243 | struct pci_dev *pdev = to_pci_dev(dev); | |
2244 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2245 | int ret; | |
2246 | ||
2247 | ret = nvme_dev_start(ndev); | |
2248 | /* XXX: should remove gendisks if resume fails */ | |
2249 | if (ret) | |
2250 | nvme_free_queues(ndev); | |
2251 | return ret; | |
2252 | } | |
2253 | ||
2254 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2255 | |
1d352035 | 2256 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2257 | .error_detected = nvme_error_detected, |
2258 | .mmio_enabled = nvme_dump_registers, | |
2259 | .link_reset = nvme_link_reset, | |
2260 | .slot_reset = nvme_slot_reset, | |
2261 | .resume = nvme_error_resume, | |
2262 | }; | |
2263 | ||
2264 | /* Move to pci_ids.h later */ | |
2265 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2266 | ||
2267 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
2268 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
2269 | { 0, } | |
2270 | }; | |
2271 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2272 | ||
2273 | static struct pci_driver nvme_driver = { | |
2274 | .name = "nvme", | |
2275 | .id_table = nvme_id_table, | |
2276 | .probe = nvme_probe, | |
8d85fce7 | 2277 | .remove = nvme_remove, |
cd638946 KB |
2278 | .driver = { |
2279 | .pm = &nvme_dev_pm_ops, | |
2280 | }, | |
b60503ba MW |
2281 | .err_handler = &nvme_err_handler, |
2282 | }; | |
2283 | ||
2284 | static int __init nvme_init(void) | |
2285 | { | |
0ac13140 | 2286 | int result; |
1fa6aead MW |
2287 | |
2288 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
2289 | if (IS_ERR(nvme_thread)) | |
2290 | return PTR_ERR(nvme_thread); | |
b60503ba | 2291 | |
5c42ea16 KB |
2292 | result = register_blkdev(nvme_major, "nvme"); |
2293 | if (result < 0) | |
1fa6aead | 2294 | goto kill_kthread; |
5c42ea16 | 2295 | else if (result > 0) |
0ac13140 | 2296 | nvme_major = result; |
b60503ba MW |
2297 | |
2298 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
2299 | if (result) |
2300 | goto unregister_blkdev; | |
2301 | return 0; | |
b60503ba | 2302 | |
1fa6aead | 2303 | unregister_blkdev: |
b60503ba | 2304 | unregister_blkdev(nvme_major, "nvme"); |
1fa6aead MW |
2305 | kill_kthread: |
2306 | kthread_stop(nvme_thread); | |
b60503ba MW |
2307 | return result; |
2308 | } | |
2309 | ||
2310 | static void __exit nvme_exit(void) | |
2311 | { | |
2312 | pci_unregister_driver(&nvme_driver); | |
2313 | unregister_blkdev(nvme_major, "nvme"); | |
1fa6aead | 2314 | kthread_stop(nvme_thread); |
b60503ba MW |
2315 | } |
2316 | ||
2317 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2318 | MODULE_LICENSE("GPL"); | |
366e8217 | 2319 | MODULE_VERSION("0.8"); |
b60503ba MW |
2320 | module_init(nvme_init); |
2321 | module_exit(nvme_exit); |