[deliverable/linux.git] / drivers / bus / brcmstb_gisb.c

/*
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/io.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/bitops.h>

#ifdef CONFIG_ARM
#include <asm/bug.h>
#include <asm/signal.h>
#endif

#define  ARB_ERR_CAP_CLEAR		(1 << 0)
#define  ARB_ERR_CAP_STATUS_TIMEOUT	(1 << 12)
#define  ARB_ERR_CAP_STATUS_TEA		(1 << 11)
#define  ARB_ERR_CAP_STATUS_BS_SHIFT	(1 << 2)
#define  ARB_ERR_CAP_STATUS_BS_MASK	0x3c
#define  ARB_ERR_CAP_STATUS_WRITE	(1 << 1)
#define  ARB_ERR_CAP_STATUS_VALID	(1 << 0)

enum {
	ARB_TIMER,
	ARB_ERR_CAP_CLR,
	ARB_ERR_CAP_HI_ADDR,
	ARB_ERR_CAP_ADDR,
	ARB_ERR_CAP_DATA,
	ARB_ERR_CAP_STATUS,
	ARB_ERR_CAP_MASTER,
};

static const int gisb_offsets_bcm7445[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_ERR_CAP_CLR]	= 0x7e4,
	[ARB_ERR_CAP_HI_ADDR]	= 0x7e8,
	[ARB_ERR_CAP_ADDR]	= 0x7ec,
	[ARB_ERR_CAP_DATA]	= 0x7f0,
	[ARB_ERR_CAP_STATUS]	= 0x7f4,
	[ARB_ERR_CAP_MASTER]	= 0x7f8,
};

struct brcmstb_gisb_arb_device {
	void __iomem	*base;
	const int	*gisb_offsets;
	struct mutex	lock;
	struct list_head next;
	u32 valid_mask;
	const char *master_names[sizeof(u32) * BITS_PER_BYTE];
};

static LIST_HEAD(brcmstb_gisb_arb_device_list);

static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
	if (offset == -1)
		return 1;

	return ioread32(gdev->base + offset);
}

static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	if (offset == -1)
		return;
	iowrite32(val, gdev->base + reg);
}

static ssize_t gisb_arb_get_timeout(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
	u32 timeout;

	mutex_lock(&gdev->lock);
	timeout = gisb_read(gdev, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return sprintf(buf, "%d", timeout);
}

static ssize_t gisb_arb_set_timeout(struct device *dev,
				    struct device_attribute *attr,
				    const char *buf, size_t count)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
	int val, ret;

	ret = kstrtoint(buf, 10, &val);
	if (ret < 0)
		return ret;

	if (val == 0 || val >= 0xffffffff)
		return -EINVAL;

	mutex_lock(&gdev->lock);
	gisb_write(gdev, val, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return count;
}

static const char *
brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
						u32 masters)
{
	u32 mask = gdev->valid_mask & masters;

	if (hweight_long(mask) != 1)
		return NULL;

	return gdev->master_names[ffs(mask) - 1];
}

static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
					const char *reason)
{
	u32 cap_status;
	unsigned long arb_addr;
	u32 master;
	const char *m_name;
	char m_fmt[11];

	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);

	/* Invalid captured address, bail out */
	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
		return 1;

	/* Read the address and master */
	arb_addr = gisb_read(gdev, ARB_ERR_CAP_ADDR) & 0xffffffff;
#if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
	arb_addr |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
#endif
	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);

	m_name = brcmstb_gisb_master_to_str(gdev, master);
	if (!m_name) {
		snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
		m_name = m_fmt;
	}

	pr_crit("%s: %s at 0x%lx [%c %s], core: %s\n",
		__func__, reason, arb_addr,
		cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
		cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
		m_name);

	/* clear the GISB error */
	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);

	return 0;
}

#ifdef CONFIG_ARM
static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
				     struct pt_regs *regs)
{
	int ret = 0;
	struct brcmstb_gisb_arb_device *gdev;

	/* iterate over each GISB arb registered handlers */
	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
		ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	/*
	 * If it was an imprecise abort, then we need to correct the
	 * return address to be _after_ the instruction.
	*/
	if (fsr & (1 << 10))
		regs->ARM_pc += 4;

	return ret;
}

void __init brcmstb_hook_fault_code(void)
{
	hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
			"imprecise external abort");
}
#endif

static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");

	return IRQ_HANDLED;
}

static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");

	return IRQ_HANDLED;
}

static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
		gisb_arb_get_timeout, gisb_arb_set_timeout);

static struct attribute *gisb_arb_sysfs_attrs[] = {
	&dev_attr_gisb_arb_timeout.attr,
	NULL,
};

static struct attribute_group gisb_arb_sysfs_attr_group = {
	.attrs = gisb_arb_sysfs_attrs,
};

static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
{
	struct device_node *dn = pdev->dev.of_node;
	struct brcmstb_gisb_arb_device *gdev;
	struct resource *r;
	int err, timeout_irq, tea_irq;
	unsigned int num_masters, j = 0;
	int i, first, last;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	timeout_irq = platform_get_irq(pdev, 0);
	tea_irq = platform_get_irq(pdev, 1);

	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	if (!gdev)
		return -ENOMEM;

	mutex_init(&gdev->lock);
	INIT_LIST_HEAD(&gdev->next);

	gdev->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(gdev->base))
		return PTR_ERR(gdev->base);

	gdev->gisb_offsets = gisb_offsets_bcm7445;

	err = devm_request_irq(&pdev->dev, timeout_irq,
				brcmstb_gisb_timeout_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	err = devm_request_irq(&pdev->dev, tea_irq,
				brcmstb_gisb_tea_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	/* If we do not have a valid mask, assume all masters are enabled */
	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
				&gdev->valid_mask))
		gdev->valid_mask = 0xffffffff;

	/* Proceed with reading the litteral names if we agree on the
	 * number of masters
	 */
	num_masters = of_property_count_strings(dn,
			"brcm,gisb-arb-master-names");
	if (hweight_long(gdev->valid_mask) == num_masters) {
		first = ffs(gdev->valid_mask) - 1;
		last = fls(gdev->valid_mask) - 1;

		for (i = first; i < last; i++) {
			if (!(gdev->valid_mask & BIT(i)))
				continue;

			of_property_read_string_index(dn,
					"brcm,gisb-arb-master-names", j,
					&gdev->master_names[i]);
			j++;
		}
	}

	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	if (err)
		return err;

	platform_set_drvdata(pdev, gdev);

	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);

	dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
			gdev->base, timeout_irq, tea_irq);

	return 0;
}

static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	{ .compatible = "brcm,gisb-arb" },
	{ },
};

static struct platform_driver brcmstb_gisb_arb_driver = {
	.probe	= brcmstb_gisb_arb_probe,
	.driver = {
		.name	= "brcm-gisb-arb",
		.owner	= THIS_MODULE,
		.of_match_table = brcmstb_gisb_arb_of_match,
	},
};

static int __init brcm_gisb_driver_init(void)
{
	return platform_driver_register(&brcmstb_gisb_arb_driver);
}

module_init(brcm_gisb_driver_init);
Commit	Line	Data
44127b77 FF	1	/*
	2	* Copyright (C) 2014 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/types.h>
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/sysfs.h>
	20	#include <linux/io.h>
	21	#include <linux/string.h>
	22	#include <linux/device.h>
	23	#include <linux/list.h>
	24	#include <linux/of.h>
	25	#include <linux/bitops.h>
	26
dd1d78a1	27	#ifdef CONFIG_ARM
44127b77 FF	28	#include <asm/bug.h>
44127b77 FF	29	#include <asm/signal.h>
dd1d78a1	30	#endif
44127b77	31
44127b77	32	#define ARB_ERR_CAP_CLEAR (1 << 0)
44127b77 FF	33	#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
	34	#define ARB_ERR_CAP_STATUS_TEA (1 << 11)
	35	#define ARB_ERR_CAP_STATUS_BS_SHIFT (1 << 2)
	36	#define ARB_ERR_CAP_STATUS_BS_MASK 0x3c
	37	#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
	38	#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
f8083587 KC	39
	40	enum {
	41	ARB_TIMER,
	42	ARB_ERR_CAP_CLR,
	43	ARB_ERR_CAP_HI_ADDR,
	44	ARB_ERR_CAP_ADDR,
	45	ARB_ERR_CAP_DATA,
	46	ARB_ERR_CAP_STATUS,
	47	ARB_ERR_CAP_MASTER,
	48	};
	49
	50	static const int gisb_offsets_bcm7445[] = {
	51	[ARB_TIMER] = 0x008,
	52	[ARB_ERR_CAP_CLR] = 0x7e4,
	53	[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
	54	[ARB_ERR_CAP_ADDR] = 0x7ec,
	55	[ARB_ERR_CAP_DATA] = 0x7f0,
	56	[ARB_ERR_CAP_STATUS] = 0x7f4,
	57	[ARB_ERR_CAP_MASTER] = 0x7f8,
	58	};
44127b77 FF	59
	60	struct brcmstb_gisb_arb_device {
	61	void __iomem *base;
f8083587	62	const int *gisb_offsets;
44127b77 FF	63	struct mutex lock;
	64	struct list_head next;
	65	u32 valid_mask;
	66	const char master_names[sizeof(u32) BITS_PER_BYTE];
	67	};
	68
	69	static LIST_HEAD(brcmstb_gisb_arb_device_list);
	70
2b53eadc KC	71	static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
2b53eadc KC	72	{
f8083587 KC	73	int offset = gdev->gisb_offsets[reg];
	74
	75	/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
	76	if (offset == -1)
	77	return 1;
	78
	79	return ioread32(gdev->base + offset);
2b53eadc KC	80	}
	81
	82	static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
	83	{
f8083587 KC	84	int offset = gdev->gisb_offsets[reg];
	85
	86	if (offset == -1)
	87	return;
2b53eadc KC	88	iowrite32(val, gdev->base + reg);
	89	}
	90
44127b77 FF	91	static ssize_t gisb_arb_get_timeout(struct device *dev,
	92	struct device_attribute *attr,
	93	char *buf)
	94	{
	95	struct platform_device *pdev = to_platform_device(dev);
	96	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
	97	u32 timeout;
	98
	99	mutex_lock(&gdev->lock);
2b53eadc	100	timeout = gisb_read(gdev, ARB_TIMER);
44127b77 FF	101	mutex_unlock(&gdev->lock);
	102
	103	return sprintf(buf, "%d", timeout);
	104	}
	105
	106	static ssize_t gisb_arb_set_timeout(struct device *dev,
	107	struct device_attribute *attr,
	108	const char *buf, size_t count)
	109	{
	110	struct platform_device *pdev = to_platform_device(dev);
	111	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
	112	int val, ret;
	113
	114	ret = kstrtoint(buf, 10, &val);
	115	if (ret < 0)
	116	return ret;
	117
	118	if (val == 0 \|\| val >= 0xffffffff)
	119	return -EINVAL;
	120
	121	mutex_lock(&gdev->lock);
2b53eadc	122	gisb_write(gdev, val, ARB_TIMER);
44127b77 FF	123	mutex_unlock(&gdev->lock);
	124
	125	return count;
	126	}
	127
	128	static const char *
	129	brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
	130	u32 masters)
	131	{
	132	u32 mask = gdev->valid_mask & masters;
	133
	134	if (hweight_long(mask) != 1)
	135	return NULL;
	136
	137	return gdev->master_names[ffs(mask) - 1];
	138	}
	139
	140	static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
	141	const char *reason)
	142	{
	143	u32 cap_status;
	144	unsigned long arb_addr;
	145	u32 master;
	146	const char *m_name;
	147	char m_fmt[11];
	148
2b53eadc	149	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
44127b77 FF	150
	151	/* Invalid captured address, bail out */
	152	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
	153	return 1;
	154
	155	/* Read the address and master */
2b53eadc	156	arb_addr = gisb_read(gdev, ARB_ERR_CAP_ADDR) & 0xffffffff;
44127b77	157	#if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
2b53eadc	158	arb_addr \|= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
44127b77	159	#endif
2b53eadc	160	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
44127b77 FF	161
	162	m_name = brcmstb_gisb_master_to_str(gdev, master);
	163	if (!m_name) {
	164	snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
	165	m_name = m_fmt;
	166	}
	167
	168	pr_crit("%s: %s at 0x%lx [%c %s], core: %s\n",
	169	__func__, reason, arb_addr,
	170	cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
	171	cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
	172	m_name);
	173
	174	/* clear the GISB error */
2b53eadc	175	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
44127b77 FF	176
	177	return 0;
	178	}
	179
dd1d78a1	180	#ifdef CONFIG_ARM
44127b77 FF	181	static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
	182	struct pt_regs *regs)
	183	{
	184	int ret = 0;
	185	struct brcmstb_gisb_arb_device *gdev;
	186
	187	/* iterate over each GISB arb registered handlers */
	188	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
	189	ret \|= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	190	/*
	191	* If it was an imprecise abort, then we need to correct the
	192	* return address to be _after_ the instruction.
	193	*/
	194	if (fsr & (1 << 10))
	195	regs->ARM_pc += 4;
	196
	197	return ret;
	198	}
	199
	200	void __init brcmstb_hook_fault_code(void)
	201	{
	202	hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
	203	"imprecise external abort");
	204	}
dd1d78a1	205	#endif
44127b77 FF	206
	207	static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
	208	{
	209	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
	210
	211	return IRQ_HANDLED;
	212	}
	213
	214	static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
	215	{
	216	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");
	217
	218	return IRQ_HANDLED;
	219	}
	220
	221	static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR \| S_IRUGO,
	222	gisb_arb_get_timeout, gisb_arb_set_timeout);
	223
	224	static struct attribute *gisb_arb_sysfs_attrs[] = {
	225	&dev_attr_gisb_arb_timeout.attr,
	226	NULL,
	227	};
	228
	229	static struct attribute_group gisb_arb_sysfs_attr_group = {
	230	.attrs = gisb_arb_sysfs_attrs,
	231	};
	232
	233	static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
	234	{
	235	struct device_node *dn = pdev->dev.of_node;
	236	struct brcmstb_gisb_arb_device *gdev;
	237	struct resource *r;
	238	int err, timeout_irq, tea_irq;
	239	unsigned int num_masters, j = 0;
	240	int i, first, last;
	241
	242	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	243	timeout_irq = platform_get_irq(pdev, 0);
	244	tea_irq = platform_get_irq(pdev, 1);
	245
	246	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	247	if (!gdev)
	248	return -ENOMEM;
	249
	250	mutex_init(&gdev->lock);
	251	INIT_LIST_HEAD(&gdev->next);
	252
c9d53c0f JH	253	gdev->base = devm_ioremap_resource(&pdev->dev, r);
	254	if (IS_ERR(gdev->base))
	255	return PTR_ERR(gdev->base);
44127b77	256
f8083587 KC	257	gdev->gisb_offsets = gisb_offsets_bcm7445;
f8083587 KC	258
44127b77 FF	259	err = devm_request_irq(&pdev->dev, timeout_irq,
	260	brcmstb_gisb_timeout_handler, 0, pdev->name,
	261	gdev);
	262	if (err < 0)
	263	return err;
	264
	265	err = devm_request_irq(&pdev->dev, tea_irq,
	266	brcmstb_gisb_tea_handler, 0, pdev->name,
	267	gdev);
	268	if (err < 0)
	269	return err;
	270
	271	/* If we do not have a valid mask, assume all masters are enabled */
	272	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
	273	&gdev->valid_mask))
	274	gdev->valid_mask = 0xffffffff;
	275
	276	/* Proceed with reading the litteral names if we agree on the
	277	* number of masters
	278	*/
	279	num_masters = of_property_count_strings(dn,
	280	"brcm,gisb-arb-master-names");
	281	if (hweight_long(gdev->valid_mask) == num_masters) {
	282	first = ffs(gdev->valid_mask) - 1;
	283	last = fls(gdev->valid_mask) - 1;
	284
	285	for (i = first; i < last; i++) {
	286	if (!(gdev->valid_mask & BIT(i)))
	287	continue;
	288
	289	of_property_read_string_index(dn,
	290	"brcm,gisb-arb-master-names", j,
	291	&gdev->master_names[i]);
	292	j++;
	293	}
	294	}
	295
	296	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	297	if (err)
	298	return err;
	299
	300	platform_set_drvdata(pdev, gdev);
	301
	302	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
	303
	304	dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
	305	gdev->base, timeout_irq, tea_irq);
	306
	307	return 0;
	308	}
	309
	310	static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	311	{ .compatible = "brcm,gisb-arb" },
	312	{ },
	313	};
	314
	315	static struct platform_driver brcmstb_gisb_arb_driver = {
	316	.probe = brcmstb_gisb_arb_probe,
	317	.driver = {
	318	.name = "brcm-gisb-arb",
	319	.owner = THIS_MODULE,
	320	.of_match_table = brcmstb_gisb_arb_of_match,
	321	},
	322	};
323
324	static int __init brcm_gisb_driver_init(void)
325	{
326	return platform_driver_register(&brcmstb_gisb_arb_driver);
327	}
328
329	module_init(brcm_gisb_driver_init);