[deliverable/linux.git] / drivers / bus / omap_l3_noc.c

/*
 * OMAP4XXX L3 Interconnect error handling driver
 *
 * Copyright (C) 2011 Texas Corporation
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *	Sricharan <r.sricharan@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/slab.h>

#include "soc.h"
#include "omap_l3_noc.h"

/*
 * Interrupt Handler for L3 error detection.
 *	1) Identify the L3 clockdomain partition to which the error belongs to.
 *	2) Identify the slave where the error information is logged
 *	3) Print the logged information.
 *	4) Add dump stack to provide kernel trace.
 *
 * Two Types of errors :
 *	1) Custom errors in L3 :
 *		Target like DMM/FW/EMIF generates SRESP=ERR error
 *	2) Standard L3 error:
 *		- Unsupported CMD.
 *			L3 tries to access target while it is idle
 *		- OCP disconnect.
 *		- Address hole error:
 *			If DSS/ISS/FDIF/USBHOSTFS access a target where they
 *			do not have connectivity, the error is logged in
 *			their default target which is DMM2.
 *
 *	On High Secure devices, firewall errors are possible and those
 *	can be trapped as well. But the trapping is implemented as part
 *	secure software and hence need not be implemented here.
 */
static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
{

	struct omap4_l3 *l3 = _l3;
	int inttype, i, k;
	int err_src = 0;
	u32 std_err_main, err_reg, clear, masterid;
	void __iomem *base, *l3_targ_base;
	char *target_name, *master_name = "UN IDENTIFIED";

	/* Get the Type of interrupt */
	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;

	for (i = 0; i < L3_MODULES; i++) {
		/*
		 * Read the regerr register of the clock domain
		 * to determine the source
		 */
		base = l3->l3_base[i];
		err_reg = __raw_readl(base + l3_flagmux[i] +
					+ L3_FLAGMUX_REGERR0 + (inttype << 3));

		/* Get the corresponding error and analyse */
		if (err_reg) {
			/* Identify the source from control status register */
			err_src = __ffs(err_reg);

			/* Read the stderrlog_main_source from clk domain */
			l3_targ_base = base + *(l3_targ[i] + err_src);
			std_err_main =  __raw_readl(l3_targ_base +
					L3_TARG_STDERRLOG_MAIN);
			masterid = __raw_readl(l3_targ_base +
					L3_TARG_STDERRLOG_MSTADDR);

			switch (std_err_main & CUSTOM_ERROR) {
			case STANDARD_ERROR:
				target_name =
					l3_targ_inst_name[i][err_src];
				WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
					target_name,
					__raw_readl(l3_targ_base +
						L3_TARG_STDERRLOG_SLVOFSLSB));
				/* clear the std error log*/
				clear = std_err_main | CLEAR_STDERR_LOG;
				writel(clear, l3_targ_base +
					L3_TARG_STDERRLOG_MAIN);
				break;

			case CUSTOM_ERROR:
				target_name =
					l3_targ_inst_name[i][err_src];
				for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
					if (masterid == l3_masters[k].id)
						master_name =
							l3_masters[k].name;
				}
				WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
					master_name, target_name);
				/* clear the std error log*/
				clear = std_err_main | CLEAR_STDERR_LOG;
				writel(clear, l3_targ_base +
					L3_TARG_STDERRLOG_MAIN);
				break;

			default:
				/* Nothing to be handled here as of now */
				break;
			}
		/* Error found so break the for loop */
		break;
		}
	}
	return IRQ_HANDLED;
}

static int __devinit omap4_l3_probe(struct platform_device *pdev)
{
	static struct omap4_l3 *l3;
	struct resource	*res;
	int ret;

	l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
	if (!l3)
		return -ENOMEM;

	platform_set_drvdata(pdev, l3);
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "couldn't find resource 0\n");
		ret = -ENODEV;
		goto err0;
	}

	l3->l3_base[0] = ioremap(res->start, resource_size(res));
	if (!l3->l3_base[0]) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err0;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "couldn't find resource 1\n");
		ret = -ENODEV;
		goto err1;
	}

	l3->l3_base[1] = ioremap(res->start, resource_size(res));
	if (!l3->l3_base[1]) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err1;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	if (!res) {
		dev_err(&pdev->dev, "couldn't find resource 2\n");
		ret = -ENODEV;
		goto err2;
	}

	l3->l3_base[2] = ioremap(res->start, resource_size(res));
	if (!l3->l3_base[2]) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err2;
	}

	/*
	 * Setup interrupt Handlers
	 */
	l3->debug_irq = platform_get_irq(pdev, 0);
	ret = request_irq(l3->debug_irq,
			l3_interrupt_handler,
			IRQF_DISABLED, "l3-dbg-irq", l3);
	if (ret) {
		pr_crit("L3: request_irq failed to register for 0x%x\n",
						l3->debug_irq);
		goto err3;
	}

	l3->app_irq = platform_get_irq(pdev, 1);
	ret = request_irq(l3->app_irq,
			l3_interrupt_handler,
			IRQF_DISABLED, "l3-app-irq", l3);
	if (ret) {
		pr_crit("L3: request_irq failed to register for 0x%x\n",
						l3->app_irq);
		goto err4;
	}

	return 0;

err4:
	free_irq(l3->debug_irq, l3);
err3:
	iounmap(l3->l3_base[2]);
err2:
	iounmap(l3->l3_base[1]);
err1:
	iounmap(l3->l3_base[0]);
err0:
	kfree(l3);
	return ret;
}

static int __devexit omap4_l3_remove(struct platform_device *pdev)
{
	struct omap4_l3 *l3 = platform_get_drvdata(pdev);

	free_irq(l3->app_irq, l3);
	free_irq(l3->debug_irq, l3);
	iounmap(l3->l3_base[0]);
	iounmap(l3->l3_base[1]);
	iounmap(l3->l3_base[2]);
	kfree(l3);

	return 0;
}

#if defined(CONFIG_OF)
static const struct of_device_id l3_noc_match[] = {
	{.compatible = "ti,omap4-l3-noc", },
	{},
};
MODULE_DEVICE_TABLE(of, l3_noc_match);
#else
#define l3_noc_match NULL
#endif

static struct platform_driver omap4_l3_driver = {
	.probe		= omap4_l3_probe,
	.remove		= __devexit_p(omap4_l3_remove),
	.driver		= {
		.name		= "omap_l3_noc",
		.owner		= THIS_MODULE,
		.of_match_table = l3_noc_match,
	},
};

static int __init omap4_l3_init(void)
{
	return platform_driver_register(&omap4_l3_driver);
}
postcore_initcall_sync(omap4_l3_init);

static void __exit omap4_l3_exit(void)
{
	platform_driver_unregister(&omap4_l3_driver);
}
module_exit(omap4_l3_exit);
Commit	Line	Data
2722e56d	1	/*
ed0e3520	2	* OMAP4XXX L3 Interconnect error handling driver
	3	*
	4	* Copyright (C) 2011 Texas Corporation
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Sricharan <r.sricharan@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	21	* USA
	22	*/
d4fc7eb5	23	#include <linux/module.h>
2722e56d SS	24	#include <linux/init.h>
	25	#include <linux/io.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/kernel.h>
	29	#include <linux/slab.h>
	30
dbc04161	31	#include "soc.h"
2722e56d SS	32	#include "omap_l3_noc.h"
	33
	34	/*
	35	* Interrupt Handler for L3 error detection.
	36	* 1) Identify the L3 clockdomain partition to which the error belongs to.
	37	* 2) Identify the slave where the error information is logged
	38	* 3) Print the logged information.
	39	* 4) Add dump stack to provide kernel trace.
	40	*
	41	* Two Types of errors :
	42	* 1) Custom errors in L3 :
	43	* Target like DMM/FW/EMIF generates SRESP=ERR error
	44	* 2) Standard L3 error:
	45	* - Unsupported CMD.
	46	* L3 tries to access target while it is idle
	47	* - OCP disconnect.
	48	* - Address hole error:
	49	* If DSS/ISS/FDIF/USBHOSTFS access a target where they
	50	* do not have connectivity, the error is logged in
	51	* their default target which is DMM2.
	52	*
	53	* On High Secure devices, firewall errors are possible and those
	54	* can be trapped as well. But the trapping is implemented as part
	55	* secure software and hence need not be implemented here.
	56	*/
	57	static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
	58	{
	59
ed0e3520	60	struct omap4_l3 *l3 = _l3;
551a9fa9	61	int inttype, i, k;
2722e56d	62	int err_src = 0;
551a9fa9	63	u32 std_err_main, err_reg, clear, masterid;
6616aac6	64	void __iomem base, l3_targ_base;
551a9fa9	65	char target_name, master_name = "UN IDENTIFIED";
2722e56d SS	66
2722e56d SS	67	/* Get the Type of interrupt */
35f7b961	68	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
2722e56d SS	69
	70	for (i = 0; i < L3_MODULES; i++) {
	71	/*
	72	* Read the regerr register of the clock domain
	73	* to determine the source
	74	*/
6616aac6	75	base = l3->l3_base[i];
6616aac6	76	err_reg = __raw_readl(base + l3_flagmux[i] +
342fd144	77	+ L3_FLAGMUX_REGERR0 + (inttype << 3));
2722e56d SS	78
	79	/* Get the corresponding error and analyse */
	80	if (err_reg) {
	81	/* Identify the source from control status register */
342fd144	82	err_src = __ffs(err_reg);
2722e56d	83
2722e56d	84	/* Read the stderrlog_main_source from clk domain */
342fd144	85	l3_targ_base = base + *(l3_targ[i] + err_src);
6616aac6	86	std_err_main = __raw_readl(l3_targ_base +
342fd144	87	L3_TARG_STDERRLOG_MAIN);
551a9fa9	88	masterid = __raw_readl(l3_targ_base +
551a9fa9	89	L3_TARG_STDERRLOG_MSTADDR);
2722e56d	90
35f7b961	91	switch (std_err_main & CUSTOM_ERROR) {
2722e56d	92	case STANDARD_ERROR:
551a9fa9	93	target_name =
342fd144	94	l3_targ_inst_name[i][err_src];
551a9fa9	95	WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
551a9fa9	96	target_name,
6616aac6	97	__raw_readl(l3_targ_base +
342fd144	98	L3_TARG_STDERRLOG_SLVOFSLSB));
2722e56d SS	99	/* clear the std error log*/
2722e56d SS	100	clear = std_err_main \| CLEAR_STDERR_LOG;
342fd144 TP	101	writel(clear, l3_targ_base +
342fd144 TP	102	L3_TARG_STDERRLOG_MAIN);
2722e56d SS	103	break;
	104
	105	case CUSTOM_ERROR:
551a9fa9	106	target_name =
342fd144	107	l3_targ_inst_name[i][err_src];
551a9fa9	108	for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
	109	if (masterid == l3_masters[k].id)
	110	master_name =
	111	l3_masters[k].name;
	112	}
	113	WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
	114	master_name, target_name);
2722e56d SS	115	/* clear the std error log*/
2722e56d SS	116	clear = std_err_main \| CLEAR_STDERR_LOG;
342fd144 TP	117	writel(clear, l3_targ_base +
342fd144 TP	118	L3_TARG_STDERRLOG_MAIN);
2722e56d SS	119	break;
	120
	121	default:
	122	/* Nothing to be handled here as of now */
	123	break;
	124	}
	125	/* Error found so break the for loop */
	126	break;
	127	}
	128	}
	129	return IRQ_HANDLED;
	130	}
	131
d039c5b9	132	static int __devinit omap4_l3_probe(struct platform_device *pdev)
2722e56d	133	{
ed0e3520	134	static struct omap4_l3 *l3;
342fd144	135	struct resource *res;
c1df2dcc	136	int ret;
2722e56d SS	137
	138	l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
	139	if (!l3)
7529b703	140	return -ENOMEM;
2722e56d SS	141
	142	platform_set_drvdata(pdev, l3);
	143	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	144	if (!res) {
	145	dev_err(&pdev->dev, "couldn't find resource 0\n");
	146	ret = -ENODEV;
7529b703	147	goto err0;
2722e56d SS	148	}
	149
	150	l3->l3_base[0] = ioremap(res->start, resource_size(res));
35f7b961	151	if (!l3->l3_base[0]) {
2722e56d SS	152	dev_err(&pdev->dev, "ioremap failed\n");
2722e56d SS	153	ret = -ENOMEM;
7529b703	154	goto err0;
2722e56d SS	155	}
	156
	157	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	158	if (!res) {
	159	dev_err(&pdev->dev, "couldn't find resource 1\n");
	160	ret = -ENODEV;
7529b703	161	goto err1;
2722e56d SS	162	}
	163
	164	l3->l3_base[1] = ioremap(res->start, resource_size(res));
35f7b961	165	if (!l3->l3_base[1]) {
2722e56d SS	166	dev_err(&pdev->dev, "ioremap failed\n");
2722e56d SS	167	ret = -ENOMEM;
7529b703	168	goto err1;
2722e56d SS	169	}
	170
	171	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	172	if (!res) {
	173	dev_err(&pdev->dev, "couldn't find resource 2\n");
	174	ret = -ENODEV;
7529b703	175	goto err2;
2722e56d SS	176	}
	177
	178	l3->l3_base[2] = ioremap(res->start, resource_size(res));
35f7b961	179	if (!l3->l3_base[2]) {
2722e56d SS	180	dev_err(&pdev->dev, "ioremap failed\n");
2722e56d SS	181	ret = -ENOMEM;
7529b703	182	goto err2;
2722e56d SS	183	}
	184
	185	/*
	186	* Setup interrupt Handlers
	187	*/
c1df2dcc TP	188	l3->debug_irq = platform_get_irq(pdev, 0);
c1df2dcc TP	189	ret = request_irq(l3->debug_irq,
2722e56d SS	190	l3_interrupt_handler,
	191	IRQF_DISABLED, "l3-dbg-irq", l3);
	192	if (ret) {
	193	pr_crit("L3: request_irq failed to register for 0x%x\n",
2c2d1674	194	l3->debug_irq);
7529b703	195	goto err3;
2722e56d	196	}
2722e56d	197
c1df2dcc TP	198	l3->app_irq = platform_get_irq(pdev, 1);
c1df2dcc TP	199	ret = request_irq(l3->app_irq,
2722e56d SS	200	l3_interrupt_handler,
	201	IRQF_DISABLED, "l3-app-irq", l3);
	202	if (ret) {
	203	pr_crit("L3: request_irq failed to register for 0x%x\n",
2c2d1674	204	l3->app_irq);
7529b703	205	goto err4;
2722e56d	206	}
2722e56d	207
7529b703	208	return 0;
7529b703	209
2722e56d	210	err4:
7529b703	211	free_irq(l3->debug_irq, l3);
2722e56d	212	err3:
7529b703	213	iounmap(l3->l3_base[2]);
2722e56d	214	err2:
7529b703	215	iounmap(l3->l3_base[1]);
2722e56d	216	err1:
7529b703	217	iounmap(l3->l3_base[0]);
2722e56d	218	err0:
7529b703	219	kfree(l3);
2722e56d SS	220	return ret;
	221	}
	222
d039c5b9	223	static int __devexit omap4_l3_remove(struct platform_device *pdev)
2722e56d	224	{
ed0e3520	225	struct omap4_l3 *l3 = platform_get_drvdata(pdev);
2722e56d SS	226
	227	free_irq(l3->app_irq, l3);
	228	free_irq(l3->debug_irq, l3);
	229	iounmap(l3->l3_base[0]);
	230	iounmap(l3->l3_base[1]);
	231	iounmap(l3->l3_base[2]);
	232	kfree(l3);
	233
	234	return 0;
	235	}
	236
d039c5b9 BC	237	#if defined(CONFIG_OF)
	238	static const struct of_device_id l3_noc_match[] = {
	239	{.compatible = "ti,omap4-l3-noc", },
	240	{},
8770b07c	241	};
d039c5b9 BC	242	MODULE_DEVICE_TABLE(of, l3_noc_match);
	243	#else
	244	#define l3_noc_match NULL
	245	#endif
	246
2722e56d	247	static struct platform_driver omap4_l3_driver = {
d039c5b9 BC	248	.probe = omap4_l3_probe,
	249	.remove = __devexit_p(omap4_l3_remove),
	250	.driver = {
	251	.name = "omap_l3_noc",
	252	.owner = THIS_MODULE,
	253	.of_match_table = l3_noc_match,
2722e56d SS	254	},
	255	};
	256
	257	static int __init omap4_l3_init(void)
	258	{
d039c5b9	259	return platform_driver_register(&omap4_l3_driver);
2722e56d SS	260	}
	261	postcore_initcall_sync(omap4_l3_init);
	262
	263	static void __exit omap4_l3_exit(void)
	264	{
	265	platform_driver_unregister(&omap4_l3_driver);
	266	}
	267	module_exit(omap4_l3_exit);