Commit | Line | Data |
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2722e56d | 1 | /* |
c10d5c9e | 2 | * OMAP L3 Interconnect error handling driver |
ed0e3520 | 3 | * |
c5f2aea0 | 4 | * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ |
ed0e3520 | 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
6 | * Sricharan <r.sricharan@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
c5f2aea0 NM |
9 | * it under the terms of the GNU General Public License version 2 as |
10 | * published by the Free Software Foundation. | |
ed0e3520 | 11 | * |
c5f2aea0 NM |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
ed0e3520 | 15 | * GNU General Public License for more details. |
ed0e3520 | 16 | */ |
d4fc7eb5 | 17 | #include <linux/module.h> |
2722e56d SS |
18 | #include <linux/init.h> |
19 | #include <linux/io.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/slab.h> | |
24 | ||
25 | #include "omap_l3_noc.h" | |
26 | ||
27 | /* | |
28 | * Interrupt Handler for L3 error detection. | |
29 | * 1) Identify the L3 clockdomain partition to which the error belongs to. | |
30 | * 2) Identify the slave where the error information is logged | |
31 | * 3) Print the logged information. | |
32 | * 4) Add dump stack to provide kernel trace. | |
33 | * | |
34 | * Two Types of errors : | |
35 | * 1) Custom errors in L3 : | |
36 | * Target like DMM/FW/EMIF generates SRESP=ERR error | |
37 | * 2) Standard L3 error: | |
38 | * - Unsupported CMD. | |
39 | * L3 tries to access target while it is idle | |
40 | * - OCP disconnect. | |
41 | * - Address hole error: | |
42 | * If DSS/ISS/FDIF/USBHOSTFS access a target where they | |
43 | * do not have connectivity, the error is logged in | |
44 | * their default target which is DMM2. | |
45 | * | |
46 | * On High Secure devices, firewall errors are possible and those | |
47 | * can be trapped as well. But the trapping is implemented as part | |
48 | * secure software and hence need not be implemented here. | |
49 | */ | |
50 | static irqreturn_t l3_interrupt_handler(int irq, void *_l3) | |
51 | { | |
52 | ||
c10d5c9e | 53 | struct omap_l3 *l3 = _l3; |
551a9fa9 | 54 | int inttype, i, k; |
2722e56d | 55 | int err_src = 0; |
551a9fa9 | 56 | u32 std_err_main, err_reg, clear, masterid; |
6616aac6 | 57 | void __iomem *base, *l3_targ_base; |
9e224c8f | 58 | void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr; |
551a9fa9 | 59 | char *target_name, *master_name = "UN IDENTIFIED"; |
3ae9af7c | 60 | struct l3_target_data *l3_targ_inst; |
2722e56d SS |
61 | |
62 | /* Get the Type of interrupt */ | |
35f7b961 | 63 | inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; |
2722e56d SS |
64 | |
65 | for (i = 0; i < L3_MODULES; i++) { | |
66 | /* | |
67 | * Read the regerr register of the clock domain | |
68 | * to determine the source | |
69 | */ | |
6616aac6 | 70 | base = l3->l3_base[i]; |
9e224c8f NM |
71 | err_reg = readl_relaxed(base + l3_flagmux[i] + |
72 | L3_FLAGMUX_REGERR0 + (inttype << 3)); | |
2722e56d SS |
73 | |
74 | /* Get the corresponding error and analyse */ | |
75 | if (err_reg) { | |
76 | /* Identify the source from control status register */ | |
342fd144 | 77 | err_src = __ffs(err_reg); |
3ae9af7c NM |
78 | l3_targ_inst = &l3_targ[i][err_src]; |
79 | target_name = l3_targ_inst->name; | |
80 | l3_targ_base = base + l3_targ_inst->offset; | |
2722e56d | 81 | |
2722e56d | 82 | /* Read the stderrlog_main_source from clk domain */ |
9e224c8f NM |
83 | l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN; |
84 | l3_targ_slvofslsb = l3_targ_base + | |
85 | L3_TARG_STDERRLOG_SLVOFSLSB; | |
86 | l3_targ_mstaddr = l3_targ_base + | |
87 | L3_TARG_STDERRLOG_MSTADDR; | |
88 | ||
89 | std_err_main = readl_relaxed(l3_targ_stderr); | |
90 | masterid = readl_relaxed(l3_targ_mstaddr); | |
2722e56d | 91 | |
35f7b961 | 92 | switch (std_err_main & CUSTOM_ERROR) { |
2722e56d | 93 | case STANDARD_ERROR: |
551a9fa9 | 94 | WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n", |
95 | target_name, | |
9e224c8f | 96 | readl_relaxed(l3_targ_slvofslsb)); |
2722e56d SS |
97 | /* clear the std error log*/ |
98 | clear = std_err_main | CLEAR_STDERR_LOG; | |
9e224c8f | 99 | writel_relaxed(clear, l3_targ_stderr); |
2722e56d SS |
100 | break; |
101 | ||
102 | case CUSTOM_ERROR: | |
551a9fa9 | 103 | for (k = 0; k < NUM_OF_L3_MASTERS; k++) { |
104 | if (masterid == l3_masters[k].id) | |
105 | master_name = | |
106 | l3_masters[k].name; | |
107 | } | |
108 | WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n", | |
109 | master_name, target_name); | |
2722e56d SS |
110 | /* clear the std error log*/ |
111 | clear = std_err_main | CLEAR_STDERR_LOG; | |
9e224c8f | 112 | writel_relaxed(clear, l3_targ_stderr); |
2722e56d SS |
113 | break; |
114 | ||
115 | default: | |
116 | /* Nothing to be handled here as of now */ | |
117 | break; | |
118 | } | |
119 | /* Error found so break the for loop */ | |
120 | break; | |
121 | } | |
122 | } | |
123 | return IRQ_HANDLED; | |
124 | } | |
125 | ||
c10d5c9e | 126 | static int omap_l3_probe(struct platform_device *pdev) |
2722e56d | 127 | { |
c10d5c9e | 128 | static struct omap_l3 *l3; |
56c4a022 | 129 | int ret, i; |
2722e56d | 130 | |
bae74510 | 131 | l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL); |
2722e56d | 132 | if (!l3) |
7529b703 | 133 | return -ENOMEM; |
2722e56d | 134 | |
ca6a3493 | 135 | l3->dev = &pdev->dev; |
2722e56d | 136 | platform_set_drvdata(pdev, l3); |
2722e56d | 137 | |
56c4a022 PU |
138 | /* Get mem resources */ |
139 | for (i = 0; i < L3_MODULES; i++) { | |
140 | struct resource *res = platform_get_resource(pdev, | |
141 | IORESOURCE_MEM, i); | |
2722e56d | 142 | |
56c4a022 PU |
143 | l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res); |
144 | if (IS_ERR(l3->l3_base[i])) { | |
ca6a3493 | 145 | dev_err(l3->dev, "ioremap %d failed\n", i); |
56c4a022 PU |
146 | return PTR_ERR(l3->l3_base[i]); |
147 | } | |
2722e56d SS |
148 | } |
149 | ||
150 | /* | |
151 | * Setup interrupt Handlers | |
152 | */ | |
c1df2dcc | 153 | l3->debug_irq = platform_get_irq(pdev, 0); |
ca6a3493 | 154 | ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler, |
a0ef78f3 | 155 | IRQF_DISABLED, "l3-dbg-irq", l3); |
2722e56d | 156 | if (ret) { |
ca6a3493 | 157 | dev_err(l3->dev, "request_irq failed for %d\n", |
ae22598a | 158 | l3->debug_irq); |
56c4a022 | 159 | return ret; |
2722e56d | 160 | } |
2722e56d | 161 | |
c1df2dcc | 162 | l3->app_irq = platform_get_irq(pdev, 1); |
ca6a3493 | 163 | ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler, |
a0ef78f3 PU |
164 | IRQF_DISABLED, "l3-app-irq", l3); |
165 | if (ret) | |
ca6a3493 | 166 | dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq); |
7529b703 | 167 | |
2722e56d SS |
168 | return ret; |
169 | } | |
170 | ||
d039c5b9 BC |
171 | #if defined(CONFIG_OF) |
172 | static const struct of_device_id l3_noc_match[] = { | |
173 | {.compatible = "ti,omap4-l3-noc", }, | |
174 | {}, | |
8770b07c | 175 | }; |
d039c5b9 BC |
176 | MODULE_DEVICE_TABLE(of, l3_noc_match); |
177 | #else | |
178 | #define l3_noc_match NULL | |
179 | #endif | |
180 | ||
c10d5c9e S |
181 | static struct platform_driver omap_l3_driver = { |
182 | .probe = omap_l3_probe, | |
d039c5b9 BC |
183 | .driver = { |
184 | .name = "omap_l3_noc", | |
185 | .owner = THIS_MODULE, | |
186 | .of_match_table = l3_noc_match, | |
2722e56d SS |
187 | }, |
188 | }; | |
189 | ||
c10d5c9e | 190 | static int __init omap_l3_init(void) |
2722e56d | 191 | { |
c10d5c9e | 192 | return platform_driver_register(&omap_l3_driver); |
2722e56d | 193 | } |
c10d5c9e | 194 | postcore_initcall_sync(omap_l3_init); |
2722e56d | 195 | |
c10d5c9e | 196 | static void __exit omap_l3_exit(void) |
2722e56d | 197 | { |
c10d5c9e | 198 | platform_driver_unregister(&omap_l3_driver); |
2722e56d | 199 | } |
c10d5c9e | 200 | module_exit(omap_l3_exit); |