bus: omap_l3_noc: improve readability by using helper for slave event parsing
[deliverable/linux.git] / drivers / bus / omap_l3_noc.c
CommitLineData
2722e56d 1/*
c10d5c9e 2 * OMAP L3 Interconnect error handling driver
ed0e3520 3 *
c5f2aea0 4 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
ed0e3520 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
c5f2aea0
NM
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
ed0e3520 11 *
c5f2aea0
NM
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ed0e3520 15 * GNU General Public License for more details.
ed0e3520 16 */
2722e56d 17#include <linux/init.h>
2722e56d 18#include <linux/interrupt.h>
0659452d 19#include <linux/io.h>
2722e56d 20#include <linux/kernel.h>
0659452d
S
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/of.h>
24#include <linux/platform_device.h>
2722e56d
SS
25#include <linux/slab.h>
26
27#include "omap_l3_noc.h"
28
e4be3f3a
NM
29/**
30 * l3_handle_target() - Handle Target specific parse and reporting
31 * @l3: pointer to l3 struct
32 * @base: base address of clkdm
33 * @flag_mux: flagmux corresponding to the event
34 * @err_src: error source index of the slave (target)
2722e56d 35 *
e4be3f3a
NM
36 * This does the second part of the error interrupt handling:
37 * 3) Parse in the slave information
38 * 4) Print the logged information.
39 * 5) Add dump stack to provide kernel trace.
40 * 6) Clear the source if known.
41 *
42 * This handles two types of errors:
2722e56d
SS
43 * 1) Custom errors in L3 :
44 * Target like DMM/FW/EMIF generates SRESP=ERR error
45 * 2) Standard L3 error:
46 * - Unsupported CMD.
47 * L3 tries to access target while it is idle
48 * - OCP disconnect.
49 * - Address hole error:
50 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
51 * do not have connectivity, the error is logged in
52 * their default target which is DMM2.
53 *
54 * On High Secure devices, firewall errors are possible and those
55 * can be trapped as well. But the trapping is implemented as part
56 * secure software and hence need not be implemented here.
57 */
e4be3f3a
NM
58static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
59 struct l3_flagmux_data *flag_mux, int err_src)
2722e56d 60{
e4be3f3a
NM
61 int k;
62 u32 std_err_main, clear, masterid;
63 void __iomem *l3_targ_base;
9e224c8f 64 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
3ae9af7c 65 struct l3_target_data *l3_targ_inst;
0659452d 66 struct l3_masters_data *master;
e4be3f3a 67 char *target_name, *master_name = "UN IDENTIFIED";
c98aa7aa
NM
68 char *err_description;
69 char err_string[30] = { 0 };
2722e56d 70
e4be3f3a
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71 /* We DONOT expect err_src to go out of bounds */
72 BUG_ON(err_src > MAX_CLKDM_TARGETS);
73
74 if (err_src < flag_mux->num_targ_data) {
75 l3_targ_inst = &flag_mux->l3_targ[err_src];
76 target_name = l3_targ_inst->name;
77 l3_targ_base = base + l3_targ_inst->offset;
78 } else {
79 target_name = L3_TARGET_NOT_SUPPORTED;
80 }
81
82 if (target_name == L3_TARGET_NOT_SUPPORTED)
83 return -ENODEV;
84
85 /* Read the stderrlog_main_source from clk domain */
86 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
87 l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
88
89 std_err_main = readl_relaxed(l3_targ_stderr);
90
91 switch (std_err_main & CUSTOM_ERROR) {
92 case STANDARD_ERROR:
93 err_description = "Standard";
94 snprintf(err_string, sizeof(err_string),
95 ": At Address: 0x%08X ",
96 readl_relaxed(l3_targ_slvofslsb));
97
98 l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
99 break;
100
101 case CUSTOM_ERROR:
102 err_description = "Custom";
103
104 l3_targ_mstaddr = l3_targ_base +
105 L3_TARG_STDERRLOG_CINFO_MSTADDR;
106 break;
107
108 default:
109 /* Nothing to be handled here as of now */
110 return 0;
111 }
112
113 /* STDERRLOG_MSTADDR Stores the NTTP master address. */
114 masterid = (readl_relaxed(l3_targ_mstaddr) &
115 l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
116
117 for (k = 0, master = l3->l3_masters; k < l3->num_masters;
118 k++, master++) {
119 if (masterid == master->id) {
120 master_name = master->name;
121 break;
122 }
123 }
124
125 WARN(true,
126 "%s:L3 %s Error: MASTER %s TARGET %s%s\n",
127 dev_name(l3->dev),
128 err_description,
129 master_name, target_name,
130 err_string);
131
132 /* clear the std error log*/
133 clear = std_err_main | CLEAR_STDERR_LOG;
134 writel_relaxed(clear, l3_targ_stderr);
135
136 return 0;
137}
138
139/**
140 * l3_interrupt_handler() - interrupt handler for l3 events
141 * @irq: irq number
142 * @_l3: pointer to l3 structure
143 *
144 * Interrupt Handler for L3 error detection.
145 * 1) Identify the L3 clockdomain partition to which the error belongs to.
146 * 2) Identify the slave where the error information is logged
147 * ... handle the slave event..
148 * 7) if the slave is unknown, mask out the slave.
149 */
150static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
151{
152 struct omap_l3 *l3 = _l3;
153 int inttype, i, ret;
154 int err_src = 0;
155 u32 err_reg, mask_val;
156 void __iomem *base, *mask_reg;
157 struct l3_flagmux_data *flag_mux;
158
2722e56d 159 /* Get the Type of interrupt */
35f7b961 160 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
2722e56d 161
0659452d 162 for (i = 0; i < l3->num_modules; i++) {
2722e56d
SS
163 /*
164 * Read the regerr register of the clock domain
165 * to determine the source
166 */
6616aac6 167 base = l3->l3_base[i];
97708c08
NM
168 flag_mux = l3->l3_flagmux[i];
169 err_reg = readl_relaxed(base + flag_mux->offset +
9e224c8f 170 L3_FLAGMUX_REGERR0 + (inttype << 3));
2722e56d
SS
171
172 /* Get the corresponding error and analyse */
173 if (err_reg) {
174 /* Identify the source from control status register */
342fd144 175 err_src = __ffs(err_reg);
3340d739 176
e4be3f3a 177 ret = l3_handle_target(l3, base, flag_mux, err_src);
2722e56d 178
3340d739 179 /*
e4be3f3a
NM
180 * Certain plaforms may have "undocumented" status
181 * pending on boot. So dont generate a severe warning
182 * here. Just mask it off to prevent the error from
183 * reoccuring and locking up the system.
3340d739 184 */
e4be3f3a 185 if (ret) {
3340d739
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186 dev_err(l3->dev,
187 "L3 %s error: target %d mod:%d %s\n",
188 inttype ? "debug" : "application",
189 err_src, i, "(unclearable)");
190
97708c08 191 mask_reg = base + flag_mux->offset +
3340d739
RN
192 L3_FLAGMUX_MASK0 + (inttype << 3);
193 mask_val = readl_relaxed(mask_reg);
194 mask_val &= ~(1 << err_src);
195 writel_relaxed(mask_val, mask_reg);
3340d739
RN
196 }
197
c98aa7aa
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198 /* Error found so break the for loop */
199 break;
2722e56d
SS
200 }
201 }
202 return IRQ_HANDLED;
203}
204
0659452d
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205static const struct of_device_id l3_noc_match[] = {
206 {.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
207 {},
208};
209MODULE_DEVICE_TABLE(of, l3_noc_match);
210
c10d5c9e 211static int omap_l3_probe(struct platform_device *pdev)
2722e56d 212{
0659452d 213 const struct of_device_id *of_id;
c10d5c9e 214 static struct omap_l3 *l3;
56c4a022 215 int ret, i;
2722e56d 216
0659452d
S
217 of_id = of_match_device(l3_noc_match, &pdev->dev);
218 if (!of_id) {
219 dev_err(&pdev->dev, "OF data missing\n");
220 return -EINVAL;
221 }
222
bae74510 223 l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
2722e56d 224 if (!l3)
7529b703 225 return -ENOMEM;
2722e56d 226
0659452d 227 memcpy(l3, of_id->data, sizeof(*l3));
ca6a3493 228 l3->dev = &pdev->dev;
2722e56d 229 platform_set_drvdata(pdev, l3);
2722e56d 230
56c4a022 231 /* Get mem resources */
0659452d 232 for (i = 0; i < l3->num_modules; i++) {
56c4a022
PU
233 struct resource *res = platform_get_resource(pdev,
234 IORESOURCE_MEM, i);
2722e56d 235
56c4a022
PU
236 l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
237 if (IS_ERR(l3->l3_base[i])) {
ca6a3493 238 dev_err(l3->dev, "ioremap %d failed\n", i);
56c4a022
PU
239 return PTR_ERR(l3->l3_base[i]);
240 }
2722e56d
SS
241 }
242
243 /*
244 * Setup interrupt Handlers
245 */
c1df2dcc 246 l3->debug_irq = platform_get_irq(pdev, 0);
ca6a3493 247 ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
a0ef78f3 248 IRQF_DISABLED, "l3-dbg-irq", l3);
2722e56d 249 if (ret) {
ca6a3493 250 dev_err(l3->dev, "request_irq failed for %d\n",
ae22598a 251 l3->debug_irq);
56c4a022 252 return ret;
2722e56d 253 }
2722e56d 254
c1df2dcc 255 l3->app_irq = platform_get_irq(pdev, 1);
ca6a3493 256 ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
a0ef78f3
PU
257 IRQF_DISABLED, "l3-app-irq", l3);
258 if (ret)
ca6a3493 259 dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
7529b703 260
2722e56d
SS
261 return ret;
262}
263
c10d5c9e
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264static struct platform_driver omap_l3_driver = {
265 .probe = omap_l3_probe,
d039c5b9
BC
266 .driver = {
267 .name = "omap_l3_noc",
268 .owner = THIS_MODULE,
0659452d 269 .of_match_table = of_match_ptr(l3_noc_match),
2722e56d
SS
270 },
271};
272
c10d5c9e 273static int __init omap_l3_init(void)
2722e56d 274{
c10d5c9e 275 return platform_driver_register(&omap_l3_driver);
2722e56d 276}
c10d5c9e 277postcore_initcall_sync(omap_l3_init);
2722e56d 278
c10d5c9e 279static void __exit omap_l3_exit(void)
2722e56d 280{
c10d5c9e 281 platform_driver_unregister(&omap_l3_driver);
2722e56d 282}
c10d5c9e 283module_exit(omap_l3_exit);
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