Commit | Line | Data |
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ed0e3520 | 1 | /* |
2 | * OMAP4XXX L3 Interconnect error handling driver header | |
3 | * | |
4 | * Copyright (C) 2011 Texas Corporation | |
5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
6 | * sricharan <r.sricharan@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
21 | * USA | |
22 | */ | |
2722e56d SS |
23 | #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H |
24 | #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H | |
25 | ||
2722e56d SS |
26 | #define L3_MODULES 3 |
27 | #define CLEAR_STDERR_LOG (1 << 31) | |
28 | #define CUSTOM_ERROR 0x2 | |
29 | #define STANDARD_ERROR 0x0 | |
30 | #define INBAND_ERROR 0x0 | |
2722e56d SS |
31 | #define L3_APPLICATION_ERROR 0x0 |
32 | #define L3_DEBUG_ERROR 0x1 | |
33 | ||
342fd144 | 34 | /* L3 TARG register offsets */ |
ed0e3520 | 35 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
36 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c | |
551a9fa9 | 37 | #define L3_TARG_STDERRLOG_MSTADDR 0x68 |
ed0e3520 | 38 | #define L3_FLAGMUX_REGERR0 0xc |
342fd144 | 39 | |
551a9fa9 | 40 | #define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0])) |
41 | ||
6616aac6 | 42 | static u32 l3_flagmux[L3_MODULES] = { |
342fd144 TP |
43 | 0x500, |
44 | 0x1000, | |
45 | 0X0200 | |
2722e56d SS |
46 | }; |
47 | ||
342fd144 | 48 | /* L3 Target standard Error register offsets */ |
6616aac6 | 49 | static u32 l3_targ_inst_clk1[] = { |
342fd144 TP |
50 | 0x100, /* DMM1 */ |
51 | 0x200, /* DMM2 */ | |
52 | 0x300, /* ABE */ | |
53 | 0x400, /* L4CFG */ | |
e17933c2 S |
54 | 0x600, /* CLK2 PWR DISC */ |
55 | 0x0, /* Host CLK1 */ | |
56 | 0x900 /* L4 Wakeup */ | |
2722e56d SS |
57 | }; |
58 | ||
6616aac6 | 59 | static u32 l3_targ_inst_clk2[] = { |
342fd144 TP |
60 | 0x500, /* CORTEX M3 */ |
61 | 0x300, /* DSS */ | |
62 | 0x100, /* GPMC */ | |
63 | 0x400, /* ISS */ | |
64 | 0x700, /* IVAHD */ | |
65 | 0xD00, /* missing in TRM corresponds to AES1*/ | |
66 | 0x900, /* L4 PER0*/ | |
67 | 0x200, /* OCMRAM */ | |
68 | 0x100, /* missing in TRM corresponds to GPMC sERROR*/ | |
69 | 0x600, /* SGX */ | |
70 | 0x800, /* SL2 */ | |
71 | 0x1600, /* C2C */ | |
72 | 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/ | |
73 | 0xF00, /* missing in TRM corrsponds to SHA1*/ | |
74 | 0xE00, /* missing in TRM corresponds to AES2*/ | |
75 | 0xC00, /* L4 PER3 */ | |
76 | 0xA00, /* L4 PER1*/ | |
e17933c2 S |
77 | 0xB00, /* L4 PER2*/ |
78 | 0x0, /* HOST CLK2 */ | |
79 | 0x1800, /* CAL */ | |
80 | 0x1700 /* LLI */ | |
2722e56d SS |
81 | }; |
82 | ||
6616aac6 | 83 | static u32 l3_targ_inst_clk3[] = { |
e17933c2 S |
84 | 0x0100 /* EMUSS */, |
85 | 0x0300, /* DEBUGSS_CT_TBR */ | |
86 | 0x0 /* HOST CLK3 */ | |
2722e56d SS |
87 | }; |
88 | ||
551a9fa9 | 89 | static struct l3_masters_data { |
90 | u32 id; | |
91 | char name[10]; | |
92 | } l3_masters[] = { | |
93 | { 0x0 , "MPU"}, | |
94 | { 0x10, "CS_ADP"}, | |
95 | { 0x14, "xxx"}, | |
96 | { 0x20, "DSP"}, | |
97 | { 0x30, "IVAHD"}, | |
98 | { 0x40, "ISS"}, | |
99 | { 0x44, "DucatiM3"}, | |
100 | { 0x48, "FaceDetect"}, | |
101 | { 0x50, "SDMA_Rd"}, | |
102 | { 0x54, "SDMA_Wr"}, | |
103 | { 0x58, "xxx"}, | |
104 | { 0x5C, "xxx"}, | |
105 | { 0x60, "SGX"}, | |
106 | { 0x70, "DSS"}, | |
107 | { 0x80, "C2C"}, | |
108 | { 0x88, "xxx"}, | |
109 | { 0x8C, "xxx"}, | |
110 | { 0x90, "HSI"}, | |
111 | { 0xA0, "MMC1"}, | |
112 | { 0xA4, "MMC2"}, | |
113 | { 0xA8, "MMC6"}, | |
114 | { 0xB0, "UNIPRO1"}, | |
115 | { 0xC0, "USBHOSTHS"}, | |
116 | { 0xC4, "USBOTGHS"}, | |
117 | { 0xC8, "USBHOSTFS"} | |
118 | }; | |
119 | ||
e17933c2 | 120 | static char *l3_targ_inst_name[L3_MODULES][21] = { |
2722e56d | 121 | { |
ed0e3520 | 122 | "DMM1", |
123 | "DMM2", | |
124 | "ABE", | |
125 | "L4CFG", | |
126 | "CLK2 PWR DISC", | |
e17933c2 S |
127 | "HOST CLK1", |
128 | "L4 WAKEUP" | |
2722e56d SS |
129 | }, |
130 | { | |
ed0e3520 | 131 | "CORTEX M3" , |
132 | "DSS ", | |
133 | "GPMC ", | |
134 | "ISS ", | |
135 | "IVAHD ", | |
136 | "AES1", | |
137 | "L4 PER0", | |
138 | "OCMRAM ", | |
139 | "GPMC sERROR", | |
140 | "SGX ", | |
141 | "SL2 ", | |
142 | "C2C ", | |
143 | "PWR DISC CLK1", | |
144 | "SHA1", | |
145 | "AES2", | |
146 | "L4 PER3", | |
147 | "L4 PER1", | |
148 | "L4 PER2", | |
e17933c2 S |
149 | "HOST CLK2", |
150 | "CAL", | |
151 | "LLI" | |
2722e56d SS |
152 | }, |
153 | { | |
ed0e3520 | 154 | "EMUSS", |
e17933c2 S |
155 | "DEBUG SOURCE", |
156 | "HOST CLK3" | |
2722e56d SS |
157 | }, |
158 | }; | |
159 | ||
6616aac6 | 160 | static u32 *l3_targ[L3_MODULES] = { |
342fd144 TP |
161 | l3_targ_inst_clk1, |
162 | l3_targ_inst_clk2, | |
163 | l3_targ_inst_clk3, | |
2722e56d SS |
164 | }; |
165 | ||
166 | struct omap4_l3 { | |
ed0e3520 | 167 | struct device *dev; |
168 | struct clk *ick; | |
2722e56d SS |
169 | |
170 | /* memory base */ | |
342fd144 | 171 | void __iomem *l3_base[L3_MODULES]; |
2722e56d | 172 | |
ed0e3520 | 173 | int debug_irq; |
174 | int app_irq; | |
2722e56d | 175 | }; |
2722e56d | 176 | #endif |