Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel AGPGART routines. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
1eaf122c | 8 | #include <linux/kernel.h> |
1da177e4 LT |
9 | #include <linux/pagemap.h> |
10 | #include <linux/agp_backend.h> | |
11 | #include "agp.h" | |
12 | ||
e914a36a CM |
13 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
14 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
65c25aad EA |
15 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
16 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
9119f85a ZW |
17 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 |
18 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
65c25aad EA |
19 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 |
20 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
21 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
22 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
4598af33 WZ |
23 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
24 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
dde47876 | 25 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
c8eebfd6 | 26 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
dde47876 | 27 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
df80b148 | 28 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
2177832f SL |
29 | #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010 |
30 | #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011 | |
31 | #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000 | |
32 | #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001 | |
874808c6 WZ |
33 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
34 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
35 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
36 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
37 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
38 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
99d32bd5 ZW |
39 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
40 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
25ce77ab ZW |
41 | #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 |
42 | #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 | |
43 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | |
44 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
45 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
46 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
a50ccc6c ZW |
47 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
48 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
32cb055b ZW |
49 | #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040 |
50 | #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042 | |
51 | #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044 | |
52 | #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046 | |
65c25aad | 53 | |
f011ae74 DA |
54 | /* cover 915 and 945 variants */ |
55 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
56 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
57 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
58 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
59 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
60 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
61 | ||
65c25aad | 62 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ |
f011ae74 DA |
63 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ |
64 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
65 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
66 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
82e14a62 | 67 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) |
65c25aad | 68 | |
874808c6 WZ |
69 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ |
70 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
2177832f SL |
71 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ |
72 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ | |
73 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) | |
74 | ||
75 | #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ | |
76 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) | |
65c25aad | 77 | |
25ce77ab ZW |
78 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ |
79 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | |
82e14a62 | 80 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ |
a50ccc6c | 81 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ |
32cb055b ZW |
82 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ |
83 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ | |
84 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB) | |
25ce77ab | 85 | |
a030ce44 TH |
86 | extern int agp_memory_reserved; |
87 | ||
88 | ||
1da177e4 LT |
89 | /* Intel 815 register */ |
90 | #define INTEL_815_APCONT 0x51 | |
91 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
92 | ||
93 | /* Intel i820 registers */ | |
94 | #define INTEL_I820_RDCR 0x51 | |
95 | #define INTEL_I820_ERRSTS 0xc8 | |
96 | ||
97 | /* Intel i840 registers */ | |
98 | #define INTEL_I840_MCHCFG 0x50 | |
99 | #define INTEL_I840_ERRSTS 0xc8 | |
100 | ||
101 | /* Intel i850 registers */ | |
102 | #define INTEL_I850_MCHCFG 0x50 | |
103 | #define INTEL_I850_ERRSTS 0xc8 | |
104 | ||
105 | /* intel 915G registers */ | |
106 | #define I915_GMADDR 0x18 | |
107 | #define I915_MMADDR 0x10 | |
108 | #define I915_PTEADDR 0x1C | |
109 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
110 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
25ce77ab ZW |
111 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
112 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
113 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
114 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
115 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
116 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
117 | ||
6c00a61e | 118 | #define I915_IFPADDR 0x60 |
1da177e4 | 119 | |
65c25aad EA |
120 | /* Intel 965G registers */ |
121 | #define I965_MSAC 0x62 | |
6c00a61e | 122 | #define I965_IFPADDR 0x70 |
1da177e4 LT |
123 | |
124 | /* Intel 7505 registers */ | |
125 | #define INTEL_I7505_APSIZE 0x74 | |
126 | #define INTEL_I7505_NCAPID 0x60 | |
127 | #define INTEL_I7505_NISTAT 0x6c | |
128 | #define INTEL_I7505_ATTBASE 0x78 | |
129 | #define INTEL_I7505_ERRSTS 0x42 | |
130 | #define INTEL_I7505_AGPCTRL 0x70 | |
131 | #define INTEL_I7505_MCHCFG 0x50 | |
132 | ||
e5524f35 | 133 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
1da177e4 LT |
134 | { |
135 | {64, 16384, 4}, | |
136 | /* The 32M mode still requires a 64k gatt */ | |
137 | {32, 8192, 4} | |
138 | }; | |
139 | ||
140 | #define AGP_DCACHE_MEMORY 1 | |
141 | #define AGP_PHYS_MEMORY 2 | |
a030ce44 | 142 | #define INTEL_AGP_CACHED_MEMORY 3 |
1da177e4 LT |
143 | |
144 | static struct gatt_mask intel_i810_masks[] = | |
145 | { | |
146 | {.mask = I810_PTE_VALID, .type = 0}, | |
147 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
a030ce44 TH |
148 | {.mask = I810_PTE_VALID, .type = 0}, |
149 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
150 | .type = INTEL_AGP_CACHED_MEMORY} | |
1da177e4 LT |
151 | }; |
152 | ||
c4ca8817 WZ |
153 | static struct _intel_private { |
154 | struct pci_dev *pcidev; /* device one */ | |
155 | u8 __iomem *registers; | |
156 | u32 __iomem *gtt; /* I915G */ | |
1da177e4 | 157 | int num_dcache_entries; |
c4ca8817 WZ |
158 | /* gtt_entries is the number of gtt entries that are already mapped |
159 | * to stolen memory. Stolen memory is larger than the memory mapped | |
160 | * through gtt_entries, as it includes some reserved space for the BIOS | |
161 | * popup and for the GTT. | |
162 | */ | |
163 | int gtt_entries; /* i830+ */ | |
2162e6a2 DA |
164 | union { |
165 | void __iomem *i9xx_flush_page; | |
166 | void *i8xx_flush_page; | |
167 | }; | |
168 | struct page *i8xx_page; | |
6c00a61e | 169 | struct resource ifp_resource; |
4d64dd9e | 170 | int resource_valid; |
c4ca8817 | 171 | } intel_private; |
1da177e4 LT |
172 | |
173 | static int intel_i810_fetch_size(void) | |
174 | { | |
175 | u32 smram_miscc; | |
176 | struct aper_size_info_fixed *values; | |
177 | ||
178 | pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); | |
179 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
180 | ||
181 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
e3cf6951 | 182 | dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); |
1da177e4 LT |
183 | return 0; |
184 | } | |
185 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
186 | agp_bridge->previous_size = | |
187 | agp_bridge->current_size = (void *) (values + 1); | |
188 | agp_bridge->aperture_size_idx = 1; | |
189 | return values[1].size; | |
190 | } else { | |
191 | agp_bridge->previous_size = | |
192 | agp_bridge->current_size = (void *) (values); | |
193 | agp_bridge->aperture_size_idx = 0; | |
194 | return values[0].size; | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | static int intel_i810_configure(void) | |
201 | { | |
202 | struct aper_size_info_fixed *current_size; | |
203 | u32 temp; | |
204 | int i; | |
205 | ||
206 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
207 | ||
c4ca8817 WZ |
208 | if (!intel_private.registers) { |
209 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
e4ac5e4f DJ |
210 | temp &= 0xfff80000; |
211 | ||
c4ca8817 WZ |
212 | intel_private.registers = ioremap(temp, 128 * 4096); |
213 | if (!intel_private.registers) { | |
e3cf6951 BH |
214 | dev_err(&intel_private.pcidev->dev, |
215 | "can't remap memory\n"); | |
e4ac5e4f DJ |
216 | return -ENOMEM; |
217 | } | |
1da177e4 LT |
218 | } |
219 | ||
c4ca8817 | 220 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
1da177e4 LT |
221 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
222 | /* This will need to be dynamically assigned */ | |
e3cf6951 BH |
223 | dev_info(&intel_private.pcidev->dev, |
224 | "detected 4MB dedicated video ram\n"); | |
c4ca8817 | 225 | intel_private.num_dcache_entries = 1024; |
1da177e4 | 226 | } |
c4ca8817 | 227 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 | 228 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
c4ca8817 WZ |
229 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
230 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
231 | |
232 | if (agp_bridge->driver->needs_scratch_page) { | |
233 | for (i = 0; i < current_size->num_entries; i++) { | |
c4ca8817 | 234 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 235 | } |
44d49441 | 236 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ |
1da177e4 LT |
237 | } |
238 | global_cache_flush(); | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static void intel_i810_cleanup(void) | |
243 | { | |
c4ca8817 WZ |
244 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
245 | readl(intel_private.registers); /* PCI Posting. */ | |
246 | iounmap(intel_private.registers); | |
1da177e4 LT |
247 | } |
248 | ||
249 | static void intel_i810_tlbflush(struct agp_memory *mem) | |
250 | { | |
251 | return; | |
252 | } | |
253 | ||
254 | static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
255 | { | |
256 | return; | |
257 | } | |
258 | ||
259 | /* Exists to support ARGB cursors */ | |
07613ba2 | 260 | static struct page *i8xx_alloc_pages(void) |
1da177e4 | 261 | { |
f011ae74 | 262 | struct page *page; |
1da177e4 | 263 | |
66c669ba | 264 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
1da177e4 LT |
265 | if (page == NULL) |
266 | return NULL; | |
267 | ||
6d238cc4 AV |
268 | if (set_pages_uc(page, 4) < 0) { |
269 | set_pages_wb(page, 4); | |
89cf7ccc | 270 | __free_pages(page, 2); |
1da177e4 LT |
271 | return NULL; |
272 | } | |
1da177e4 | 273 | get_page(page); |
1da177e4 | 274 | atomic_inc(&agp_bridge->current_memory_agp); |
07613ba2 | 275 | return page; |
1da177e4 LT |
276 | } |
277 | ||
07613ba2 | 278 | static void i8xx_destroy_pages(struct page *page) |
1da177e4 | 279 | { |
07613ba2 | 280 | if (page == NULL) |
1da177e4 LT |
281 | return; |
282 | ||
6d238cc4 | 283 | set_pages_wb(page, 4); |
1da177e4 | 284 | put_page(page); |
89cf7ccc | 285 | __free_pages(page, 2); |
1da177e4 LT |
286 | atomic_dec(&agp_bridge->current_memory_agp); |
287 | } | |
288 | ||
a030ce44 TH |
289 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, |
290 | int type) | |
291 | { | |
292 | if (type < AGP_USER_TYPES) | |
293 | return type; | |
294 | else if (type == AGP_USER_CACHED_MEMORY) | |
295 | return INTEL_AGP_CACHED_MEMORY; | |
296 | else | |
297 | return 0; | |
298 | } | |
299 | ||
1da177e4 LT |
300 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
301 | int type) | |
302 | { | |
303 | int i, j, num_entries; | |
304 | void *temp; | |
a030ce44 TH |
305 | int ret = -EINVAL; |
306 | int mask_type; | |
1da177e4 | 307 | |
5aa80c72 | 308 | if (mem->page_count == 0) |
a030ce44 | 309 | goto out; |
5aa80c72 | 310 | |
1da177e4 LT |
311 | temp = agp_bridge->current_size; |
312 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
313 | ||
6a92a4e0 | 314 | if ((pg_start + mem->page_count) > num_entries) |
a030ce44 | 315 | goto out_err; |
6a92a4e0 | 316 | |
1da177e4 | 317 | |
a030ce44 TH |
318 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { |
319 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
320 | ret = -EBUSY; | |
321 | goto out_err; | |
1da177e4 | 322 | } |
1da177e4 LT |
323 | } |
324 | ||
a030ce44 TH |
325 | if (type != mem->type) |
326 | goto out_err; | |
5aa80c72 | 327 | |
a030ce44 TH |
328 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); |
329 | ||
330 | switch (mask_type) { | |
331 | case AGP_DCACHE_MEMORY: | |
332 | if (!mem->is_flushed) | |
333 | global_cache_flush(); | |
334 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
335 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
c4ca8817 | 336 | intel_private.registers+I810_PTE_BASE+(i*4)); |
a030ce44 | 337 | } |
c4ca8817 | 338 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
a030ce44 TH |
339 | break; |
340 | case AGP_PHYS_MEMORY: | |
341 | case AGP_NORMAL_MEMORY: | |
342 | if (!mem->is_flushed) | |
343 | global_cache_flush(); | |
344 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
345 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
2a4ceb6d | 346 | phys_to_gart(page_to_phys(mem->pages[i])), |
a030ce44 | 347 | mask_type), |
c4ca8817 | 348 | intel_private.registers+I810_PTE_BASE+(j*4)); |
a030ce44 | 349 | } |
c4ca8817 | 350 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
a030ce44 TH |
351 | break; |
352 | default: | |
353 | goto out_err; | |
1da177e4 | 354 | } |
1da177e4 LT |
355 | |
356 | agp_bridge->driver->tlb_flush(mem); | |
a030ce44 TH |
357 | out: |
358 | ret = 0; | |
359 | out_err: | |
9516b030 | 360 | mem->is_flushed = true; |
a030ce44 | 361 | return ret; |
1da177e4 LT |
362 | } |
363 | ||
364 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
365 | int type) | |
366 | { | |
367 | int i; | |
368 | ||
5aa80c72 TH |
369 | if (mem->page_count == 0) |
370 | return 0; | |
371 | ||
1da177e4 | 372 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
c4ca8817 | 373 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 374 | } |
c4ca8817 | 375 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 376 | |
1da177e4 LT |
377 | agp_bridge->driver->tlb_flush(mem); |
378 | return 0; | |
379 | } | |
380 | ||
381 | /* | |
382 | * The i810/i830 requires a physical address to program its mouse | |
383 | * pointer into hardware. | |
384 | * However the Xserver still writes to it through the agp aperture. | |
385 | */ | |
386 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
387 | { | |
388 | struct agp_memory *new; | |
07613ba2 | 389 | struct page *page; |
1da177e4 | 390 | |
1da177e4 | 391 | switch (pg_count) { |
07613ba2 | 392 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
1da177e4 LT |
393 | break; |
394 | case 4: | |
395 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 | 396 | page = i8xx_alloc_pages(); |
1da177e4 LT |
397 | break; |
398 | default: | |
399 | return NULL; | |
400 | } | |
401 | ||
07613ba2 | 402 | if (page == NULL) |
1da177e4 LT |
403 | return NULL; |
404 | ||
405 | new = agp_create_memory(pg_count); | |
406 | if (new == NULL) | |
407 | return NULL; | |
408 | ||
07613ba2 | 409 | new->pages[0] = page; |
1da177e4 LT |
410 | if (pg_count == 4) { |
411 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 DA |
412 | new->pages[1] = new->pages[0] + 1; |
413 | new->pages[2] = new->pages[1] + 1; | |
414 | new->pages[3] = new->pages[2] + 1; | |
1da177e4 LT |
415 | } |
416 | new->page_count = pg_count; | |
417 | new->num_scratch_pages = pg_count; | |
418 | new->type = AGP_PHYS_MEMORY; | |
07613ba2 | 419 | new->physical = page_to_phys(new->pages[0]); |
1da177e4 LT |
420 | return new; |
421 | } | |
422 | ||
423 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
424 | { | |
425 | struct agp_memory *new; | |
426 | ||
427 | if (type == AGP_DCACHE_MEMORY) { | |
c4ca8817 | 428 | if (pg_count != intel_private.num_dcache_entries) |
1da177e4 LT |
429 | return NULL; |
430 | ||
431 | new = agp_create_memory(1); | |
432 | if (new == NULL) | |
433 | return NULL; | |
434 | ||
435 | new->type = AGP_DCACHE_MEMORY; | |
436 | new->page_count = pg_count; | |
437 | new->num_scratch_pages = 0; | |
a030ce44 | 438 | agp_free_page_array(new); |
1da177e4 LT |
439 | return new; |
440 | } | |
441 | if (type == AGP_PHYS_MEMORY) | |
442 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
443 | return NULL; |
444 | } | |
445 | ||
446 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
447 | { | |
448 | agp_free_key(curr->key); | |
6a92a4e0 | 449 | if (curr->type == AGP_PHYS_MEMORY) { |
1da177e4 | 450 | if (curr->page_count == 4) |
07613ba2 | 451 | i8xx_destroy_pages(curr->pages[0]); |
88d51967 | 452 | else { |
07613ba2 | 453 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 454 | AGP_PAGE_DESTROY_UNMAP); |
07613ba2 | 455 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 456 | AGP_PAGE_DESTROY_FREE); |
88d51967 | 457 | } |
a030ce44 | 458 | agp_free_page_array(curr); |
1da177e4 LT |
459 | } |
460 | kfree(curr); | |
461 | } | |
462 | ||
463 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 464 | dma_addr_t addr, int type) |
1da177e4 LT |
465 | { |
466 | /* Type checking must be done elsewhere */ | |
467 | return addr | bridge->driver->masks[type].mask; | |
468 | } | |
469 | ||
470 | static struct aper_size_info_fixed intel_i830_sizes[] = | |
471 | { | |
472 | {128, 32768, 5}, | |
473 | /* The 64M mode still requires a 128k gatt */ | |
474 | {64, 16384, 5}, | |
475 | {256, 65536, 6}, | |
65c25aad | 476 | {512, 131072, 7}, |
1da177e4 LT |
477 | }; |
478 | ||
1da177e4 LT |
479 | static void intel_i830_init_gtt_entries(void) |
480 | { | |
481 | u16 gmch_ctrl; | |
482 | int gtt_entries; | |
483 | u8 rdct; | |
484 | int local = 0; | |
485 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
c41e0deb | 486 | int size; /* reserved space (in kb) at the top of stolen memory */ |
1da177e4 | 487 | |
f011ae74 | 488 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 489 | |
c41e0deb EA |
490 | if (IS_I965) { |
491 | u32 pgetbl_ctl; | |
c4ca8817 | 492 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
c41e0deb | 493 | |
c41e0deb EA |
494 | /* The 965 has a field telling us the size of the GTT, |
495 | * which may be larger than what is necessary to map the | |
496 | * aperture. | |
497 | */ | |
498 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
499 | case I965_PGETBL_SIZE_128KB: | |
500 | size = 128; | |
501 | break; | |
502 | case I965_PGETBL_SIZE_256KB: | |
503 | size = 256; | |
504 | break; | |
505 | case I965_PGETBL_SIZE_512KB: | |
506 | size = 512; | |
507 | break; | |
4e8b6e25 ZW |
508 | case I965_PGETBL_SIZE_1MB: |
509 | size = 1024; | |
510 | break; | |
511 | case I965_PGETBL_SIZE_2MB: | |
512 | size = 2048; | |
513 | break; | |
514 | case I965_PGETBL_SIZE_1_5MB: | |
515 | size = 1024 + 512; | |
516 | break; | |
c41e0deb | 517 | default: |
e3cf6951 BH |
518 | dev_info(&intel_private.pcidev->dev, |
519 | "unknown page table size, assuming 512KB\n"); | |
c41e0deb EA |
520 | size = 512; |
521 | } | |
522 | size += 4; /* add in BIOS popup space */ | |
2177832f | 523 | } else if (IS_G33 && !IS_IGD) { |
874808c6 WZ |
524 | /* G33's GTT size defined in gmch_ctrl */ |
525 | switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { | |
526 | case G33_PGETBL_SIZE_1M: | |
527 | size = 1024; | |
528 | break; | |
529 | case G33_PGETBL_SIZE_2M: | |
530 | size = 2048; | |
531 | break; | |
532 | default: | |
e3cf6951 BH |
533 | dev_info(&agp_bridge->dev->dev, |
534 | "unknown page table size 0x%x, assuming 512KB\n", | |
874808c6 WZ |
535 | (gmch_ctrl & G33_PGETBL_SIZE_MASK)); |
536 | size = 512; | |
537 | } | |
538 | size += 4; | |
2177832f | 539 | } else if (IS_G4X || IS_IGD) { |
25ce77ab | 540 | /* On 4 series hardware, GTT stolen is separate from graphics |
82e14a62 EA |
541 | * stolen, ignore it in stolen gtt entries counting. However, |
542 | * 4KB of the stolen memory doesn't get mapped to the GTT. | |
543 | */ | |
544 | size = 4; | |
c41e0deb EA |
545 | } else { |
546 | /* On previous hardware, the GTT size was just what was | |
547 | * required to map the aperture. | |
548 | */ | |
549 | size = agp_bridge->driver->fetch_size() + 4; | |
550 | } | |
1da177e4 LT |
551 | |
552 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || | |
553 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
554 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { | |
555 | case I830_GMCH_GMS_STOLEN_512: | |
556 | gtt_entries = KB(512) - KB(size); | |
557 | break; | |
558 | case I830_GMCH_GMS_STOLEN_1024: | |
559 | gtt_entries = MB(1) - KB(size); | |
560 | break; | |
561 | case I830_GMCH_GMS_STOLEN_8192: | |
562 | gtt_entries = MB(8) - KB(size); | |
563 | break; | |
564 | case I830_GMCH_GMS_LOCAL: | |
c4ca8817 | 565 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
1da177e4 LT |
566 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
567 | MB(ddt[I830_RDRAM_DDT(rdct)]); | |
568 | local = 1; | |
569 | break; | |
570 | default: | |
571 | gtt_entries = 0; | |
572 | break; | |
573 | } | |
574 | } else { | |
e67aa27a | 575 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
1da177e4 LT |
576 | case I855_GMCH_GMS_STOLEN_1M: |
577 | gtt_entries = MB(1) - KB(size); | |
578 | break; | |
579 | case I855_GMCH_GMS_STOLEN_4M: | |
580 | gtt_entries = MB(4) - KB(size); | |
581 | break; | |
582 | case I855_GMCH_GMS_STOLEN_8M: | |
583 | gtt_entries = MB(8) - KB(size); | |
584 | break; | |
585 | case I855_GMCH_GMS_STOLEN_16M: | |
586 | gtt_entries = MB(16) - KB(size); | |
587 | break; | |
588 | case I855_GMCH_GMS_STOLEN_32M: | |
589 | gtt_entries = MB(32) - KB(size); | |
590 | break; | |
591 | case I915_GMCH_GMS_STOLEN_48M: | |
592 | /* Check it's really I915G */ | |
25ce77ab | 593 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
594 | gtt_entries = MB(48) - KB(size); |
595 | else | |
596 | gtt_entries = 0; | |
597 | break; | |
598 | case I915_GMCH_GMS_STOLEN_64M: | |
599 | /* Check it's really I915G */ | |
25ce77ab | 600 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
601 | gtt_entries = MB(64) - KB(size); |
602 | else | |
603 | gtt_entries = 0; | |
874808c6 WZ |
604 | break; |
605 | case G33_GMCH_GMS_STOLEN_128M: | |
25ce77ab | 606 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
607 | gtt_entries = MB(128) - KB(size); |
608 | else | |
609 | gtt_entries = 0; | |
610 | break; | |
611 | case G33_GMCH_GMS_STOLEN_256M: | |
25ce77ab | 612 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
613 | gtt_entries = MB(256) - KB(size); |
614 | else | |
615 | gtt_entries = 0; | |
616 | break; | |
25ce77ab ZW |
617 | case INTEL_GMCH_GMS_STOLEN_96M: |
618 | if (IS_I965 || IS_G4X) | |
619 | gtt_entries = MB(96) - KB(size); | |
620 | else | |
621 | gtt_entries = 0; | |
622 | break; | |
623 | case INTEL_GMCH_GMS_STOLEN_160M: | |
624 | if (IS_I965 || IS_G4X) | |
625 | gtt_entries = MB(160) - KB(size); | |
626 | else | |
627 | gtt_entries = 0; | |
628 | break; | |
629 | case INTEL_GMCH_GMS_STOLEN_224M: | |
630 | if (IS_I965 || IS_G4X) | |
631 | gtt_entries = MB(224) - KB(size); | |
632 | else | |
633 | gtt_entries = 0; | |
634 | break; | |
635 | case INTEL_GMCH_GMS_STOLEN_352M: | |
636 | if (IS_I965 || IS_G4X) | |
637 | gtt_entries = MB(352) - KB(size); | |
638 | else | |
639 | gtt_entries = 0; | |
640 | break; | |
1da177e4 LT |
641 | default: |
642 | gtt_entries = 0; | |
643 | break; | |
644 | } | |
645 | } | |
9c1e8a4e | 646 | if (gtt_entries > 0) { |
e3cf6951 | 647 | dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", |
1da177e4 | 648 | gtt_entries / KB(1), local ? "local" : "stolen"); |
9c1e8a4e LR |
649 | gtt_entries /= KB(4); |
650 | } else { | |
e3cf6951 BH |
651 | dev_info(&agp_bridge->dev->dev, |
652 | "no pre-allocated video memory detected\n"); | |
9c1e8a4e LR |
653 | gtt_entries = 0; |
654 | } | |
1da177e4 | 655 | |
c4ca8817 | 656 | intel_private.gtt_entries = gtt_entries; |
1da177e4 LT |
657 | } |
658 | ||
2162e6a2 DA |
659 | static void intel_i830_fini_flush(void) |
660 | { | |
661 | kunmap(intel_private.i8xx_page); | |
662 | intel_private.i8xx_flush_page = NULL; | |
663 | unmap_page_from_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
664 | |
665 | __free_page(intel_private.i8xx_page); | |
4d64dd9e | 666 | intel_private.i8xx_page = NULL; |
2162e6a2 DA |
667 | } |
668 | ||
669 | static void intel_i830_setup_flush(void) | |
670 | { | |
4d64dd9e DA |
671 | /* return if we've already set the flush mechanism up */ |
672 | if (intel_private.i8xx_page) | |
673 | return; | |
2162e6a2 DA |
674 | |
675 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
f011ae74 | 676 | if (!intel_private.i8xx_page) |
2162e6a2 | 677 | return; |
2162e6a2 DA |
678 | |
679 | /* make page uncached */ | |
680 | map_page_into_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
681 | |
682 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); | |
683 | if (!intel_private.i8xx_flush_page) | |
684 | intel_i830_fini_flush(); | |
685 | } | |
686 | ||
687 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) | |
688 | { | |
689 | unsigned int *pg = intel_private.i8xx_flush_page; | |
690 | int i; | |
691 | ||
f011ae74 | 692 | for (i = 0; i < 256; i += 2) |
2162e6a2 | 693 | *(pg + i) = i; |
f011ae74 | 694 | |
2162e6a2 DA |
695 | wmb(); |
696 | } | |
697 | ||
1da177e4 LT |
698 | /* The intel i830 automatically initializes the agp aperture during POST. |
699 | * Use the memory already set aside for in the GTT. | |
700 | */ | |
701 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
702 | { | |
703 | int page_order; | |
704 | struct aper_size_info_fixed *size; | |
705 | int num_entries; | |
706 | u32 temp; | |
707 | ||
708 | size = agp_bridge->current_size; | |
709 | page_order = size->page_order; | |
710 | num_entries = size->num_entries; | |
711 | agp_bridge->gatt_table_real = NULL; | |
712 | ||
f011ae74 | 713 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); |
1da177e4 LT |
714 | temp &= 0xfff80000; |
715 | ||
f011ae74 | 716 | intel_private.registers = ioremap(temp, 128 * 4096); |
c4ca8817 | 717 | if (!intel_private.registers) |
1da177e4 LT |
718 | return -ENOMEM; |
719 | ||
c4ca8817 | 720 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
721 | global_cache_flush(); /* FIXME: ?? */ |
722 | ||
723 | /* we have to call this as early as possible after the MMIO base address is known */ | |
724 | intel_i830_init_gtt_entries(); | |
725 | ||
726 | agp_bridge->gatt_table = NULL; | |
727 | ||
728 | agp_bridge->gatt_bus_addr = temp; | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | /* Return the gatt table to a sane state. Use the top of stolen | |
734 | * memory for the GTT. | |
735 | */ | |
736 | static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) | |
737 | { | |
738 | return 0; | |
739 | } | |
740 | ||
741 | static int intel_i830_fetch_size(void) | |
742 | { | |
743 | u16 gmch_ctrl; | |
744 | struct aper_size_info_fixed *values; | |
745 | ||
746 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
747 | ||
748 | if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && | |
749 | agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { | |
750 | /* 855GM/852GM/865G has 128MB aperture size */ | |
751 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
752 | agp_bridge->aperture_size_idx = 0; | |
753 | return values[0].size; | |
754 | } | |
755 | ||
f011ae74 | 756 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 LT |
757 | |
758 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { | |
759 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
760 | agp_bridge->aperture_size_idx = 0; | |
761 | return values[0].size; | |
762 | } else { | |
763 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); | |
764 | agp_bridge->aperture_size_idx = 1; | |
765 | return values[1].size; | |
766 | } | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
771 | static int intel_i830_configure(void) | |
772 | { | |
773 | struct aper_size_info_fixed *current_size; | |
774 | u32 temp; | |
775 | u16 gmch_ctrl; | |
776 | int i; | |
777 | ||
778 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
779 | ||
f011ae74 | 780 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 LT |
781 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
782 | ||
f011ae74 | 783 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 784 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 785 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 786 | |
c4ca8817 WZ |
787 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
788 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
789 | |
790 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
791 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
792 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
1da177e4 | 793 | } |
44d49441 | 794 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ |
1da177e4 LT |
795 | } |
796 | ||
797 | global_cache_flush(); | |
2162e6a2 DA |
798 | |
799 | intel_i830_setup_flush(); | |
1da177e4 LT |
800 | return 0; |
801 | } | |
802 | ||
803 | static void intel_i830_cleanup(void) | |
804 | { | |
c4ca8817 | 805 | iounmap(intel_private.registers); |
1da177e4 LT |
806 | } |
807 | ||
f011ae74 DA |
808 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
809 | int type) | |
1da177e4 | 810 | { |
f011ae74 | 811 | int i, j, num_entries; |
1da177e4 | 812 | void *temp; |
a030ce44 TH |
813 | int ret = -EINVAL; |
814 | int mask_type; | |
1da177e4 | 815 | |
5aa80c72 | 816 | if (mem->page_count == 0) |
a030ce44 | 817 | goto out; |
5aa80c72 | 818 | |
1da177e4 LT |
819 | temp = agp_bridge->current_size; |
820 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
821 | ||
c4ca8817 | 822 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
823 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
824 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
825 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 826 | |
e3cf6951 BH |
827 | dev_info(&intel_private.pcidev->dev, |
828 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 829 | goto out_err; |
1da177e4 LT |
830 | } |
831 | ||
832 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 833 | goto out_err; |
1da177e4 LT |
834 | |
835 | /* The i830 can't check the GTT for entries since its read only, | |
836 | * depend on the caller to make the correct offset decisions. | |
837 | */ | |
838 | ||
a030ce44 TH |
839 | if (type != mem->type) |
840 | goto out_err; | |
841 | ||
842 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 843 | |
a030ce44 TH |
844 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
845 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
846 | goto out_err; | |
847 | ||
848 | if (!mem->is_flushed) | |
5aa80c72 | 849 | global_cache_flush(); |
1da177e4 LT |
850 | |
851 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
852 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
2a4ceb6d | 853 | phys_to_gart(page_to_phys(mem->pages[i])), mask_type), |
c4ca8817 | 854 | intel_private.registers+I810_PTE_BASE+(j*4)); |
1da177e4 | 855 | } |
c4ca8817 | 856 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
1da177e4 | 857 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
858 | |
859 | out: | |
860 | ret = 0; | |
861 | out_err: | |
9516b030 | 862 | mem->is_flushed = true; |
a030ce44 | 863 | return ret; |
1da177e4 LT |
864 | } |
865 | ||
f011ae74 DA |
866 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, |
867 | int type) | |
1da177e4 LT |
868 | { |
869 | int i; | |
870 | ||
5aa80c72 TH |
871 | if (mem->page_count == 0) |
872 | return 0; | |
1da177e4 | 873 | |
c4ca8817 | 874 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
875 | dev_info(&intel_private.pcidev->dev, |
876 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
877 | return -EINVAL; |
878 | } | |
879 | ||
880 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 881 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 882 | } |
c4ca8817 | 883 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 884 | |
1da177e4 LT |
885 | agp_bridge->driver->tlb_flush(mem); |
886 | return 0; | |
887 | } | |
888 | ||
f011ae74 | 889 | static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) |
1da177e4 LT |
890 | { |
891 | if (type == AGP_PHYS_MEMORY) | |
892 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
893 | /* always return NULL for other allocation types for now */ |
894 | return NULL; | |
895 | } | |
896 | ||
6c00a61e DA |
897 | static int intel_alloc_chipset_flush_resource(void) |
898 | { | |
899 | int ret; | |
900 | ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, | |
901 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, | |
902 | pcibios_align_resource, agp_bridge->dev); | |
6c00a61e | 903 | |
2162e6a2 | 904 | return ret; |
6c00a61e DA |
905 | } |
906 | ||
907 | static void intel_i915_setup_chipset_flush(void) | |
908 | { | |
909 | int ret; | |
910 | u32 temp; | |
911 | ||
912 | pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); | |
913 | if (!(temp & 0x1)) { | |
914 | intel_alloc_chipset_flush_resource(); | |
4d64dd9e | 915 | intel_private.resource_valid = 1; |
6c00a61e DA |
916 | pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
917 | } else { | |
918 | temp &= ~1; | |
919 | ||
4d64dd9e | 920 | intel_private.resource_valid = 1; |
6c00a61e DA |
921 | intel_private.ifp_resource.start = temp; |
922 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
923 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
924 | /* some BIOSes reserve this area in a pnp some don't */ |
925 | if (ret) | |
926 | intel_private.resource_valid = 0; | |
6c00a61e DA |
927 | } |
928 | } | |
929 | ||
930 | static void intel_i965_g33_setup_chipset_flush(void) | |
931 | { | |
932 | u32 temp_hi, temp_lo; | |
933 | int ret; | |
934 | ||
935 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); | |
936 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); | |
937 | ||
938 | if (!(temp_lo & 0x1)) { | |
939 | ||
940 | intel_alloc_chipset_flush_resource(); | |
941 | ||
4d64dd9e | 942 | intel_private.resource_valid = 1; |
1fa4db7d AM |
943 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, |
944 | upper_32_bits(intel_private.ifp_resource.start)); | |
6c00a61e | 945 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
6c00a61e DA |
946 | } else { |
947 | u64 l64; | |
f011ae74 | 948 | |
6c00a61e DA |
949 | temp_lo &= ~0x1; |
950 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
951 | ||
4d64dd9e | 952 | intel_private.resource_valid = 1; |
6c00a61e DA |
953 | intel_private.ifp_resource.start = l64; |
954 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
955 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
956 | /* some BIOSes reserve this area in a pnp some don't */ |
957 | if (ret) | |
958 | intel_private.resource_valid = 0; | |
6c00a61e DA |
959 | } |
960 | } | |
961 | ||
2162e6a2 DA |
962 | static void intel_i9xx_setup_flush(void) |
963 | { | |
4d64dd9e DA |
964 | /* return if already configured */ |
965 | if (intel_private.ifp_resource.start) | |
966 | return; | |
2162e6a2 | 967 | |
4d64dd9e | 968 | /* setup a resource for this object */ |
2162e6a2 DA |
969 | intel_private.ifp_resource.name = "Intel Flush Page"; |
970 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
971 | ||
972 | /* Setup chipset flush for 915 */ | |
7d15ddf7 | 973 | if (IS_I965 || IS_G33 || IS_G4X) { |
2162e6a2 DA |
974 | intel_i965_g33_setup_chipset_flush(); |
975 | } else { | |
976 | intel_i915_setup_chipset_flush(); | |
977 | } | |
978 | ||
979 | if (intel_private.ifp_resource.start) { | |
980 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
981 | if (!intel_private.i9xx_flush_page) | |
e3cf6951 | 982 | dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); |
2162e6a2 DA |
983 | } |
984 | } | |
985 | ||
1da177e4 LT |
986 | static int intel_i915_configure(void) |
987 | { | |
988 | struct aper_size_info_fixed *current_size; | |
989 | u32 temp; | |
990 | u16 gmch_ctrl; | |
991 | int i; | |
992 | ||
993 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
994 | ||
c4ca8817 | 995 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
1da177e4 LT |
996 | |
997 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
998 | ||
f011ae74 | 999 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 1000 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 1001 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 1002 | |
c4ca8817 WZ |
1003 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
1004 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
1005 | |
1006 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
1007 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
1008 | writel(agp_bridge->scratch_page, intel_private.gtt+i); | |
1da177e4 | 1009 | } |
44d49441 | 1010 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
1da177e4 LT |
1011 | } |
1012 | ||
1013 | global_cache_flush(); | |
6c00a61e | 1014 | |
2162e6a2 | 1015 | intel_i9xx_setup_flush(); |
f011ae74 | 1016 | |
1da177e4 LT |
1017 | return 0; |
1018 | } | |
1019 | ||
1020 | static void intel_i915_cleanup(void) | |
1021 | { | |
2162e6a2 DA |
1022 | if (intel_private.i9xx_flush_page) |
1023 | iounmap(intel_private.i9xx_flush_page); | |
4d64dd9e DA |
1024 | if (intel_private.resource_valid) |
1025 | release_resource(&intel_private.ifp_resource); | |
1026 | intel_private.ifp_resource.start = 0; | |
1027 | intel_private.resource_valid = 0; | |
c4ca8817 WZ |
1028 | iounmap(intel_private.gtt); |
1029 | iounmap(intel_private.registers); | |
1da177e4 LT |
1030 | } |
1031 | ||
6c00a61e DA |
1032 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) |
1033 | { | |
2162e6a2 DA |
1034 | if (intel_private.i9xx_flush_page) |
1035 | writel(1, intel_private.i9xx_flush_page); | |
6c00a61e DA |
1036 | } |
1037 | ||
f011ae74 DA |
1038 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, |
1039 | int type) | |
1da177e4 | 1040 | { |
f011ae74 | 1041 | int i, j, num_entries; |
1da177e4 | 1042 | void *temp; |
a030ce44 TH |
1043 | int ret = -EINVAL; |
1044 | int mask_type; | |
1da177e4 | 1045 | |
5aa80c72 | 1046 | if (mem->page_count == 0) |
a030ce44 | 1047 | goto out; |
5aa80c72 | 1048 | |
1da177e4 LT |
1049 | temp = agp_bridge->current_size; |
1050 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1051 | ||
c4ca8817 | 1052 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1053 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
1054 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
1055 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1056 | |
e3cf6951 BH |
1057 | dev_info(&intel_private.pcidev->dev, |
1058 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 1059 | goto out_err; |
1da177e4 LT |
1060 | } |
1061 | ||
1062 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1063 | goto out_err; |
1da177e4 | 1064 | |
a030ce44 | 1065 | /* The i915 can't check the GTT for entries since its read only, |
1da177e4 LT |
1066 | * depend on the caller to make the correct offset decisions. |
1067 | */ | |
1068 | ||
a030ce44 TH |
1069 | if (type != mem->type) |
1070 | goto out_err; | |
1071 | ||
1072 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1073 | |
a030ce44 TH |
1074 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1075 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1076 | goto out_err; | |
1077 | ||
1078 | if (!mem->is_flushed) | |
5aa80c72 | 1079 | global_cache_flush(); |
1da177e4 LT |
1080 | |
1081 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1082 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
2a4ceb6d DW |
1083 | phys_to_gart(page_to_phys(mem->pages[i])), |
1084 | mask_type), | |
1085 | intel_private.gtt+j); | |
1da177e4 LT |
1086 | } |
1087 | ||
c4ca8817 | 1088 | readl(intel_private.gtt+j-1); |
1da177e4 | 1089 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1090 | |
1091 | out: | |
1092 | ret = 0; | |
1093 | out_err: | |
9516b030 | 1094 | mem->is_flushed = true; |
a030ce44 | 1095 | return ret; |
1da177e4 LT |
1096 | } |
1097 | ||
f011ae74 DA |
1098 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, |
1099 | int type) | |
1da177e4 LT |
1100 | { |
1101 | int i; | |
1102 | ||
5aa80c72 TH |
1103 | if (mem->page_count == 0) |
1104 | return 0; | |
1da177e4 | 1105 | |
c4ca8817 | 1106 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1107 | dev_info(&intel_private.pcidev->dev, |
1108 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1109 | return -EINVAL; |
1110 | } | |
1111 | ||
f011ae74 | 1112 | for (i = pg_start; i < (mem->page_count + pg_start); i++) |
c4ca8817 | 1113 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f011ae74 | 1114 | |
c4ca8817 | 1115 | readl(intel_private.gtt+i-1); |
1da177e4 | 1116 | |
1da177e4 LT |
1117 | agp_bridge->driver->tlb_flush(mem); |
1118 | return 0; | |
1119 | } | |
1120 | ||
c41e0deb EA |
1121 | /* Return the aperture size by just checking the resource length. The effect |
1122 | * described in the spec of the MSAC registers is just changing of the | |
1123 | * resource size. | |
1124 | */ | |
1125 | static int intel_i9xx_fetch_size(void) | |
1da177e4 | 1126 | { |
1eaf122c | 1127 | int num_sizes = ARRAY_SIZE(intel_i830_sizes); |
c41e0deb EA |
1128 | int aper_size; /* size in megabytes */ |
1129 | int i; | |
1da177e4 | 1130 | |
c4ca8817 | 1131 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
1da177e4 | 1132 | |
c41e0deb EA |
1133 | for (i = 0; i < num_sizes; i++) { |
1134 | if (aper_size == intel_i830_sizes[i].size) { | |
1135 | agp_bridge->current_size = intel_i830_sizes + i; | |
1136 | agp_bridge->previous_size = agp_bridge->current_size; | |
1137 | return aper_size; | |
1138 | } | |
1139 | } | |
1da177e4 | 1140 | |
c41e0deb | 1141 | return 0; |
1da177e4 LT |
1142 | } |
1143 | ||
1144 | /* The intel i915 automatically initializes the agp aperture during POST. | |
1145 | * Use the memory already set aside for in the GTT. | |
1146 | */ | |
1147 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1148 | { | |
1149 | int page_order; | |
1150 | struct aper_size_info_fixed *size; | |
1151 | int num_entries; | |
1152 | u32 temp, temp2; | |
4740622c | 1153 | int gtt_map_size = 256 * 1024; |
1da177e4 LT |
1154 | |
1155 | size = agp_bridge->current_size; | |
1156 | page_order = size->page_order; | |
1157 | num_entries = size->num_entries; | |
1158 | agp_bridge->gatt_table_real = NULL; | |
1159 | ||
c4ca8817 | 1160 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
f011ae74 | 1161 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); |
1da177e4 | 1162 | |
4740622c ZW |
1163 | if (IS_G33) |
1164 | gtt_map_size = 1024 * 1024; /* 1M on G33 */ | |
1165 | intel_private.gtt = ioremap(temp2, gtt_map_size); | |
c4ca8817 | 1166 | if (!intel_private.gtt) |
1da177e4 LT |
1167 | return -ENOMEM; |
1168 | ||
1169 | temp &= 0xfff80000; | |
1170 | ||
f011ae74 | 1171 | intel_private.registers = ioremap(temp, 128 * 4096); |
5bdbc7dc ST |
1172 | if (!intel_private.registers) { |
1173 | iounmap(intel_private.gtt); | |
1da177e4 | 1174 | return -ENOMEM; |
5bdbc7dc | 1175 | } |
1da177e4 | 1176 | |
c4ca8817 | 1177 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
1178 | global_cache_flush(); /* FIXME: ? */ |
1179 | ||
1180 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1181 | intel_i830_init_gtt_entries(); | |
1182 | ||
1183 | agp_bridge->gatt_table = NULL; | |
1184 | ||
1185 | agp_bridge->gatt_bus_addr = temp; | |
1186 | ||
1187 | return 0; | |
1188 | } | |
7d915a38 LT |
1189 | |
1190 | /* | |
1191 | * The i965 supports 36-bit physical addresses, but to keep | |
1192 | * the format of the GTT the same, the bits that don't fit | |
1193 | * in a 32-bit word are shifted down to bits 4..7. | |
1194 | * | |
1195 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1196 | * is always zero on 32-bit architectures, so no need to make | |
1197 | * this conditional. | |
1198 | */ | |
1199 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 1200 | dma_addr_t addr, int type) |
7d915a38 LT |
1201 | { |
1202 | /* Shift high bits down */ | |
1203 | addr |= (addr >> 28) & 0xf0; | |
1204 | ||
1205 | /* Type checking must be done elsewhere */ | |
1206 | return addr | bridge->driver->masks[type].mask; | |
1207 | } | |
1208 | ||
25ce77ab ZW |
1209 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) |
1210 | { | |
1211 | switch (agp_bridge->dev->device) { | |
99d32bd5 | 1212 | case PCI_DEVICE_ID_INTEL_GM45_HB: |
25ce77ab ZW |
1213 | case PCI_DEVICE_ID_INTEL_IGD_E_HB: |
1214 | case PCI_DEVICE_ID_INTEL_Q45_HB: | |
1215 | case PCI_DEVICE_ID_INTEL_G45_HB: | |
a50ccc6c | 1216 | case PCI_DEVICE_ID_INTEL_G41_HB: |
32cb055b ZW |
1217 | case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: |
1218 | case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: | |
25ce77ab ZW |
1219 | *gtt_offset = *gtt_size = MB(2); |
1220 | break; | |
1221 | default: | |
1222 | *gtt_offset = *gtt_size = KB(512); | |
1223 | } | |
1224 | } | |
1225 | ||
65c25aad | 1226 | /* The intel i965 automatically initializes the agp aperture during POST. |
c41e0deb EA |
1227 | * Use the memory already set aside for in the GTT. |
1228 | */ | |
65c25aad EA |
1229 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1230 | { | |
62c96b9d DA |
1231 | int page_order; |
1232 | struct aper_size_info_fixed *size; | |
1233 | int num_entries; | |
1234 | u32 temp; | |
1235 | int gtt_offset, gtt_size; | |
65c25aad | 1236 | |
62c96b9d DA |
1237 | size = agp_bridge->current_size; |
1238 | page_order = size->page_order; | |
1239 | num_entries = size->num_entries; | |
1240 | agp_bridge->gatt_table_real = NULL; | |
65c25aad | 1241 | |
62c96b9d | 1242 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
65c25aad | 1243 | |
62c96b9d | 1244 | temp &= 0xfff00000; |
65c25aad | 1245 | |
25ce77ab | 1246 | intel_i965_get_gtt_range(>t_offset, >t_size); |
4e8b6e25 | 1247 | |
62c96b9d | 1248 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); |
65c25aad | 1249 | |
62c96b9d DA |
1250 | if (!intel_private.gtt) |
1251 | return -ENOMEM; | |
65c25aad | 1252 | |
62c96b9d DA |
1253 | intel_private.registers = ioremap(temp, 128 * 4096); |
1254 | if (!intel_private.registers) { | |
5bdbc7dc ST |
1255 | iounmap(intel_private.gtt); |
1256 | return -ENOMEM; | |
1257 | } | |
65c25aad | 1258 | |
62c96b9d DA |
1259 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1260 | global_cache_flush(); /* FIXME: ? */ | |
65c25aad | 1261 | |
62c96b9d DA |
1262 | /* we have to call this as early as possible after the MMIO base address is known */ |
1263 | intel_i830_init_gtt_entries(); | |
65c25aad | 1264 | |
62c96b9d | 1265 | agp_bridge->gatt_table = NULL; |
65c25aad | 1266 | |
62c96b9d | 1267 | agp_bridge->gatt_bus_addr = temp; |
65c25aad | 1268 | |
62c96b9d | 1269 | return 0; |
65c25aad EA |
1270 | } |
1271 | ||
1da177e4 LT |
1272 | |
1273 | static int intel_fetch_size(void) | |
1274 | { | |
1275 | int i; | |
1276 | u16 temp; | |
1277 | struct aper_size_info_16 *values; | |
1278 | ||
1279 | pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1280 | values = A_SIZE_16(agp_bridge->driver->aperture_sizes); | |
1281 | ||
1282 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1283 | if (temp == values[i].size_value) { | |
1284 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); | |
1285 | agp_bridge->aperture_size_idx = i; | |
1286 | return values[i].size; | |
1287 | } | |
1288 | } | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | static int __intel_8xx_fetch_size(u8 temp) | |
1294 | { | |
1295 | int i; | |
1296 | struct aper_size_info_8 *values; | |
1297 | ||
1298 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
1299 | ||
1300 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1301 | if (temp == values[i].size_value) { | |
1302 | agp_bridge->previous_size = | |
1303 | agp_bridge->current_size = (void *) (values + i); | |
1304 | agp_bridge->aperture_size_idx = i; | |
1305 | return values[i].size; | |
1306 | } | |
1307 | } | |
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | static int intel_8xx_fetch_size(void) | |
1312 | { | |
1313 | u8 temp; | |
1314 | ||
1315 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1316 | return __intel_8xx_fetch_size(temp); | |
1317 | } | |
1318 | ||
1319 | static int intel_815_fetch_size(void) | |
1320 | { | |
1321 | u8 temp; | |
1322 | ||
1323 | /* Intel 815 chipsets have a _weird_ APSIZE register with only | |
1324 | * one non-reserved bit, so mask the others out ... */ | |
1325 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1326 | temp &= (1 << 3); | |
1327 | ||
1328 | return __intel_8xx_fetch_size(temp); | |
1329 | } | |
1330 | ||
1331 | static void intel_tlbflush(struct agp_memory *mem) | |
1332 | { | |
1333 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); | |
1334 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1335 | } | |
1336 | ||
1337 | ||
1338 | static void intel_8xx_tlbflush(struct agp_memory *mem) | |
1339 | { | |
1340 | u32 temp; | |
1341 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1342 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); | |
1343 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1344 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); | |
1345 | } | |
1346 | ||
1347 | ||
1348 | static void intel_cleanup(void) | |
1349 | { | |
1350 | u16 temp; | |
1351 | struct aper_size_info_16 *previous_size; | |
1352 | ||
1353 | previous_size = A_SIZE_16(agp_bridge->previous_size); | |
1354 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1355 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1356 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1357 | } | |
1358 | ||
1359 | ||
1360 | static void intel_8xx_cleanup(void) | |
1361 | { | |
1362 | u16 temp; | |
1363 | struct aper_size_info_8 *previous_size; | |
1364 | ||
1365 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1366 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1367 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1368 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1369 | } | |
1370 | ||
1371 | ||
1372 | static int intel_configure(void) | |
1373 | { | |
1374 | u32 temp; | |
1375 | u16 temp2; | |
1376 | struct aper_size_info_16 *current_size; | |
1377 | ||
1378 | current_size = A_SIZE_16(agp_bridge->current_size); | |
1379 | ||
1380 | /* aperture size */ | |
1381 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1382 | ||
1383 | /* address to map to */ | |
1384 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1385 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1386 | ||
1387 | /* attbase - aperture base */ | |
1388 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1389 | ||
1390 | /* agpctrl */ | |
1391 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1392 | ||
1393 | /* paccfg/nbxcfg */ | |
1394 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1395 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, | |
1396 | (temp2 & ~(1 << 10)) | (1 << 9)); | |
1397 | /* clear any possible error conditions */ | |
1398 | pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); | |
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | static int intel_815_configure(void) | |
1403 | { | |
1404 | u32 temp, addr; | |
1405 | u8 temp2; | |
1406 | struct aper_size_info_8 *current_size; | |
1407 | ||
1408 | /* attbase - aperture base */ | |
1409 | /* the Intel 815 chipset spec. says that bits 29-31 in the | |
1410 | * ATTBASE register are reserved -> try not to write them */ | |
1411 | if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { | |
e3cf6951 | 1412 | dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); |
1da177e4 LT |
1413 | return -EINVAL; |
1414 | } | |
1415 | ||
1416 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1417 | ||
1418 | /* aperture size */ | |
1419 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1420 | current_size->size_value); | |
1421 | ||
1422 | /* address to map to */ | |
1423 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1424 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1425 | ||
1426 | pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); | |
1427 | addr &= INTEL_815_ATTBASE_MASK; | |
1428 | addr |= agp_bridge->gatt_bus_addr; | |
1429 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); | |
1430 | ||
1431 | /* agpctrl */ | |
1432 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1433 | ||
1434 | /* apcont */ | |
1435 | pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); | |
1436 | pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); | |
1437 | ||
1438 | /* clear any possible error conditions */ | |
1439 | /* Oddness : this chipset seems to have no ERRSTS register ! */ | |
1440 | return 0; | |
1441 | } | |
1442 | ||
1443 | static void intel_820_tlbflush(struct agp_memory *mem) | |
1444 | { | |
1445 | return; | |
1446 | } | |
1447 | ||
1448 | static void intel_820_cleanup(void) | |
1449 | { | |
1450 | u8 temp; | |
1451 | struct aper_size_info_8 *previous_size; | |
1452 | ||
1453 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1454 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); | |
1455 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, | |
1456 | temp & ~(1 << 1)); | |
1457 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1458 | previous_size->size_value); | |
1459 | } | |
1460 | ||
1461 | ||
1462 | static int intel_820_configure(void) | |
1463 | { | |
1464 | u32 temp; | |
1465 | u8 temp2; | |
1466 | struct aper_size_info_8 *current_size; | |
1467 | ||
1468 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1469 | ||
1470 | /* aperture size */ | |
1471 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1472 | ||
1473 | /* address to map to */ | |
1474 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1475 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1476 | ||
1477 | /* attbase - aperture base */ | |
1478 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1479 | ||
1480 | /* agpctrl */ | |
1481 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1482 | ||
1483 | /* global enable aperture access */ | |
1484 | /* This flag is not accessed through MCHCFG register as in */ | |
1485 | /* i850 chipset. */ | |
1486 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); | |
1487 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); | |
1488 | /* clear any possible AGP-related error conditions */ | |
1489 | pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); | |
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | static int intel_840_configure(void) | |
1494 | { | |
1495 | u32 temp; | |
1496 | u16 temp2; | |
1497 | struct aper_size_info_8 *current_size; | |
1498 | ||
1499 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1500 | ||
1501 | /* aperture size */ | |
1502 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1503 | ||
1504 | /* address to map to */ | |
1505 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1506 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1507 | ||
1508 | /* attbase - aperture base */ | |
1509 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1510 | ||
1511 | /* agpctrl */ | |
1512 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1513 | ||
1514 | /* mcgcfg */ | |
1515 | pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); | |
1516 | pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); | |
1517 | /* clear any possible error conditions */ | |
1518 | pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); | |
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | static int intel_845_configure(void) | |
1523 | { | |
1524 | u32 temp; | |
1525 | u8 temp2; | |
1526 | struct aper_size_info_8 *current_size; | |
1527 | ||
1528 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1529 | ||
1530 | /* aperture size */ | |
1531 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1532 | ||
b0825488 MG |
1533 | if (agp_bridge->apbase_config != 0) { |
1534 | pci_write_config_dword(agp_bridge->dev, AGP_APBASE, | |
1535 | agp_bridge->apbase_config); | |
1536 | } else { | |
1537 | /* address to map to */ | |
1538 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1539 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1540 | agp_bridge->apbase_config = temp; | |
1541 | } | |
1da177e4 LT |
1542 | |
1543 | /* attbase - aperture base */ | |
1544 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1545 | ||
1546 | /* agpctrl */ | |
1547 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1548 | ||
1549 | /* agpm */ | |
1550 | pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); | |
1551 | pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); | |
1552 | /* clear any possible error conditions */ | |
1553 | pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); | |
2162e6a2 DA |
1554 | |
1555 | intel_i830_setup_flush(); | |
1da177e4 LT |
1556 | return 0; |
1557 | } | |
1558 | ||
1559 | static int intel_850_configure(void) | |
1560 | { | |
1561 | u32 temp; | |
1562 | u16 temp2; | |
1563 | struct aper_size_info_8 *current_size; | |
1564 | ||
1565 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1566 | ||
1567 | /* aperture size */ | |
1568 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1569 | ||
1570 | /* address to map to */ | |
1571 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1572 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1573 | ||
1574 | /* attbase - aperture base */ | |
1575 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1576 | ||
1577 | /* agpctrl */ | |
1578 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1579 | ||
1580 | /* mcgcfg */ | |
1581 | pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); | |
1582 | pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); | |
1583 | /* clear any possible AGP-related error conditions */ | |
1584 | pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); | |
1585 | return 0; | |
1586 | } | |
1587 | ||
1588 | static int intel_860_configure(void) | |
1589 | { | |
1590 | u32 temp; | |
1591 | u16 temp2; | |
1592 | struct aper_size_info_8 *current_size; | |
1593 | ||
1594 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1595 | ||
1596 | /* aperture size */ | |
1597 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1598 | ||
1599 | /* address to map to */ | |
1600 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1601 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1602 | ||
1603 | /* attbase - aperture base */ | |
1604 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1605 | ||
1606 | /* agpctrl */ | |
1607 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1608 | ||
1609 | /* mcgcfg */ | |
1610 | pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); | |
1611 | pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); | |
1612 | /* clear any possible AGP-related error conditions */ | |
1613 | pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); | |
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | static int intel_830mp_configure(void) | |
1618 | { | |
1619 | u32 temp; | |
1620 | u16 temp2; | |
1621 | struct aper_size_info_8 *current_size; | |
1622 | ||
1623 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1624 | ||
1625 | /* aperture size */ | |
1626 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1627 | ||
1628 | /* address to map to */ | |
1629 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1630 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1631 | ||
1632 | /* attbase - aperture base */ | |
1633 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1634 | ||
1635 | /* agpctrl */ | |
1636 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1637 | ||
1638 | /* gmch */ | |
1639 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1640 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); | |
1641 | /* clear any possible AGP-related error conditions */ | |
1642 | pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); | |
1643 | return 0; | |
1644 | } | |
1645 | ||
1646 | static int intel_7505_configure(void) | |
1647 | { | |
1648 | u32 temp; | |
1649 | u16 temp2; | |
1650 | struct aper_size_info_8 *current_size; | |
1651 | ||
1652 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1653 | ||
1654 | /* aperture size */ | |
1655 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1656 | ||
1657 | /* address to map to */ | |
1658 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1659 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1660 | ||
1661 | /* attbase - aperture base */ | |
1662 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1663 | ||
1664 | /* agpctrl */ | |
1665 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1666 | ||
1667 | /* mchcfg */ | |
1668 | pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); | |
1669 | pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); | |
1670 | ||
1671 | return 0; | |
1672 | } | |
1673 | ||
1674 | /* Setup function */ | |
e5524f35 | 1675 | static const struct gatt_mask intel_generic_masks[] = |
1da177e4 LT |
1676 | { |
1677 | {.mask = 0x00000017, .type = 0} | |
1678 | }; | |
1679 | ||
e5524f35 | 1680 | static const struct aper_size_info_8 intel_815_sizes[2] = |
1da177e4 LT |
1681 | { |
1682 | {64, 16384, 4, 0}, | |
1683 | {32, 8192, 3, 8}, | |
1684 | }; | |
1685 | ||
e5524f35 | 1686 | static const struct aper_size_info_8 intel_8xx_sizes[7] = |
1da177e4 LT |
1687 | { |
1688 | {256, 65536, 6, 0}, | |
1689 | {128, 32768, 5, 32}, | |
1690 | {64, 16384, 4, 48}, | |
1691 | {32, 8192, 3, 56}, | |
1692 | {16, 4096, 2, 60}, | |
1693 | {8, 2048, 1, 62}, | |
1694 | {4, 1024, 0, 63} | |
1695 | }; | |
1696 | ||
e5524f35 | 1697 | static const struct aper_size_info_16 intel_generic_sizes[7] = |
1da177e4 LT |
1698 | { |
1699 | {256, 65536, 6, 0}, | |
1700 | {128, 32768, 5, 32}, | |
1701 | {64, 16384, 4, 48}, | |
1702 | {32, 8192, 3, 56}, | |
1703 | {16, 4096, 2, 60}, | |
1704 | {8, 2048, 1, 62}, | |
1705 | {4, 1024, 0, 63} | |
1706 | }; | |
1707 | ||
e5524f35 | 1708 | static const struct aper_size_info_8 intel_830mp_sizes[4] = |
1da177e4 LT |
1709 | { |
1710 | {256, 65536, 6, 0}, | |
1711 | {128, 32768, 5, 32}, | |
1712 | {64, 16384, 4, 48}, | |
1713 | {32, 8192, 3, 56} | |
1714 | }; | |
1715 | ||
e5524f35 | 1716 | static const struct agp_bridge_driver intel_generic_driver = { |
1da177e4 LT |
1717 | .owner = THIS_MODULE, |
1718 | .aperture_sizes = intel_generic_sizes, | |
1719 | .size_type = U16_APER_SIZE, | |
1720 | .num_aperture_sizes = 7, | |
1721 | .configure = intel_configure, | |
1722 | .fetch_size = intel_fetch_size, | |
1723 | .cleanup = intel_cleanup, | |
1724 | .tlb_flush = intel_tlbflush, | |
1725 | .mask_memory = agp_generic_mask_memory, | |
1726 | .masks = intel_generic_masks, | |
1727 | .agp_enable = agp_generic_enable, | |
1728 | .cache_flush = global_cache_flush, | |
1729 | .create_gatt_table = agp_generic_create_gatt_table, | |
1730 | .free_gatt_table = agp_generic_free_gatt_table, | |
1731 | .insert_memory = agp_generic_insert_memory, | |
1732 | .remove_memory = agp_generic_remove_memory, | |
1733 | .alloc_by_type = agp_generic_alloc_by_type, | |
1734 | .free_by_type = agp_generic_free_by_type, | |
1735 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1736 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1737 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1738 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1739 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1740 | }; |
1741 | ||
e5524f35 | 1742 | static const struct agp_bridge_driver intel_810_driver = { |
1da177e4 LT |
1743 | .owner = THIS_MODULE, |
1744 | .aperture_sizes = intel_i810_sizes, | |
1745 | .size_type = FIXED_APER_SIZE, | |
1746 | .num_aperture_sizes = 2, | |
c7258012 | 1747 | .needs_scratch_page = true, |
1da177e4 LT |
1748 | .configure = intel_i810_configure, |
1749 | .fetch_size = intel_i810_fetch_size, | |
1750 | .cleanup = intel_i810_cleanup, | |
1751 | .tlb_flush = intel_i810_tlbflush, | |
1752 | .mask_memory = intel_i810_mask_memory, | |
1753 | .masks = intel_i810_masks, | |
1754 | .agp_enable = intel_i810_agp_enable, | |
1755 | .cache_flush = global_cache_flush, | |
1756 | .create_gatt_table = agp_generic_create_gatt_table, | |
1757 | .free_gatt_table = agp_generic_free_gatt_table, | |
1758 | .insert_memory = intel_i810_insert_entries, | |
1759 | .remove_memory = intel_i810_remove_entries, | |
1760 | .alloc_by_type = intel_i810_alloc_by_type, | |
1761 | .free_by_type = intel_i810_free_by_type, | |
1762 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1763 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1764 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1765 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1766 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1767 | }; |
1768 | ||
e5524f35 | 1769 | static const struct agp_bridge_driver intel_815_driver = { |
1da177e4 LT |
1770 | .owner = THIS_MODULE, |
1771 | .aperture_sizes = intel_815_sizes, | |
1772 | .size_type = U8_APER_SIZE, | |
1773 | .num_aperture_sizes = 2, | |
1774 | .configure = intel_815_configure, | |
1775 | .fetch_size = intel_815_fetch_size, | |
1776 | .cleanup = intel_8xx_cleanup, | |
1777 | .tlb_flush = intel_8xx_tlbflush, | |
1778 | .mask_memory = agp_generic_mask_memory, | |
1779 | .masks = intel_generic_masks, | |
1780 | .agp_enable = agp_generic_enable, | |
1781 | .cache_flush = global_cache_flush, | |
1782 | .create_gatt_table = agp_generic_create_gatt_table, | |
1783 | .free_gatt_table = agp_generic_free_gatt_table, | |
1784 | .insert_memory = agp_generic_insert_memory, | |
1785 | .remove_memory = agp_generic_remove_memory, | |
1786 | .alloc_by_type = agp_generic_alloc_by_type, | |
1787 | .free_by_type = agp_generic_free_by_type, | |
1788 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1789 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1790 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1791 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 1792 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1793 | }; |
1794 | ||
e5524f35 | 1795 | static const struct agp_bridge_driver intel_830_driver = { |
1da177e4 LT |
1796 | .owner = THIS_MODULE, |
1797 | .aperture_sizes = intel_i830_sizes, | |
1798 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1799 | .num_aperture_sizes = 4, |
c7258012 | 1800 | .needs_scratch_page = true, |
1da177e4 LT |
1801 | .configure = intel_i830_configure, |
1802 | .fetch_size = intel_i830_fetch_size, | |
1803 | .cleanup = intel_i830_cleanup, | |
1804 | .tlb_flush = intel_i810_tlbflush, | |
1805 | .mask_memory = intel_i810_mask_memory, | |
1806 | .masks = intel_i810_masks, | |
1807 | .agp_enable = intel_i810_agp_enable, | |
1808 | .cache_flush = global_cache_flush, | |
1809 | .create_gatt_table = intel_i830_create_gatt_table, | |
1810 | .free_gatt_table = intel_i830_free_gatt_table, | |
1811 | .insert_memory = intel_i830_insert_entries, | |
1812 | .remove_memory = intel_i830_remove_entries, | |
1813 | .alloc_by_type = intel_i830_alloc_by_type, | |
1814 | .free_by_type = intel_i810_free_by_type, | |
1815 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1816 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1817 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1818 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1819 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
2162e6a2 | 1820 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
1821 | }; |
1822 | ||
e5524f35 | 1823 | static const struct agp_bridge_driver intel_820_driver = { |
1da177e4 LT |
1824 | .owner = THIS_MODULE, |
1825 | .aperture_sizes = intel_8xx_sizes, | |
1826 | .size_type = U8_APER_SIZE, | |
1827 | .num_aperture_sizes = 7, | |
1828 | .configure = intel_820_configure, | |
1829 | .fetch_size = intel_8xx_fetch_size, | |
1830 | .cleanup = intel_820_cleanup, | |
1831 | .tlb_flush = intel_820_tlbflush, | |
1832 | .mask_memory = agp_generic_mask_memory, | |
1833 | .masks = intel_generic_masks, | |
1834 | .agp_enable = agp_generic_enable, | |
1835 | .cache_flush = global_cache_flush, | |
1836 | .create_gatt_table = agp_generic_create_gatt_table, | |
1837 | .free_gatt_table = agp_generic_free_gatt_table, | |
1838 | .insert_memory = agp_generic_insert_memory, | |
1839 | .remove_memory = agp_generic_remove_memory, | |
1840 | .alloc_by_type = agp_generic_alloc_by_type, | |
1841 | .free_by_type = agp_generic_free_by_type, | |
1842 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1843 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1844 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1845 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1846 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1847 | }; |
1848 | ||
e5524f35 | 1849 | static const struct agp_bridge_driver intel_830mp_driver = { |
1da177e4 LT |
1850 | .owner = THIS_MODULE, |
1851 | .aperture_sizes = intel_830mp_sizes, | |
1852 | .size_type = U8_APER_SIZE, | |
1853 | .num_aperture_sizes = 4, | |
1854 | .configure = intel_830mp_configure, | |
1855 | .fetch_size = intel_8xx_fetch_size, | |
1856 | .cleanup = intel_8xx_cleanup, | |
1857 | .tlb_flush = intel_8xx_tlbflush, | |
1858 | .mask_memory = agp_generic_mask_memory, | |
1859 | .masks = intel_generic_masks, | |
1860 | .agp_enable = agp_generic_enable, | |
1861 | .cache_flush = global_cache_flush, | |
1862 | .create_gatt_table = agp_generic_create_gatt_table, | |
1863 | .free_gatt_table = agp_generic_free_gatt_table, | |
1864 | .insert_memory = agp_generic_insert_memory, | |
1865 | .remove_memory = agp_generic_remove_memory, | |
1866 | .alloc_by_type = agp_generic_alloc_by_type, | |
1867 | .free_by_type = agp_generic_free_by_type, | |
1868 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1869 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1870 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1871 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1872 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1873 | }; |
1874 | ||
e5524f35 | 1875 | static const struct agp_bridge_driver intel_840_driver = { |
1da177e4 LT |
1876 | .owner = THIS_MODULE, |
1877 | .aperture_sizes = intel_8xx_sizes, | |
1878 | .size_type = U8_APER_SIZE, | |
1879 | .num_aperture_sizes = 7, | |
1880 | .configure = intel_840_configure, | |
1881 | .fetch_size = intel_8xx_fetch_size, | |
1882 | .cleanup = intel_8xx_cleanup, | |
1883 | .tlb_flush = intel_8xx_tlbflush, | |
1884 | .mask_memory = agp_generic_mask_memory, | |
1885 | .masks = intel_generic_masks, | |
1886 | .agp_enable = agp_generic_enable, | |
1887 | .cache_flush = global_cache_flush, | |
1888 | .create_gatt_table = agp_generic_create_gatt_table, | |
1889 | .free_gatt_table = agp_generic_free_gatt_table, | |
1890 | .insert_memory = agp_generic_insert_memory, | |
1891 | .remove_memory = agp_generic_remove_memory, | |
1892 | .alloc_by_type = agp_generic_alloc_by_type, | |
1893 | .free_by_type = agp_generic_free_by_type, | |
1894 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1895 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1896 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1897 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1898 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1899 | }; |
1900 | ||
e5524f35 | 1901 | static const struct agp_bridge_driver intel_845_driver = { |
1da177e4 LT |
1902 | .owner = THIS_MODULE, |
1903 | .aperture_sizes = intel_8xx_sizes, | |
1904 | .size_type = U8_APER_SIZE, | |
1905 | .num_aperture_sizes = 7, | |
1906 | .configure = intel_845_configure, | |
1907 | .fetch_size = intel_8xx_fetch_size, | |
1908 | .cleanup = intel_8xx_cleanup, | |
1909 | .tlb_flush = intel_8xx_tlbflush, | |
1910 | .mask_memory = agp_generic_mask_memory, | |
1911 | .masks = intel_generic_masks, | |
1912 | .agp_enable = agp_generic_enable, | |
1913 | .cache_flush = global_cache_flush, | |
1914 | .create_gatt_table = agp_generic_create_gatt_table, | |
1915 | .free_gatt_table = agp_generic_free_gatt_table, | |
1916 | .insert_memory = agp_generic_insert_memory, | |
1917 | .remove_memory = agp_generic_remove_memory, | |
1918 | .alloc_by_type = agp_generic_alloc_by_type, | |
1919 | .free_by_type = agp_generic_free_by_type, | |
1920 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1921 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1922 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1923 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1924 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
2162e6a2 | 1925 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
1926 | }; |
1927 | ||
e5524f35 | 1928 | static const struct agp_bridge_driver intel_850_driver = { |
1da177e4 LT |
1929 | .owner = THIS_MODULE, |
1930 | .aperture_sizes = intel_8xx_sizes, | |
1931 | .size_type = U8_APER_SIZE, | |
1932 | .num_aperture_sizes = 7, | |
1933 | .configure = intel_850_configure, | |
1934 | .fetch_size = intel_8xx_fetch_size, | |
1935 | .cleanup = intel_8xx_cleanup, | |
1936 | .tlb_flush = intel_8xx_tlbflush, | |
1937 | .mask_memory = agp_generic_mask_memory, | |
1938 | .masks = intel_generic_masks, | |
1939 | .agp_enable = agp_generic_enable, | |
1940 | .cache_flush = global_cache_flush, | |
1941 | .create_gatt_table = agp_generic_create_gatt_table, | |
1942 | .free_gatt_table = agp_generic_free_gatt_table, | |
1943 | .insert_memory = agp_generic_insert_memory, | |
1944 | .remove_memory = agp_generic_remove_memory, | |
1945 | .alloc_by_type = agp_generic_alloc_by_type, | |
1946 | .free_by_type = agp_generic_free_by_type, | |
1947 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1948 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1949 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1950 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1951 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1952 | }; |
1953 | ||
e5524f35 | 1954 | static const struct agp_bridge_driver intel_860_driver = { |
1da177e4 LT |
1955 | .owner = THIS_MODULE, |
1956 | .aperture_sizes = intel_8xx_sizes, | |
1957 | .size_type = U8_APER_SIZE, | |
1958 | .num_aperture_sizes = 7, | |
1959 | .configure = intel_860_configure, | |
1960 | .fetch_size = intel_8xx_fetch_size, | |
1961 | .cleanup = intel_8xx_cleanup, | |
1962 | .tlb_flush = intel_8xx_tlbflush, | |
1963 | .mask_memory = agp_generic_mask_memory, | |
1964 | .masks = intel_generic_masks, | |
1965 | .agp_enable = agp_generic_enable, | |
1966 | .cache_flush = global_cache_flush, | |
1967 | .create_gatt_table = agp_generic_create_gatt_table, | |
1968 | .free_gatt_table = agp_generic_free_gatt_table, | |
1969 | .insert_memory = agp_generic_insert_memory, | |
1970 | .remove_memory = agp_generic_remove_memory, | |
1971 | .alloc_by_type = agp_generic_alloc_by_type, | |
1972 | .free_by_type = agp_generic_free_by_type, | |
1973 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1974 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1975 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1976 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1977 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1978 | }; |
1979 | ||
e5524f35 | 1980 | static const struct agp_bridge_driver intel_915_driver = { |
1da177e4 LT |
1981 | .owner = THIS_MODULE, |
1982 | .aperture_sizes = intel_i830_sizes, | |
1983 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1984 | .num_aperture_sizes = 4, |
c7258012 | 1985 | .needs_scratch_page = true, |
1da177e4 | 1986 | .configure = intel_i915_configure, |
c41e0deb | 1987 | .fetch_size = intel_i9xx_fetch_size, |
1da177e4 LT |
1988 | .cleanup = intel_i915_cleanup, |
1989 | .tlb_flush = intel_i810_tlbflush, | |
1990 | .mask_memory = intel_i810_mask_memory, | |
1991 | .masks = intel_i810_masks, | |
1992 | .agp_enable = intel_i810_agp_enable, | |
1993 | .cache_flush = global_cache_flush, | |
1994 | .create_gatt_table = intel_i915_create_gatt_table, | |
1995 | .free_gatt_table = intel_i830_free_gatt_table, | |
1996 | .insert_memory = intel_i915_insert_entries, | |
1997 | .remove_memory = intel_i915_remove_entries, | |
1998 | .alloc_by_type = intel_i830_alloc_by_type, | |
1999 | .free_by_type = intel_i810_free_by_type, | |
2000 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2001 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2002 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2003 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2004 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2005 | .chipset_flush = intel_i915_chipset_flush, |
1da177e4 LT |
2006 | }; |
2007 | ||
e5524f35 | 2008 | static const struct agp_bridge_driver intel_i965_driver = { |
62c96b9d DA |
2009 | .owner = THIS_MODULE, |
2010 | .aperture_sizes = intel_i830_sizes, | |
2011 | .size_type = FIXED_APER_SIZE, | |
2012 | .num_aperture_sizes = 4, | |
2013 | .needs_scratch_page = true, | |
0e480e5f DA |
2014 | .configure = intel_i915_configure, |
2015 | .fetch_size = intel_i9xx_fetch_size, | |
62c96b9d DA |
2016 | .cleanup = intel_i915_cleanup, |
2017 | .tlb_flush = intel_i810_tlbflush, | |
2018 | .mask_memory = intel_i965_mask_memory, | |
2019 | .masks = intel_i810_masks, | |
2020 | .agp_enable = intel_i810_agp_enable, | |
2021 | .cache_flush = global_cache_flush, | |
2022 | .create_gatt_table = intel_i965_create_gatt_table, | |
2023 | .free_gatt_table = intel_i830_free_gatt_table, | |
2024 | .insert_memory = intel_i915_insert_entries, | |
2025 | .remove_memory = intel_i915_remove_entries, | |
2026 | .alloc_by_type = intel_i830_alloc_by_type, | |
2027 | .free_by_type = intel_i810_free_by_type, | |
2028 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2029 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2030 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2031 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2032 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2033 | .chipset_flush = intel_i915_chipset_flush, |
65c25aad | 2034 | }; |
1da177e4 | 2035 | |
e5524f35 | 2036 | static const struct agp_bridge_driver intel_7505_driver = { |
1da177e4 LT |
2037 | .owner = THIS_MODULE, |
2038 | .aperture_sizes = intel_8xx_sizes, | |
2039 | .size_type = U8_APER_SIZE, | |
2040 | .num_aperture_sizes = 7, | |
2041 | .configure = intel_7505_configure, | |
2042 | .fetch_size = intel_8xx_fetch_size, | |
2043 | .cleanup = intel_8xx_cleanup, | |
2044 | .tlb_flush = intel_8xx_tlbflush, | |
2045 | .mask_memory = agp_generic_mask_memory, | |
2046 | .masks = intel_generic_masks, | |
2047 | .agp_enable = agp_generic_enable, | |
2048 | .cache_flush = global_cache_flush, | |
2049 | .create_gatt_table = agp_generic_create_gatt_table, | |
2050 | .free_gatt_table = agp_generic_free_gatt_table, | |
2051 | .insert_memory = agp_generic_insert_memory, | |
2052 | .remove_memory = agp_generic_remove_memory, | |
2053 | .alloc_by_type = agp_generic_alloc_by_type, | |
2054 | .free_by_type = agp_generic_free_by_type, | |
2055 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2056 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2057 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2058 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2059 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2060 | }; |
2061 | ||
874808c6 | 2062 | static const struct agp_bridge_driver intel_g33_driver = { |
62c96b9d DA |
2063 | .owner = THIS_MODULE, |
2064 | .aperture_sizes = intel_i830_sizes, | |
2065 | .size_type = FIXED_APER_SIZE, | |
2066 | .num_aperture_sizes = 4, | |
2067 | .needs_scratch_page = true, | |
2068 | .configure = intel_i915_configure, | |
2069 | .fetch_size = intel_i9xx_fetch_size, | |
2070 | .cleanup = intel_i915_cleanup, | |
2071 | .tlb_flush = intel_i810_tlbflush, | |
2072 | .mask_memory = intel_i965_mask_memory, | |
2073 | .masks = intel_i810_masks, | |
2074 | .agp_enable = intel_i810_agp_enable, | |
2075 | .cache_flush = global_cache_flush, | |
2076 | .create_gatt_table = intel_i915_create_gatt_table, | |
2077 | .free_gatt_table = intel_i830_free_gatt_table, | |
2078 | .insert_memory = intel_i915_insert_entries, | |
2079 | .remove_memory = intel_i915_remove_entries, | |
2080 | .alloc_by_type = intel_i830_alloc_by_type, | |
2081 | .free_by_type = intel_i810_free_by_type, | |
2082 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2083 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2084 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2085 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2086 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2087 | .chipset_flush = intel_i915_chipset_flush, |
874808c6 | 2088 | }; |
1da177e4 | 2089 | |
9614ece1 | 2090 | static int find_gmch(u16 device) |
1da177e4 | 2091 | { |
9614ece1 | 2092 | struct pci_dev *gmch_device; |
1da177e4 | 2093 | |
9614ece1 WZ |
2094 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
2095 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
2096 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
f011ae74 | 2097 | device, gmch_device); |
1da177e4 LT |
2098 | } |
2099 | ||
9614ece1 | 2100 | if (!gmch_device) |
1da177e4 LT |
2101 | return 0; |
2102 | ||
9614ece1 | 2103 | intel_private.pcidev = gmch_device; |
1da177e4 LT |
2104 | return 1; |
2105 | } | |
2106 | ||
9614ece1 WZ |
2107 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
2108 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
2109 | * which one should be used if a gmch_chip_id is present. | |
2110 | */ | |
2111 | static const struct intel_driver_description { | |
2112 | unsigned int chip_id; | |
2113 | unsigned int gmch_chip_id; | |
88889851 | 2114 | unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ |
9614ece1 WZ |
2115 | char *name; |
2116 | const struct agp_bridge_driver *driver; | |
2117 | const struct agp_bridge_driver *gmch_driver; | |
2118 | } intel_agp_chipsets[] = { | |
88889851 WZ |
2119 | { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, |
2120 | { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, | |
2121 | { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, | |
2122 | { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", | |
9614ece1 | 2123 | NULL, &intel_810_driver }, |
88889851 | 2124 | { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", |
9614ece1 | 2125 | NULL, &intel_810_driver }, |
88889851 | 2126 | { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", |
9614ece1 | 2127 | NULL, &intel_810_driver }, |
88889851 WZ |
2128 | { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", |
2129 | &intel_815_driver, &intel_810_driver }, | |
2130 | { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2131 | { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2132 | { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", | |
9614ece1 | 2133 | &intel_830mp_driver, &intel_830_driver }, |
88889851 WZ |
2134 | { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, |
2135 | { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, | |
2136 | { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", | |
9614ece1 | 2137 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2138 | { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, |
347486bb SH |
2139 | { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", |
2140 | &intel_845_driver, &intel_830_driver }, | |
88889851 WZ |
2141 | { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, |
2142 | { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", | |
9614ece1 | 2143 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
2144 | { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, |
2145 | { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", | |
9614ece1 | 2146 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2147 | { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, |
e914a36a CM |
2148 | { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", |
2149 | NULL, &intel_915_driver }, | |
88889851 | 2150 | { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", |
47d46379 | 2151 | NULL, &intel_915_driver }, |
88889851 | 2152 | { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", |
47d46379 | 2153 | NULL, &intel_915_driver }, |
88889851 | 2154 | { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", |
47d46379 | 2155 | NULL, &intel_915_driver }, |
dde47876 | 2156 | { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", |
47d46379 | 2157 | NULL, &intel_915_driver }, |
dde47876 | 2158 | { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", |
47d46379 | 2159 | NULL, &intel_915_driver }, |
88889851 | 2160 | { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", |
47d46379 | 2161 | NULL, &intel_i965_driver }, |
9119f85a | 2162 | { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", |
47d46379 | 2163 | NULL, &intel_i965_driver }, |
88889851 | 2164 | { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", |
47d46379 | 2165 | NULL, &intel_i965_driver }, |
88889851 | 2166 | { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", |
47d46379 | 2167 | NULL, &intel_i965_driver }, |
dde47876 | 2168 | { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", |
47d46379 | 2169 | NULL, &intel_i965_driver }, |
dde47876 | 2170 | { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", |
47d46379 | 2171 | NULL, &intel_i965_driver }, |
88889851 WZ |
2172 | { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, |
2173 | { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, | |
2174 | { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", | |
47d46379 | 2175 | NULL, &intel_g33_driver }, |
88889851 | 2176 | { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", |
47d46379 | 2177 | NULL, &intel_g33_driver }, |
88889851 | 2178 | { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", |
47d46379 | 2179 | NULL, &intel_g33_driver }, |
2177832f SL |
2180 | { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD", |
2181 | NULL, &intel_g33_driver }, | |
2182 | { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD", | |
2183 | NULL, &intel_g33_driver }, | |
99d32bd5 | 2184 | { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, |
b854b2ab | 2185 | "Mobile Intel® GM45 Express", NULL, &intel_i965_driver }, |
25ce77ab ZW |
2186 | { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, |
2187 | "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, | |
2188 | { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, | |
2189 | "Q45/Q43", NULL, &intel_i965_driver }, | |
2190 | { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, | |
2191 | "G45/G43", NULL, &intel_i965_driver }, | |
a50ccc6c ZW |
2192 | { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, |
2193 | "G41", NULL, &intel_i965_driver }, | |
32cb055b ZW |
2194 | { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, |
2195 | "IGDNG/D", NULL, &intel_i965_driver }, | |
2196 | { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, | |
2197 | "IGDNG/M", NULL, &intel_i965_driver }, | |
88889851 | 2198 | { 0, 0, 0, NULL, NULL, NULL } |
9614ece1 WZ |
2199 | }; |
2200 | ||
1da177e4 LT |
2201 | static int __devinit agp_intel_probe(struct pci_dev *pdev, |
2202 | const struct pci_device_id *ent) | |
2203 | { | |
2204 | struct agp_bridge_data *bridge; | |
1da177e4 LT |
2205 | u8 cap_ptr = 0; |
2206 | struct resource *r; | |
9614ece1 | 2207 | int i; |
1da177e4 LT |
2208 | |
2209 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
2210 | ||
2211 | bridge = agp_alloc_bridge(); | |
2212 | if (!bridge) | |
2213 | return -ENOMEM; | |
2214 | ||
9614ece1 WZ |
2215 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
2216 | /* In case that multiple models of gfx chip may | |
2217 | stand on same host bridge type, this can be | |
2218 | sure we detect the right IGD. */ | |
88889851 WZ |
2219 | if (pdev->device == intel_agp_chipsets[i].chip_id) { |
2220 | if ((intel_agp_chipsets[i].gmch_chip_id != 0) && | |
2221 | find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { | |
2222 | bridge->driver = | |
2223 | intel_agp_chipsets[i].gmch_driver; | |
2224 | break; | |
2225 | } else if (intel_agp_chipsets[i].multi_gmch_chip) { | |
2226 | continue; | |
2227 | } else { | |
2228 | bridge->driver = intel_agp_chipsets[i].driver; | |
2229 | break; | |
2230 | } | |
2231 | } | |
9614ece1 WZ |
2232 | } |
2233 | ||
2234 | if (intel_agp_chipsets[i].name == NULL) { | |
1da177e4 | 2235 | if (cap_ptr) |
e3cf6951 BH |
2236 | dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", |
2237 | pdev->vendor, pdev->device); | |
9614ece1 WZ |
2238 | agp_put_bridge(bridge); |
2239 | return -ENODEV; | |
2240 | } | |
2241 | ||
9614ece1 | 2242 | if (bridge->driver == NULL) { |
47d46379 WZ |
2243 | /* bridge has no AGP and no IGD detected */ |
2244 | if (cap_ptr) | |
e3cf6951 BH |
2245 | dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", |
2246 | intel_agp_chipsets[i].gmch_chip_id); | |
1da177e4 LT |
2247 | agp_put_bridge(bridge); |
2248 | return -ENODEV; | |
f011ae74 | 2249 | } |
1da177e4 LT |
2250 | |
2251 | bridge->dev = pdev; | |
2252 | bridge->capndx = cap_ptr; | |
c4ca8817 | 2253 | bridge->dev_private_data = &intel_private; |
1da177e4 | 2254 | |
e3cf6951 | 2255 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); |
1da177e4 LT |
2256 | |
2257 | /* | |
2258 | * The following fixes the case where the BIOS has "forgotten" to | |
2259 | * provide an address range for the GART. | |
2260 | * 20030610 - hamish@zot.org | |
2261 | */ | |
2262 | r = &pdev->resource[0]; | |
2263 | if (!r->start && r->end) { | |
6a92a4e0 | 2264 | if (pci_assign_resource(pdev, 0)) { |
e3cf6951 | 2265 | dev_err(&pdev->dev, "can't assign resource 0\n"); |
1da177e4 LT |
2266 | agp_put_bridge(bridge); |
2267 | return -ENODEV; | |
2268 | } | |
2269 | } | |
2270 | ||
2271 | /* | |
2272 | * If the device has not been properly setup, the following will catch | |
2273 | * the problem and should stop the system from crashing. | |
2274 | * 20030610 - hamish@zot.org | |
2275 | */ | |
2276 | if (pci_enable_device(pdev)) { | |
e3cf6951 | 2277 | dev_err(&pdev->dev, "can't enable PCI device\n"); |
1da177e4 LT |
2278 | agp_put_bridge(bridge); |
2279 | return -ENODEV; | |
2280 | } | |
2281 | ||
2282 | /* Fill in the mode register */ | |
2283 | if (cap_ptr) { | |
2284 | pci_read_config_dword(pdev, | |
2285 | bridge->capndx+PCI_AGP_STATUS, | |
2286 | &bridge->mode); | |
2287 | } | |
2288 | ||
2289 | pci_set_drvdata(pdev, bridge); | |
2290 | return agp_add_bridge(bridge); | |
1da177e4 LT |
2291 | } |
2292 | ||
2293 | static void __devexit agp_intel_remove(struct pci_dev *pdev) | |
2294 | { | |
2295 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2296 | ||
2297 | agp_remove_bridge(bridge); | |
2298 | ||
c4ca8817 WZ |
2299 | if (intel_private.pcidev) |
2300 | pci_dev_put(intel_private.pcidev); | |
1da177e4 LT |
2301 | |
2302 | agp_put_bridge(bridge); | |
2303 | } | |
2304 | ||
85be7d60 | 2305 | #ifdef CONFIG_PM |
1da177e4 LT |
2306 | static int agp_intel_resume(struct pci_dev *pdev) |
2307 | { | |
2308 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
a8c84df9 | 2309 | int ret_val; |
1da177e4 LT |
2310 | |
2311 | pci_restore_state(pdev); | |
2312 | ||
4b95320f WZ |
2313 | /* We should restore our graphics device's config space, |
2314 | * as host bridge (00:00) resumes before graphics device (02:00), | |
2315 | * then our access to its pci space can work right. | |
2316 | */ | |
c4ca8817 WZ |
2317 | if (intel_private.pcidev) |
2318 | pci_restore_state(intel_private.pcidev); | |
4b95320f | 2319 | |
1da177e4 LT |
2320 | if (bridge->driver == &intel_generic_driver) |
2321 | intel_configure(); | |
2322 | else if (bridge->driver == &intel_850_driver) | |
2323 | intel_850_configure(); | |
2324 | else if (bridge->driver == &intel_845_driver) | |
2325 | intel_845_configure(); | |
2326 | else if (bridge->driver == &intel_830mp_driver) | |
2327 | intel_830mp_configure(); | |
2328 | else if (bridge->driver == &intel_915_driver) | |
2329 | intel_i915_configure(); | |
2330 | else if (bridge->driver == &intel_830_driver) | |
2331 | intel_i830_configure(); | |
2332 | else if (bridge->driver == &intel_810_driver) | |
2333 | intel_i810_configure(); | |
08da3f41 DJ |
2334 | else if (bridge->driver == &intel_i965_driver) |
2335 | intel_i915_configure(); | |
1da177e4 | 2336 | |
a8c84df9 KP |
2337 | ret_val = agp_rebind_memory(); |
2338 | if (ret_val != 0) | |
2339 | return ret_val; | |
2340 | ||
1da177e4 LT |
2341 | return 0; |
2342 | } | |
85be7d60 | 2343 | #endif |
1da177e4 LT |
2344 | |
2345 | static struct pci_device_id agp_intel_pci_table[] = { | |
2346 | #define ID(x) \ | |
2347 | { \ | |
2348 | .class = (PCI_CLASS_BRIDGE_HOST << 8), \ | |
2349 | .class_mask = ~0, \ | |
2350 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
2351 | .device = x, \ | |
2352 | .subvendor = PCI_ANY_ID, \ | |
2353 | .subdevice = PCI_ANY_ID, \ | |
2354 | } | |
2355 | ID(PCI_DEVICE_ID_INTEL_82443LX_0), | |
2356 | ID(PCI_DEVICE_ID_INTEL_82443BX_0), | |
2357 | ID(PCI_DEVICE_ID_INTEL_82443GX_0), | |
2358 | ID(PCI_DEVICE_ID_INTEL_82810_MC1), | |
2359 | ID(PCI_DEVICE_ID_INTEL_82810_MC3), | |
2360 | ID(PCI_DEVICE_ID_INTEL_82810E_MC), | |
2361 | ID(PCI_DEVICE_ID_INTEL_82815_MC), | |
2362 | ID(PCI_DEVICE_ID_INTEL_82820_HB), | |
2363 | ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), | |
2364 | ID(PCI_DEVICE_ID_INTEL_82830_HB), | |
2365 | ID(PCI_DEVICE_ID_INTEL_82840_HB), | |
2366 | ID(PCI_DEVICE_ID_INTEL_82845_HB), | |
2367 | ID(PCI_DEVICE_ID_INTEL_82845G_HB), | |
2368 | ID(PCI_DEVICE_ID_INTEL_82850_HB), | |
347486bb | 2369 | ID(PCI_DEVICE_ID_INTEL_82854_HB), |
1da177e4 LT |
2370 | ID(PCI_DEVICE_ID_INTEL_82855PM_HB), |
2371 | ID(PCI_DEVICE_ID_INTEL_82855GM_HB), | |
2372 | ID(PCI_DEVICE_ID_INTEL_82860_HB), | |
2373 | ID(PCI_DEVICE_ID_INTEL_82865_HB), | |
2374 | ID(PCI_DEVICE_ID_INTEL_82875_HB), | |
2375 | ID(PCI_DEVICE_ID_INTEL_7505_0), | |
2376 | ID(PCI_DEVICE_ID_INTEL_7205_0), | |
e914a36a | 2377 | ID(PCI_DEVICE_ID_INTEL_E7221_HB), |
1da177e4 LT |
2378 | ID(PCI_DEVICE_ID_INTEL_82915G_HB), |
2379 | ID(PCI_DEVICE_ID_INTEL_82915GM_HB), | |
d0de98fa | 2380 | ID(PCI_DEVICE_ID_INTEL_82945G_HB), |
3b0e8ead | 2381 | ID(PCI_DEVICE_ID_INTEL_82945GM_HB), |
dde47876 | 2382 | ID(PCI_DEVICE_ID_INTEL_82945GME_HB), |
2177832f SL |
2383 | ID(PCI_DEVICE_ID_INTEL_IGDGM_HB), |
2384 | ID(PCI_DEVICE_ID_INTEL_IGDG_HB), | |
65c25aad | 2385 | ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), |
9119f85a | 2386 | ID(PCI_DEVICE_ID_INTEL_82G35_HB), |
65c25aad EA |
2387 | ID(PCI_DEVICE_ID_INTEL_82965Q_HB), |
2388 | ID(PCI_DEVICE_ID_INTEL_82965G_HB), | |
4598af33 | 2389 | ID(PCI_DEVICE_ID_INTEL_82965GM_HB), |
dde47876 | 2390 | ID(PCI_DEVICE_ID_INTEL_82965GME_HB), |
874808c6 WZ |
2391 | ID(PCI_DEVICE_ID_INTEL_G33_HB), |
2392 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | |
2393 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | |
99d32bd5 | 2394 | ID(PCI_DEVICE_ID_INTEL_GM45_HB), |
25ce77ab ZW |
2395 | ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), |
2396 | ID(PCI_DEVICE_ID_INTEL_Q45_HB), | |
2397 | ID(PCI_DEVICE_ID_INTEL_G45_HB), | |
a50ccc6c | 2398 | ID(PCI_DEVICE_ID_INTEL_G41_HB), |
32cb055b ZW |
2399 | ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), |
2400 | ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), | |
1da177e4 LT |
2401 | { } |
2402 | }; | |
2403 | ||
2404 | MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); | |
2405 | ||
2406 | static struct pci_driver agp_intel_pci_driver = { | |
2407 | .name = "agpgart-intel", | |
2408 | .id_table = agp_intel_pci_table, | |
2409 | .probe = agp_intel_probe, | |
2410 | .remove = __devexit_p(agp_intel_remove), | |
85be7d60 | 2411 | #ifdef CONFIG_PM |
1da177e4 | 2412 | .resume = agp_intel_resume, |
85be7d60 | 2413 | #endif |
1da177e4 LT |
2414 | }; |
2415 | ||
2416 | static int __init agp_intel_init(void) | |
2417 | { | |
2418 | if (agp_off) | |
2419 | return -EINVAL; | |
2420 | return pci_register_driver(&agp_intel_pci_driver); | |
2421 | } | |
2422 | ||
2423 | static void __exit agp_intel_cleanup(void) | |
2424 | { | |
2425 | pci_unregister_driver(&agp_intel_pci_driver); | |
2426 | } | |
2427 | ||
2428 | module_init(agp_intel_init); | |
2429 | module_exit(agp_intel_cleanup); | |
2430 | ||
f4432c5c | 2431 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
1da177e4 | 2432 | MODULE_LICENSE("GPL and additional rights"); |