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ff7cdd69 DV |
1 | /* |
2 | * Common Intel AGPGART and GTT definitions. | |
3 | */ | |
4 | ||
5 | /* Intel registers */ | |
6 | #define INTEL_APSIZE 0xb4 | |
7 | #define INTEL_ATTBASE 0xb8 | |
8 | #define INTEL_AGPCTRL 0xb0 | |
9 | #define INTEL_NBXCFG 0x50 | |
10 | #define INTEL_ERRSTS 0x91 | |
11 | ||
12 | /* Intel i830 registers */ | |
13 | #define I830_GMCH_CTRL 0x52 | |
14 | #define I830_GMCH_ENABLED 0x4 | |
15 | #define I830_GMCH_MEM_MASK 0x1 | |
16 | #define I830_GMCH_MEM_64M 0x1 | |
17 | #define I830_GMCH_MEM_128M 0 | |
18 | #define I830_GMCH_GMS_MASK 0x70 | |
19 | #define I830_GMCH_GMS_DISABLED 0x00 | |
20 | #define I830_GMCH_GMS_LOCAL 0x10 | |
21 | #define I830_GMCH_GMS_STOLEN_512 0x20 | |
22 | #define I830_GMCH_GMS_STOLEN_1024 0x30 | |
23 | #define I830_GMCH_GMS_STOLEN_8192 0x40 | |
24 | #define I830_RDRAM_CHANNEL_TYPE 0x03010 | |
25 | #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) | |
26 | #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) | |
27 | ||
28 | /* This one is for I830MP w. an external graphic card */ | |
29 | #define INTEL_I830_ERRSTS 0x92 | |
30 | ||
31 | /* Intel 855GM/852GM registers */ | |
32 | #define I855_GMCH_GMS_MASK 0xF0 | |
33 | #define I855_GMCH_GMS_STOLEN_0M 0x0 | |
34 | #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) | |
35 | #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) | |
36 | #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) | |
37 | #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) | |
38 | #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) | |
39 | #define I85X_CAPID 0x44 | |
40 | #define I85X_VARIANT_MASK 0x7 | |
41 | #define I85X_VARIANT_SHIFT 5 | |
42 | #define I855_GME 0x0 | |
43 | #define I855_GM 0x4 | |
44 | #define I852_GME 0x2 | |
45 | #define I852_GM 0x5 | |
46 | ||
47 | /* Intel i845 registers */ | |
48 | #define INTEL_I845_AGPM 0x51 | |
49 | #define INTEL_I845_ERRSTS 0xc8 | |
50 | ||
51 | /* Intel i860 registers */ | |
52 | #define INTEL_I860_MCHCFG 0x50 | |
53 | #define INTEL_I860_ERRSTS 0xc8 | |
54 | ||
55 | /* Intel i810 registers */ | |
56 | #define I810_GMADDR 0x10 | |
57 | #define I810_MMADDR 0x14 | |
58 | #define I810_PTE_BASE 0x10000 | |
59 | #define I810_PTE_MAIN_UNCACHED 0x00000000 | |
60 | #define I810_PTE_LOCAL 0x00000002 | |
61 | #define I810_PTE_VALID 0x00000001 | |
62 | #define I830_PTE_SYSTEM_CACHED 0x00000006 | |
63 | #define I810_SMRAM_MISCC 0x70 | |
64 | #define I810_GFX_MEM_WIN_SIZE 0x00010000 | |
65 | #define I810_GFX_MEM_WIN_32M 0x00010000 | |
66 | #define I810_GMS 0x000000c0 | |
67 | #define I810_GMS_DISABLE 0x00000000 | |
68 | #define I810_PGETBL_CTL 0x2020 | |
69 | #define I810_PGETBL_ENABLED 0x00000001 | |
70 | #define I965_PGETBL_SIZE_MASK 0x0000000e | |
71 | #define I965_PGETBL_SIZE_512KB (0 << 1) | |
72 | #define I965_PGETBL_SIZE_256KB (1 << 1) | |
73 | #define I965_PGETBL_SIZE_128KB (2 << 1) | |
74 | #define I965_PGETBL_SIZE_1MB (3 << 1) | |
75 | #define I965_PGETBL_SIZE_2MB (4 << 1) | |
76 | #define I965_PGETBL_SIZE_1_5MB (5 << 1) | |
77 | #define G33_PGETBL_SIZE_MASK (3 << 8) | |
78 | #define G33_PGETBL_SIZE_1M (1 << 8) | |
79 | #define G33_PGETBL_SIZE_2M (2 << 8) | |
80 | ||
81 | #define I810_DRAM_CTL 0x3000 | |
82 | #define I810_DRAM_ROW_0 0x00000001 | |
83 | #define I810_DRAM_ROW_0_SDRAM 0x00000001 | |
84 | ||
85 | /* Intel 815 register */ | |
86 | #define INTEL_815_APCONT 0x51 | |
87 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
88 | ||
89 | /* Intel i820 registers */ | |
90 | #define INTEL_I820_RDCR 0x51 | |
91 | #define INTEL_I820_ERRSTS 0xc8 | |
92 | ||
93 | /* Intel i840 registers */ | |
94 | #define INTEL_I840_MCHCFG 0x50 | |
95 | #define INTEL_I840_ERRSTS 0xc8 | |
96 | ||
97 | /* Intel i850 registers */ | |
98 | #define INTEL_I850_MCHCFG 0x50 | |
99 | #define INTEL_I850_ERRSTS 0xc8 | |
100 | ||
101 | /* intel 915G registers */ | |
102 | #define I915_GMADDR 0x18 | |
103 | #define I915_MMADDR 0x10 | |
104 | #define I915_PTEADDR 0x1C | |
105 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
106 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
107 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) | |
108 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
109 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
110 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
111 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
112 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
113 | ||
114 | #define I915_IFPADDR 0x60 | |
115 | ||
116 | /* Intel 965G registers */ | |
117 | #define I965_MSAC 0x62 | |
118 | #define I965_IFPADDR 0x70 | |
119 | ||
120 | /* Intel 7505 registers */ | |
121 | #define INTEL_I7505_APSIZE 0x74 | |
122 | #define INTEL_I7505_NCAPID 0x60 | |
123 | #define INTEL_I7505_NISTAT 0x6c | |
124 | #define INTEL_I7505_ATTBASE 0x78 | |
125 | #define INTEL_I7505_ERRSTS 0x42 | |
126 | #define INTEL_I7505_AGPCTRL 0x70 | |
127 | #define INTEL_I7505_MCHCFG 0x50 | |
128 | ||
129 | #define SNB_GMCH_CTRL 0x50 | |
130 | #define SNB_GMCH_GMS_STOLEN_MASK 0xF8 | |
131 | #define SNB_GMCH_GMS_STOLEN_32M (1 << 3) | |
132 | #define SNB_GMCH_GMS_STOLEN_64M (2 << 3) | |
133 | #define SNB_GMCH_GMS_STOLEN_96M (3 << 3) | |
134 | #define SNB_GMCH_GMS_STOLEN_128M (4 << 3) | |
135 | #define SNB_GMCH_GMS_STOLEN_160M (5 << 3) | |
136 | #define SNB_GMCH_GMS_STOLEN_192M (6 << 3) | |
137 | #define SNB_GMCH_GMS_STOLEN_224M (7 << 3) | |
138 | #define SNB_GMCH_GMS_STOLEN_256M (8 << 3) | |
139 | #define SNB_GMCH_GMS_STOLEN_288M (9 << 3) | |
140 | #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) | |
141 | #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) | |
142 | #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) | |
143 | #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) | |
144 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) | |
145 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) | |
146 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) | |
147 | #define SNB_GTT_SIZE_0M (0 << 8) | |
148 | #define SNB_GTT_SIZE_1M (1 << 8) | |
149 | #define SNB_GTT_SIZE_2M (2 << 8) | |
150 | #define SNB_GTT_SIZE_MASK (3 << 8) | |
151 | ||
152 | /* pci devices ids */ | |
153 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 | |
154 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
155 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 | |
156 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
157 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 | |
158 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
159 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 | |
160 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
161 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
162 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
163 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 | |
164 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
165 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 | |
166 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 | |
167 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC | |
168 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE | |
169 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 | |
170 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 | |
171 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 | |
172 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 | |
173 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 | |
174 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
175 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
176 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
177 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
178 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
179 | #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 | |
180 | #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 | |
181 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 | |
182 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
183 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 | |
184 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 | |
185 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | |
186 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
187 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
188 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
189 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 | |
190 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
191 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 | |
192 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 | |
193 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 | |
194 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 | |
195 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a | |
196 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 | |
197 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 | |
198 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 | |
199 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 | |
200 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106 | |
201 | ||
202 | /* cover 915 and 945 variants */ | |
203 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
204 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
205 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
206 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
207 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
208 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
209 | ||
210 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ | |
211 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ | |
212 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
213 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
214 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
215 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) | |
216 | ||
217 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ | |
218 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
219 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ | |
220 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ | |
221 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
222 | ||
223 | #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ | |
224 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
225 | ||
226 | #define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ | |
227 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) | |
228 | ||
229 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ | |
230 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | |
231 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ | |
232 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ | |
233 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ | |
234 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ | |
235 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \ | |
236 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ | |
237 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ | |
238 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ | |
239 | IS_SNB) |