projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ff7cdd69 DV |
1 | /* |
| 2 | * Common Intel AGPGART and GTT definitions. | |
| 3 | */ | |
| 93f5f7f1 ZW |
4 | #ifndef _INTEL_AGP_H |
| 5 | #define _INTEL_AGP_H | |
| ff7cdd69 DV |
6 | |
| 7 | /* Intel registers */ | |
| 8 | #define INTEL_APSIZE 0xb4 | |
| 9 | #define INTEL_ATTBASE 0xb8 | |
| 10 | #define INTEL_AGPCTRL 0xb0 | |
| 11 | #define INTEL_NBXCFG 0x50 | |
| 12 | #define INTEL_ERRSTS 0x91 | |
| 13 | ||
| 14 | /* Intel i830 registers */ | |
| 15 | #define I830_GMCH_CTRL 0x52 | |
| 16 | #define I830_GMCH_ENABLED 0x4 | |
| 17 | #define I830_GMCH_MEM_MASK 0x1 | |
| 18 | #define I830_GMCH_MEM_64M 0x1 | |
| 19 | #define I830_GMCH_MEM_128M 0 | |
| 20 | #define I830_GMCH_GMS_MASK 0x70 | |
| 21 | #define I830_GMCH_GMS_DISABLED 0x00 | |
| 22 | #define I830_GMCH_GMS_LOCAL 0x10 | |
| 23 | #define I830_GMCH_GMS_STOLEN_512 0x20 | |
| 24 | #define I830_GMCH_GMS_STOLEN_1024 0x30 | |
| 25 | #define I830_GMCH_GMS_STOLEN_8192 0x40 | |
| 26 | #define I830_RDRAM_CHANNEL_TYPE 0x03010 | |
| 27 | #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) | |
| 28 | #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) | |
| 29 | ||
| 30 | /* This one is for I830MP w. an external graphic card */ | |
| 31 | #define INTEL_I830_ERRSTS 0x92 | |
| 32 | ||
| 33 | /* Intel 855GM/852GM registers */ | |
| 34 | #define I855_GMCH_GMS_MASK 0xF0 | |
| 35 | #define I855_GMCH_GMS_STOLEN_0M 0x0 | |
| 36 | #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) | |
| 37 | #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) | |
| 38 | #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) | |
| 39 | #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) | |
| 40 | #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) | |
| 41 | #define I85X_CAPID 0x44 | |
| 42 | #define I85X_VARIANT_MASK 0x7 | |
| 43 | #define I85X_VARIANT_SHIFT 5 | |
| 44 | #define I855_GME 0x0 | |
| 45 | #define I855_GM 0x4 | |
| 46 | #define I852_GME 0x2 | |
| 47 | #define I852_GM 0x5 | |
| 48 | ||
| 49 | /* Intel i845 registers */ | |
| 50 | #define INTEL_I845_AGPM 0x51 | |
| 51 | #define INTEL_I845_ERRSTS 0xc8 | |
| 52 | ||
| 53 | /* Intel i860 registers */ | |
| 54 | #define INTEL_I860_MCHCFG 0x50 | |
| 55 | #define INTEL_I860_ERRSTS 0xc8 | |
| 56 | ||
| 57 | /* Intel i810 registers */ | |
| 58 | #define I810_GMADDR 0x10 | |
| 59 | #define I810_MMADDR 0x14 | |
| 60 | #define I810_PTE_BASE 0x10000 | |
| 61 | #define I810_PTE_MAIN_UNCACHED 0x00000000 | |
| 62 | #define I810_PTE_LOCAL 0x00000002 | |
| 63 | #define I810_PTE_VALID 0x00000001 | |
| 64 | #define I830_PTE_SYSTEM_CACHED 0x00000006 | |
| a2757b6f ZW |
65 | /* GT PTE cache control fields */ |
| 66 | #define GEN6_PTE_UNCACHED 0x00000002 | |
| 67 | #define GEN6_PTE_LLC 0x00000004 | |
| 68 | #define GEN6_PTE_LLC_MLC 0x00000006 | |
| 69 | #define GEN6_PTE_GFDT 0x00000008 | |
| 70 | ||
| ff7cdd69 DV |
71 | #define I810_SMRAM_MISCC 0x70 |
| 72 | #define I810_GFX_MEM_WIN_SIZE 0x00010000 | |
| 73 | #define I810_GFX_MEM_WIN_32M 0x00010000 | |
| 74 | #define I810_GMS 0x000000c0 | |
| 75 | #define I810_GMS_DISABLE 0x00000000 | |
| 76 | #define I810_PGETBL_CTL 0x2020 | |
| 77 | #define I810_PGETBL_ENABLED 0x00000001 | |
| 20172842 DV |
78 | /* Note: PGETBL_CTL2 has a different offset on G33. */ |
| 79 | #define I965_PGETBL_CTL2 0x20c4 | |
| ff7cdd69 DV |
80 | #define I965_PGETBL_SIZE_MASK 0x0000000e |
| 81 | #define I965_PGETBL_SIZE_512KB (0 << 1) | |
| 82 | #define I965_PGETBL_SIZE_256KB (1 << 1) | |
| 83 | #define I965_PGETBL_SIZE_128KB (2 << 1) | |
| 84 | #define I965_PGETBL_SIZE_1MB (3 << 1) | |
| 85 | #define I965_PGETBL_SIZE_2MB (4 << 1) | |
| 86 | #define I965_PGETBL_SIZE_1_5MB (5 << 1) | |
| 20172842 DV |
87 | #define G33_GMCH_SIZE_MASK (3 << 8) |
| 88 | #define G33_GMCH_SIZE_1M (1 << 8) | |
| 89 | #define G33_GMCH_SIZE_2M (2 << 8) | |
| 90 | #define G4x_GMCH_SIZE_MASK (0xf << 8) | |
| 91 | #define G4x_GMCH_SIZE_1M (0x1 << 8) | |
| 92 | #define G4x_GMCH_SIZE_2M (0x3 << 8) | |
| 780d7cc4 CW |
93 | #define G4x_GMCH_SIZE_VT_EN (0x8 << 8) |
| 94 | #define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN) | |
| 95 | #define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN) | |
| 96 | #define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) | |
| ff7cdd69 | 97 | |
| c97689d8 CW |
98 | #define GFX_FLSH_CNTL 0x2170 /* 915+ */ |
| 99 | ||
| ff7cdd69 DV |
100 | #define I810_DRAM_CTL 0x3000 |
| 101 | #define I810_DRAM_ROW_0 0x00000001 | |
| 102 | #define I810_DRAM_ROW_0_SDRAM 0x00000001 | |
| 103 | ||
| 104 | /* Intel 815 register */ | |
| 105 | #define INTEL_815_APCONT 0x51 | |
| 106 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
| 107 | ||
| 108 | /* Intel i820 registers */ | |
| 109 | #define INTEL_I820_RDCR 0x51 | |
| 110 | #define INTEL_I820_ERRSTS 0xc8 | |
| 111 | ||
| 112 | /* Intel i840 registers */ | |
| 113 | #define INTEL_I840_MCHCFG 0x50 | |
| 114 | #define INTEL_I840_ERRSTS 0xc8 | |
| 115 | ||
| 116 | /* Intel i850 registers */ | |
| 117 | #define INTEL_I850_MCHCFG 0x50 | |
| 118 | #define INTEL_I850_ERRSTS 0xc8 | |
| 119 | ||
| 120 | /* intel 915G registers */ | |
| 121 | #define I915_GMADDR 0x18 | |
| 122 | #define I915_MMADDR 0x10 | |
| 123 | #define I915_PTEADDR 0x1C | |
| 124 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
| 125 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
| 126 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) | |
| 127 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
| 128 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
| 129 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
| 130 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
| 131 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
| 132 | ||
| 133 | #define I915_IFPADDR 0x60 | |
| bdb8b975 | 134 | #define I830_HIC 0x70 |
| ff7cdd69 DV |
135 | |
| 136 | /* Intel 965G registers */ | |
| 137 | #define I965_MSAC 0x62 | |
| 138 | #define I965_IFPADDR 0x70 | |
| 139 | ||
| 140 | /* Intel 7505 registers */ | |
| 141 | #define INTEL_I7505_APSIZE 0x74 | |
| 142 | #define INTEL_I7505_NCAPID 0x60 | |
| 143 | #define INTEL_I7505_NISTAT 0x6c | |
| 144 | #define INTEL_I7505_ATTBASE 0x78 | |
| 145 | #define INTEL_I7505_ERRSTS 0x42 | |
| 146 | #define INTEL_I7505_AGPCTRL 0x70 | |
| 147 | #define INTEL_I7505_MCHCFG 0x50 | |
| 148 | ||
| 149 | #define SNB_GMCH_CTRL 0x50 | |
| 150 | #define SNB_GMCH_GMS_STOLEN_MASK 0xF8 | |
| 151 | #define SNB_GMCH_GMS_STOLEN_32M (1 << 3) | |
| 152 | #define SNB_GMCH_GMS_STOLEN_64M (2 << 3) | |
| 153 | #define SNB_GMCH_GMS_STOLEN_96M (3 << 3) | |
| 154 | #define SNB_GMCH_GMS_STOLEN_128M (4 << 3) | |
| 155 | #define SNB_GMCH_GMS_STOLEN_160M (5 << 3) | |
| 156 | #define SNB_GMCH_GMS_STOLEN_192M (6 << 3) | |
| 157 | #define SNB_GMCH_GMS_STOLEN_224M (7 << 3) | |
| 158 | #define SNB_GMCH_GMS_STOLEN_256M (8 << 3) | |
| 159 | #define SNB_GMCH_GMS_STOLEN_288M (9 << 3) | |
| 160 | #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) | |
| 161 | #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) | |
| 162 | #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) | |
| 163 | #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) | |
| 164 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) | |
| 165 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) | |
| 166 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) | |
| 167 | #define SNB_GTT_SIZE_0M (0 << 8) | |
| 168 | #define SNB_GTT_SIZE_1M (1 << 8) | |
| 169 | #define SNB_GTT_SIZE_2M (2 << 8) | |
| 170 | #define SNB_GTT_SIZE_MASK (3 << 8) | |
| 171 | ||
| 172 | /* pci devices ids */ | |
| 173 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 | |
| 174 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
| 175 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 | |
| 176 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
| 177 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 | |
| 178 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
| 179 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 | |
| 180 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
| 181 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
| 182 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
| 183 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 | |
| 184 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
| 185 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 | |
| 186 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 | |
| 187 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC | |
| 188 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE | |
| 189 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 | |
| 190 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 | |
| 191 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 | |
| 192 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 | |
| 193 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 | |
| 194 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
| 195 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
| 196 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
| 197 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
| 198 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
| 199 | #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 | |
| 200 | #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 | |
| 41a51428 CW |
201 | #define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90 |
| 202 | #define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92 | |
| ff7cdd69 DV |
203 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
| 204 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
| 205 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 | |
| 206 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 | |
| 207 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | |
| 208 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
| 209 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
| 210 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
| 211 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 | |
| 212 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
| 213 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 | |
| 214 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 | |
| 215 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 | |
| 216 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 | |
| 217 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a | |
| 218 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 | |
| 85540480 ZW |
219 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */ |
| 220 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102 | |
| 221 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112 | |
| 222 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122 | |
| 223 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */ | |
| 224 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106 | |
| 225 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116 | |
| 226 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126 | |
| 227 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */ | |
| 228 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A | |
| 246d08b8 JB |
229 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */ |
| 230 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152 | |
| 231 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162 | |
| 232 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */ | |
| 233 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156 | |
| 234 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166 | |
| 235 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */ | |
| 236 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A | |
| cc22a938 | 237 | #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A |
| ff7cdd69 | 238 | |
| e2404e7c DV |
239 | int intel_gmch_probe(struct pci_dev *pdev, |
| 240 | struct agp_bridge_data *bridge); | |
| 241 | void intel_gmch_remove(struct pci_dev *pdev); | |
| 93f5f7f1 | 242 | #endif |