Commit | Line | Data |
---|---|---|
f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/pagemap.h> | |
23 | #include <linux/agp_backend.h> | |
bdb8b975 | 24 | #include <linux/delay.h> |
e2404e7c DV |
25 | #include <asm/smp.h> |
26 | #include "agp.h" | |
27 | #include "intel-agp.h" | |
0ade6386 | 28 | #include <drm/intel-gtt.h> |
e2404e7c | 29 | |
f51b7662 DV |
30 | /* |
31 | * If we have Intel graphics, we're not going to have anything other than | |
32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
d3f13810 | 33 | * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). |
f51b7662 DV |
34 | * Only newer chipsets need to bother with this, of course. |
35 | */ | |
d3f13810 | 36 | #ifdef CONFIG_INTEL_IOMMU |
f51b7662 | 37 | #define USE_PCI_DMA_API 1 |
0e87d2b0 DV |
38 | #else |
39 | #define USE_PCI_DMA_API 0 | |
f51b7662 DV |
40 | #endif |
41 | ||
1a997ff2 DV |
42 | struct intel_gtt_driver { |
43 | unsigned int gen : 8; | |
44 | unsigned int is_g33 : 1; | |
45 | unsigned int is_pineview : 1; | |
46 | unsigned int is_ironlake : 1; | |
100519e2 | 47 | unsigned int has_pgtbl_enable : 1; |
22533b49 | 48 | unsigned int dma_mask_size : 8; |
73800422 DV |
49 | /* Chipset specific GTT setup */ |
50 | int (*setup)(void); | |
ae83dd5c DV |
51 | /* This should undo anything done in ->setup() save the unmapping |
52 | * of the mmio register file, that's done in the generic code. */ | |
53 | void (*cleanup)(void); | |
351bb278 DV |
54 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
55 | /* Flags is a more or less chipset specific opaque value. | |
56 | * For chipsets that need to support old ums (non-gem) code, this | |
57 | * needs to be identical to the various supported agp memory types! */ | |
5cbecafc | 58 | bool (*check_flags)(unsigned int flags); |
1b263f24 | 59 | void (*chipset_flush)(void); |
1a997ff2 DV |
60 | }; |
61 | ||
f51b7662 | 62 | static struct _intel_private { |
0ade6386 | 63 | struct intel_gtt base; |
1a997ff2 | 64 | const struct intel_gtt_driver *driver; |
f51b7662 | 65 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 66 | struct pci_dev *bridge_dev; |
f51b7662 | 67 | u8 __iomem *registers; |
f67eab66 | 68 | phys_addr_t gtt_bus_addr; |
b3eafc5a | 69 | u32 PGETBL_save; |
f51b7662 | 70 | u32 __iomem *gtt; /* I915G */ |
bee4a186 | 71 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
f51b7662 | 72 | int num_dcache_entries; |
bdb8b975 | 73 | void __iomem *i9xx_flush_page; |
820647b9 | 74 | char *i81x_gtt_table; |
f51b7662 DV |
75 | struct resource ifp_resource; |
76 | int resource_valid; | |
0e87d2b0 | 77 | struct page *scratch_page; |
14be93dd | 78 | int refcount; |
f51b7662 DV |
79 | } intel_private; |
80 | ||
1a997ff2 DV |
81 | #define INTEL_GTT_GEN intel_private.driver->gen |
82 | #define IS_G33 intel_private.driver->is_g33 | |
83 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
84 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
100519e2 | 85 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
1a997ff2 | 86 | |
9da3da66 CW |
87 | static int intel_gtt_map_memory(struct page **pages, |
88 | unsigned int num_entries, | |
89 | struct sg_table *st) | |
f51b7662 | 90 | { |
f51b7662 DV |
91 | struct scatterlist *sg; |
92 | int i; | |
93 | ||
4080775b | 94 | DBG("try mapping %lu pages\n", (unsigned long)num_entries); |
f51b7662 | 95 | |
9da3da66 | 96 | if (sg_alloc_table(st, num_entries, GFP_KERNEL)) |
831cd445 | 97 | goto err; |
f51b7662 | 98 | |
9da3da66 | 99 | for_each_sg(st->sgl, sg, num_entries, i) |
4080775b | 100 | sg_set_page(sg, pages[i], PAGE_SIZE, 0); |
f51b7662 | 101 | |
9da3da66 CW |
102 | if (!pci_map_sg(intel_private.pcidev, |
103 | st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) | |
831cd445 CW |
104 | goto err; |
105 | ||
f51b7662 | 106 | return 0; |
831cd445 CW |
107 | |
108 | err: | |
9da3da66 | 109 | sg_free_table(st); |
831cd445 | 110 | return -ENOMEM; |
f51b7662 DV |
111 | } |
112 | ||
9da3da66 | 113 | static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) |
f51b7662 | 114 | { |
4080775b | 115 | struct sg_table st; |
f51b7662 DV |
116 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
117 | ||
4080775b DV |
118 | pci_unmap_sg(intel_private.pcidev, sg_list, |
119 | num_sg, PCI_DMA_BIDIRECTIONAL); | |
120 | ||
121 | st.sgl = sg_list; | |
122 | st.orig_nents = st.nents = num_sg; | |
123 | ||
124 | sg_free_table(&st); | |
f51b7662 DV |
125 | } |
126 | ||
ffdd7510 | 127 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
128 | { |
129 | return; | |
130 | } | |
131 | ||
132 | /* Exists to support ARGB cursors */ | |
133 | static struct page *i8xx_alloc_pages(void) | |
134 | { | |
135 | struct page *page; | |
136 | ||
137 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
138 | if (page == NULL) | |
139 | return NULL; | |
140 | ||
141 | if (set_pages_uc(page, 4) < 0) { | |
142 | set_pages_wb(page, 4); | |
143 | __free_pages(page, 2); | |
144 | return NULL; | |
145 | } | |
146 | get_page(page); | |
147 | atomic_inc(&agp_bridge->current_memory_agp); | |
148 | return page; | |
149 | } | |
150 | ||
151 | static void i8xx_destroy_pages(struct page *page) | |
152 | { | |
153 | if (page == NULL) | |
154 | return; | |
155 | ||
156 | set_pages_wb(page, 4); | |
157 | put_page(page); | |
158 | __free_pages(page, 2); | |
159 | atomic_dec(&agp_bridge->current_memory_agp); | |
160 | } | |
161 | ||
820647b9 DV |
162 | #define I810_GTT_ORDER 4 |
163 | static int i810_setup(void) | |
164 | { | |
165 | u32 reg_addr; | |
166 | char *gtt_table; | |
167 | ||
168 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ | |
169 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); | |
170 | if (gtt_table == NULL) | |
171 | return -ENOMEM; | |
172 | intel_private.i81x_gtt_table = gtt_table; | |
173 | ||
174 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
175 | reg_addr &= 0xfff80000; | |
176 | ||
177 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
178 | if (!intel_private.registers) | |
179 | return -ENOMEM; | |
180 | ||
181 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, | |
182 | intel_private.registers+I810_PGETBL_CTL); | |
183 | ||
184 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; | |
185 | ||
186 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
187 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
188 | dev_info(&intel_private.pcidev->dev, | |
189 | "detected 4MB dedicated video ram\n"); | |
190 | intel_private.num_dcache_entries = 1024; | |
191 | } | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | static void i810_cleanup(void) | |
197 | { | |
198 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
199 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); | |
200 | } | |
201 | ||
ff26860f DV |
202 | static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, |
203 | int type) | |
f51b7662 | 204 | { |
625dd9d3 | 205 | int i; |
f51b7662 | 206 | |
ff26860f DV |
207 | if ((pg_start + mem->page_count) |
208 | > intel_private.num_dcache_entries) | |
209 | return -EINVAL; | |
625dd9d3 | 210 | |
ff26860f DV |
211 | if (!mem->is_flushed) |
212 | global_cache_flush(); | |
f51b7662 | 213 | |
ff26860f DV |
214 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
215 | dma_addr_t addr = i << PAGE_SHIFT; | |
216 | intel_private.driver->write_entry(addr, | |
217 | i, type); | |
f51b7662 | 218 | } |
ff26860f | 219 | readl(intel_private.gtt+i-1); |
f51b7662 | 220 | |
ff26860f | 221 | return 0; |
f51b7662 DV |
222 | } |
223 | ||
224 | /* | |
225 | * The i810/i830 requires a physical address to program its mouse | |
226 | * pointer into hardware. | |
227 | * However the Xserver still writes to it through the agp aperture. | |
228 | */ | |
229 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
230 | { | |
231 | struct agp_memory *new; | |
232 | struct page *page; | |
233 | ||
234 | switch (pg_count) { | |
235 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
236 | break; | |
237 | case 4: | |
238 | /* kludge to get 4 physical pages for ARGB cursor */ | |
239 | page = i8xx_alloc_pages(); | |
240 | break; | |
241 | default: | |
242 | return NULL; | |
243 | } | |
244 | ||
245 | if (page == NULL) | |
246 | return NULL; | |
247 | ||
248 | new = agp_create_memory(pg_count); | |
249 | if (new == NULL) | |
250 | return NULL; | |
251 | ||
252 | new->pages[0] = page; | |
253 | if (pg_count == 4) { | |
254 | /* kludge to get 4 physical pages for ARGB cursor */ | |
255 | new->pages[1] = new->pages[0] + 1; | |
256 | new->pages[2] = new->pages[1] + 1; | |
257 | new->pages[3] = new->pages[2] + 1; | |
258 | } | |
259 | new->page_count = pg_count; | |
260 | new->num_scratch_pages = pg_count; | |
261 | new->type = AGP_PHYS_MEMORY; | |
262 | new->physical = page_to_phys(new->pages[0]); | |
263 | return new; | |
264 | } | |
265 | ||
f51b7662 DV |
266 | static void intel_i810_free_by_type(struct agp_memory *curr) |
267 | { | |
268 | agp_free_key(curr->key); | |
269 | if (curr->type == AGP_PHYS_MEMORY) { | |
270 | if (curr->page_count == 4) | |
271 | i8xx_destroy_pages(curr->pages[0]); | |
272 | else { | |
273 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
274 | AGP_PAGE_DESTROY_UNMAP); | |
275 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
276 | AGP_PAGE_DESTROY_FREE); | |
277 | } | |
278 | agp_free_page_array(curr); | |
279 | } | |
280 | kfree(curr); | |
281 | } | |
282 | ||
0e87d2b0 DV |
283 | static int intel_gtt_setup_scratch_page(void) |
284 | { | |
285 | struct page *page; | |
286 | dma_addr_t dma_addr; | |
287 | ||
288 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
289 | if (page == NULL) | |
290 | return -ENOMEM; | |
291 | get_page(page); | |
292 | set_pages_uc(page, 1); | |
293 | ||
4080775b | 294 | if (intel_private.base.needs_dmar) { |
0e87d2b0 DV |
295 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
296 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
297 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) | |
298 | return -EINVAL; | |
299 | ||
50a4c4a9 | 300 | intel_private.base.scratch_page_dma = dma_addr; |
0e87d2b0 | 301 | } else |
50a4c4a9 | 302 | intel_private.base.scratch_page_dma = page_to_phys(page); |
0e87d2b0 DV |
303 | |
304 | intel_private.scratch_page = page; | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
625dd9d3 DV |
309 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
310 | unsigned int flags) | |
311 | { | |
312 | u32 pte_flags = I810_PTE_VALID; | |
313 | ||
314 | switch (flags) { | |
315 | case AGP_DCACHE_MEMORY: | |
316 | pte_flags |= I810_PTE_LOCAL; | |
317 | break; | |
318 | case AGP_USER_CACHED_MEMORY: | |
319 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
320 | break; | |
321 | } | |
322 | ||
323 | writel(addr | pte_flags, intel_private.gtt + entry); | |
324 | } | |
325 | ||
7bdc9ab0 | 326 | static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { |
820647b9 DV |
327 | {32, 8192, 3}, |
328 | {64, 16384, 4}, | |
f51b7662 | 329 | {128, 32768, 5}, |
f51b7662 DV |
330 | {256, 65536, 6}, |
331 | {512, 131072, 7}, | |
332 | }; | |
333 | ||
c64f7ba5 | 334 | static unsigned int intel_gtt_stolen_size(void) |
f51b7662 DV |
335 | { |
336 | u16 gmch_ctrl; | |
f51b7662 DV |
337 | u8 rdct; |
338 | int local = 0; | |
339 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
d8d9abcd | 340 | unsigned int stolen_size = 0; |
f51b7662 | 341 | |
820647b9 DV |
342 | if (INTEL_GTT_GEN == 1) |
343 | return 0; /* no stolen mem on i81x */ | |
344 | ||
d7cca2f7 DV |
345 | pci_read_config_word(intel_private.bridge_dev, |
346 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 347 | |
d7cca2f7 DV |
348 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
349 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
350 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
351 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 352 | stolen_size = KB(512); |
f51b7662 DV |
353 | break; |
354 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 355 | stolen_size = MB(1); |
f51b7662 DV |
356 | break; |
357 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 358 | stolen_size = MB(8); |
f51b7662 DV |
359 | break; |
360 | case I830_GMCH_GMS_LOCAL: | |
361 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 362 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
363 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
364 | local = 1; | |
365 | break; | |
366 | default: | |
d8d9abcd | 367 | stolen_size = 0; |
f51b7662 DV |
368 | break; |
369 | } | |
1a997ff2 | 370 | } else if (INTEL_GTT_GEN == 6) { |
f51b7662 DV |
371 | /* |
372 | * SandyBridge has new memory control reg at 0x50.w | |
373 | */ | |
374 | u16 snb_gmch_ctl; | |
375 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
376 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
377 | case SNB_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 378 | stolen_size = MB(32); |
f51b7662 DV |
379 | break; |
380 | case SNB_GMCH_GMS_STOLEN_64M: | |
d8d9abcd | 381 | stolen_size = MB(64); |
f51b7662 DV |
382 | break; |
383 | case SNB_GMCH_GMS_STOLEN_96M: | |
d8d9abcd | 384 | stolen_size = MB(96); |
f51b7662 DV |
385 | break; |
386 | case SNB_GMCH_GMS_STOLEN_128M: | |
d8d9abcd | 387 | stolen_size = MB(128); |
f51b7662 DV |
388 | break; |
389 | case SNB_GMCH_GMS_STOLEN_160M: | |
d8d9abcd | 390 | stolen_size = MB(160); |
f51b7662 DV |
391 | break; |
392 | case SNB_GMCH_GMS_STOLEN_192M: | |
d8d9abcd | 393 | stolen_size = MB(192); |
f51b7662 DV |
394 | break; |
395 | case SNB_GMCH_GMS_STOLEN_224M: | |
d8d9abcd | 396 | stolen_size = MB(224); |
f51b7662 DV |
397 | break; |
398 | case SNB_GMCH_GMS_STOLEN_256M: | |
d8d9abcd | 399 | stolen_size = MB(256); |
f51b7662 DV |
400 | break; |
401 | case SNB_GMCH_GMS_STOLEN_288M: | |
d8d9abcd | 402 | stolen_size = MB(288); |
f51b7662 DV |
403 | break; |
404 | case SNB_GMCH_GMS_STOLEN_320M: | |
d8d9abcd | 405 | stolen_size = MB(320); |
f51b7662 DV |
406 | break; |
407 | case SNB_GMCH_GMS_STOLEN_352M: | |
d8d9abcd | 408 | stolen_size = MB(352); |
f51b7662 DV |
409 | break; |
410 | case SNB_GMCH_GMS_STOLEN_384M: | |
d8d9abcd | 411 | stolen_size = MB(384); |
f51b7662 DV |
412 | break; |
413 | case SNB_GMCH_GMS_STOLEN_416M: | |
d8d9abcd | 414 | stolen_size = MB(416); |
f51b7662 DV |
415 | break; |
416 | case SNB_GMCH_GMS_STOLEN_448M: | |
d8d9abcd | 417 | stolen_size = MB(448); |
f51b7662 DV |
418 | break; |
419 | case SNB_GMCH_GMS_STOLEN_480M: | |
d8d9abcd | 420 | stolen_size = MB(480); |
f51b7662 DV |
421 | break; |
422 | case SNB_GMCH_GMS_STOLEN_512M: | |
d8d9abcd | 423 | stolen_size = MB(512); |
f51b7662 DV |
424 | break; |
425 | } | |
426 | } else { | |
427 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
428 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 429 | stolen_size = MB(1); |
f51b7662 DV |
430 | break; |
431 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 432 | stolen_size = MB(4); |
f51b7662 DV |
433 | break; |
434 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 435 | stolen_size = MB(8); |
f51b7662 DV |
436 | break; |
437 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 438 | stolen_size = MB(16); |
f51b7662 DV |
439 | break; |
440 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 441 | stolen_size = MB(32); |
f51b7662 DV |
442 | break; |
443 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 444 | stolen_size = MB(48); |
f51b7662 DV |
445 | break; |
446 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 447 | stolen_size = MB(64); |
f51b7662 DV |
448 | break; |
449 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 450 | stolen_size = MB(128); |
f51b7662 DV |
451 | break; |
452 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 453 | stolen_size = MB(256); |
f51b7662 DV |
454 | break; |
455 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 456 | stolen_size = MB(96); |
f51b7662 DV |
457 | break; |
458 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 459 | stolen_size = MB(160); |
f51b7662 DV |
460 | break; |
461 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 462 | stolen_size = MB(224); |
f51b7662 DV |
463 | break; |
464 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 465 | stolen_size = MB(352); |
f51b7662 DV |
466 | break; |
467 | default: | |
d8d9abcd | 468 | stolen_size = 0; |
f51b7662 DV |
469 | break; |
470 | } | |
471 | } | |
1784a5fb | 472 | |
1b6064d7 | 473 | if (stolen_size > 0) { |
d7cca2f7 | 474 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
d8d9abcd | 475 | stolen_size / KB(1), local ? "local" : "stolen"); |
f51b7662 | 476 | } else { |
d7cca2f7 | 477 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 478 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 479 | stolen_size = 0; |
f51b7662 DV |
480 | } |
481 | ||
c64f7ba5 | 482 | return stolen_size; |
f51b7662 DV |
483 | } |
484 | ||
20172842 DV |
485 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
486 | { | |
487 | u32 pgetbl_ctl, pgetbl_ctl2; | |
488 | ||
489 | /* ensure that ppgtt is disabled */ | |
490 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); | |
491 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; | |
492 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); | |
493 | ||
494 | /* write the new ggtt size */ | |
495 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
496 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; | |
497 | pgetbl_ctl |= size_flag; | |
498 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); | |
499 | } | |
500 | ||
501 | static unsigned int i965_gtt_total_entries(void) | |
fbe40783 DV |
502 | { |
503 | int size; | |
20172842 DV |
504 | u32 pgetbl_ctl; |
505 | u16 gmch_ctl; | |
fbe40783 | 506 | |
20172842 DV |
507 | pci_read_config_word(intel_private.bridge_dev, |
508 | I830_GMCH_CTRL, &gmch_ctl); | |
fbe40783 | 509 | |
20172842 DV |
510 | if (INTEL_GTT_GEN == 5) { |
511 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { | |
512 | case G4x_GMCH_SIZE_1M: | |
513 | case G4x_GMCH_SIZE_VT_1M: | |
514 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); | |
fbe40783 | 515 | break; |
20172842 DV |
516 | case G4x_GMCH_SIZE_VT_1_5M: |
517 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); | |
fbe40783 | 518 | break; |
20172842 DV |
519 | case G4x_GMCH_SIZE_2M: |
520 | case G4x_GMCH_SIZE_VT_2M: | |
521 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); | |
fbe40783 | 522 | break; |
fbe40783 | 523 | } |
20172842 | 524 | } |
e5e408fc | 525 | |
20172842 DV |
526 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
527 | ||
528 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
529 | case I965_PGETBL_SIZE_128KB: | |
530 | size = KB(128); | |
531 | break; | |
532 | case I965_PGETBL_SIZE_256KB: | |
533 | size = KB(256); | |
534 | break; | |
535 | case I965_PGETBL_SIZE_512KB: | |
536 | size = KB(512); | |
537 | break; | |
538 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ | |
539 | case I965_PGETBL_SIZE_1MB: | |
540 | size = KB(1024); | |
541 | break; | |
542 | case I965_PGETBL_SIZE_2MB: | |
543 | size = KB(2048); | |
544 | break; | |
545 | case I965_PGETBL_SIZE_1_5MB: | |
546 | size = KB(1024 + 512); | |
547 | break; | |
548 | default: | |
549 | dev_info(&intel_private.pcidev->dev, | |
550 | "unknown page table size, assuming 512KB\n"); | |
551 | size = KB(512); | |
552 | } | |
553 | ||
554 | return size/4; | |
555 | } | |
556 | ||
557 | static unsigned int intel_gtt_total_entries(void) | |
558 | { | |
559 | int size; | |
560 | ||
561 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) | |
562 | return i965_gtt_total_entries(); | |
563 | else if (INTEL_GTT_GEN == 6) { | |
210b23c2 DV |
564 | u16 snb_gmch_ctl; |
565 | ||
566 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
567 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { | |
568 | default: | |
569 | case SNB_GTT_SIZE_0M: | |
570 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); | |
571 | size = MB(0); | |
572 | break; | |
573 | case SNB_GTT_SIZE_1M: | |
574 | size = MB(1); | |
575 | break; | |
576 | case SNB_GTT_SIZE_2M: | |
577 | size = MB(2); | |
578 | break; | |
579 | } | |
e5e408fc | 580 | return size/4; |
fbe40783 DV |
581 | } else { |
582 | /* On previous hardware, the GTT size was just what was | |
583 | * required to map the aperture. | |
584 | */ | |
e5e408fc | 585 | return intel_private.base.gtt_mappable_entries; |
fbe40783 | 586 | } |
fbe40783 | 587 | } |
fbe40783 | 588 | |
1784a5fb DV |
589 | static unsigned int intel_gtt_mappable_entries(void) |
590 | { | |
591 | unsigned int aperture_size; | |
1784a5fb | 592 | |
820647b9 DV |
593 | if (INTEL_GTT_GEN == 1) { |
594 | u32 smram_miscc; | |
595 | ||
596 | pci_read_config_dword(intel_private.bridge_dev, | |
597 | I810_SMRAM_MISCC, &smram_miscc); | |
598 | ||
599 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) | |
600 | == I810_GFX_MEM_WIN_32M) | |
601 | aperture_size = MB(32); | |
602 | else | |
603 | aperture_size = MB(64); | |
604 | } else if (INTEL_GTT_GEN == 2) { | |
b1c5b0f8 | 605 | u16 gmch_ctrl; |
1784a5fb | 606 | |
b1c5b0f8 CW |
607 | pci_read_config_word(intel_private.bridge_dev, |
608 | I830_GMCH_CTRL, &gmch_ctrl); | |
1784a5fb | 609 | |
1784a5fb | 610 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
b1c5b0f8 | 611 | aperture_size = MB(64); |
1784a5fb | 612 | else |
b1c5b0f8 | 613 | aperture_size = MB(128); |
239918f7 | 614 | } else { |
1784a5fb DV |
615 | /* 9xx supports large sizes, just look at the length */ |
616 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
1784a5fb DV |
617 | } |
618 | ||
619 | return aperture_size >> PAGE_SHIFT; | |
620 | } | |
621 | ||
0e87d2b0 DV |
622 | static void intel_gtt_teardown_scratch_page(void) |
623 | { | |
624 | set_pages_wb(intel_private.scratch_page, 1); | |
50a4c4a9 | 625 | pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma, |
0e87d2b0 DV |
626 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
627 | put_page(intel_private.scratch_page); | |
628 | __free_page(intel_private.scratch_page); | |
629 | } | |
630 | ||
631 | static void intel_gtt_cleanup(void) | |
632 | { | |
ae83dd5c DV |
633 | intel_private.driver->cleanup(); |
634 | ||
0e87d2b0 DV |
635 | iounmap(intel_private.gtt); |
636 | iounmap(intel_private.registers); | |
625dd9d3 | 637 | |
0e87d2b0 DV |
638 | intel_gtt_teardown_scratch_page(); |
639 | } | |
640 | ||
1784a5fb DV |
641 | static int intel_gtt_init(void) |
642 | { | |
32e3cd6e | 643 | u32 gma_addr; |
f67eab66 | 644 | u32 gtt_map_size; |
3b15a9d7 DV |
645 | int ret; |
646 | ||
3b15a9d7 DV |
647 | ret = intel_private.driver->setup(); |
648 | if (ret != 0) | |
649 | return ret; | |
f67eab66 DV |
650 | |
651 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); | |
652 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); | |
653 | ||
b3eafc5a DV |
654 | /* save the PGETBL reg for resume */ |
655 | intel_private.PGETBL_save = | |
656 | readl(intel_private.registers+I810_PGETBL_CTL) | |
657 | & ~I810_PGETBL_ENABLED; | |
100519e2 CW |
658 | /* we only ever restore the register when enabling the PGTBL... */ |
659 | if (HAS_PGTBL_EN) | |
660 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; | |
b3eafc5a | 661 | |
0af9e92e DV |
662 | dev_info(&intel_private.bridge_dev->dev, |
663 | "detected gtt size: %dK total, %dK mappable\n", | |
664 | intel_private.base.gtt_total_entries * 4, | |
665 | intel_private.base.gtt_mappable_entries * 4); | |
666 | ||
f67eab66 DV |
667 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
668 | ||
669 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, | |
670 | gtt_map_size); | |
671 | if (!intel_private.gtt) { | |
ae83dd5c | 672 | intel_private.driver->cleanup(); |
f67eab66 DV |
673 | iounmap(intel_private.registers); |
674 | return -ENOMEM; | |
675 | } | |
428ccb21 | 676 | intel_private.base.gtt = intel_private.gtt; |
f67eab66 DV |
677 | |
678 | global_cache_flush(); /* FIXME: ? */ | |
679 | ||
c64f7ba5 | 680 | intel_private.base.stolen_size = intel_gtt_stolen_size(); |
1784a5fb | 681 | |
a46f3108 DA |
682 | intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
683 | ||
0e87d2b0 DV |
684 | ret = intel_gtt_setup_scratch_page(); |
685 | if (ret != 0) { | |
686 | intel_gtt_cleanup(); | |
687 | return ret; | |
688 | } | |
689 | ||
32e3cd6e DV |
690 | if (INTEL_GTT_GEN <= 2) |
691 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, | |
692 | &gma_addr); | |
693 | else | |
694 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, | |
695 | &gma_addr); | |
696 | ||
697 | intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); | |
698 | ||
1784a5fb DV |
699 | return 0; |
700 | } | |
701 | ||
3e921f98 DV |
702 | static int intel_fake_agp_fetch_size(void) |
703 | { | |
9e76e7b8 | 704 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
705 | unsigned int aper_size; |
706 | int i; | |
3e921f98 DV |
707 | |
708 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) | |
709 | / MB(1); | |
710 | ||
711 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 | 712 | if (aper_size == intel_fake_agp_sizes[i].size) { |
9e76e7b8 CW |
713 | agp_bridge->current_size = |
714 | (void *) (intel_fake_agp_sizes + i); | |
3e921f98 DV |
715 | return aper_size; |
716 | } | |
717 | } | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
ae83dd5c | 722 | static void i830_cleanup(void) |
f51b7662 | 723 | { |
f51b7662 DV |
724 | } |
725 | ||
726 | /* The chipset_flush interface needs to get data that has already been | |
727 | * flushed out of the CPU all the way out to main memory, because the GPU | |
728 | * doesn't snoop those buffers. | |
729 | * | |
730 | * The 8xx series doesn't have the same lovely interface for flushing the | |
731 | * chipset write buffers that the later chips do. According to the 865 | |
732 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
733 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
734 | * that it'll push whatever was in there out. It appears to work. | |
735 | */ | |
1b263f24 | 736 | static void i830_chipset_flush(void) |
f51b7662 | 737 | { |
bdb8b975 CW |
738 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
739 | ||
740 | /* Forcibly evict everything from the CPU write buffers. | |
741 | * clflush appears to be insufficient. | |
742 | */ | |
743 | wbinvd_on_all_cpus(); | |
744 | ||
745 | /* Now we've only seen documents for this magic bit on 855GM, | |
746 | * we hope it exists for the other gen2 chipsets... | |
747 | * | |
748 | * Also works as advertised on my 845G. | |
749 | */ | |
750 | writel(readl(intel_private.registers+I830_HIC) | (1<<31), | |
751 | intel_private.registers+I830_HIC); | |
f51b7662 | 752 | |
bdb8b975 CW |
753 | while (readl(intel_private.registers+I830_HIC) & (1<<31)) { |
754 | if (time_after(jiffies, timeout)) | |
755 | break; | |
f51b7662 | 756 | |
bdb8b975 CW |
757 | udelay(50); |
758 | } | |
f51b7662 DV |
759 | } |
760 | ||
351bb278 DV |
761 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
762 | unsigned int flags) | |
763 | { | |
764 | u32 pte_flags = I810_PTE_VALID; | |
625dd9d3 | 765 | |
b47cf66f | 766 | if (flags == AGP_USER_CACHED_MEMORY) |
351bb278 | 767 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
351bb278 DV |
768 | |
769 | writel(addr | pte_flags, intel_private.gtt + entry); | |
770 | } | |
771 | ||
8ecd1a66 | 772 | bool intel_enable_gtt(void) |
f51b7662 | 773 | { |
e380f60b | 774 | u8 __iomem *reg; |
f51b7662 | 775 | |
e380f60b CW |
776 | if (INTEL_GTT_GEN >= 6) |
777 | return true; | |
778 | ||
100519e2 CW |
779 | if (INTEL_GTT_GEN == 2) { |
780 | u16 gmch_ctrl; | |
73800422 | 781 | |
100519e2 CW |
782 | pci_read_config_word(intel_private.bridge_dev, |
783 | I830_GMCH_CTRL, &gmch_ctrl); | |
784 | gmch_ctrl |= I830_GMCH_ENABLED; | |
785 | pci_write_config_word(intel_private.bridge_dev, | |
786 | I830_GMCH_CTRL, gmch_ctrl); | |
787 | ||
788 | pci_read_config_word(intel_private.bridge_dev, | |
789 | I830_GMCH_CTRL, &gmch_ctrl); | |
790 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { | |
791 | dev_err(&intel_private.pcidev->dev, | |
792 | "failed to enable the GTT: GMCH_CTRL=%x\n", | |
793 | gmch_ctrl); | |
794 | return false; | |
795 | } | |
e380f60b CW |
796 | } |
797 | ||
c97689d8 CW |
798 | /* On the resume path we may be adjusting the PGTBL value, so |
799 | * be paranoid and flush all chipset write buffers... | |
800 | */ | |
801 | if (INTEL_GTT_GEN >= 3) | |
802 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
803 | ||
e380f60b | 804 | reg = intel_private.registers+I810_PGETBL_CTL; |
100519e2 CW |
805 | writel(intel_private.PGETBL_save, reg); |
806 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { | |
e380f60b | 807 | dev_err(&intel_private.pcidev->dev, |
100519e2 | 808 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
e380f60b CW |
809 | readl(reg), intel_private.PGETBL_save); |
810 | return false; | |
811 | } | |
812 | ||
c97689d8 CW |
813 | if (INTEL_GTT_GEN >= 3) |
814 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
815 | ||
e380f60b | 816 | return true; |
73800422 | 817 | } |
8ecd1a66 | 818 | EXPORT_SYMBOL(intel_enable_gtt); |
73800422 DV |
819 | |
820 | static int i830_setup(void) | |
821 | { | |
822 | u32 reg_addr; | |
823 | ||
824 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
825 | reg_addr &= 0xfff80000; | |
826 | ||
827 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
f51b7662 DV |
828 | if (!intel_private.registers) |
829 | return -ENOMEM; | |
830 | ||
73800422 DV |
831 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
832 | ||
73800422 DV |
833 | return 0; |
834 | } | |
835 | ||
3b15a9d7 | 836 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
73800422 | 837 | { |
73800422 | 838 | agp_bridge->gatt_table_real = NULL; |
f51b7662 | 839 | agp_bridge->gatt_table = NULL; |
73800422 | 840 | agp_bridge->gatt_bus_addr = 0; |
f51b7662 DV |
841 | |
842 | return 0; | |
843 | } | |
844 | ||
ffdd7510 | 845 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
846 | { |
847 | return 0; | |
848 | } | |
849 | ||
351bb278 | 850 | static int intel_fake_agp_configure(void) |
f51b7662 | 851 | { |
e380f60b CW |
852 | if (!intel_enable_gtt()) |
853 | return -EIO; | |
f51b7662 | 854 | |
bee4a186 | 855 | intel_private.clear_fake_agp = true; |
dd2757f8 | 856 | agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr; |
f51b7662 | 857 | |
f51b7662 DV |
858 | return 0; |
859 | } | |
860 | ||
5cbecafc | 861 | static bool i830_check_flags(unsigned int flags) |
f51b7662 | 862 | { |
5cbecafc DV |
863 | switch (flags) { |
864 | case 0: | |
865 | case AGP_PHYS_MEMORY: | |
866 | case AGP_USER_CACHED_MEMORY: | |
867 | case AGP_USER_MEMORY: | |
868 | return true; | |
869 | } | |
870 | ||
871 | return false; | |
872 | } | |
873 | ||
9da3da66 | 874 | void intel_gtt_insert_sg_entries(struct sg_table *st, |
4080775b DV |
875 | unsigned int pg_start, |
876 | unsigned int flags) | |
fefaa70f DV |
877 | { |
878 | struct scatterlist *sg; | |
879 | unsigned int len, m; | |
880 | int i, j; | |
881 | ||
882 | j = pg_start; | |
883 | ||
884 | /* sg may merge pages, but we have to separate | |
885 | * per-page addr for GTT */ | |
9da3da66 | 886 | for_each_sg(st->sgl, sg, st->nents, i) { |
fefaa70f DV |
887 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
888 | for (m = 0; m < len; m++) { | |
889 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
9da3da66 | 890 | intel_private.driver->write_entry(addr, j, flags); |
fefaa70f DV |
891 | j++; |
892 | } | |
893 | } | |
894 | readl(intel_private.gtt+j-1); | |
895 | } | |
4080775b DV |
896 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
897 | ||
9da3da66 CW |
898 | static void intel_gtt_insert_pages(unsigned int first_entry, |
899 | unsigned int num_entries, | |
900 | struct page **pages, | |
901 | unsigned int flags) | |
4080775b DV |
902 | { |
903 | int i, j; | |
904 | ||
905 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { | |
906 | dma_addr_t addr = page_to_phys(pages[i]); | |
907 | intel_private.driver->write_entry(addr, | |
908 | j, flags); | |
909 | } | |
910 | readl(intel_private.gtt+j-1); | |
911 | } | |
fefaa70f | 912 | |
5cbecafc DV |
913 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
914 | off_t pg_start, int type) | |
915 | { | |
f51b7662 | 916 | int ret = -EINVAL; |
f51b7662 | 917 | |
5c042287 BW |
918 | if (intel_private.base.do_idle_maps) |
919 | return -ENODEV; | |
920 | ||
bee4a186 CW |
921 | if (intel_private.clear_fake_agp) { |
922 | int start = intel_private.base.stolen_size / PAGE_SIZE; | |
923 | int end = intel_private.base.gtt_mappable_entries; | |
924 | intel_gtt_clear_range(start, end - start); | |
925 | intel_private.clear_fake_agp = false; | |
926 | } | |
927 | ||
ff26860f DV |
928 | if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) |
929 | return i810_insert_dcache_entries(mem, pg_start, type); | |
930 | ||
f51b7662 DV |
931 | if (mem->page_count == 0) |
932 | goto out; | |
933 | ||
c64f7ba5 | 934 | if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) |
f51b7662 DV |
935 | goto out_err; |
936 | ||
f51b7662 DV |
937 | if (type != mem->type) |
938 | goto out_err; | |
939 | ||
5cbecafc | 940 | if (!intel_private.driver->check_flags(type)) |
f51b7662 DV |
941 | goto out_err; |
942 | ||
943 | if (!mem->is_flushed) | |
944 | global_cache_flush(); | |
945 | ||
4080775b | 946 | if (intel_private.base.needs_dmar) { |
9da3da66 CW |
947 | struct sg_table st; |
948 | ||
949 | ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); | |
fefaa70f DV |
950 | if (ret != 0) |
951 | return ret; | |
952 | ||
9da3da66 CW |
953 | intel_gtt_insert_sg_entries(&st, pg_start, type); |
954 | mem->sg_list = st.sgl; | |
955 | mem->num_sg = st.nents; | |
4080775b DV |
956 | } else |
957 | intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, | |
958 | type); | |
f51b7662 DV |
959 | |
960 | out: | |
961 | ret = 0; | |
962 | out_err: | |
963 | mem->is_flushed = true; | |
964 | return ret; | |
965 | } | |
966 | ||
4080775b DV |
967 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
968 | { | |
969 | unsigned int i; | |
970 | ||
971 | for (i = first_entry; i < (first_entry + num_entries); i++) { | |
50a4c4a9 | 972 | intel_private.driver->write_entry(intel_private.base.scratch_page_dma, |
4080775b DV |
973 | i, 0); |
974 | } | |
975 | readl(intel_private.gtt+i-1); | |
976 | } | |
977 | EXPORT_SYMBOL(intel_gtt_clear_range); | |
978 | ||
5cbecafc DV |
979 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
980 | off_t pg_start, int type) | |
f51b7662 | 981 | { |
f51b7662 DV |
982 | if (mem->page_count == 0) |
983 | return 0; | |
984 | ||
5c042287 BW |
985 | if (intel_private.base.do_idle_maps) |
986 | return -ENODEV; | |
987 | ||
d15eda5c DA |
988 | intel_gtt_clear_range(pg_start, mem->page_count); |
989 | ||
4080775b DV |
990 | if (intel_private.base.needs_dmar) { |
991 | intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); | |
992 | mem->sg_list = NULL; | |
993 | mem->num_sg = 0; | |
f51b7662 | 994 | } |
4080775b | 995 | |
f51b7662 DV |
996 | return 0; |
997 | } | |
998 | ||
ffdd7510 DV |
999 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
1000 | int type) | |
f51b7662 | 1001 | { |
625dd9d3 DV |
1002 | struct agp_memory *new; |
1003 | ||
1004 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { | |
1005 | if (pg_count != intel_private.num_dcache_entries) | |
1006 | return NULL; | |
1007 | ||
1008 | new = agp_create_memory(1); | |
1009 | if (new == NULL) | |
1010 | return NULL; | |
1011 | ||
1012 | new->type = AGP_DCACHE_MEMORY; | |
1013 | new->page_count = pg_count; | |
1014 | new->num_scratch_pages = 0; | |
1015 | agp_free_page_array(new); | |
1016 | return new; | |
1017 | } | |
f51b7662 DV |
1018 | if (type == AGP_PHYS_MEMORY) |
1019 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1020 | /* always return NULL for other allocation types for now */ | |
1021 | return NULL; | |
1022 | } | |
1023 | ||
1024 | static int intel_alloc_chipset_flush_resource(void) | |
1025 | { | |
1026 | int ret; | |
d7cca2f7 | 1027 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1028 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1029 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1030 | |
1031 | return ret; | |
1032 | } | |
1033 | ||
1034 | static void intel_i915_setup_chipset_flush(void) | |
1035 | { | |
1036 | int ret; | |
1037 | u32 temp; | |
1038 | ||
d7cca2f7 | 1039 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1040 | if (!(temp & 0x1)) { |
1041 | intel_alloc_chipset_flush_resource(); | |
1042 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1043 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1044 | } else { |
1045 | temp &= ~1; | |
1046 | ||
1047 | intel_private.resource_valid = 1; | |
1048 | intel_private.ifp_resource.start = temp; | |
1049 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1050 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1051 | /* some BIOSes reserve this area in a pnp some don't */ | |
1052 | if (ret) | |
1053 | intel_private.resource_valid = 0; | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | static void intel_i965_g33_setup_chipset_flush(void) | |
1058 | { | |
1059 | u32 temp_hi, temp_lo; | |
1060 | int ret; | |
1061 | ||
d7cca2f7 DV |
1062 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1063 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1064 | |
1065 | if (!(temp_lo & 0x1)) { | |
1066 | ||
1067 | intel_alloc_chipset_flush_resource(); | |
1068 | ||
1069 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1070 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1071 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1072 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1073 | } else { |
1074 | u64 l64; | |
1075 | ||
1076 | temp_lo &= ~0x1; | |
1077 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1078 | ||
1079 | intel_private.resource_valid = 1; | |
1080 | intel_private.ifp_resource.start = l64; | |
1081 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1082 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1083 | /* some BIOSes reserve this area in a pnp some don't */ | |
1084 | if (ret) | |
1085 | intel_private.resource_valid = 0; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static void intel_i9xx_setup_flush(void) | |
1090 | { | |
1091 | /* return if already configured */ | |
1092 | if (intel_private.ifp_resource.start) | |
1093 | return; | |
1094 | ||
1a997ff2 | 1095 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1096 | return; |
1097 | ||
1098 | /* setup a resource for this object */ | |
1099 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1100 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1101 | ||
1102 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1103 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1104 | intel_i965_g33_setup_chipset_flush(); |
1105 | } else { | |
1106 | intel_i915_setup_chipset_flush(); | |
1107 | } | |
1108 | ||
df51e7aa | 1109 | if (intel_private.ifp_resource.start) |
f51b7662 | 1110 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1111 | if (!intel_private.i9xx_flush_page) |
1112 | dev_err(&intel_private.pcidev->dev, | |
1113 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1114 | } |
1115 | ||
ae83dd5c DV |
1116 | static void i9xx_cleanup(void) |
1117 | { | |
1118 | if (intel_private.i9xx_flush_page) | |
1119 | iounmap(intel_private.i9xx_flush_page); | |
1120 | if (intel_private.resource_valid) | |
1121 | release_resource(&intel_private.ifp_resource); | |
1122 | intel_private.ifp_resource.start = 0; | |
1123 | intel_private.resource_valid = 0; | |
1124 | } | |
1125 | ||
1b263f24 | 1126 | static void i9xx_chipset_flush(void) |
f51b7662 DV |
1127 | { |
1128 | if (intel_private.i9xx_flush_page) | |
1129 | writel(1, intel_private.i9xx_flush_page); | |
1130 | } | |
1131 | ||
71f45660 CW |
1132 | static void i965_write_entry(dma_addr_t addr, |
1133 | unsigned int entry, | |
a6963596 DV |
1134 | unsigned int flags) |
1135 | { | |
71f45660 CW |
1136 | u32 pte_flags; |
1137 | ||
1138 | pte_flags = I810_PTE_VALID; | |
1139 | if (flags == AGP_USER_CACHED_MEMORY) | |
1140 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
1141 | ||
a6963596 DV |
1142 | /* Shift high bits down */ |
1143 | addr |= (addr >> 28) & 0xf0; | |
71f45660 | 1144 | writel(addr | pte_flags, intel_private.gtt + entry); |
a6963596 DV |
1145 | } |
1146 | ||
90cb149e DV |
1147 | static bool gen6_check_flags(unsigned int flags) |
1148 | { | |
1149 | return true; | |
1150 | } | |
1151 | ||
a843af18 DV |
1152 | static void haswell_write_entry(dma_addr_t addr, unsigned int entry, |
1153 | unsigned int flags) | |
1154 | { | |
1155 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; | |
1156 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; | |
1157 | u32 pte_flags; | |
1158 | ||
1159 | if (type_mask == AGP_USER_MEMORY) | |
1160 | pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID; | |
1161 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { | |
1162 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; | |
1163 | if (gfdt) | |
1164 | pte_flags |= GEN6_PTE_GFDT; | |
1165 | } else { /* set 'normal'/'cached' to LLC by default */ | |
1166 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; | |
1167 | if (gfdt) | |
1168 | pte_flags |= GEN6_PTE_GFDT; | |
1169 | } | |
1170 | ||
1171 | /* gen6 has bit11-4 for physical addr bit39-32 */ | |
1172 | addr |= (addr >> 28) & 0xff0; | |
1173 | writel(addr | pte_flags, intel_private.gtt + entry); | |
1174 | } | |
1175 | ||
97ef1bdd DV |
1176 | static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
1177 | unsigned int flags) | |
1178 | { | |
1179 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; | |
1180 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; | |
1181 | u32 pte_flags; | |
1182 | ||
897ef192 | 1183 | if (type_mask == AGP_USER_MEMORY) |
85ccc35b | 1184 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
97ef1bdd | 1185 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
d1108525 | 1186 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
97ef1bdd DV |
1187 | if (gfdt) |
1188 | pte_flags |= GEN6_PTE_GFDT; | |
1189 | } else { /* set 'normal'/'cached' to LLC by default */ | |
d1108525 | 1190 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
97ef1bdd DV |
1191 | if (gfdt) |
1192 | pte_flags |= GEN6_PTE_GFDT; | |
1193 | } | |
1194 | ||
1195 | /* gen6 has bit11-4 for physical addr bit39-32 */ | |
1196 | addr |= (addr >> 28) & 0xff0; | |
1197 | writel(addr | pte_flags, intel_private.gtt + entry); | |
1198 | } | |
1199 | ||
64757876 JB |
1200 | static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, |
1201 | unsigned int flags) | |
1202 | { | |
e87c4699 JB |
1203 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; |
1204 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; | |
64757876 JB |
1205 | u32 pte_flags; |
1206 | ||
e87c4699 JB |
1207 | if (type_mask == AGP_USER_MEMORY) |
1208 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; | |
1209 | else { | |
1210 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; | |
1211 | if (gfdt) | |
1212 | pte_flags |= GEN6_PTE_GFDT; | |
1213 | } | |
64757876 JB |
1214 | |
1215 | /* gen6 has bit11-4 for physical addr bit39-32 */ | |
1216 | addr |= (addr >> 28) & 0xff0; | |
1217 | writel(addr | pte_flags, intel_private.gtt + entry); | |
1218 | ||
1219 | writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV); | |
1220 | } | |
1221 | ||
ae83dd5c DV |
1222 | static void gen6_cleanup(void) |
1223 | { | |
1224 | } | |
1225 | ||
5c042287 BW |
1226 | /* Certain Gen5 chipsets require require idling the GPU before |
1227 | * unmapping anything from the GTT when VT-d is enabled. | |
1228 | */ | |
5c042287 BW |
1229 | static inline int needs_idle_maps(void) |
1230 | { | |
a08185a3 | 1231 | #ifdef CONFIG_INTEL_IOMMU |
5c042287 BW |
1232 | const unsigned short gpu_devid = intel_private.pcidev->device; |
1233 | ||
1234 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1235 | * was loaded first. | |
1236 | */ | |
1237 | if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || | |
1238 | gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && | |
1239 | intel_iommu_gfx_mapped) | |
1240 | return 1; | |
a08185a3 | 1241 | #endif |
5c042287 BW |
1242 | return 0; |
1243 | } | |
1244 | ||
2d2430cf | 1245 | static int i9xx_setup(void) |
f51b7662 | 1246 | { |
2d2430cf | 1247 | u32 reg_addr; |
4b60d29e | 1248 | int size = KB(512); |
f51b7662 | 1249 | |
2d2430cf | 1250 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
f51b7662 | 1251 | |
2d2430cf | 1252 | reg_addr &= 0xfff80000; |
f1befe71 | 1253 | |
4b60d29e JB |
1254 | if (INTEL_GTT_GEN >= 7) |
1255 | size = MB(2); | |
1256 | ||
1257 | intel_private.registers = ioremap(reg_addr, size); | |
ccc4e67b | 1258 | if (!intel_private.registers) |
f51b7662 DV |
1259 | return -ENOMEM; |
1260 | ||
2d2430cf DV |
1261 | if (INTEL_GTT_GEN == 3) { |
1262 | u32 gtt_addr; | |
3f08e4ef | 1263 | |
2d2430cf DV |
1264 | pci_read_config_dword(intel_private.pcidev, |
1265 | I915_PTEADDR, >t_addr); | |
1266 | intel_private.gtt_bus_addr = gtt_addr; | |
1267 | } else { | |
1268 | u32 gtt_offset; | |
1269 | ||
1270 | switch (INTEL_GTT_GEN) { | |
1271 | case 5: | |
1272 | case 6: | |
e597dad8 | 1273 | case 7: |
2d2430cf DV |
1274 | gtt_offset = MB(2); |
1275 | break; | |
1276 | case 4: | |
1277 | default: | |
1278 | gtt_offset = KB(512); | |
1279 | break; | |
1280 | } | |
1281 | intel_private.gtt_bus_addr = reg_addr + gtt_offset; | |
1282 | } | |
1283 | ||
35b09c9b | 1284 | if (needs_idle_maps()) |
5c042287 BW |
1285 | intel_private.base.do_idle_maps = 1; |
1286 | ||
2d2430cf DV |
1287 | intel_i9xx_setup_flush(); |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
e9b1cc81 | 1292 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
f51b7662 | 1293 | .owner = THIS_MODULE, |
f51b7662 | 1294 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1295 | .aperture_sizes = intel_fake_agp_sizes, |
1296 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
a6963596 | 1297 | .configure = intel_fake_agp_configure, |
3e921f98 | 1298 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1299 | .cleanup = intel_gtt_cleanup, |
ffdd7510 | 1300 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1301 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1302 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1303 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
450f2b3d DV |
1304 | .insert_memory = intel_fake_agp_insert_entries, |
1305 | .remove_memory = intel_fake_agp_remove_entries, | |
ffdd7510 | 1306 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1307 | .free_by_type = intel_i810_free_by_type, |
1308 | .agp_alloc_page = agp_generic_alloc_page, | |
1309 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1310 | .agp_destroy_page = agp_generic_destroy_page, | |
1311 | .agp_destroy_pages = agp_generic_destroy_pages, | |
f51b7662 | 1312 | }; |
02c026ce | 1313 | |
bdd30729 DV |
1314 | static const struct intel_gtt_driver i81x_gtt_driver = { |
1315 | .gen = 1, | |
820647b9 | 1316 | .has_pgtbl_enable = 1, |
22533b49 | 1317 | .dma_mask_size = 32, |
820647b9 DV |
1318 | .setup = i810_setup, |
1319 | .cleanup = i810_cleanup, | |
625dd9d3 DV |
1320 | .check_flags = i830_check_flags, |
1321 | .write_entry = i810_write_entry, | |
bdd30729 | 1322 | }; |
1a997ff2 DV |
1323 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1324 | .gen = 2, | |
100519e2 | 1325 | .has_pgtbl_enable = 1, |
73800422 | 1326 | .setup = i830_setup, |
ae83dd5c | 1327 | .cleanup = i830_cleanup, |
351bb278 | 1328 | .write_entry = i830_write_entry, |
22533b49 | 1329 | .dma_mask_size = 32, |
5cbecafc | 1330 | .check_flags = i830_check_flags, |
1b263f24 | 1331 | .chipset_flush = i830_chipset_flush, |
1a997ff2 DV |
1332 | }; |
1333 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1334 | .gen = 3, | |
100519e2 | 1335 | .has_pgtbl_enable = 1, |
2d2430cf | 1336 | .setup = i9xx_setup, |
ae83dd5c | 1337 | .cleanup = i9xx_cleanup, |
351bb278 | 1338 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
625dd9d3 | 1339 | .write_entry = i830_write_entry, |
22533b49 | 1340 | .dma_mask_size = 32, |
fefaa70f | 1341 | .check_flags = i830_check_flags, |
1b263f24 | 1342 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1343 | }; |
1344 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1345 | .gen = 3, | |
1346 | .is_g33 = 1, | |
2d2430cf | 1347 | .setup = i9xx_setup, |
ae83dd5c | 1348 | .cleanup = i9xx_cleanup, |
a6963596 | 1349 | .write_entry = i965_write_entry, |
22533b49 | 1350 | .dma_mask_size = 36, |
450f2b3d | 1351 | .check_flags = i830_check_flags, |
1b263f24 | 1352 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1353 | }; |
1354 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1355 | .gen = 3, | |
1356 | .is_pineview = 1, .is_g33 = 1, | |
2d2430cf | 1357 | .setup = i9xx_setup, |
ae83dd5c | 1358 | .cleanup = i9xx_cleanup, |
a6963596 | 1359 | .write_entry = i965_write_entry, |
22533b49 | 1360 | .dma_mask_size = 36, |
450f2b3d | 1361 | .check_flags = i830_check_flags, |
1b263f24 | 1362 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1363 | }; |
1364 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1365 | .gen = 4, | |
100519e2 | 1366 | .has_pgtbl_enable = 1, |
2d2430cf | 1367 | .setup = i9xx_setup, |
ae83dd5c | 1368 | .cleanup = i9xx_cleanup, |
a6963596 | 1369 | .write_entry = i965_write_entry, |
22533b49 | 1370 | .dma_mask_size = 36, |
450f2b3d | 1371 | .check_flags = i830_check_flags, |
1b263f24 | 1372 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1373 | }; |
1374 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1375 | .gen = 5, | |
2d2430cf | 1376 | .setup = i9xx_setup, |
ae83dd5c | 1377 | .cleanup = i9xx_cleanup, |
a6963596 | 1378 | .write_entry = i965_write_entry, |
22533b49 | 1379 | .dma_mask_size = 36, |
450f2b3d | 1380 | .check_flags = i830_check_flags, |
1b263f24 | 1381 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1382 | }; |
1383 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1384 | .gen = 5, | |
1385 | .is_ironlake = 1, | |
2d2430cf | 1386 | .setup = i9xx_setup, |
ae83dd5c | 1387 | .cleanup = i9xx_cleanup, |
a6963596 | 1388 | .write_entry = i965_write_entry, |
22533b49 | 1389 | .dma_mask_size = 36, |
450f2b3d | 1390 | .check_flags = i830_check_flags, |
1b263f24 | 1391 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1392 | }; |
1393 | static const struct intel_gtt_driver sandybridge_gtt_driver = { | |
1394 | .gen = 6, | |
2d2430cf | 1395 | .setup = i9xx_setup, |
ae83dd5c | 1396 | .cleanup = gen6_cleanup, |
97ef1bdd | 1397 | .write_entry = gen6_write_entry, |
22533b49 | 1398 | .dma_mask_size = 40, |
90cb149e | 1399 | .check_flags = gen6_check_flags, |
1b263f24 | 1400 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 | 1401 | }; |
a843af18 DV |
1402 | static const struct intel_gtt_driver haswell_gtt_driver = { |
1403 | .gen = 6, | |
1404 | .setup = i9xx_setup, | |
1405 | .cleanup = gen6_cleanup, | |
1406 | .write_entry = haswell_write_entry, | |
1407 | .dma_mask_size = 40, | |
1408 | .check_flags = gen6_check_flags, | |
1409 | .chipset_flush = i9xx_chipset_flush, | |
1410 | }; | |
64757876 JB |
1411 | static const struct intel_gtt_driver valleyview_gtt_driver = { |
1412 | .gen = 7, | |
1413 | .setup = i9xx_setup, | |
1414 | .cleanup = gen6_cleanup, | |
1415 | .write_entry = valleyview_write_entry, | |
1416 | .dma_mask_size = 40, | |
1417 | .check_flags = gen6_check_flags, | |
64757876 | 1418 | }; |
1a997ff2 | 1419 | |
02c026ce DV |
1420 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1421 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1422 | * which one should be used if a gmch_chip_id is present. | |
1423 | */ | |
1424 | static const struct intel_gtt_driver_description { | |
1425 | unsigned int gmch_chip_id; | |
1426 | char *name; | |
1a997ff2 | 1427 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1428 | } intel_gtt_chipsets[] = { |
ff26860f | 1429 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", |
bdd30729 | 1430 | &i81x_gtt_driver}, |
ff26860f | 1431 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", |
bdd30729 | 1432 | &i81x_gtt_driver}, |
ff26860f | 1433 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", |
bdd30729 | 1434 | &i81x_gtt_driver}, |
ff26860f | 1435 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", |
bdd30729 | 1436 | &i81x_gtt_driver}, |
1a997ff2 | 1437 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
ff26860f | 1438 | &i8xx_gtt_driver}, |
53371eda | 1439 | { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", |
ff26860f | 1440 | &i8xx_gtt_driver}, |
1a997ff2 | 1441 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
ff26860f | 1442 | &i8xx_gtt_driver}, |
1a997ff2 | 1443 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
ff26860f | 1444 | &i8xx_gtt_driver}, |
1a997ff2 | 1445 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
ff26860f | 1446 | &i8xx_gtt_driver}, |
1a997ff2 | 1447 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
ff26860f | 1448 | &i915_gtt_driver }, |
1a997ff2 | 1449 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
ff26860f | 1450 | &i915_gtt_driver }, |
1a997ff2 | 1451 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
ff26860f | 1452 | &i915_gtt_driver }, |
1a997ff2 | 1453 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
ff26860f | 1454 | &i915_gtt_driver }, |
1a997ff2 | 1455 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
ff26860f | 1456 | &i915_gtt_driver }, |
1a997ff2 | 1457 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
ff26860f | 1458 | &i915_gtt_driver }, |
1a997ff2 | 1459 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
ff26860f | 1460 | &i965_gtt_driver }, |
1a997ff2 | 1461 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
ff26860f | 1462 | &i965_gtt_driver }, |
1a997ff2 | 1463 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
ff26860f | 1464 | &i965_gtt_driver }, |
1a997ff2 | 1465 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
ff26860f | 1466 | &i965_gtt_driver }, |
1a997ff2 | 1467 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
ff26860f | 1468 | &i965_gtt_driver }, |
1a997ff2 | 1469 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
ff26860f | 1470 | &i965_gtt_driver }, |
1a997ff2 | 1471 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
ff26860f | 1472 | &g33_gtt_driver }, |
1a997ff2 | 1473 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
ff26860f | 1474 | &g33_gtt_driver }, |
1a997ff2 | 1475 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
ff26860f | 1476 | &g33_gtt_driver }, |
1a997ff2 | 1477 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
ff26860f | 1478 | &pineview_gtt_driver }, |
1a997ff2 | 1479 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
ff26860f | 1480 | &pineview_gtt_driver }, |
1a997ff2 | 1481 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
ff26860f | 1482 | &g4x_gtt_driver }, |
1a997ff2 | 1483 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
ff26860f | 1484 | &g4x_gtt_driver }, |
1a997ff2 | 1485 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
ff26860f | 1486 | &g4x_gtt_driver }, |
1a997ff2 | 1487 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
ff26860f | 1488 | &g4x_gtt_driver }, |
1a997ff2 | 1489 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
ff26860f | 1490 | &g4x_gtt_driver }, |
e9e5f8e8 | 1491 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
ff26860f | 1492 | &g4x_gtt_driver }, |
1a997ff2 | 1493 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
ff26860f | 1494 | &g4x_gtt_driver }, |
02c026ce | 1495 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
ff26860f | 1496 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1497 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
ff26860f | 1498 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1499 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
ff26860f | 1500 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1501 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
ff26860f | 1502 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1503 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
ff26860f | 1504 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1505 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
ff26860f | 1506 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1507 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
ff26860f | 1508 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1509 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
ff26860f | 1510 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1511 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
ff26860f | 1512 | "Sandybridge", &sandybridge_gtt_driver }, |
246d08b8 JB |
1513 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG, |
1514 | "Ivybridge", &sandybridge_gtt_driver }, | |
1515 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG, | |
1516 | "Ivybridge", &sandybridge_gtt_driver }, | |
1517 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG, | |
1518 | "Ivybridge", &sandybridge_gtt_driver }, | |
1519 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG, | |
1520 | "Ivybridge", &sandybridge_gtt_driver }, | |
1521 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, | |
cc22a938 ED |
1522 | "Ivybridge", &sandybridge_gtt_driver }, |
1523 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG, | |
246d08b8 | 1524 | "Ivybridge", &sandybridge_gtt_driver }, |
64757876 JB |
1525 | { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, |
1526 | "ValleyView", &valleyview_gtt_driver }, | |
4cae9ae0 | 1527 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG, |
a843af18 | 1528 | "Haswell", &haswell_gtt_driver }, |
4cae9ae0 | 1529 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG, |
a843af18 | 1530 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1531 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG, |
a843af18 | 1532 | "Haswell", &haswell_gtt_driver }, |
4cae9ae0 | 1533 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG, |
a843af18 | 1534 | "Haswell", &haswell_gtt_driver }, |
4cae9ae0 | 1535 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG, |
a843af18 | 1536 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1537 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG, |
a843af18 | 1538 | "Haswell", &haswell_gtt_driver }, |
4cae9ae0 | 1539 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG, |
a843af18 | 1540 | "Haswell", &haswell_gtt_driver }, |
4cae9ae0 | 1541 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG, |
a843af18 | 1542 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1543 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG, |
a843af18 | 1544 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1545 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG, |
a843af18 | 1546 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1547 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG, |
a843af18 | 1548 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1549 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG, |
a843af18 | 1550 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1551 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG, |
a843af18 | 1552 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1553 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG, |
a843af18 | 1554 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1555 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG, |
a843af18 | 1556 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1557 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG, |
a843af18 | 1558 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1559 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG, |
a843af18 | 1560 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1561 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG, |
a843af18 | 1562 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1563 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG, |
a843af18 | 1564 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1565 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG, |
a843af18 | 1566 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1567 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG, |
a843af18 | 1568 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1569 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG, |
a843af18 | 1570 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1571 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG, |
a843af18 | 1572 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1573 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG, |
a843af18 | 1574 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1575 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG, |
a843af18 | 1576 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1577 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG, |
a843af18 | 1578 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1579 | { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG, |
a843af18 | 1580 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1581 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG, |
a843af18 | 1582 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1583 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG, |
a843af18 | 1584 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1585 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG, |
a843af18 | 1586 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1587 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG, |
a843af18 | 1588 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1589 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG, |
a843af18 | 1590 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1591 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG, |
a843af18 | 1592 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1593 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG, |
a843af18 | 1594 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1595 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG, |
a843af18 | 1596 | "Haswell", &haswell_gtt_driver }, |
da612d88 | 1597 | { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG, |
a843af18 | 1598 | "Haswell", &haswell_gtt_driver }, |
02c026ce DV |
1599 | { 0, NULL, NULL } |
1600 | }; | |
1601 | ||
1602 | static int find_gmch(u16 device) | |
1603 | { | |
1604 | struct pci_dev *gmch_device; | |
1605 | ||
1606 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1607 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1608 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1609 | device, gmch_device); | |
1610 | } | |
1611 | ||
1612 | if (!gmch_device) | |
1613 | return 0; | |
1614 | ||
1615 | intel_private.pcidev = gmch_device; | |
1616 | return 1; | |
1617 | } | |
1618 | ||
14be93dd DV |
1619 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
1620 | struct agp_bridge_data *bridge) | |
02c026ce DV |
1621 | { |
1622 | int i, mask; | |
14be93dd DV |
1623 | |
1624 | /* | |
1625 | * Can be called from the fake agp driver but also directly from | |
1626 | * drm/i915.ko. Hence we need to check whether everything is set up | |
1627 | * already. | |
1628 | */ | |
1629 | if (intel_private.driver) { | |
1630 | intel_private.refcount++; | |
1631 | return 1; | |
1632 | } | |
02c026ce DV |
1633 | |
1634 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { | |
14be93dd DV |
1635 | if (gpu_pdev) { |
1636 | if (gpu_pdev->device == | |
1637 | intel_gtt_chipsets[i].gmch_chip_id) { | |
1638 | intel_private.pcidev = pci_dev_get(gpu_pdev); | |
1639 | intel_private.driver = | |
1640 | intel_gtt_chipsets[i].gtt_driver; | |
1641 | ||
1642 | break; | |
1643 | } | |
1644 | } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
625dd9d3 | 1645 | intel_private.driver = |
1a997ff2 | 1646 | intel_gtt_chipsets[i].gtt_driver; |
02c026ce DV |
1647 | break; |
1648 | } | |
1649 | } | |
1650 | ||
ff26860f | 1651 | if (!intel_private.driver) |
02c026ce DV |
1652 | return 0; |
1653 | ||
14be93dd DV |
1654 | intel_private.refcount++; |
1655 | ||
7e8f6306 DV |
1656 | if (bridge) { |
1657 | bridge->driver = &intel_fake_agp_driver; | |
1658 | bridge->dev_private_data = &intel_private; | |
14be93dd | 1659 | bridge->dev = bridge_pdev; |
7e8f6306 | 1660 | } |
02c026ce | 1661 | |
14be93dd | 1662 | intel_private.bridge_dev = pci_dev_get(bridge_pdev); |
d7cca2f7 | 1663 | |
14be93dd | 1664 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
02c026ce | 1665 | |
22533b49 | 1666 | mask = intel_private.driver->dma_mask_size; |
02c026ce DV |
1667 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
1668 | dev_err(&intel_private.pcidev->dev, | |
1669 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1670 | else | |
1671 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1672 | DMA_BIT_MASK(mask)); | |
1673 | ||
14be93dd DV |
1674 | if (intel_gtt_init() != 0) { |
1675 | intel_gmch_remove(); | |
1676 | ||
3b15a9d7 | 1677 | return 0; |
14be93dd | 1678 | } |
1784a5fb | 1679 | |
02c026ce DV |
1680 | return 1; |
1681 | } | |
e2404e7c | 1682 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1683 | |
c64f7ba5 | 1684 | const struct intel_gtt *intel_gtt_get(void) |
19966754 DV |
1685 | { |
1686 | return &intel_private.base; | |
1687 | } | |
1688 | EXPORT_SYMBOL(intel_gtt_get); | |
1689 | ||
40ce6575 DV |
1690 | void intel_gtt_chipset_flush(void) |
1691 | { | |
1692 | if (intel_private.driver->chipset_flush) | |
1693 | intel_private.driver->chipset_flush(); | |
1694 | } | |
1695 | EXPORT_SYMBOL(intel_gtt_chipset_flush); | |
1696 | ||
14be93dd | 1697 | void intel_gmch_remove(void) |
02c026ce | 1698 | { |
14be93dd DV |
1699 | if (--intel_private.refcount) |
1700 | return; | |
1701 | ||
02c026ce DV |
1702 | if (intel_private.pcidev) |
1703 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1704 | if (intel_private.bridge_dev) |
1705 | pci_dev_put(intel_private.bridge_dev); | |
14be93dd | 1706 | intel_private.driver = NULL; |
02c026ce | 1707 | } |
e2404e7c DV |
1708 | EXPORT_SYMBOL(intel_gmch_remove); |
1709 | ||
1710 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); | |
1711 | MODULE_LICENSE("GPL and additional rights"); |