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intel-gtt: store a local pointer to the bridge pci dev
[deliverable/linux.git] / drivers / char / agp / intel-gtt.c
CommitLineData
f51b7662
DV		 1/*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
e2404e7c
DV		 18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/pagemap.h>
23#include <linux/agp_backend.h>
24#include <asm/smp.h>
25#include "agp.h"
26#include "intel-agp.h"
27#include <linux/intel-gtt.h>
0ade6386 28#include <drm/intel-gtt.h>
e2404e7c 29
f51b7662
DV		 30/*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36#ifdef CONFIG_DMAR
37#define USE_PCI_DMA_API 1
38#endif
39
d1d6ca73
JB		 40/* Max amount of stolen space, anything above will be returned to Linux */
41int intel_max_stolen = 32 * 1024 * 1024;
42EXPORT_SYMBOL(intel_max_stolen);
43
f51b7662
DV		 44static const struct aper_size_info_fixed intel_i810_sizes[] =
45{
46 {64, 16384, 4},
47 /* The 32M mode still requires a 64k gatt */
48 {32, 8192, 4}
49};
50
51#define AGP_DCACHE_MEMORY 1
52#define AGP_PHYS_MEMORY 2
53#define INTEL_AGP_CACHED_MEMORY 3
54
55static struct gatt_mask intel_i810_masks[] =
56{
57 {.mask = I810_PTE_VALID, .type = 0},
58 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
59 {.mask = I810_PTE_VALID, .type = 0},
60 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
61 .type = INTEL_AGP_CACHED_MEMORY}
62};
63
f8f235e5
ZW		 64#define INTEL_AGP_UNCACHED_MEMORY 0
65#define INTEL_AGP_CACHED_MEMORY_LLC 1
66#define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67#define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68#define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
69
70static struct gatt_mask intel_gen6_masks[] =
71{
72 {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
73 .type = INTEL_AGP_UNCACHED_MEMORY },
74 {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
75 .type = INTEL_AGP_CACHED_MEMORY_LLC },
76 {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
77 .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
78 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
79 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
80 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
81 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
82};
83
f51b7662 84static struct _intel_private {
0ade6386 85 struct intel_gtt base;
f51b7662 86 struct pci_dev *pcidev; /* device one */
d7cca2f7 87 struct pci_dev *bridge_dev;
f51b7662
DV		 88 u8 __iomem *registers;
89 u32 __iomem *gtt; /* I915G */
90 int num_dcache_entries;
f51b7662
DV		 91 union {
92 void __iomem *i9xx_flush_page;
93 void *i8xx_flush_page;
94 };
95 struct page *i8xx_page;
96 struct resource ifp_resource;
97 int resource_valid;
98} intel_private;
99
100#ifdef USE_PCI_DMA_API
101static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
102{
103 *ret = pci_map_page(intel_private.pcidev, page, 0,
104 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
105 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
106 return -EINVAL;
107 return 0;
108}
109
110static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
111{
112 pci_unmap_page(intel_private.pcidev, dma,
113 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
114}
115
116static void intel_agp_free_sglist(struct agp_memory *mem)
117{
118 struct sg_table st;
119
120 st.sgl = mem->sg_list;
121 st.orig_nents = st.nents = mem->page_count;
122
123 sg_free_table(&st);
124
125 mem->sg_list = NULL;
126 mem->num_sg = 0;
127}
128
129static int intel_agp_map_memory(struct agp_memory *mem)
130{
131 struct sg_table st;
132 struct scatterlist *sg;
133 int i;
134
135 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
136
137 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
831cd445 138 goto err;
f51b7662
DV		 139
140 mem->sg_list = sg = st.sgl;
141
142 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
143 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
144
145 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
146 mem->page_count, PCI_DMA_BIDIRECTIONAL);
831cd445
CW		 147 if (unlikely(!mem->num_sg))
148 goto err;
149
f51b7662 150 return 0;
831cd445
CW		 151
152err:
153 sg_free_table(&st);
154 return -ENOMEM;
f51b7662
DV		 155}
156
157static void intel_agp_unmap_memory(struct agp_memory *mem)
158{
159 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
160
161 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
162 mem->page_count, PCI_DMA_BIDIRECTIONAL);
163 intel_agp_free_sglist(mem);
164}
165
166static void intel_agp_insert_sg_entries(struct agp_memory *mem,
167 off_t pg_start, int mask_type)
168{
169 struct scatterlist *sg;
170 int i, j;
171
172 j = pg_start;
173
174 WARN_ON(!mem->num_sg);
175
176 if (mem->num_sg == mem->page_count) {
177 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
178 writel(agp_bridge->driver->mask_memory(agp_bridge,
179 sg_dma_address(sg), mask_type),
180 intel_private.gtt+j);
181 j++;
182 }
183 } else {
184 /* sg may merge pages, but we have to separate
185 * per-page addr for GTT */
186 unsigned int len, m;
187
188 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
189 len = sg_dma_len(sg) / PAGE_SIZE;
190 for (m = 0; m < len; m++) {
191 writel(agp_bridge->driver->mask_memory(agp_bridge,
192 sg_dma_address(sg) + m * PAGE_SIZE,
193 mask_type),
194 intel_private.gtt+j);
195 j++;
196 }
197 }
198 }
199 readl(intel_private.gtt+j-1);
200}
201
202#else
203
204static void intel_agp_insert_sg_entries(struct agp_memory *mem,
205 off_t pg_start, int mask_type)
206{
207 int i, j;
f51b7662
DV		 208
209 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
210 writel(agp_bridge->driver->mask_memory(agp_bridge,
211 page_to_phys(mem->pages[i]), mask_type),
212 intel_private.gtt+j);
213 }
214
215 readl(intel_private.gtt+j-1);
216}
217
218#endif
219
220static int intel_i810_fetch_size(void)
221{
222 u32 smram_miscc;
223 struct aper_size_info_fixed *values;
224
d7cca2f7
DV		 225 pci_read_config_dword(intel_private.bridge_dev,
226 I810_SMRAM_MISCC, &smram_miscc);
f51b7662
DV		 227 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
228
229 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
d7cca2f7 230 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
f51b7662
DV		 231 return 0;
232 }
233 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
e1583165 234 agp_bridge->current_size = (void *) (values + 1);
f51b7662
DV		 235 agp_bridge->aperture_size_idx = 1;
236 return values[1].size;
237 } else {
e1583165 238 agp_bridge->current_size = (void *) (values);
f51b7662
DV		 239 agp_bridge->aperture_size_idx = 0;
240 return values[0].size;
241 }
242
243 return 0;
244}
245
246static int intel_i810_configure(void)
247{
248 struct aper_size_info_fixed *current_size;
249 u32 temp;
250 int i;
251
252 current_size = A_SIZE_FIX(agp_bridge->current_size);
253
254 if (!intel_private.registers) {
255 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
256 temp &= 0xfff80000;
257
258 intel_private.registers = ioremap(temp, 128 * 4096);
259 if (!intel_private.registers) {
260 dev_err(&intel_private.pcidev->dev,
261 "can't remap memory\n");
262 return -ENOMEM;
263 }
264 }
265
266 if ((readl(intel_private.registers+I810_DRAM_CTL)
267 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
268 /* This will need to be dynamically assigned */
269 dev_info(&intel_private.pcidev->dev,
270 "detected 4MB dedicated video ram\n");
271 intel_private.num_dcache_entries = 1024;
272 }
273 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
274 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
275 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
276 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
277
278 if (agp_bridge->driver->needs_scratch_page) {
279 for (i = 0; i < current_size->num_entries; i++) {
280 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
281 }
282 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
283 }
284 global_cache_flush();
285 return 0;
286}
287
288static void intel_i810_cleanup(void)
289{
290 writel(0, intel_private.registers+I810_PGETBL_CTL);
291 readl(intel_private.registers); /* PCI Posting. */
292 iounmap(intel_private.registers);
293}
294
f51b7662
DV		 295static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
296{
297 return;
298}
299
300/* Exists to support ARGB cursors */
301static struct page *i8xx_alloc_pages(void)
302{
303 struct page *page;
304
305 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
306 if (page == NULL)
307 return NULL;
308
309 if (set_pages_uc(page, 4) < 0) {
310 set_pages_wb(page, 4);
311 __free_pages(page, 2);
312 return NULL;
313 }
314 get_page(page);
315 atomic_inc(&agp_bridge->current_memory_agp);
316 return page;
317}
318
319static void i8xx_destroy_pages(struct page *page)
320{
321 if (page == NULL)
322 return;
323
324 set_pages_wb(page, 4);
325 put_page(page);
326 __free_pages(page, 2);
327 atomic_dec(&agp_bridge->current_memory_agp);
328}
329
330static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
331 int type)
332{
333 if (type < AGP_USER_TYPES)
334 return type;
335 else if (type == AGP_USER_CACHED_MEMORY)
336 return INTEL_AGP_CACHED_MEMORY;
337 else
338 return 0;
339}
340
f8f235e5
ZW		 341static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
342 int type)
343{
344 unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
345 unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
346
347 if (type_mask == AGP_USER_UNCACHED_MEMORY)
348 return INTEL_AGP_UNCACHED_MEMORY;
349 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
350 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
351 INTEL_AGP_CACHED_MEMORY_LLC_MLC;
352 else /* set 'normal'/'cached' to LLC by default */
353 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
354 INTEL_AGP_CACHED_MEMORY_LLC;
355}
356
357
f51b7662
DV		 358static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
359 int type)
360{
361 int i, j, num_entries;
362 void *temp;
363 int ret = -EINVAL;
364 int mask_type;
365
366 if (mem->page_count == 0)
367 goto out;
368
369 temp = agp_bridge->current_size;
370 num_entries = A_SIZE_FIX(temp)->num_entries;
371
372 if ((pg_start + mem->page_count) > num_entries)
373 goto out_err;
374
375
376 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
377 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
378 ret = -EBUSY;
379 goto out_err;
380 }
381 }
382
383 if (type != mem->type)
384 goto out_err;
385
386 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
387
388 switch (mask_type) {
389 case AGP_DCACHE_MEMORY:
390 if (!mem->is_flushed)
391 global_cache_flush();
392 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
393 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
394 intel_private.registers+I810_PTE_BASE+(i*4));
395 }
396 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
397 break;
398 case AGP_PHYS_MEMORY:
399 case AGP_NORMAL_MEMORY:
400 if (!mem->is_flushed)
401 global_cache_flush();
402 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
403 writel(agp_bridge->driver->mask_memory(agp_bridge,
404 page_to_phys(mem->pages[i]), mask_type),
405 intel_private.registers+I810_PTE_BASE+(j*4));
406 }
407 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
408 break;
409 default:
410 goto out_err;
411 }
412
f51b7662
DV		 413out:
414 ret = 0;
415out_err:
416 mem->is_flushed = true;
417 return ret;
418}
419
420static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
421 int type)
422{
423 int i;
424
425 if (mem->page_count == 0)
426 return 0;
427
428 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
429 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
430 }
431 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
432
f51b7662
DV		 433 return 0;
434}
435
436/*
437 * The i810/i830 requires a physical address to program its mouse
438 * pointer into hardware.
439 * However the Xserver still writes to it through the agp aperture.
440 */
441static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
442{
443 struct agp_memory *new;
444 struct page *page;
445
446 switch (pg_count) {
447 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
448 break;
449 case 4:
450 /* kludge to get 4 physical pages for ARGB cursor */
451 page = i8xx_alloc_pages();
452 break;
453 default:
454 return NULL;
455 }
456
457 if (page == NULL)
458 return NULL;
459
460 new = agp_create_memory(pg_count);
461 if (new == NULL)
462 return NULL;
463
464 new->pages[0] = page;
465 if (pg_count == 4) {
466 /* kludge to get 4 physical pages for ARGB cursor */
467 new->pages[1] = new->pages[0] + 1;
468 new->pages[2] = new->pages[1] + 1;
469 new->pages[3] = new->pages[2] + 1;
470 }
471 new->page_count = pg_count;
472 new->num_scratch_pages = pg_count;
473 new->type = AGP_PHYS_MEMORY;
474 new->physical = page_to_phys(new->pages[0]);
475 return new;
476}
477
478static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
479{
480 struct agp_memory *new;
481
482 if (type == AGP_DCACHE_MEMORY) {
483 if (pg_count != intel_private.num_dcache_entries)
484 return NULL;
485
486 new = agp_create_memory(1);
487 if (new == NULL)
488 return NULL;
489
490 new->type = AGP_DCACHE_MEMORY;
491 new->page_count = pg_count;
492 new->num_scratch_pages = 0;
493 agp_free_page_array(new);
494 return new;
495 }
496 if (type == AGP_PHYS_MEMORY)
497 return alloc_agpphysmem_i8xx(pg_count, type);
498 return NULL;
499}
500
501static void intel_i810_free_by_type(struct agp_memory *curr)
502{
503 agp_free_key(curr->key);
504 if (curr->type == AGP_PHYS_MEMORY) {
505 if (curr->page_count == 4)
506 i8xx_destroy_pages(curr->pages[0]);
507 else {
508 agp_bridge->driver->agp_destroy_page(curr->pages[0],
509 AGP_PAGE_DESTROY_UNMAP);
510 agp_bridge->driver->agp_destroy_page(curr->pages[0],
511 AGP_PAGE_DESTROY_FREE);
512 }
513 agp_free_page_array(curr);
514 }
515 kfree(curr);
516}
517
518static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
519 dma_addr_t addr, int type)
520{
521 /* Type checking must be done elsewhere */
522 return addr | bridge->driver->masks[type].mask;
523}
524
525static struct aper_size_info_fixed intel_i830_sizes[] =
526{
527 {128, 32768, 5},
528 /* The 64M mode still requires a 128k gatt */
529 {64, 16384, 5},
530 {256, 65536, 6},
531 {512, 131072, 7},
532};
533
534static void intel_i830_init_gtt_entries(void)
535{
536 u16 gmch_ctrl;
537 int gtt_entries = 0;
538 u8 rdct;
539 int local = 0;
540 static const int ddt[4] = { 0, 16, 32, 64 };
541 int size; /* reserved space (in kb) at the top of stolen memory */
542
d7cca2f7
DV		 543 pci_read_config_word(intel_private.bridge_dev,
544 I830_GMCH_CTRL, &gmch_ctrl);
f51b7662
DV		 545
546 if (IS_I965) {
547 u32 pgetbl_ctl;
548 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
549
550 /* The 965 has a field telling us the size of the GTT,
551 * which may be larger than what is necessary to map the
552 * aperture.
553 */
554 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
555 case I965_PGETBL_SIZE_128KB:
556 size = 128;
557 break;
558 case I965_PGETBL_SIZE_256KB:
559 size = 256;
560 break;
561 case I965_PGETBL_SIZE_512KB:
562 size = 512;
563 break;
564 case I965_PGETBL_SIZE_1MB:
565 size = 1024;
566 break;
567 case I965_PGETBL_SIZE_2MB:
568 size = 2048;
569 break;
570 case I965_PGETBL_SIZE_1_5MB:
571 size = 1024 + 512;
572 break;
573 default:
574 dev_info(&intel_private.pcidev->dev,
575 "unknown page table size, assuming 512KB\n");
576 size = 512;
577 }
578 size += 4; /* add in BIOS popup space */
579 } else if (IS_G33 && !IS_PINEVIEW) {
580 /* G33's GTT size defined in gmch_ctrl */
581 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
582 case G33_PGETBL_SIZE_1M:
583 size = 1024;
584 break;
585 case G33_PGETBL_SIZE_2M:
586 size = 2048;
587 break;
588 default:
d7cca2f7 589 dev_info(&intel_private.bridge_dev->dev,
f51b7662
DV		 590 "unknown page table size 0x%x, assuming 512KB\n",
591 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
592 size = 512;
593 }
594 size += 4;
595 } else if (IS_G4X || IS_PINEVIEW) {
596 /* On 4 series hardware, GTT stolen is separate from graphics
597 * stolen, ignore it in stolen gtt entries counting. However,
598 * 4KB of the stolen memory doesn't get mapped to the GTT.
599 */
600 size = 4;
601 } else {
602 /* On previous hardware, the GTT size was just what was
603 * required to map the aperture.
604 */
605 size = agp_bridge->driver->fetch_size() + 4;
606 }
607
d7cca2f7
DV		 608 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
609 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
f51b7662
DV		 610 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
611 case I830_GMCH_GMS_STOLEN_512:
612 gtt_entries = KB(512) - KB(size);
613 break;
614 case I830_GMCH_GMS_STOLEN_1024:
615 gtt_entries = MB(1) - KB(size);
616 break;
617 case I830_GMCH_GMS_STOLEN_8192:
618 gtt_entries = MB(8) - KB(size);
619 break;
620 case I830_GMCH_GMS_LOCAL:
621 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
622 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
623 MB(ddt[I830_RDRAM_DDT(rdct)]);
624 local = 1;
625 break;
626 default:
627 gtt_entries = 0;
628 break;
629 }
85540480 630 } else if (IS_SNB) {
f51b7662
DV		 631 /*
632 * SandyBridge has new memory control reg at 0x50.w
633 */
634 u16 snb_gmch_ctl;
635 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
636 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
637 case SNB_GMCH_GMS_STOLEN_32M:
638 gtt_entries = MB(32) - KB(size);
639 break;
640 case SNB_GMCH_GMS_STOLEN_64M:
641 gtt_entries = MB(64) - KB(size);
642 break;
643 case SNB_GMCH_GMS_STOLEN_96M:
644 gtt_entries = MB(96) - KB(size);
645 break;
646 case SNB_GMCH_GMS_STOLEN_128M:
647 gtt_entries = MB(128) - KB(size);
648 break;
649 case SNB_GMCH_GMS_STOLEN_160M:
650 gtt_entries = MB(160) - KB(size);
651 break;
652 case SNB_GMCH_GMS_STOLEN_192M:
653 gtt_entries = MB(192) - KB(size);
654 break;
655 case SNB_GMCH_GMS_STOLEN_224M:
656 gtt_entries = MB(224) - KB(size);
657 break;
658 case SNB_GMCH_GMS_STOLEN_256M:
659 gtt_entries = MB(256) - KB(size);
660 break;
661 case SNB_GMCH_GMS_STOLEN_288M:
662 gtt_entries = MB(288) - KB(size);
663 break;
664 case SNB_GMCH_GMS_STOLEN_320M:
665 gtt_entries = MB(320) - KB(size);
666 break;
667 case SNB_GMCH_GMS_STOLEN_352M:
668 gtt_entries = MB(352) - KB(size);
669 break;
670 case SNB_GMCH_GMS_STOLEN_384M:
671 gtt_entries = MB(384) - KB(size);
672 break;
673 case SNB_GMCH_GMS_STOLEN_416M:
674 gtt_entries = MB(416) - KB(size);
675 break;
676 case SNB_GMCH_GMS_STOLEN_448M:
677 gtt_entries = MB(448) - KB(size);
678 break;
679 case SNB_GMCH_GMS_STOLEN_480M:
680 gtt_entries = MB(480) - KB(size);
681 break;
682 case SNB_GMCH_GMS_STOLEN_512M:
683 gtt_entries = MB(512) - KB(size);
684 break;
685 }
686 } else {
687 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
688 case I855_GMCH_GMS_STOLEN_1M:
689 gtt_entries = MB(1) - KB(size);
690 break;
691 case I855_GMCH_GMS_STOLEN_4M:
692 gtt_entries = MB(4) - KB(size);
693 break;
694 case I855_GMCH_GMS_STOLEN_8M:
695 gtt_entries = MB(8) - KB(size);
696 break;
697 case I855_GMCH_GMS_STOLEN_16M:
698 gtt_entries = MB(16) - KB(size);
699 break;
700 case I855_GMCH_GMS_STOLEN_32M:
701 gtt_entries = MB(32) - KB(size);
702 break;
703 case I915_GMCH_GMS_STOLEN_48M:
704 /* Check it's really I915G */
705 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
706 gtt_entries = MB(48) - KB(size);
707 else
708 gtt_entries = 0;
709 break;
710 case I915_GMCH_GMS_STOLEN_64M:
711 /* Check it's really I915G */
712 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
713 gtt_entries = MB(64) - KB(size);
714 else
715 gtt_entries = 0;
716 break;
717 case G33_GMCH_GMS_STOLEN_128M:
718 if (IS_G33 || IS_I965 || IS_G4X)
719 gtt_entries = MB(128) - KB(size);
720 else
721 gtt_entries = 0;
722 break;
723 case G33_GMCH_GMS_STOLEN_256M:
724 if (IS_G33 || IS_I965 || IS_G4X)
725 gtt_entries = MB(256) - KB(size);
726 else
727 gtt_entries = 0;
728 break;
729 case INTEL_GMCH_GMS_STOLEN_96M:
730 if (IS_I965 || IS_G4X)
731 gtt_entries = MB(96) - KB(size);
732 else
733 gtt_entries = 0;
734 break;
735 case INTEL_GMCH_GMS_STOLEN_160M:
736 if (IS_I965 || IS_G4X)
737 gtt_entries = MB(160) - KB(size);
738 else
739 gtt_entries = 0;
740 break;
741 case INTEL_GMCH_GMS_STOLEN_224M:
742 if (IS_I965 || IS_G4X)
743 gtt_entries = MB(224) - KB(size);
744 else
745 gtt_entries = 0;
746 break;
747 case INTEL_GMCH_GMS_STOLEN_352M:
748 if (IS_I965 || IS_G4X)
749 gtt_entries = MB(352) - KB(size);
750 else
751 gtt_entries = 0;
752 break;
753 default:
754 gtt_entries = 0;
755 break;
756 }
757 }
d1d6ca73 758 if (!local && gtt_entries > intel_max_stolen) {
d7cca2f7 759 dev_info(&intel_private.bridge_dev->dev,
d1d6ca73
JB		 760 "detected %dK stolen memory, trimming to %dK\n",
761 gtt_entries / KB(1), intel_max_stolen / KB(1));
762 gtt_entries = intel_max_stolen / KB(4);
763 } else if (gtt_entries > 0) {
d7cca2f7 764 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
f51b7662
DV		 765 gtt_entries / KB(1), local ? "local" : "stolen");
766 gtt_entries /= KB(4);
767 } else {
d7cca2f7 768 dev_info(&intel_private.bridge_dev->dev,
f51b7662
DV		 769 "no pre-allocated video memory detected\n");
770 gtt_entries = 0;
771 }
772
0ade6386 773 intel_private.base.gtt_stolen_entries = gtt_entries;
f51b7662
DV		 774}
775
776static void intel_i830_fini_flush(void)
777{
778 kunmap(intel_private.i8xx_page);
779 intel_private.i8xx_flush_page = NULL;
780 unmap_page_from_agp(intel_private.i8xx_page);
781
782 __free_page(intel_private.i8xx_page);
783 intel_private.i8xx_page = NULL;
784}
785
786static void intel_i830_setup_flush(void)
787{
788 /* return if we've already set the flush mechanism up */
789 if (intel_private.i8xx_page)
790 return;
791
792 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
793 if (!intel_private.i8xx_page)
794 return;
795
796 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
797 if (!intel_private.i8xx_flush_page)
798 intel_i830_fini_flush();
799}
800
801/* The chipset_flush interface needs to get data that has already been
802 * flushed out of the CPU all the way out to main memory, because the GPU
803 * doesn't snoop those buffers.
804 *
805 * The 8xx series doesn't have the same lovely interface for flushing the
806 * chipset write buffers that the later chips do. According to the 865
807 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
808 * that buffer out, we just fill 1KB and clflush it out, on the assumption
809 * that it'll push whatever was in there out. It appears to work.
810 */
811static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
812{
813 unsigned int *pg = intel_private.i8xx_flush_page;
814
815 memset(pg, 0, 1024);
816
817 if (cpu_has_clflush)
818 clflush_cache_range(pg, 1024);
819 else if (wbinvd_on_all_cpus() != 0)
820 printk(KERN_ERR "Timed out waiting for cache flush.\n");
821}
822
823/* The intel i830 automatically initializes the agp aperture during POST.
824 * Use the memory already set aside for in the GTT.
825 */
826static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
827{
828 int page_order;
829 struct aper_size_info_fixed *size;
830 int num_entries;
831 u32 temp;
832
833 size = agp_bridge->current_size;
834 page_order = size->page_order;
835 num_entries = size->num_entries;
836 agp_bridge->gatt_table_real = NULL;
837
838 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
839 temp &= 0xfff80000;
840
841 intel_private.registers = ioremap(temp, 128 * 4096);
842 if (!intel_private.registers)
843 return -ENOMEM;
844
845 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
846 global_cache_flush(); /* FIXME: ?? */
847
848 /* we have to call this as early as possible after the MMIO base address is known */
849 intel_i830_init_gtt_entries();
0ade6386 850 if (intel_private.base.gtt_stolen_entries == 0) {
8699be3e
OZ		 851 iounmap(intel_private.registers);
852 return -ENOMEM;
853 }
f51b7662
DV		 854
855 agp_bridge->gatt_table = NULL;
856
857 agp_bridge->gatt_bus_addr = temp;
858
859 return 0;
860}
861
862/* Return the gatt table to a sane state. Use the top of stolen
863 * memory for the GTT.
864 */
865static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
866{
867 return 0;
868}
869
870static int intel_i830_fetch_size(void)
871{
872 u16 gmch_ctrl;
873 struct aper_size_info_fixed *values;
874
875 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
876
d7cca2f7
DV		 877 if (intel_private.bridge_dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
878 intel_private.bridge_dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
f51b7662 879 /* 855GM/852GM/865G has 128MB aperture size */
e1583165 880 agp_bridge->current_size = (void *) values;
f51b7662
DV		 881 agp_bridge->aperture_size_idx = 0;
882 return values[0].size;
883 }
884
d7cca2f7 885 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
f51b7662
DV		 886
887 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
e1583165 888 agp_bridge->current_size = (void *) values;
f51b7662
DV		 889 agp_bridge->aperture_size_idx = 0;
890 return values[0].size;
891 } else {
e1583165 892 agp_bridge->current_size = (void *) (values + 1);
f51b7662
DV		 893 agp_bridge->aperture_size_idx = 1;
894 return values[1].size;
895 }
896
897 return 0;
898}
899
900static int intel_i830_configure(void)
901{
902 struct aper_size_info_fixed *current_size;
903 u32 temp;
904 u16 gmch_ctrl;
905 int i;
906
907 current_size = A_SIZE_FIX(agp_bridge->current_size);
908
909 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
910 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
911
d7cca2f7 912 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
f51b7662 913 gmch_ctrl |= I830_GMCH_ENABLED;
d7cca2f7 914 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
f51b7662
DV		 915
916 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
917 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
918
919 if (agp_bridge->driver->needs_scratch_page) {
0ade6386 920 for (i = intel_private.base.gtt_stolen_entries; i < current_size->num_entries; i++) {
f51b7662
DV		 921 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
922 }
923 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
924 }
925
926 global_cache_flush();
927
928 intel_i830_setup_flush();
929 return 0;
930}
931
932static void intel_i830_cleanup(void)
933{
934 iounmap(intel_private.registers);
935}
936
937static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
938 int type)
939{
940 int i, j, num_entries;
941 void *temp;
942 int ret = -EINVAL;
943 int mask_type;
944
945 if (mem->page_count == 0)
946 goto out;
947
948 temp = agp_bridge->current_size;
949 num_entries = A_SIZE_FIX(temp)->num_entries;
950
0ade6386 951 if (pg_start < intel_private.base.gtt_stolen_entries) {
f51b7662 952 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
0ade6386
DV		 953 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
954 pg_start, intel_private.base.gtt_stolen_entries);
f51b7662
DV		 955
956 dev_info(&intel_private.pcidev->dev,
957 "trying to insert into local/stolen memory\n");
958 goto out_err;
959 }
960
961 if ((pg_start + mem->page_count) > num_entries)
962 goto out_err;
963
964 /* The i830 can't check the GTT for entries since its read only,
965 * depend on the caller to make the correct offset decisions.
966 */
967
968 if (type != mem->type)
969 goto out_err;
970
971 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
972
973 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
974 mask_type != INTEL_AGP_CACHED_MEMORY)
975 goto out_err;
976
977 if (!mem->is_flushed)
978 global_cache_flush();
979
980 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
981 writel(agp_bridge->driver->mask_memory(agp_bridge,
982 page_to_phys(mem->pages[i]), mask_type),
983 intel_private.registers+I810_PTE_BASE+(j*4));
984 }
985 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
f51b7662
DV		 986
987out:
988 ret = 0;
989out_err:
990 mem->is_flushed = true;
991 return ret;
992}
993
994static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
995 int type)
996{
997 int i;
998
999 if (mem->page_count == 0)
1000 return 0;
1001
0ade6386 1002 if (pg_start < intel_private.base.gtt_stolen_entries) {
f51b7662
DV		 1003 dev_info(&intel_private.pcidev->dev,
1004 "trying to disable local/stolen memory\n");
1005 return -EINVAL;
1006 }
1007
1008 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1009 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1010 }
1011 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1012
f51b7662
DV		 1013 return 0;
1014}
1015
1016static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1017{
1018 if (type == AGP_PHYS_MEMORY)
1019 return alloc_agpphysmem_i8xx(pg_count, type);
1020 /* always return NULL for other allocation types for now */
1021 return NULL;
1022}
1023
1024static int intel_alloc_chipset_flush_resource(void)
1025{
1026 int ret;
d7cca2f7 1027 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
f51b7662 1028 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
d7cca2f7 1029 pcibios_align_resource, intel_private.bridge_dev);
f51b7662
DV		 1030
1031 return ret;
1032}
1033
1034static void intel_i915_setup_chipset_flush(void)
1035{
1036 int ret;
1037 u32 temp;
1038
d7cca2f7 1039 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
f51b7662
DV		 1040 if (!(temp & 0x1)) {
1041 intel_alloc_chipset_flush_resource();
1042 intel_private.resource_valid = 1;
d7cca2f7 1043 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
f51b7662
DV		 1044 } else {
1045 temp &= ~1;
1046
1047 intel_private.resource_valid = 1;
1048 intel_private.ifp_resource.start = temp;
1049 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1050 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1051 /* some BIOSes reserve this area in a pnp some don't */
1052 if (ret)
1053 intel_private.resource_valid = 0;
1054 }
1055}
1056
1057static void intel_i965_g33_setup_chipset_flush(void)
1058{
1059 u32 temp_hi, temp_lo;
1060 int ret;
1061
d7cca2f7
DV		 1062 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1063 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
f51b7662
DV		 1064
1065 if (!(temp_lo & 0x1)) {
1066
1067 intel_alloc_chipset_flush_resource();
1068
1069 intel_private.resource_valid = 1;
d7cca2f7 1070 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
f51b7662 1071 upper_32_bits(intel_private.ifp_resource.start));
d7cca2f7 1072 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
f51b7662
DV		 1073 } else {
1074 u64 l64;
1075
1076 temp_lo &= ~0x1;
1077 l64 = ((u64)temp_hi << 32) | temp_lo;
1078
1079 intel_private.resource_valid = 1;
1080 intel_private.ifp_resource.start = l64;
1081 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1082 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1083 /* some BIOSes reserve this area in a pnp some don't */
1084 if (ret)
1085 intel_private.resource_valid = 0;
1086 }
1087}
1088
1089static void intel_i9xx_setup_flush(void)
1090{
1091 /* return if already configured */
1092 if (intel_private.ifp_resource.start)
1093 return;
1094
1095 if (IS_SNB)
1096 return;
1097
1098 /* setup a resource for this object */
1099 intel_private.ifp_resource.name = "Intel Flush Page";
1100 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1101
1102 /* Setup chipset flush for 915 */
1103 if (IS_I965 || IS_G33 || IS_G4X) {
1104 intel_i965_g33_setup_chipset_flush();
1105 } else {
1106 intel_i915_setup_chipset_flush();
1107 }
1108
df51e7aa 1109 if (intel_private.ifp_resource.start)
f51b7662 1110 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
df51e7aa
CW		 1111 if (!intel_private.i9xx_flush_page)
1112 dev_err(&intel_private.pcidev->dev,
1113 "can't ioremap flush page - no chipset flushing\n");
f51b7662
DV		 1114}
1115
f1befe71 1116static int intel_i9xx_configure(void)
f51b7662
DV		 1117{
1118 struct aper_size_info_fixed *current_size;
1119 u32 temp;
1120 u16 gmch_ctrl;
1121 int i;
1122
1123 current_size = A_SIZE_FIX(agp_bridge->current_size);
1124
1125 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1126
1127 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1128
d7cca2f7 1129 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
f51b7662 1130 gmch_ctrl |= I830_GMCH_ENABLED;
d7cca2f7 1131 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
f51b7662
DV		 1132
1133 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1134 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1135
1136 if (agp_bridge->driver->needs_scratch_page) {
0ade6386
DV		 1137 for (i = intel_private.base.gtt_stolen_entries; i <
1138 intel_private.base.gtt_total_entries; i++) {
f51b7662
DV		 1139 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1140 }
1141 readl(intel_private.gtt+i-1); /* PCI Posting. */
1142 }
1143
1144 global_cache_flush();
1145
1146 intel_i9xx_setup_flush();
1147
1148 return 0;
1149}
1150
1151static void intel_i915_cleanup(void)
1152{
1153 if (intel_private.i9xx_flush_page)
1154 iounmap(intel_private.i9xx_flush_page);
1155 if (intel_private.resource_valid)
1156 release_resource(&intel_private.ifp_resource);
1157 intel_private.ifp_resource.start = 0;
1158 intel_private.resource_valid = 0;
1159 iounmap(intel_private.gtt);
1160 iounmap(intel_private.registers);
1161}
1162
1163static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1164{
1165 if (intel_private.i9xx_flush_page)
1166 writel(1, intel_private.i9xx_flush_page);
1167}
1168
1169static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1170 int type)
1171{
1172 int num_entries;
1173 void *temp;
1174 int ret = -EINVAL;
1175 int mask_type;
1176
1177 if (mem->page_count == 0)
1178 goto out;
1179
1180 temp = agp_bridge->current_size;
1181 num_entries = A_SIZE_FIX(temp)->num_entries;
1182
0ade6386 1183 if (pg_start < intel_private.base.gtt_stolen_entries) {
f51b7662 1184 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
0ade6386
DV		 1185 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1186 pg_start, intel_private.base.gtt_stolen_entries);
f51b7662
DV		 1187
1188 dev_info(&intel_private.pcidev->dev,
1189 "trying to insert into local/stolen memory\n");
1190 goto out_err;
1191 }
1192
1193 if ((pg_start + mem->page_count) > num_entries)
1194 goto out_err;
1195
1196 /* The i915 can't check the GTT for entries since it's read only;
1197 * depend on the caller to make the correct offset decisions.
1198 */
1199
1200 if (type != mem->type)
1201 goto out_err;
1202
1203 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1204
f8f235e5 1205 if (!IS_SNB && mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
f51b7662
DV		 1206 mask_type != INTEL_AGP_CACHED_MEMORY)
1207 goto out_err;
1208
1209 if (!mem->is_flushed)
1210 global_cache_flush();
1211
1212 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
f51b7662
DV		 1213
1214 out:
1215 ret = 0;
1216 out_err:
1217 mem->is_flushed = true;
1218 return ret;
1219}
1220
1221static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1222 int type)
1223{
1224 int i;
1225
1226 if (mem->page_count == 0)
1227 return 0;
1228
0ade6386 1229 if (pg_start < intel_private.base.gtt_stolen_entries) {
f51b7662
DV		 1230 dev_info(&intel_private.pcidev->dev,
1231 "trying to disable local/stolen memory\n");
1232 return -EINVAL;
1233 }
1234
1235 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1236 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1237
1238 readl(intel_private.gtt+i-1);
1239
f51b7662
DV		 1240 return 0;
1241}
1242
1243/* Return the aperture size by just checking the resource length. The effect
1244 * described in the spec of the MSAC registers is just changing of the
1245 * resource size.
1246 */
1247static int intel_i9xx_fetch_size(void)
1248{
1249 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1250 int aper_size; /* size in megabytes */
1251 int i;
1252
1253 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1254
1255 for (i = 0; i < num_sizes; i++) {
1256 if (aper_size == intel_i830_sizes[i].size) {
1257 agp_bridge->current_size = intel_i830_sizes + i;
f51b7662
DV		 1258 return aper_size;
1259 }
1260 }
1261
1262 return 0;
1263}
1264
f1befe71
CW		 1265static int intel_i915_get_gtt_size(void)
1266{
1267 int size;
1268
1269 if (IS_G33) {
1270 u16 gmch_ctrl;
1271
1272 /* G33's GTT size defined in gmch_ctrl */
d7cca2f7 1273 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
e7b96f28
TG		 1274 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
1275 case I830_GMCH_GMS_STOLEN_512:
1276 size = 512;
1277 break;
1278 case I830_GMCH_GMS_STOLEN_1024:
f1befe71
CW		 1279 size = 1024;
1280 break;
e7b96f28
TG		 1281 case I830_GMCH_GMS_STOLEN_8192:
1282 size = 8*1024;
f1befe71
CW		 1283 break;
1284 default:
d7cca2f7 1285 dev_info(&intel_private.bridge_dev->dev,
f1befe71 1286 "unknown page table size 0x%x, assuming 512KB\n",
e7b96f28 1287 (gmch_ctrl & I830_GMCH_GMS_MASK));
f1befe71
CW		 1288 size = 512;
1289 }
1290 } else {
1291 /* On previous hardware, the GTT size was just what was
1292 * required to map the aperture.
1293 */
1294 size = agp_bridge->driver->fetch_size();
1295 }
1296
1297 return KB(size);
1298}
1299
f51b7662
DV		 1300/* The intel i915 automatically initializes the agp aperture during POST.
1301 * Use the memory already set aside for in the GTT.
1302 */
1303static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1304{
1305 int page_order;
1306 struct aper_size_info_fixed *size;
1307 int num_entries;
1308 u32 temp, temp2;
f1befe71 1309 int gtt_map_size;
f51b7662
DV		 1310
1311 size = agp_bridge->current_size;
1312 page_order = size->page_order;
1313 num_entries = size->num_entries;
1314 agp_bridge->gatt_table_real = NULL;
1315
1316 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1317 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1318
f1befe71
CW		 1319 gtt_map_size = intel_i915_get_gtt_size();
1320
f51b7662
DV		 1321 intel_private.gtt = ioremap(temp2, gtt_map_size);
1322 if (!intel_private.gtt)
1323 return -ENOMEM;
1324
0ade6386 1325 intel_private.base.gtt_total_entries = gtt_map_size / 4;
f51b7662
DV		 1326
1327 temp &= 0xfff80000;
1328
1329 intel_private.registers = ioremap(temp, 128 * 4096);
1330 if (!intel_private.registers) {
1331 iounmap(intel_private.gtt);
1332 return -ENOMEM;
1333 }
1334
1335 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1336 global_cache_flush(); /* FIXME: ? */
1337
1338 /* we have to call this as early as possible after the MMIO base address is known */
1339 intel_i830_init_gtt_entries();
0ade6386 1340 if (intel_private.base.gtt_stolen_entries == 0) {
8699be3e
OZ		 1341 iounmap(intel_private.gtt);
1342 iounmap(intel_private.registers);
1343 return -ENOMEM;
1344 }
f51b7662
DV		 1345
1346 agp_bridge->gatt_table = NULL;
1347
1348 agp_bridge->gatt_bus_addr = temp;
1349
1350 return 0;
1351}
1352
1353/*
1354 * The i965 supports 36-bit physical addresses, but to keep
1355 * the format of the GTT the same, the bits that don't fit
1356 * in a 32-bit word are shifted down to bits 4..7.
1357 *
1358 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1359 * is always zero on 32-bit architectures, so no need to make
1360 * this conditional.
1361 */
1362static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1363 dma_addr_t addr, int type)
1364{
1365 /* Shift high bits down */
1366 addr |= (addr >> 28) & 0xf0;
1367
1368 /* Type checking must be done elsewhere */
1369 return addr | bridge->driver->masks[type].mask;
1370}
1371
3869d4a8
ZW		 1372static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1373 dma_addr_t addr, int type)
1374{
8dfc2b14
ZW		 1375 /* gen6 has bit11-4 for physical addr bit39-32 */
1376 addr |= (addr >> 28) & 0xff0;
3869d4a8
ZW		 1377
1378 /* Type checking must be done elsewhere */
1379 return addr | bridge->driver->masks[type].mask;
1380}
1381
f51b7662
DV		 1382static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1383{
1384 u16 snb_gmch_ctl;
1385
d7cca2f7 1386 switch (intel_private.bridge_dev->device) {
f51b7662
DV		 1387 case PCI_DEVICE_ID_INTEL_GM45_HB:
1388 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1389 case PCI_DEVICE_ID_INTEL_Q45_HB:
1390 case PCI_DEVICE_ID_INTEL_G45_HB:
1391 case PCI_DEVICE_ID_INTEL_G41_HB:
1392 case PCI_DEVICE_ID_INTEL_B43_HB:
1393 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1394 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1395 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1396 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1397 *gtt_offset = *gtt_size = MB(2);
1398 break;
1399 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1400 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
85540480 1401 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
f51b7662
DV		 1402 *gtt_offset = MB(2);
1403
1404 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1405 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1406 default:
1407 case SNB_GTT_SIZE_0M:
1408 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1409 *gtt_size = MB(0);
1410 break;
1411 case SNB_GTT_SIZE_1M:
1412 *gtt_size = MB(1);
1413 break;
1414 case SNB_GTT_SIZE_2M:
1415 *gtt_size = MB(2);
1416 break;
1417 }
1418 break;
1419 default:
1420 *gtt_offset = *gtt_size = KB(512);
1421 }
1422}
1423
1424/* The intel i965 automatically initializes the agp aperture during POST.
1425 * Use the memory already set aside for in the GTT.
1426 */
1427static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1428{
1429 int page_order;
1430 struct aper_size_info_fixed *size;
1431 int num_entries;
1432 u32 temp;
1433 int gtt_offset, gtt_size;
1434
1435 size = agp_bridge->current_size;
1436 page_order = size->page_order;
1437 num_entries = size->num_entries;
1438 agp_bridge->gatt_table_real = NULL;
1439
1440 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1441
1442 temp &= 0xfff00000;
1443
1444 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1445
1446 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1447
1448 if (!intel_private.gtt)
1449 return -ENOMEM;
1450
0ade6386 1451 intel_private.base.gtt_total_entries = gtt_size / 4;
f51b7662
DV		 1452
1453 intel_private.registers = ioremap(temp, 128 * 4096);
1454 if (!intel_private.registers) {
1455 iounmap(intel_private.gtt);
1456 return -ENOMEM;
1457 }
1458
1459 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1460 global_cache_flush(); /* FIXME: ? */
1461
1462 /* we have to call this as early as possible after the MMIO base address is known */
1463 intel_i830_init_gtt_entries();
0ade6386 1464 if (intel_private.base.gtt_stolen_entries == 0) {
8699be3e
OZ		 1465 iounmap(intel_private.gtt);
1466 iounmap(intel_private.registers);
1467 return -ENOMEM;
1468 }
f51b7662
DV		 1469
1470 agp_bridge->gatt_table = NULL;
1471
1472 agp_bridge->gatt_bus_addr = temp;
1473
1474 return 0;
1475}
1476
1477static const struct agp_bridge_driver intel_810_driver = {
1478 .owner = THIS_MODULE,
1479 .aperture_sizes = intel_i810_sizes,
1480 .size_type = FIXED_APER_SIZE,
1481 .num_aperture_sizes = 2,
1482 .needs_scratch_page = true,
1483 .configure = intel_i810_configure,
1484 .fetch_size = intel_i810_fetch_size,
1485 .cleanup = intel_i810_cleanup,
f51b7662
DV		 1486 .mask_memory = intel_i810_mask_memory,
1487 .masks = intel_i810_masks,
1488 .agp_enable = intel_i810_agp_enable,
1489 .cache_flush = global_cache_flush,
1490 .create_gatt_table = agp_generic_create_gatt_table,
1491 .free_gatt_table = agp_generic_free_gatt_table,
1492 .insert_memory = intel_i810_insert_entries,
1493 .remove_memory = intel_i810_remove_entries,
1494 .alloc_by_type = intel_i810_alloc_by_type,
1495 .free_by_type = intel_i810_free_by_type,
1496 .agp_alloc_page = agp_generic_alloc_page,
1497 .agp_alloc_pages = agp_generic_alloc_pages,
1498 .agp_destroy_page = agp_generic_destroy_page,
1499 .agp_destroy_pages = agp_generic_destroy_pages,
1500 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1501};
1502
1503static const struct agp_bridge_driver intel_830_driver = {
1504 .owner = THIS_MODULE,
1505 .aperture_sizes = intel_i830_sizes,
1506 .size_type = FIXED_APER_SIZE,
1507 .num_aperture_sizes = 4,
1508 .needs_scratch_page = true,
1509 .configure = intel_i830_configure,
1510 .fetch_size = intel_i830_fetch_size,
1511 .cleanup = intel_i830_cleanup,
f51b7662
DV		 1512 .mask_memory = intel_i810_mask_memory,
1513 .masks = intel_i810_masks,
1514 .agp_enable = intel_i810_agp_enable,
1515 .cache_flush = global_cache_flush,
1516 .create_gatt_table = intel_i830_create_gatt_table,
1517 .free_gatt_table = intel_i830_free_gatt_table,
1518 .insert_memory = intel_i830_insert_entries,
1519 .remove_memory = intel_i830_remove_entries,
1520 .alloc_by_type = intel_i830_alloc_by_type,
1521 .free_by_type = intel_i810_free_by_type,
1522 .agp_alloc_page = agp_generic_alloc_page,
1523 .agp_alloc_pages = agp_generic_alloc_pages,
1524 .agp_destroy_page = agp_generic_destroy_page,
1525 .agp_destroy_pages = agp_generic_destroy_pages,
1526 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1527 .chipset_flush = intel_i830_chipset_flush,
1528};
1529
1530static const struct agp_bridge_driver intel_915_driver = {
1531 .owner = THIS_MODULE,
1532 .aperture_sizes = intel_i830_sizes,
1533 .size_type = FIXED_APER_SIZE,
1534 .num_aperture_sizes = 4,
1535 .needs_scratch_page = true,
f1befe71 1536 .configure = intel_i9xx_configure,
f51b7662
DV		 1537 .fetch_size = intel_i9xx_fetch_size,
1538 .cleanup = intel_i915_cleanup,
f51b7662
DV		 1539 .mask_memory = intel_i810_mask_memory,
1540 .masks = intel_i810_masks,
1541 .agp_enable = intel_i810_agp_enable,
1542 .cache_flush = global_cache_flush,
1543 .create_gatt_table = intel_i915_create_gatt_table,
1544 .free_gatt_table = intel_i830_free_gatt_table,
1545 .insert_memory = intel_i915_insert_entries,
1546 .remove_memory = intel_i915_remove_entries,
1547 .alloc_by_type = intel_i830_alloc_by_type,
1548 .free_by_type = intel_i810_free_by_type,
1549 .agp_alloc_page = agp_generic_alloc_page,
1550 .agp_alloc_pages = agp_generic_alloc_pages,
1551 .agp_destroy_page = agp_generic_destroy_page,
1552 .agp_destroy_pages = agp_generic_destroy_pages,
1553 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1554 .chipset_flush = intel_i915_chipset_flush,
1555#ifdef USE_PCI_DMA_API
1556 .agp_map_page = intel_agp_map_page,
1557 .agp_unmap_page = intel_agp_unmap_page,
1558 .agp_map_memory = intel_agp_map_memory,
1559 .agp_unmap_memory = intel_agp_unmap_memory,
1560#endif
1561};
1562
1563static const struct agp_bridge_driver intel_i965_driver = {
1564 .owner = THIS_MODULE,
1565 .aperture_sizes = intel_i830_sizes,
1566 .size_type = FIXED_APER_SIZE,
1567 .num_aperture_sizes = 4,
1568 .needs_scratch_page = true,
f1befe71 1569 .configure = intel_i9xx_configure,
f51b7662
DV		 1570 .fetch_size = intel_i9xx_fetch_size,
1571 .cleanup = intel_i915_cleanup,
f51b7662
DV		 1572 .mask_memory = intel_i965_mask_memory,
1573 .masks = intel_i810_masks,
1574 .agp_enable = intel_i810_agp_enable,
1575 .cache_flush = global_cache_flush,
3869d4a8
ZW		 1576 .create_gatt_table = intel_i965_create_gatt_table,
1577 .free_gatt_table = intel_i830_free_gatt_table,
1578 .insert_memory = intel_i915_insert_entries,
1579 .remove_memory = intel_i915_remove_entries,
1580 .alloc_by_type = intel_i830_alloc_by_type,
1581 .free_by_type = intel_i810_free_by_type,
1582 .agp_alloc_page = agp_generic_alloc_page,
1583 .agp_alloc_pages = agp_generic_alloc_pages,
1584 .agp_destroy_page = agp_generic_destroy_page,
1585 .agp_destroy_pages = agp_generic_destroy_pages,
1586 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1587 .chipset_flush = intel_i915_chipset_flush,
1588#ifdef USE_PCI_DMA_API
1589 .agp_map_page = intel_agp_map_page,
1590 .agp_unmap_page = intel_agp_unmap_page,
1591 .agp_map_memory = intel_agp_map_memory,
1592 .agp_unmap_memory = intel_agp_unmap_memory,
1593#endif
1594};
1595
1596static const struct agp_bridge_driver intel_gen6_driver = {
1597 .owner = THIS_MODULE,
1598 .aperture_sizes = intel_i830_sizes,
1599 .size_type = FIXED_APER_SIZE,
1600 .num_aperture_sizes = 4,
1601 .needs_scratch_page = true,
1602 .configure = intel_i9xx_configure,
1603 .fetch_size = intel_i9xx_fetch_size,
1604 .cleanup = intel_i915_cleanup,
1605 .mask_memory = intel_gen6_mask_memory,
f8f235e5 1606 .masks = intel_gen6_masks,
3869d4a8
ZW		 1607 .agp_enable = intel_i810_agp_enable,
1608 .cache_flush = global_cache_flush,
f51b7662
DV		 1609 .create_gatt_table = intel_i965_create_gatt_table,
1610 .free_gatt_table = intel_i830_free_gatt_table,
1611 .insert_memory = intel_i915_insert_entries,
1612 .remove_memory = intel_i915_remove_entries,
1613 .alloc_by_type = intel_i830_alloc_by_type,
1614 .free_by_type = intel_i810_free_by_type,
1615 .agp_alloc_page = agp_generic_alloc_page,
1616 .agp_alloc_pages = agp_generic_alloc_pages,
1617 .agp_destroy_page = agp_generic_destroy_page,
1618 .agp_destroy_pages = agp_generic_destroy_pages,
f8f235e5 1619 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
f51b7662
DV		 1620 .chipset_flush = intel_i915_chipset_flush,
1621#ifdef USE_PCI_DMA_API
1622 .agp_map_page = intel_agp_map_page,
1623 .agp_unmap_page = intel_agp_unmap_page,
1624 .agp_map_memory = intel_agp_map_memory,
1625 .agp_unmap_memory = intel_agp_unmap_memory,
1626#endif
1627};
1628
1629static const struct agp_bridge_driver intel_g33_driver = {
1630 .owner = THIS_MODULE,
1631 .aperture_sizes = intel_i830_sizes,
1632 .size_type = FIXED_APER_SIZE,
1633 .num_aperture_sizes = 4,
1634 .needs_scratch_page = true,
f1befe71 1635 .configure = intel_i9xx_configure,
f51b7662
DV		 1636 .fetch_size = intel_i9xx_fetch_size,
1637 .cleanup = intel_i915_cleanup,
f51b7662
DV		 1638 .mask_memory = intel_i965_mask_memory,
1639 .masks = intel_i810_masks,
1640 .agp_enable = intel_i810_agp_enable,
1641 .cache_flush = global_cache_flush,
1642 .create_gatt_table = intel_i915_create_gatt_table,
1643 .free_gatt_table = intel_i830_free_gatt_table,
1644 .insert_memory = intel_i915_insert_entries,
1645 .remove_memory = intel_i915_remove_entries,
1646 .alloc_by_type = intel_i830_alloc_by_type,
1647 .free_by_type = intel_i810_free_by_type,
1648 .agp_alloc_page = agp_generic_alloc_page,
1649 .agp_alloc_pages = agp_generic_alloc_pages,
1650 .agp_destroy_page = agp_generic_destroy_page,
1651 .agp_destroy_pages = agp_generic_destroy_pages,
1652 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1653 .chipset_flush = intel_i915_chipset_flush,
1654#ifdef USE_PCI_DMA_API
1655 .agp_map_page = intel_agp_map_page,
1656 .agp_unmap_page = intel_agp_unmap_page,
1657 .agp_map_memory = intel_agp_map_memory,
1658 .agp_unmap_memory = intel_agp_unmap_memory,
1659#endif
1660};
02c026ce
DV		 1661
1662/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1663 * driver and gmch_driver must be non-null, and find_gmch will determine
1664 * which one should be used if a gmch_chip_id is present.
1665 */
1666static const struct intel_gtt_driver_description {
1667 unsigned int gmch_chip_id;
1668 char *name;
1669 const struct agp_bridge_driver *gmch_driver;
1670} intel_gtt_chipsets[] = {
1671 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver },
1672 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver },
1673 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver },
1674 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver },
1675 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", &intel_830_driver },
1676 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", &intel_830_driver },
1677 { PCI_DEVICE_ID_INTEL_82854_IG, "854", &intel_830_driver },
1678 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", &intel_830_driver },
1679 { PCI_DEVICE_ID_INTEL_82865_IG, "865", &intel_830_driver },
1680 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", &intel_915_driver },
1681 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", &intel_915_driver },
1682 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", &intel_915_driver },
1683 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", &intel_915_driver },
1684 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", &intel_915_driver },
1685 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", &intel_915_driver },
1686 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", &intel_i965_driver },
1687 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", &intel_i965_driver },
1688 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", &intel_i965_driver },
1689 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", &intel_i965_driver },
1690 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", &intel_i965_driver },
1691 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", &intel_i965_driver },
1692 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", &intel_g33_driver },
1693 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", &intel_g33_driver },
1694 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", &intel_g33_driver },
1695 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", &intel_g33_driver },
1696 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", &intel_g33_driver },
1697 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", &intel_i965_driver },
1698 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", &intel_i965_driver },
1699 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", &intel_i965_driver },
1700 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", &intel_i965_driver },
1701 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", &intel_i965_driver },
1702 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", &intel_i965_driver },
1703 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1704 "HD Graphics", &intel_i965_driver },
1705 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1706 "HD Graphics", &intel_i965_driver },
1707 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1708 "Sandybridge", &intel_gen6_driver },
1709 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1710 "Sandybridge", &intel_gen6_driver },
1711 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1712 "Sandybridge", &intel_gen6_driver },
1713 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1714 "Sandybridge", &intel_gen6_driver },
1715 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1716 "Sandybridge", &intel_gen6_driver },
1717 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1718 "Sandybridge", &intel_gen6_driver },
1719 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1720 "Sandybridge", &intel_gen6_driver },
1721 { 0, NULL, NULL }
1722};
1723
1724static int find_gmch(u16 device)
1725{
1726 struct pci_dev *gmch_device;
1727
1728 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1729 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1730 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1731 device, gmch_device);
1732 }
1733
1734 if (!gmch_device)
1735 return 0;
1736
1737 intel_private.pcidev = gmch_device;
1738 return 1;
1739}
1740
e2404e7c 1741int intel_gmch_probe(struct pci_dev *pdev,
02c026ce
DV		 1742 struct agp_bridge_data *bridge)
1743{
1744 int i, mask;
1745 bridge->driver = NULL;
1746
1747 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1748 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1749 bridge->driver =
1750 intel_gtt_chipsets[i].gmch_driver;
1751 break;
1752 }
1753 }
1754
1755 if (!bridge->driver)
1756 return 0;
1757
1758 bridge->dev_private_data = &intel_private;
1759 bridge->dev = pdev;
1760
d7cca2f7
DV		 1761 intel_private.bridge_dev = pci_dev_get(pdev);
1762
02c026ce
DV		 1763 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1764
1765 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1766 mask = 40;
1767 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1768 mask = 36;
1769 else
1770 mask = 32;
1771
1772 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1773 dev_err(&intel_private.pcidev->dev,
1774 "set gfx device dma mask %d-bit failed!\n", mask);
1775 else
1776 pci_set_consistent_dma_mask(intel_private.pcidev,
1777 DMA_BIT_MASK(mask));
1778
1779 return 1;
1780}
e2404e7c 1781EXPORT_SYMBOL(intel_gmch_probe);
02c026ce 1782
e2404e7c 1783void intel_gmch_remove(struct pci_dev *pdev)
02c026ce
DV		 1784{
1785 if (intel_private.pcidev)
1786 pci_dev_put(intel_private.pcidev);
d7cca2f7
DV		 1787 if (intel_private.bridge_dev)
1788 pci_dev_put(intel_private.bridge_dev);
02c026ce 1789}
e2404e7c
DV		 1790EXPORT_SYMBOL(intel_gmch_remove);
1791
1792MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1793MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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