Commit | Line | Data |
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1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file ati_pcigart.c |
1da177e4 LT |
3 | * ATI PCI GART support |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com | |
10 | * | |
11 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
12 | * All Rights Reserved. | |
13 | * | |
14 | * Permission is hereby granted, free of charge, to any person obtaining a | |
15 | * copy of this software and associated documentation files (the "Software"), | |
16 | * to deal in the Software without restriction, including without limitation | |
17 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
18 | * and/or sell copies of the Software, and to permit persons to whom the | |
19 | * Software is furnished to do so, subject to the following conditions: | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the next | |
22 | * paragraph) shall be included in all copies or substantial portions of the | |
23 | * Software. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
26 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
27 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
28 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
29 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
30 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
31 | * DEALINGS IN THE SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include "drmP.h" | |
35 | ||
1da177e4 LT |
36 | # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ |
37 | ||
f2b04cd2 | 38 | static void *drm_ati_alloc_pcigart_table(int order) |
1da177e4 LT |
39 | { |
40 | unsigned long address; | |
41 | struct page *page; | |
42 | int i; | |
f2b04cd2 | 43 | |
3e684eae | 44 | DRM_DEBUG("%d order\n", order); |
1da177e4 | 45 | |
507d256b | 46 | address = __get_free_pages(GFP_KERNEL | __GFP_COMP, |
f2b04cd2 | 47 | order); |
b5e89ed5 | 48 | if (address == 0UL) { |
f1e5c03d | 49 | return NULL; |
1da177e4 LT |
50 | } |
51 | ||
b5e89ed5 | 52 | page = virt_to_page(address); |
1da177e4 | 53 | |
f2b04cd2 | 54 | for (i = 0; i < order; i++, page++) |
b5e89ed5 | 55 | SetPageReserved(page); |
1da177e4 | 56 | |
3e684eae | 57 | DRM_DEBUG("returning 0x%08lx\n", address); |
f26c473c | 58 | return (void *)address; |
1da177e4 LT |
59 | } |
60 | ||
f2b04cd2 | 61 | static void drm_ati_free_pcigart_table(void *address, int order) |
1da177e4 LT |
62 | { |
63 | struct page *page; | |
64 | int i; | |
f2b04cd2 | 65 | int num_pages = 1 << order; |
3e684eae | 66 | DRM_DEBUG("\n"); |
1da177e4 | 67 | |
f26c473c | 68 | page = virt_to_page((unsigned long)address); |
1da177e4 | 69 | |
f2b04cd2 | 70 | for (i = 0; i < num_pages; i++, page++) |
b5e89ed5 | 71 | ClearPageReserved(page); |
1da177e4 | 72 | |
f2b04cd2 | 73 | free_pages((unsigned long)address, order); |
1da177e4 LT |
74 | } |
75 | ||
55910517 | 76 | int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 77 | { |
55910517 | 78 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
79 | unsigned long pages; |
80 | int i; | |
f2b04cd2 DA |
81 | int order; |
82 | int num_pages, max_pages; | |
1da177e4 LT |
83 | |
84 | /* we need to support large memory configurations */ | |
b5e89ed5 DA |
85 | if (!entry) { |
86 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
87 | return 0; |
88 | } | |
89 | ||
f2b04cd2 DA |
90 | order = drm_order((gart_info->table_size + (PAGE_SIZE-1)) / PAGE_SIZE); |
91 | num_pages = 1 << order; | |
92 | ||
ea98a92f | 93 | if (gart_info->bus_addr) { |
b5e89ed5 | 94 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
ea98a92f | 95 | pci_unmap_single(dev->pdev, gart_info->bus_addr, |
f2b04cd2 | 96 | num_pages * PAGE_SIZE, |
ea98a92f DA |
97 | PCI_DMA_TODEVICE); |
98 | } | |
1da177e4 | 99 | |
f2b04cd2 DA |
100 | max_pages = (gart_info->table_size / sizeof(u32)); |
101 | pages = (entry->pages <= max_pages) | |
102 | ? entry->pages : max_pages; | |
1da177e4 | 103 | |
b5e89ed5 DA |
104 | for (i = 0; i < pages; i++) { |
105 | if (!entry->busaddr[i]) | |
106 | break; | |
1da177e4 LT |
107 | pci_unmap_single(dev->pdev, entry->busaddr[i], |
108 | PAGE_SIZE, PCI_DMA_TODEVICE); | |
109 | } | |
b5e89ed5 DA |
110 | |
111 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) | |
112 | gart_info->bus_addr = 0; | |
1da177e4 LT |
113 | } |
114 | ||
b5e89ed5 DA |
115 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN |
116 | && gart_info->addr) { | |
f2b04cd2 | 117 | drm_ati_free_pcigart_table(gart_info->addr, order); |
f1e5c03d | 118 | gart_info->addr = NULL; |
1da177e4 LT |
119 | } |
120 | ||
121 | return 1; | |
122 | } | |
123 | EXPORT_SYMBOL(drm_ati_pcigart_cleanup); | |
124 | ||
55910517 | 125 | int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 126 | { |
55910517 | 127 | struct drm_sg_mem *entry = dev->sg; |
f26c473c | 128 | void *address = NULL; |
1da177e4 LT |
129 | unsigned long pages; |
130 | u32 *pci_gart, page_base, bus_address = 0; | |
131 | int i, j, ret = 0; | |
f2b04cd2 DA |
132 | int order; |
133 | int max_pages; | |
134 | int num_pages; | |
1da177e4 | 135 | |
b5e89ed5 DA |
136 | if (!entry) { |
137 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
138 | goto done; |
139 | } | |
140 | ||
b5e89ed5 | 141 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
ea98a92f | 142 | DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); |
b5e89ed5 | 143 | |
f2b04cd2 DA |
144 | order = drm_order((gart_info->table_size + |
145 | (PAGE_SIZE-1)) / PAGE_SIZE); | |
146 | num_pages = 1 << order; | |
147 | address = drm_ati_alloc_pcigart_table(order); | |
b5e89ed5 DA |
148 | if (!address) { |
149 | DRM_ERROR("cannot allocate PCI GART page!\n"); | |
ea98a92f DA |
150 | goto done; |
151 | } | |
b5e89ed5 DA |
152 | |
153 | if (!dev->pdev) { | |
154 | DRM_ERROR("PCI device unknown!\n"); | |
ea98a92f DA |
155 | goto done; |
156 | } | |
1da177e4 | 157 | |
f26c473c | 158 | bus_address = pci_map_single(dev->pdev, address, |
f2b04cd2 DA |
159 | num_pages * PAGE_SIZE, |
160 | PCI_DMA_TODEVICE); | |
ea98a92f | 161 | if (bus_address == 0) { |
b5e89ed5 | 162 | DRM_ERROR("unable to map PCIGART pages!\n"); |
f2b04cd2 DA |
163 | order = drm_order((gart_info->table_size + |
164 | (PAGE_SIZE-1)) / PAGE_SIZE); | |
165 | drm_ati_free_pcigart_table(address, order); | |
f1e5c03d | 166 | address = NULL; |
ea98a92f DA |
167 | goto done; |
168 | } | |
b5e89ed5 | 169 | } else { |
ea98a92f DA |
170 | address = gart_info->addr; |
171 | bus_address = gart_info->bus_addr; | |
b5e89ed5 | 172 | DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n", |
f26c473c | 173 | bus_address, (unsigned long)address); |
1da177e4 LT |
174 | } |
175 | ||
b5e89ed5 | 176 | pci_gart = (u32 *) address; |
1da177e4 | 177 | |
f2b04cd2 DA |
178 | max_pages = (gart_info->table_size / sizeof(u32)); |
179 | pages = (entry->pages <= max_pages) | |
180 | ? entry->pages : max_pages; | |
1da177e4 | 181 | |
f2b04cd2 | 182 | memset(pci_gart, 0, max_pages * sizeof(u32)); |
1da177e4 | 183 | |
b5e89ed5 | 184 | for (i = 0; i < pages; i++) { |
1da177e4 LT |
185 | /* we need to support large memory configurations */ |
186 | entry->busaddr[i] = pci_map_single(dev->pdev, | |
b5e89ed5 DA |
187 | page_address(entry-> |
188 | pagelist[i]), | |
189 | PAGE_SIZE, PCI_DMA_TODEVICE); | |
1da177e4 | 190 | if (entry->busaddr[i] == 0) { |
b5e89ed5 | 191 | DRM_ERROR("unable to map PCIGART pages!\n"); |
ea98a92f | 192 | drm_ati_pcigart_cleanup(dev, gart_info); |
f26c473c | 193 | address = NULL; |
1da177e4 LT |
194 | bus_address = 0; |
195 | goto done; | |
196 | } | |
197 | page_base = (u32) entry->busaddr[i]; | |
198 | ||
199 | for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { | |
f2b04cd2 DA |
200 | switch(gart_info->gart_reg_if) { |
201 | case DRM_ATI_GART_IGP: | |
202 | *pci_gart = cpu_to_le32((page_base) | 0xc); | |
203 | break; | |
204 | case DRM_ATI_GART_PCIE: | |
d34d7ae2 | 205 | *pci_gart = cpu_to_le32((page_base >> 8) | 0xc); |
f2b04cd2 DA |
206 | break; |
207 | default: | |
208 | case DRM_ATI_GART_PCI: | |
3d5efad9 | 209 | *pci_gart = cpu_to_le32(page_base); |
f2b04cd2 DA |
210 | break; |
211 | } | |
d34d7ae2 | 212 | pci_gart++; |
1da177e4 LT |
213 | page_base += ATI_PCIGART_PAGE_SIZE; |
214 | } | |
215 | } | |
216 | ||
217 | ret = 1; | |
218 | ||
219 | #if defined(__i386__) || defined(__x86_64__) | |
220 | wbinvd(); | |
221 | #else | |
222 | mb(); | |
223 | #endif | |
224 | ||
b5e89ed5 | 225 | done: |
ea98a92f | 226 | gart_info->addr = address; |
b5e89ed5 | 227 | gart_info->bus_addr = bus_address; |
1da177e4 LT |
228 | return ret; |
229 | } | |
230 | EXPORT_SYMBOL(drm_ati_pcigart_init); |