Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file drm.h |
1da177e4 | 3 | * Header for the Direct Rendering Manager |
b5e89ed5 | 4 | * |
1da177e4 LT |
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> |
6 | * | |
7 | * \par Acknowledgments: | |
8 | * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
13 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
14 | * All rights reserved. | |
15 | * | |
16 | * Permission is hereby granted, free of charge, to any person obtaining a | |
17 | * copy of this software and associated documentation files (the "Software"), | |
18 | * to deal in the Software without restriction, including without limitation | |
19 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
20 | * and/or sell copies of the Software, and to permit persons to whom the | |
21 | * Software is furnished to do so, subject to the following conditions: | |
22 | * | |
23 | * The above copyright notice and this permission notice (including the next | |
24 | * paragraph) shall be included in all copies or substantial portions of the | |
25 | * Software. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
28 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
29 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
30 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
31 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
32 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
33 | * OTHER DEALINGS IN THE SOFTWARE. | |
34 | */ | |
35 | ||
1da177e4 LT |
36 | #ifndef _DRM_H_ |
37 | #define _DRM_H_ | |
38 | ||
39 | #if defined(__linux__) | |
850eb83a | 40 | #if defined(__KERNEL__) |
850eb83a | 41 | #endif |
1da177e4 LT |
42 | #include <asm/ioctl.h> /* For _IO* macros */ |
43 | #define DRM_IOCTL_NR(n) _IOC_NR(n) | |
44 | #define DRM_IOC_VOID _IOC_NONE | |
45 | #define DRM_IOC_READ _IOC_READ | |
46 | #define DRM_IOC_WRITE _IOC_WRITE | |
47 | #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE | |
48 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | |
49 | #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) | |
50 | #if defined(__FreeBSD__) && defined(IN_MODULE) | |
51 | /* Prevent name collision when including sys/ioccom.h */ | |
52 | #undef ioctl | |
53 | #include <sys/ioccom.h> | |
54 | #define ioctl(a,b,c) xf86ioctl(a,b,c) | |
55 | #else | |
56 | #include <sys/ioccom.h> | |
b5e89ed5 | 57 | #endif /* __FreeBSD__ && xf86ioctl */ |
1da177e4 LT |
58 | #define DRM_IOCTL_NR(n) ((n) & 0xff) |
59 | #define DRM_IOC_VOID IOC_VOID | |
60 | #define DRM_IOC_READ IOC_OUT | |
61 | #define DRM_IOC_WRITE IOC_IN | |
62 | #define DRM_IOC_READWRITE IOC_INOUT | |
63 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | |
64 | #endif | |
65 | ||
66 | #define XFREE86_VERSION(major,minor,patch,snap) \ | |
67 | ((major << 16) | (minor << 8) | patch) | |
68 | ||
69 | #ifndef CONFIG_XFREE86_VERSION | |
70 | #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) | |
71 | #endif | |
72 | ||
73 | #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) | |
74 | #define DRM_PROC_DEVICES "/proc/devices" | |
75 | #define DRM_PROC_MISC "/proc/misc" | |
76 | #define DRM_PROC_DRM "/proc/drm" | |
77 | #define DRM_DEV_DRM "/dev/drm" | |
78 | #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) | |
79 | #define DRM_DEV_UID 0 | |
80 | #define DRM_DEV_GID 0 | |
81 | #endif | |
82 | ||
83 | #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) | |
84 | #define DRM_MAJOR 226 | |
85 | #define DRM_MAX_MINOR 15 | |
86 | #endif | |
87 | #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ | |
88 | #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ | |
89 | #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ | |
90 | #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ | |
91 | ||
b3a80a22 DA |
92 | #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ |
93 | #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ | |
1da177e4 LT |
94 | #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) |
95 | #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) | |
96 | #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) | |
97 | ||
b5e89ed5 DA |
98 | typedef unsigned int drm_handle_t; |
99 | typedef unsigned int drm_context_t; | |
100 | typedef unsigned int drm_drawable_t; | |
101 | typedef unsigned int drm_magic_t; | |
1da177e4 LT |
102 | |
103 | /** | |
104 | * Cliprect. | |
b5e89ed5 | 105 | * |
1da177e4 LT |
106 | * \warning: If you change this structure, make sure you change |
107 | * XF86DRIClipRectRec in the server as well | |
108 | * | |
109 | * \note KW: Actually it's illegal to change either for | |
110 | * backwards-compatibility reasons. | |
111 | */ | |
112 | typedef struct drm_clip_rect { | |
b5e89ed5 DA |
113 | unsigned short x1; |
114 | unsigned short y1; | |
115 | unsigned short x2; | |
116 | unsigned short y2; | |
1da177e4 LT |
117 | } drm_clip_rect_t; |
118 | ||
1da177e4 LT |
119 | /** |
120 | * Texture region, | |
121 | */ | |
122 | typedef struct drm_tex_region { | |
b5e89ed5 DA |
123 | unsigned char next; |
124 | unsigned char prev; | |
125 | unsigned char in_use; | |
126 | unsigned char padding; | |
127 | unsigned int age; | |
1da177e4 LT |
128 | } drm_tex_region_t; |
129 | ||
130 | /** | |
131 | * Hardware lock. | |
132 | * | |
133 | * The lock structure is a simple cache-line aligned integer. To avoid | |
134 | * processor bus contention on a multiprocessor system, there should not be any | |
135 | * other data stored in the same cache line. | |
136 | */ | |
137 | typedef struct drm_hw_lock { | |
138 | __volatile__ unsigned int lock; /**< lock variable */ | |
b5e89ed5 | 139 | char padding[60]; /**< Pad to cache line */ |
1da177e4 LT |
140 | } drm_hw_lock_t; |
141 | ||
1da177e4 LT |
142 | /** |
143 | * DRM_IOCTL_VERSION ioctl argument type. | |
b5e89ed5 | 144 | * |
1da177e4 LT |
145 | * \sa drmGetVersion(). |
146 | */ | |
147 | typedef struct drm_version { | |
b5e89ed5 DA |
148 | int version_major; /**< Major version */ |
149 | int version_minor; /**< Minor version */ | |
150 | int version_patchlevel; /**< Patch level */ | |
1da177e4 | 151 | size_t name_len; /**< Length of name buffer */ |
b5e89ed5 | 152 | char __user *name; /**< Name of driver */ |
1da177e4 | 153 | size_t date_len; /**< Length of date buffer */ |
b5e89ed5 | 154 | char __user *date; /**< User-space buffer to hold date */ |
1da177e4 | 155 | size_t desc_len; /**< Length of desc buffer */ |
b5e89ed5 | 156 | char __user *desc; /**< User-space buffer to hold desc */ |
1da177e4 LT |
157 | } drm_version_t; |
158 | ||
1da177e4 LT |
159 | /** |
160 | * DRM_IOCTL_GET_UNIQUE ioctl argument type. | |
161 | * | |
162 | * \sa drmGetBusid() and drmSetBusId(). | |
163 | */ | |
164 | typedef struct drm_unique { | |
165 | size_t unique_len; /**< Length of unique */ | |
b5e89ed5 | 166 | char __user *unique; /**< Unique name for driver instantiation */ |
1da177e4 LT |
167 | } drm_unique_t; |
168 | ||
1da177e4 | 169 | typedef struct drm_list { |
b5e89ed5 DA |
170 | int count; /**< Length of user-space structures */ |
171 | drm_version_t __user *version; | |
1da177e4 LT |
172 | } drm_list_t; |
173 | ||
1da177e4 | 174 | typedef struct drm_block { |
b5e89ed5 | 175 | int unused; |
1da177e4 LT |
176 | } drm_block_t; |
177 | ||
1da177e4 LT |
178 | /** |
179 | * DRM_IOCTL_CONTROL ioctl argument type. | |
180 | * | |
181 | * \sa drmCtlInstHandler() and drmCtlUninstHandler(). | |
182 | */ | |
183 | typedef struct drm_control { | |
184 | enum { | |
185 | DRM_ADD_COMMAND, | |
186 | DRM_RM_COMMAND, | |
187 | DRM_INST_HANDLER, | |
188 | DRM_UNINST_HANDLER | |
b5e89ed5 DA |
189 | } func; |
190 | int irq; | |
1da177e4 LT |
191 | } drm_control_t; |
192 | ||
1da177e4 LT |
193 | /** |
194 | * Type of memory to map. | |
195 | */ | |
196 | typedef enum drm_map_type { | |
b5e89ed5 DA |
197 | _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ |
198 | _DRM_REGISTERS = 1, /**< no caching, no core dump */ | |
199 | _DRM_SHM = 2, /**< shared, cached */ | |
200 | _DRM_AGP = 3, /**< AGP/GART */ | |
2d0f9eaf | 201 | _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ |
b5e89ed5 | 202 | _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ |
1da177e4 LT |
203 | } drm_map_type_t; |
204 | ||
1da177e4 LT |
205 | /** |
206 | * Memory mapping flags. | |
207 | */ | |
208 | typedef enum drm_map_flags { | |
b5e89ed5 DA |
209 | _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ |
210 | _DRM_READ_ONLY = 0x02, | |
211 | _DRM_LOCKED = 0x04, /**< shared, cached, locked */ | |
212 | _DRM_KERNEL = 0x08, /**< kernel requires access */ | |
1da177e4 | 213 | _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ |
b5e89ed5 DA |
214 | _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ |
215 | _DRM_REMOVABLE = 0x40 /**< Removable mapping */ | |
1da177e4 LT |
216 | } drm_map_flags_t; |
217 | ||
1da177e4 | 218 | typedef struct drm_ctx_priv_map { |
b5e89ed5 DA |
219 | unsigned int ctx_id; /**< Context requesting private mapping */ |
220 | void *handle; /**< Handle of map */ | |
1da177e4 LT |
221 | } drm_ctx_priv_map_t; |
222 | ||
1da177e4 LT |
223 | /** |
224 | * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls | |
225 | * argument type. | |
226 | * | |
227 | * \sa drmAddMap(). | |
228 | */ | |
229 | typedef struct drm_map { | |
b5e89ed5 DA |
230 | unsigned long offset; /**< Requested physical address (0 for SAREA)*/ |
231 | unsigned long size; /**< Requested physical size (bytes) */ | |
232 | drm_map_type_t type; /**< Type of memory to map */ | |
1da177e4 | 233 | drm_map_flags_t flags; /**< Flags */ |
b5e89ed5 | 234 | void *handle; /**< User-space: "Handle" to pass to mmap() */ |
1da177e4 | 235 | /**< Kernel-space: kernel-virtual address */ |
b5e89ed5 DA |
236 | int mtrr; /**< MTRR slot used */ |
237 | /* Private data */ | |
1da177e4 LT |
238 | } drm_map_t; |
239 | ||
1da177e4 LT |
240 | /** |
241 | * DRM_IOCTL_GET_CLIENT ioctl argument type. | |
242 | */ | |
243 | typedef struct drm_client { | |
b5e89ed5 DA |
244 | int idx; /**< Which client desired? */ |
245 | int auth; /**< Is client authenticated? */ | |
246 | unsigned long pid; /**< Process ID */ | |
247 | unsigned long uid; /**< User ID */ | |
248 | unsigned long magic; /**< Magic */ | |
249 | unsigned long iocs; /**< Ioctl count */ | |
1da177e4 LT |
250 | } drm_client_t; |
251 | ||
1da177e4 LT |
252 | typedef enum { |
253 | _DRM_STAT_LOCK, | |
254 | _DRM_STAT_OPENS, | |
255 | _DRM_STAT_CLOSES, | |
256 | _DRM_STAT_IOCTLS, | |
257 | _DRM_STAT_LOCKS, | |
258 | _DRM_STAT_UNLOCKS, | |
259 | _DRM_STAT_VALUE, /**< Generic value */ | |
260 | _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ | |
261 | _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ | |
262 | ||
263 | _DRM_STAT_IRQ, /**< IRQ */ | |
264 | _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ | |
265 | _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ | |
266 | _DRM_STAT_DMA, /**< DMA */ | |
267 | _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ | |
268 | _DRM_STAT_MISSED /**< Missed DMA opportunity */ | |
b5e89ed5 | 269 | /* Add to the *END* of the list */ |
1da177e4 LT |
270 | } drm_stat_type_t; |
271 | ||
1da177e4 LT |
272 | /** |
273 | * DRM_IOCTL_GET_STATS ioctl argument type. | |
274 | */ | |
275 | typedef struct drm_stats { | |
276 | unsigned long count; | |
277 | struct { | |
b5e89ed5 | 278 | unsigned long value; |
1da177e4 LT |
279 | drm_stat_type_t type; |
280 | } data[15]; | |
281 | } drm_stats_t; | |
282 | ||
1da177e4 LT |
283 | /** |
284 | * Hardware locking flags. | |
285 | */ | |
286 | typedef enum drm_lock_flags { | |
b5e89ed5 DA |
287 | _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ |
288 | _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ | |
289 | _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ | |
290 | _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ | |
291 | /* These *HALT* flags aren't supported yet | |
292 | -- they will be used to support the | |
293 | full-screen DGA-like mode. */ | |
1da177e4 LT |
294 | _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ |
295 | _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ | |
296 | } drm_lock_flags_t; | |
297 | ||
1da177e4 LT |
298 | /** |
299 | * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. | |
b5e89ed5 | 300 | * |
1da177e4 LT |
301 | * \sa drmGetLock() and drmUnlock(). |
302 | */ | |
303 | typedef struct drm_lock { | |
b5e89ed5 | 304 | int context; |
1da177e4 LT |
305 | drm_lock_flags_t flags; |
306 | } drm_lock_t; | |
307 | ||
1da177e4 LT |
308 | /** |
309 | * DMA flags | |
310 | * | |
b5e89ed5 | 311 | * \warning |
1da177e4 LT |
312 | * These values \e must match xf86drm.h. |
313 | * | |
314 | * \sa drm_dma. | |
315 | */ | |
b5e89ed5 DA |
316 | typedef enum drm_dma_flags { |
317 | /* Flags for DMA buffer dispatch */ | |
318 | _DRM_DMA_BLOCK = 0x01, /**< | |
1da177e4 | 319 | * Block until buffer dispatched. |
b5e89ed5 | 320 | * |
1da177e4 LT |
321 | * \note The buffer may not yet have |
322 | * been processed by the hardware -- | |
323 | * getting a hardware lock with the | |
324 | * hardware quiescent will ensure | |
325 | * that the buffer has been | |
326 | * processed. | |
327 | */ | |
328 | _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ | |
b5e89ed5 | 329 | _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ |
1da177e4 | 330 | |
b5e89ed5 DA |
331 | /* Flags for DMA buffer request */ |
332 | _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ | |
333 | _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ | |
334 | _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ | |
1da177e4 LT |
335 | } drm_dma_flags_t; |
336 | ||
1da177e4 LT |
337 | /** |
338 | * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. | |
339 | * | |
340 | * \sa drmAddBufs(). | |
341 | */ | |
342 | typedef struct drm_buf_desc { | |
b5e89ed5 DA |
343 | int count; /**< Number of buffers of this size */ |
344 | int size; /**< Size in bytes */ | |
345 | int low_mark; /**< Low water mark */ | |
346 | int high_mark; /**< High water mark */ | |
1da177e4 | 347 | enum { |
b5e89ed5 DA |
348 | _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ |
349 | _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ | |
350 | _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ | |
351 | _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */ | |
352 | } flags; | |
353 | unsigned long agp_start; /**< | |
1da177e4 LT |
354 | * Start address of where the AGP buffers are |
355 | * in the AGP aperture | |
356 | */ | |
357 | } drm_buf_desc_t; | |
358 | ||
1da177e4 LT |
359 | /** |
360 | * DRM_IOCTL_INFO_BUFS ioctl argument type. | |
361 | */ | |
362 | typedef struct drm_buf_info { | |
b5e89ed5 | 363 | int count; /**< Entries in list */ |
1da177e4 LT |
364 | drm_buf_desc_t __user *list; |
365 | } drm_buf_info_t; | |
366 | ||
1da177e4 LT |
367 | /** |
368 | * DRM_IOCTL_FREE_BUFS ioctl argument type. | |
369 | */ | |
370 | typedef struct drm_buf_free { | |
b5e89ed5 DA |
371 | int count; |
372 | int __user *list; | |
1da177e4 LT |
373 | } drm_buf_free_t; |
374 | ||
1da177e4 LT |
375 | /** |
376 | * Buffer information | |
377 | * | |
378 | * \sa drm_buf_map. | |
379 | */ | |
380 | typedef struct drm_buf_pub { | |
b5e89ed5 DA |
381 | int idx; /**< Index into the master buffer list */ |
382 | int total; /**< Buffer size */ | |
383 | int used; /**< Amount of buffer in use (for DMA) */ | |
384 | void __user *address; /**< Address of buffer */ | |
1da177e4 LT |
385 | } drm_buf_pub_t; |
386 | ||
1da177e4 LT |
387 | /** |
388 | * DRM_IOCTL_MAP_BUFS ioctl argument type. | |
389 | */ | |
390 | typedef struct drm_buf_map { | |
b5e89ed5 DA |
391 | int count; /**< Length of the buffer list */ |
392 | void __user *virtual; /**< Mmap'd area in user-virtual */ | |
1da177e4 LT |
393 | drm_buf_pub_t __user *list; /**< Buffer information */ |
394 | } drm_buf_map_t; | |
395 | ||
1da177e4 LT |
396 | /** |
397 | * DRM_IOCTL_DMA ioctl argument type. | |
398 | * | |
399 | * Indices here refer to the offset into the buffer list in drm_buf_get. | |
400 | * | |
401 | * \sa drmDMA(). | |
402 | */ | |
403 | typedef struct drm_dma { | |
b5e89ed5 DA |
404 | int context; /**< Context handle */ |
405 | int send_count; /**< Number of buffers to send */ | |
406 | int __user *send_indices; /**< List of handles to buffers */ | |
407 | int __user *send_sizes; /**< Lengths of data to send */ | |
1da177e4 | 408 | drm_dma_flags_t flags; /**< Flags */ |
b5e89ed5 DA |
409 | int request_count; /**< Number of buffers requested */ |
410 | int request_size; /**< Desired size for buffers */ | |
411 | int __user *request_indices; /**< Buffer information */ | |
412 | int __user *request_sizes; | |
413 | int granted_count; /**< Number of buffers granted */ | |
1da177e4 LT |
414 | } drm_dma_t; |
415 | ||
1da177e4 LT |
416 | typedef enum { |
417 | _DRM_CONTEXT_PRESERVED = 0x01, | |
b5e89ed5 | 418 | _DRM_CONTEXT_2DONLY = 0x02 |
1da177e4 LT |
419 | } drm_ctx_flags_t; |
420 | ||
1da177e4 LT |
421 | /** |
422 | * DRM_IOCTL_ADD_CTX ioctl argument type. | |
423 | * | |
424 | * \sa drmCreateContext() and drmDestroyContext(). | |
425 | */ | |
426 | typedef struct drm_ctx { | |
b5e89ed5 | 427 | drm_context_t handle; |
1da177e4 LT |
428 | drm_ctx_flags_t flags; |
429 | } drm_ctx_t; | |
430 | ||
1da177e4 LT |
431 | /** |
432 | * DRM_IOCTL_RES_CTX ioctl argument type. | |
433 | */ | |
434 | typedef struct drm_ctx_res { | |
b5e89ed5 DA |
435 | int count; |
436 | drm_ctx_t __user *contexts; | |
1da177e4 LT |
437 | } drm_ctx_res_t; |
438 | ||
1da177e4 LT |
439 | /** |
440 | * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. | |
441 | */ | |
442 | typedef struct drm_draw { | |
b5e89ed5 | 443 | drm_drawable_t handle; |
1da177e4 LT |
444 | } drm_draw_t; |
445 | ||
1da177e4 LT |
446 | /** |
447 | * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. | |
448 | */ | |
449 | typedef struct drm_auth { | |
b5e89ed5 | 450 | drm_magic_t magic; |
1da177e4 LT |
451 | } drm_auth_t; |
452 | ||
1da177e4 LT |
453 | /** |
454 | * DRM_IOCTL_IRQ_BUSID ioctl argument type. | |
455 | * | |
456 | * \sa drmGetInterruptFromBusID(). | |
457 | */ | |
458 | typedef struct drm_irq_busid { | |
459 | int irq; /**< IRQ number */ | |
460 | int busnum; /**< bus number */ | |
461 | int devnum; /**< device number */ | |
462 | int funcnum; /**< function number */ | |
463 | } drm_irq_busid_t; | |
464 | ||
1da177e4 | 465 | typedef enum { |
b5e89ed5 DA |
466 | _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ |
467 | _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ | |
776c9443 | 468 | _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ |
b5e89ed5 | 469 | _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ |
1da177e4 LT |
470 | } drm_vblank_seq_type_t; |
471 | ||
776c9443 MCA |
472 | #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) |
473 | #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY) | |
1da177e4 | 474 | |
1da177e4 LT |
475 | struct drm_wait_vblank_request { |
476 | drm_vblank_seq_type_t type; | |
477 | unsigned int sequence; | |
478 | unsigned long signal; | |
479 | }; | |
480 | ||
1da177e4 LT |
481 | struct drm_wait_vblank_reply { |
482 | drm_vblank_seq_type_t type; | |
483 | unsigned int sequence; | |
484 | long tval_sec; | |
485 | long tval_usec; | |
486 | }; | |
487 | ||
1da177e4 LT |
488 | /** |
489 | * DRM_IOCTL_WAIT_VBLANK ioctl argument type. | |
490 | * | |
491 | * \sa drmWaitVBlank(). | |
492 | */ | |
493 | typedef union drm_wait_vblank { | |
494 | struct drm_wait_vblank_request request; | |
495 | struct drm_wait_vblank_reply reply; | |
496 | } drm_wait_vblank_t; | |
497 | ||
1da177e4 LT |
498 | /** |
499 | * DRM_IOCTL_AGP_ENABLE ioctl argument type. | |
500 | * | |
501 | * \sa drmAgpEnable(). | |
502 | */ | |
503 | typedef struct drm_agp_mode { | |
504 | unsigned long mode; /**< AGP mode */ | |
505 | } drm_agp_mode_t; | |
506 | ||
1da177e4 LT |
507 | /** |
508 | * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. | |
509 | * | |
510 | * \sa drmAgpAlloc() and drmAgpFree(). | |
511 | */ | |
512 | typedef struct drm_agp_buffer { | |
513 | unsigned long size; /**< In bytes -- will round to page boundary */ | |
514 | unsigned long handle; /**< Used for binding / unbinding */ | |
b5e89ed5 DA |
515 | unsigned long type; /**< Type of memory to allocate */ |
516 | unsigned long physical; /**< Physical used by i810 */ | |
1da177e4 LT |
517 | } drm_agp_buffer_t; |
518 | ||
1da177e4 LT |
519 | /** |
520 | * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. | |
521 | * | |
522 | * \sa drmAgpBind() and drmAgpUnbind(). | |
523 | */ | |
524 | typedef struct drm_agp_binding { | |
b5e89ed5 | 525 | unsigned long handle; /**< From drm_agp_buffer */ |
1da177e4 LT |
526 | unsigned long offset; /**< In bytes -- will round to page boundary */ |
527 | } drm_agp_binding_t; | |
528 | ||
1da177e4 LT |
529 | /** |
530 | * DRM_IOCTL_AGP_INFO ioctl argument type. | |
531 | * | |
532 | * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), | |
533 | * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), | |
534 | * drmAgpVendorId() and drmAgpDeviceId(). | |
535 | */ | |
536 | typedef struct drm_agp_info { | |
b5e89ed5 DA |
537 | int agp_version_major; |
538 | int agp_version_minor; | |
539 | unsigned long mode; | |
540 | unsigned long aperture_base; /* physical address */ | |
541 | unsigned long aperture_size; /* bytes */ | |
542 | unsigned long memory_allowed; /* bytes */ | |
543 | unsigned long memory_used; | |
544 | ||
545 | /* PCI information */ | |
1da177e4 LT |
546 | unsigned short id_vendor; |
547 | unsigned short id_device; | |
548 | } drm_agp_info_t; | |
549 | ||
1da177e4 LT |
550 | /** |
551 | * DRM_IOCTL_SG_ALLOC ioctl argument type. | |
552 | */ | |
553 | typedef struct drm_scatter_gather { | |
554 | unsigned long size; /**< In bytes -- will round to page boundary */ | |
555 | unsigned long handle; /**< Used for mapping / unmapping */ | |
556 | } drm_scatter_gather_t; | |
557 | ||
558 | /** | |
559 | * DRM_IOCTL_SET_VERSION ioctl argument type. | |
560 | */ | |
561 | typedef struct drm_set_version { | |
562 | int drm_di_major; | |
563 | int drm_di_minor; | |
564 | int drm_dd_major; | |
565 | int drm_dd_minor; | |
566 | } drm_set_version_t; | |
567 | ||
1da177e4 LT |
568 | #define DRM_IOCTL_BASE 'd' |
569 | #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) | |
570 | #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) | |
571 | #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) | |
572 | #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) | |
573 | ||
574 | #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) | |
575 | #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) | |
576 | #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) | |
577 | #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) | |
578 | #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) | |
579 | #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) | |
580 | #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) | |
581 | #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) | |
582 | ||
583 | #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) | |
584 | #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) | |
585 | #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) | |
586 | #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) | |
587 | #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) | |
588 | #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) | |
589 | #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) | |
590 | #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) | |
591 | #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) | |
592 | #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) | |
593 | #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) | |
594 | ||
595 | #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) | |
596 | ||
597 | #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) | |
598 | #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) | |
599 | ||
600 | #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) | |
601 | #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) | |
602 | #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) | |
603 | #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) | |
604 | #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) | |
605 | #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) | |
606 | #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) | |
607 | #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) | |
608 | #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) | |
609 | #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) | |
610 | #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) | |
611 | #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) | |
612 | #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) | |
613 | ||
614 | #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) | |
615 | #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) | |
616 | #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) | |
617 | #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) | |
618 | #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) | |
619 | #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) | |
620 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) | |
621 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) | |
622 | ||
623 | #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) | |
624 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) | |
625 | ||
626 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) | |
627 | ||
628 | /** | |
629 | * Device specific ioctls should only be in their respective headers | |
630 | * The device specific ioctl range is from 0x40 to 0x79. | |
631 | * | |
632 | * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and | |
633 | * drmCommandReadWrite(). | |
634 | */ | |
635 | #define DRM_COMMAND_BASE 0x40 | |
636 | ||
637 | #endif |