[deliverable/linux.git] / drivers / char / drm / i830_drv.h

/* i830_drv.h -- Private header for the I830 driver -*- linux-c -*-
 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
 * 	    Jeff Hartmann <jhartmann@valinux.com>
 *
 */

#ifndef _I830_DRV_H_
#define _I830_DRV_H_

/* General customization:
 */

#define DRIVER_AUTHOR		"VA Linux Systems Inc."

#define DRIVER_NAME		"i830"
#define DRIVER_DESC		"Intel 830M"
#define DRIVER_DATE		"20021108"

/* Interface history:
 *
 * 1.1: Original.
 * 1.2: ?
 * 1.3: New irq emit/wait ioctls.
 *      New pageflip ioctl.
 *      New getparam ioctl.
 *      State for texunits 3&4 in sarea.
 *      New (alternative) layout for texture state.
 */
#define DRIVER_MAJOR		1
#define DRIVER_MINOR		3
#define DRIVER_PATCHLEVEL	2

/* Driver will work either way: IRQ's save cpu time when waiting for
 * the card, but are subject to subtle interactions between bios,
 * hardware and the driver.
 */
/* XXX: Add vblank support? */
#define USE_IRQS 0

typedef struct drm_i830_buf_priv {
   	u32 *in_use;
   	int my_use_idx;
	int currently_mapped;
	void __user *virtual;
	void *kernel_virtual;
} drm_i830_buf_priv_t;

typedef struct _drm_i830_ring_buffer{
	int tail_mask;
	unsigned long Start;
	unsigned long End;
	unsigned long Size;
	u8 *virtual_start;
	int head;
	int tail;
	int space;
} drm_i830_ring_buffer_t;

typedef struct drm_i830_private {
	drm_map_t *sarea_map;
	drm_map_t *mmio_map;

	drm_i830_sarea_t *sarea_priv;
   	drm_i830_ring_buffer_t ring;

      	void * hw_status_page;
   	unsigned long counter;

	dma_addr_t dma_status_page;

	drm_buf_t *mmap_buffer;
	
	u32 front_di1, back_di1, zi1;
	
	int back_offset;
	int depth_offset;
	int front_offset;
	int w, h;
	int pitch;
	int back_pitch;
	int depth_pitch;
	unsigned int cpp;

	int do_boxes;
	int dma_used;

	int current_page;
	int page_flipping;

	wait_queue_head_t irq_queue;
   	atomic_t irq_received;
   	atomic_t irq_emitted;

	int use_mi_batchbuffer_start;

} drm_i830_private_t;

/* i830_dma.c */
extern void i830_reclaim_buffers(drm_device_t *dev, struct file *filp);

/* i830_irq.c */
extern int i830_irq_emit( struct inode *inode, struct file *filp, 
			  unsigned int cmd, unsigned long arg );
extern int i830_irq_wait( struct inode *inode, struct file *filp,
			  unsigned int cmd, unsigned long arg );

extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS );
extern void i830_driver_irq_preinstall( drm_device_t *dev );
extern void i830_driver_irq_postinstall( drm_device_t *dev );
extern void i830_driver_irq_uninstall( drm_device_t *dev );
extern void i830_driver_pretakedown(drm_device_t *dev);
extern void i830_driver_release(drm_device_t *dev, struct file *filp);
extern int i830_driver_dma_quiescent(drm_device_t *dev);
extern void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp);
extern int i830_driver_device_is_agp(drm_device_t * dev);

#define I830_BASE(reg)		((unsigned long) \
				dev_priv->mmio_map->handle)
#define I830_ADDR(reg)		(I830_BASE(reg) + reg)
#define I830_DEREF(reg)		*(__volatile__ unsigned int *)I830_ADDR(reg)
#define I830_READ(reg)		readl((volatile u32 *)I830_ADDR(reg))
#define I830_WRITE(reg,val) 	writel(val, (volatile u32 *)I830_ADDR(reg))
#define I830_DEREF16(reg)	*(__volatile__ u16 *)I830_ADDR(reg)
#define I830_READ16(reg) 	I830_DEREF16(reg)
#define I830_WRITE16(reg,val)	do { I830_DEREF16(reg) = val; } while (0)


#define I830_VERBOSE 0

#define RING_LOCALS	unsigned int outring, ringmask, outcount; \
                        volatile char *virt;

#define BEGIN_LP_RING(n) do {				\
	if (I830_VERBOSE)				\
		printk("BEGIN_LP_RING(%d) in %s\n",	\
			  n, __FUNCTION__);		\
	if (dev_priv->ring.space < n*4)			\
		i830_wait_ring(dev, n*4, __FUNCTION__);		\
	outcount = 0;					\
	outring = dev_priv->ring.tail;			\
	ringmask = dev_priv->ring.tail_mask;		\
	virt = dev_priv->ring.virtual_start;		\
} while (0)


#define OUT_RING(n) do {					\
	if (I830_VERBOSE) printk("   OUT_RING %x\n", (int)(n));	\
	*(volatile unsigned int *)(virt + outring) = n;		\
        outcount++;						\
	outring += 4;						\
	outring &= ringmask;					\
} while (0)

#define ADVANCE_LP_RING() do {						\
	if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring);	\
	dev_priv->ring.tail = outring;					\
	dev_priv->ring.space -= outcount * 4;				\
	I830_WRITE(LP_RING + RING_TAIL, outring);			\
} while(0)

extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller);


#define GFX_OP_USER_INTERRUPT 		((0<<29)|(2<<23))
#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
#define CMD_REPORT_HEAD			(7<<23)
#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)

#define STATE3D_LOAD_STATE_IMMEDIATE_2      ((0x3<<29)|(0x1d<<24)|(0x03<<16))
#define LOAD_TEXTURE_MAP0                   (1<<11)

#define INST_PARSER_CLIENT   0x00000000
#define INST_OP_FLUSH        0x02000000
#define INST_FLUSH_MAP_CACHE 0x00000001


#define BB1_START_ADDR_MASK   (~0x7)
#define BB1_PROTECTED         (1<<0)
#define BB1_UNPROTECTED       (0<<0)
#define BB2_END_ADDR_MASK     (~0x7)

#define I830REG_HWSTAM		0x02098
#define I830REG_INT_IDENTITY_R	0x020a4
#define I830REG_INT_MASK_R 	0x020a8
#define I830REG_INT_ENABLE_R	0x020a0

#define I830_IRQ_RESERVED ((1<<13)|(3<<2))


#define LP_RING     		0x2030
#define HP_RING     		0x2040
#define RING_TAIL      		0x00
#define TAIL_ADDR		0x001FFFF8
#define RING_HEAD      		0x04
#define HEAD_WRAP_COUNT     	0xFFE00000
#define HEAD_WRAP_ONE       	0x00200000
#define HEAD_ADDR           	0x001FFFFC
#define RING_START     		0x08
#define START_ADDR          	0x0xFFFFF000
#define RING_LEN       		0x0C
#define RING_NR_PAGES       	0x001FF000 
#define RING_REPORT_MASK    	0x00000006
#define RING_REPORT_64K     	0x00000002
#define RING_REPORT_128K    	0x00000004
#define RING_NO_REPORT      	0x00000000
#define RING_VALID_MASK     	0x00000001
#define RING_VALID          	0x00000001
#define RING_INVALID        	0x00000000

#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define SC_UPDATE_SCISSOR       (0x1<<1)
#define SC_ENABLE_MASK          (0x1<<0)
#define SC_ENABLE               (0x1<<0)

#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
#define SCI_YMIN_MASK      (0xffff<<16)
#define SCI_XMIN_MASK      (0xffff<<0)
#define SCI_YMAX_MASK      (0xffff<<16)
#define SCI_XMAX_MASK      (0xffff<<0)

#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_PRIMITIVE         ((0x3<<29)|(0x1f<<24))

#define CMD_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
#define ASYNC_FLIP                (1<<22)

#define CMD_3D                          (0x3<<29)
#define STATE3D_CONST_BLEND_COLOR_CMD   (CMD_3D|(0x1d<<24)|(0x88<<16))
#define STATE3D_MAP_COORD_SETBIND_CMD   (CMD_3D|(0x1d<<24)|(0x02<<16))

#define BR00_BITBLT_CLIENT   0x40000000
#define BR00_OP_COLOR_BLT    0x10000000
#define BR00_OP_SRC_COPY_BLT 0x10C00000
#define BR13_SOLID_PATTERN   0x80000000

#define BUF_3D_ID_COLOR_BACK    (0x3<<24)
#define BUF_3D_ID_DEPTH         (0x7<<24)
#define BUF_3D_USE_FENCE        (1<<23)
#define BUF_3D_PITCH(x)         (((x)/4)<<2)

#define CMD_OP_MAP_PALETTE_LOAD	((3<<29)|(0x1d<<24)|(0x82<<16)|255)
#define MAP_PALETTE_NUM(x)	((x<<8) & (1<<8))
#define MAP_PALETTE_BOTH	(1<<11)

#define XY_COLOR_BLT_CMD		((2<<29)|(0x50<<22)|0x4)
#define XY_COLOR_BLT_WRITE_ALPHA	(1<<21)
#define XY_COLOR_BLT_WRITE_RGB		(1<<20)

#define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
#define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
#define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)

#define MI_BATCH_BUFFER 	((0x30<<23)|1)
#define MI_BATCH_BUFFER_START 	(0x31<<23)
#define MI_BATCH_BUFFER_END 	(0xA<<23)
#define MI_BATCH_NON_SECURE	(1)

#define MI_WAIT_FOR_EVENT       ((0x3<<23))
#define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2) 
#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 

#define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))

#endif
Commit	Line	Data
1da177e4 LT	1	/* i830_drv.h -- Private header for the I830 driver -- linux-c --
	2	* Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
	3	*
	4	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
	5	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
	6	* All rights reserved.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice (including the next
	16	* paragraph) shall be included in all copies or substantial portions of the
	17	* Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	23	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	24	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	25	* DEALINGS IN THE SOFTWARE.
	26	*
	27	* Authors: Rickard E. (Rik) Faith <faith@valinux.com>
	28	* Jeff Hartmann <jhartmann@valinux.com>
	29	*
	30	*/
	31
	32	#ifndef _I830_DRV_H_
	33	#define _I830_DRV_H_
	34
	35	/* General customization:
	36	*/
	37
	38	#define DRIVER_AUTHOR "VA Linux Systems Inc."
	39
	40	#define DRIVER_NAME "i830"
	41	#define DRIVER_DESC "Intel 830M"
	42	#define DRIVER_DATE "20021108"
	43
	44	/* Interface history:
	45	*
	46	* 1.1: Original.
	47	* 1.2: ?
	48	* 1.3: New irq emit/wait ioctls.
	49	* New pageflip ioctl.
	50	* New getparam ioctl.
	51	* State for texunits 3&4 in sarea.
	52	* New (alternative) layout for texture state.
	53	*/
	54	#define DRIVER_MAJOR 1
	55	#define DRIVER_MINOR 3
	56	#define DRIVER_PATCHLEVEL 2
	57
	58	/* Driver will work either way: IRQ's save cpu time when waiting for
	59	* the card, but are subject to subtle interactions between bios,
	60	* hardware and the driver.
	61	*/
	62	/* XXX: Add vblank support? */
	63	#define USE_IRQS 0
	64
65	typedef struct drm_i830_buf_priv {
66	u32 *in_use;
67	int my_use_idx;
68	int currently_mapped;
69	void __user *virtual;
70	void *kernel_virtual;
71	} drm_i830_buf_priv_t;
72
73	typedef struct _drm_i830_ring_buffer{
74	int tail_mask;
75	unsigned long Start;
76	unsigned long End;
77	unsigned long Size;
78	u8 *virtual_start;
79	int head;
80	int tail;
81	int space;
82	} drm_i830_ring_buffer_t;
83
84	typedef struct drm_i830_private {
85	drm_map_t *sarea_map;
86	drm_map_t *mmio_map;
87
88	drm_i830_sarea_t *sarea_priv;
89	drm_i830_ring_buffer_t ring;
90
91	void * hw_status_page;
92	unsigned long counter;
93
94	dma_addr_t dma_status_page;
95
96	drm_buf_t *mmap_buffer;
97
98	u32 front_di1, back_di1, zi1;
99
100	int back_offset;
101	int depth_offset;
102	int front_offset;
103	int w, h;
104	int pitch;
105	int back_pitch;
106	int depth_pitch;
107	unsigned int cpp;
108
109	int do_boxes;
110	int dma_used;
111
112	int current_page;
113	int page_flipping;
114
115	wait_queue_head_t irq_queue;
116	atomic_t irq_received;
117	atomic_t irq_emitted;
118
119	int use_mi_batchbuffer_start;
120
121	} drm_i830_private_t;
122
123	/* i830_dma.c */
124	extern void i830_reclaim_buffers(drm_device_t dev, struct file filp);
125
1da177e4 LT	126	/* i830_irq.c */
	127	extern int i830_irq_emit( struct inode inode, struct file filp,
	128	unsigned int cmd, unsigned long arg );
	129	extern int i830_irq_wait( struct inode inode, struct file filp,
	130	unsigned int cmd, unsigned long arg );
	131
	132	extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS );
	133	extern void i830_driver_irq_preinstall( drm_device_t *dev );
	134	extern void i830_driver_irq_postinstall( drm_device_t *dev );
	135	extern void i830_driver_irq_uninstall( drm_device_t *dev );
	136	extern void i830_driver_pretakedown(drm_device_t *dev);
	137	extern void i830_driver_release(drm_device_t dev, struct file filp);
	138	extern int i830_driver_dma_quiescent(drm_device_t *dev);
	139	extern void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp);
cda17380	140	extern int i830_driver_device_is_agp(drm_device_t * dev);
1da177e4 LT	141
	142	#define I830_BASE(reg) ((unsigned long) \
	143	dev_priv->mmio_map->handle)
	144	#define I830_ADDR(reg) (I830_BASE(reg) + reg)
	145	#define I830_DEREF(reg) (__volatile__ unsigned int )I830_ADDR(reg)
	146	#define I830_READ(reg) readl((volatile u32 *)I830_ADDR(reg))
	147	#define I830_WRITE(reg,val) writel(val, (volatile u32 *)I830_ADDR(reg))
	148	#define I830_DEREF16(reg) (__volatile__ u16 )I830_ADDR(reg)
	149	#define I830_READ16(reg) I830_DEREF16(reg)
	150	#define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0)
	151
	152
	153
	154	#define I830_VERBOSE 0
	155
	156	#define RING_LOCALS unsigned int outring, ringmask, outcount; \
	157	volatile char *virt;
	158
	159	#define BEGIN_LP_RING(n) do { \
	160	if (I830_VERBOSE) \
	161	printk("BEGIN_LP_RING(%d) in %s\n", \
	162	n, __FUNCTION__); \
	163	if (dev_priv->ring.space < n*4) \
	164	i830_wait_ring(dev, n*4, __FUNCTION__); \
	165	outcount = 0; \
	166	outring = dev_priv->ring.tail; \
	167	ringmask = dev_priv->ring.tail_mask; \
	168	virt = dev_priv->ring.virtual_start; \
	169	} while (0)
	170
	171
	172	#define OUT_RING(n) do { \
	173	if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \
	174	(volatile unsigned int )(virt + outring) = n; \
	175	outcount++; \
	176	outring += 4; \
	177	outring &= ringmask; \
	178	} while (0)
	179
	180	#define ADVANCE_LP_RING() do { \
	181	if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring); \
	182	dev_priv->ring.tail = outring; \
	183	dev_priv->ring.space -= outcount * 4; \
	184	I830_WRITE(LP_RING + RING_TAIL, outring); \
	185	} while(0)
	186
	187	extern int i830_wait_ring(drm_device_t dev, int n, const char caller);
	188
	189
	190	#define GFX_OP_USER_INTERRUPT ((0<<29)\|(2<<23))
	191	#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)\|(1<<23))
	192	#define CMD_REPORT_HEAD (7<<23)
	193	#define CMD_STORE_DWORD_IDX ((0x21<<23) \| 0x1)
	194	#define CMD_OP_BATCH_BUFFER ((0x0<<29)\|(0x30<<23)\|0x1)
	195
	196	#define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)\|(0x1d<<24)\|(0x03<<16))
	197	#define LOAD_TEXTURE_MAP0 (1<<11)
	198
	199	#define INST_PARSER_CLIENT 0x00000000
	200	#define INST_OP_FLUSH 0x02000000
	201	#define INST_FLUSH_MAP_CACHE 0x00000001
	202
	203
	204	#define BB1_START_ADDR_MASK (~0x7)
205	#define BB1_PROTECTED (1<<0)
206	#define BB1_UNPROTECTED (0<<0)
207	#define BB2_END_ADDR_MASK (~0x7)
208
209	#define I830REG_HWSTAM 0x02098
210	#define I830REG_INT_IDENTITY_R 0x020a4
211	#define I830REG_INT_MASK_R 0x020a8
212	#define I830REG_INT_ENABLE_R 0x020a0
213
214	#define I830_IRQ_RESERVED ((1<<13)\|(3<<2))
215
216
217	#define LP_RING 0x2030
218	#define HP_RING 0x2040
219	#define RING_TAIL 0x00
220	#define TAIL_ADDR 0x001FFFF8
221	#define RING_HEAD 0x04
222	#define HEAD_WRAP_COUNT 0xFFE00000
223	#define HEAD_WRAP_ONE 0x00200000
224	#define HEAD_ADDR 0x001FFFFC
225	#define RING_START 0x08
226	#define START_ADDR 0x0xFFFFF000
227	#define RING_LEN 0x0C
228	#define RING_NR_PAGES 0x001FF000
229	#define RING_REPORT_MASK 0x00000006
230	#define RING_REPORT_64K 0x00000002
231	#define RING_REPORT_128K 0x00000004
232	#define RING_NO_REPORT 0x00000000
233	#define RING_VALID_MASK 0x00000001
234	#define RING_VALID 0x00000001
235	#define RING_INVALID 0x00000000
236
237	#define GFX_OP_SCISSOR ((0x3<<29)\|(0x1c<<24)\|(0x10<<19))
238	#define SC_UPDATE_SCISSOR (0x1<<1)
239	#define SC_ENABLE_MASK (0x1<<0)
240	#define SC_ENABLE (0x1<<0)
241
242	#define GFX_OP_SCISSOR_INFO ((0x3<<29)\|(0x1d<<24)\|(0x81<<16)\|(0x1))
243	#define SCI_YMIN_MASK (0xffff<<16)
244	#define SCI_XMIN_MASK (0xffff<<0)
245	#define SCI_YMAX_MASK (0xffff<<16)
246	#define SCI_XMAX_MASK (0xffff<<0)
247
248	#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)\|(0x1c<<24)\|(0x10<<19))
249	#define GFX_OP_SCISSOR_RECT ((0x3<<29)\|(0x1d<<24)\|(0x81<<16)\|1)
250	#define GFX_OP_COLOR_FACTOR ((0x3<<29)\|(0x1d<<24)\|(0x1<<16)\|0x0)
251	#define GFX_OP_STIPPLE ((0x3<<29)\|(0x1d<<24)\|(0x83<<16))
252	#define GFX_OP_MAP_INFO ((0x3<<29)\|(0x1d<<24)\|0x4)
253	#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)\|(0x1d<<24)\|(0x85<<16)\|0x0)
254	#define GFX_OP_DRAWRECT_INFO ((0x3<<29)\|(0x1d<<24)\|(0x80<<16)\|(0x3))
255	#define GFX_OP_PRIMITIVE ((0x3<<29)\|(0x1f<<24))
256
257	#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)\|(0x1d<<24)\|(0x8e<<16)\|1)
258
259	#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)\|(0x14<<23)\|2)
260	#define ASYNC_FLIP (1<<22)
261
262	#define CMD_3D (0x3<<29)
263	#define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D\|(0x1d<<24)\|(0x88<<16))
264	#define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D\|(0x1d<<24)\|(0x02<<16))
265
266	#define BR00_BITBLT_CLIENT 0x40000000
267	#define BR00_OP_COLOR_BLT 0x10000000
268	#define BR00_OP_SRC_COPY_BLT 0x10C00000
269	#define BR13_SOLID_PATTERN 0x80000000
270
271	#define BUF_3D_ID_COLOR_BACK (0x3<<24)
272	#define BUF_3D_ID_DEPTH (0x7<<24)
273	#define BUF_3D_USE_FENCE (1<<23)
274	#define BUF_3D_PITCH(x) (((x)/4)<<2)
275
276	#define CMD_OP_MAP_PALETTE_LOAD ((3<<29)\|(0x1d<<24)\|(0x82<<16)\|255)
277	#define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8))
278	#define MAP_PALETTE_BOTH (1<<11)
279
280	#define XY_COLOR_BLT_CMD ((2<<29)\|(0x50<<22)\|0x4)
281	#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
282	#define XY_COLOR_BLT_WRITE_RGB (1<<20)
283
284	#define XY_SRC_COPY_BLT_CMD ((2<<29)\|(0x53<<22)\|6)
285	#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
286	#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
287
288	#define MI_BATCH_BUFFER ((0x30<<23)\|1)
289	#define MI_BATCH_BUFFER_START (0x31<<23)
290	#define MI_BATCH_BUFFER_END (0xA<<23)
291	#define MI_BATCH_NON_SECURE (1)
292
293	#define MI_WAIT_FOR_EVENT ((0x3<<23))
294	#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
295	#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
296
297	#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
298
299	#endif
300