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0d6aa60b | 1 | /* |
bc54fd1a DA |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial portions | |
15 | * of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
0d6aa60b | 25 | */ |
bc54fd1a | 26 | |
1da177e4 LT |
27 | #ifndef _I915_DRM_H_ |
28 | #define _I915_DRM_H_ | |
29 | ||
30 | /* Please note that modifications to all structs defined here are | |
31 | * subject to backwards-compatibility constraints. | |
32 | */ | |
33 | ||
34 | #include "drm.h" | |
35 | ||
36 | /* Each region is a minimum of 16k, and there are at most 255 of them. | |
37 | */ | |
38 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | |
39 | * of chars for next/prev indices */ | |
40 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | |
41 | ||
42 | typedef struct _drm_i915_init { | |
43 | enum { | |
44 | I915_INIT_DMA = 0x01, | |
45 | I915_CLEANUP_DMA = 0x02, | |
46 | I915_RESUME_DMA = 0x03 | |
47 | } func; | |
48 | unsigned int mmio_offset; | |
49 | int sarea_priv_offset; | |
50 | unsigned int ring_start; | |
51 | unsigned int ring_end; | |
52 | unsigned int ring_size; | |
53 | unsigned int front_offset; | |
54 | unsigned int back_offset; | |
55 | unsigned int depth_offset; | |
56 | unsigned int w; | |
57 | unsigned int h; | |
58 | unsigned int pitch; | |
59 | unsigned int pitch_bits; | |
60 | unsigned int back_pitch; | |
61 | unsigned int depth_pitch; | |
62 | unsigned int cpp; | |
63 | unsigned int chipset; | |
64 | } drm_i915_init_t; | |
65 | ||
66 | typedef struct _drm_i915_sarea { | |
c60ce623 | 67 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
1da177e4 LT |
68 | int last_upload; /* last time texture was uploaded */ |
69 | int last_enqueue; /* last time a buffer was enqueued */ | |
70 | int last_dispatch; /* age of the most recently dispatched buffer */ | |
71 | int ctxOwner; /* last context to upload state */ | |
72 | int texAge; | |
73 | int pf_enabled; /* is pageflipping allowed? */ | |
74 | int pf_active; | |
75 | int pf_current_page; /* which buffer is being displayed? */ | |
76 | int perf_boxes; /* performance boxes to be displayed */ | |
de227f5f DA |
77 | int width, height; /* screen size in pixels */ |
78 | ||
79 | drm_handle_t front_handle; | |
80 | int front_offset; | |
81 | int front_size; | |
82 | ||
83 | drm_handle_t back_handle; | |
84 | int back_offset; | |
85 | int back_size; | |
86 | ||
87 | drm_handle_t depth_handle; | |
88 | int depth_offset; | |
89 | int depth_size; | |
90 | ||
91 | drm_handle_t tex_handle; | |
92 | int tex_offset; | |
93 | int tex_size; | |
94 | int log_tex_granularity; | |
95 | int pitch; | |
96 | int rotation; /* 0, 90, 180 or 270 */ | |
97 | int rotated_offset; | |
98 | int rotated_size; | |
99 | int rotated_pitch; | |
100 | int virtualX, virtualY; | |
c29b669c AH |
101 | |
102 | unsigned int front_tiled; | |
103 | unsigned int back_tiled; | |
104 | unsigned int depth_tiled; | |
105 | unsigned int rotated_tiled; | |
106 | unsigned int rotated2_tiled; | |
376642cf | 107 | |
ac741ab7 JB |
108 | int planeA_x; |
109 | int planeA_y; | |
110 | int planeA_w; | |
111 | int planeA_h; | |
112 | int planeB_x; | |
113 | int planeB_y; | |
114 | int planeB_w; | |
115 | int planeB_h; | |
116 | ||
117 | /* Triple buffering */ | |
118 | drm_handle_t third_handle; | |
119 | int third_offset; | |
120 | int third_size; | |
121 | unsigned int third_tiled; | |
122 | ||
123 | /* buffer object handles for the static buffers. May change | |
124 | * over the lifetime of the client, though it doesn't in our current | |
125 | * implementation. | |
126 | */ | |
127 | unsigned int front_bo_handle; | |
128 | unsigned int back_bo_handle; | |
129 | unsigned int third_bo_handle; | |
130 | unsigned int depth_bo_handle; | |
1da177e4 LT |
131 | } drm_i915_sarea_t; |
132 | ||
133 | /* Flags for perf_boxes | |
134 | */ | |
135 | #define I915_BOX_RING_EMPTY 0x1 | |
136 | #define I915_BOX_FLIP 0x2 | |
137 | #define I915_BOX_WAIT 0x4 | |
138 | #define I915_BOX_TEXTURE_LOAD 0x8 | |
139 | #define I915_BOX_LOST_CONTEXT 0x10 | |
140 | ||
141 | /* I915 specific ioctls | |
142 | * The device specific ioctl range is 0x40 to 0x79. | |
143 | */ | |
144 | #define DRM_I915_INIT 0x00 | |
145 | #define DRM_I915_FLUSH 0x01 | |
146 | #define DRM_I915_FLIP 0x02 | |
147 | #define DRM_I915_BATCHBUFFER 0x03 | |
148 | #define DRM_I915_IRQ_EMIT 0x04 | |
149 | #define DRM_I915_IRQ_WAIT 0x05 | |
150 | #define DRM_I915_GETPARAM 0x06 | |
151 | #define DRM_I915_SETPARAM 0x07 | |
152 | #define DRM_I915_ALLOC 0x08 | |
153 | #define DRM_I915_FREE 0x09 | |
154 | #define DRM_I915_INIT_HEAP 0x0a | |
155 | #define DRM_I915_CMDBUFFER 0x0b | |
de227f5f | 156 | #define DRM_I915_DESTROY_HEAP 0x0c |
702880f2 DA |
157 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
158 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | |
a6b54f3f | 159 | #define DRM_I915_VBLANK_SWAP 0x0f |
dc7a9319 | 160 | #define DRM_I915_HWS_ADDR 0x11 |
1da177e4 LT |
161 | |
162 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
163 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | |
ac741ab7 | 164 | #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) |
1da177e4 LT |
165 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) |
166 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | |
167 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | |
168 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | |
169 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | |
170 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | |
171 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | |
172 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | |
173 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | |
de227f5f | 174 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
702880f2 DA |
175 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
176 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
541f29aa | 177 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) |
1da177e4 | 178 | |
ac741ab7 JB |
179 | /* Asynchronous page flipping: |
180 | */ | |
181 | typedef struct drm_i915_flip { | |
182 | /* | |
183 | * This is really talking about planes, and we could rename it | |
184 | * except for the fact that some of the duplicated i915_drm.h files | |
185 | * out there check for HAVE_I915_FLIP and so might pick up this | |
186 | * version. | |
187 | */ | |
188 | int pipes; | |
189 | } drm_i915_flip_t; | |
190 | ||
1da177e4 LT |
191 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
192 | * on the security mechanisms provided by hardware. | |
193 | */ | |
194 | typedef struct _drm_i915_batchbuffer { | |
195 | int start; /* agp offset */ | |
196 | int used; /* nr bytes in use */ | |
197 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
198 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
199 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
c60ce623 | 200 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
1da177e4 LT |
201 | } drm_i915_batchbuffer_t; |
202 | ||
203 | /* As above, but pass a pointer to userspace buffer which can be | |
204 | * validated by the kernel prior to sending to hardware. | |
205 | */ | |
206 | typedef struct _drm_i915_cmdbuffer { | |
207 | char __user *buf; /* pointer to userspace command buffer */ | |
208 | int sz; /* nr bytes in buf */ | |
209 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
210 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
211 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
c60ce623 | 212 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
1da177e4 LT |
213 | } drm_i915_cmdbuffer_t; |
214 | ||
215 | /* Userspace can request & wait on irq's: | |
216 | */ | |
217 | typedef struct drm_i915_irq_emit { | |
218 | int __user *irq_seq; | |
219 | } drm_i915_irq_emit_t; | |
220 | ||
221 | typedef struct drm_i915_irq_wait { | |
222 | int irq_seq; | |
223 | } drm_i915_irq_wait_t; | |
224 | ||
225 | /* Ioctl to query kernel params: | |
226 | */ | |
227 | #define I915_PARAM_IRQ_ACTIVE 1 | |
228 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | |
0d6aa60b | 229 | #define I915_PARAM_LAST_DISPATCH 3 |
1da177e4 LT |
230 | |
231 | typedef struct drm_i915_getparam { | |
232 | int param; | |
233 | int __user *value; | |
234 | } drm_i915_getparam_t; | |
235 | ||
236 | /* Ioctl to set kernel params: | |
237 | */ | |
238 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
239 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | |
240 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | |
241 | ||
242 | typedef struct drm_i915_setparam { | |
243 | int param; | |
244 | int value; | |
245 | } drm_i915_setparam_t; | |
246 | ||
247 | /* A memory manager for regions of shared memory: | |
248 | */ | |
249 | #define I915_MEM_REGION_AGP 1 | |
250 | ||
251 | typedef struct drm_i915_mem_alloc { | |
252 | int region; | |
253 | int alignment; | |
254 | int size; | |
255 | int __user *region_offset; /* offset from start of fb or agp */ | |
256 | } drm_i915_mem_alloc_t; | |
257 | ||
258 | typedef struct drm_i915_mem_free { | |
259 | int region; | |
260 | int region_offset; | |
261 | } drm_i915_mem_free_t; | |
262 | ||
263 | typedef struct drm_i915_mem_init_heap { | |
264 | int region; | |
265 | int size; | |
266 | int start; | |
267 | } drm_i915_mem_init_heap_t; | |
268 | ||
de227f5f DA |
269 | /* Allow memory manager to be torn down and re-initialized (eg on |
270 | * rotate): | |
271 | */ | |
272 | typedef struct drm_i915_mem_destroy_heap { | |
273 | int region; | |
274 | } drm_i915_mem_destroy_heap_t; | |
275 | ||
702880f2 DA |
276 | /* Allow X server to configure which pipes to monitor for vblank signals |
277 | */ | |
278 | #define DRM_I915_VBLANK_PIPE_A 1 | |
279 | #define DRM_I915_VBLANK_PIPE_B 2 | |
280 | ||
281 | typedef struct drm_i915_vblank_pipe { | |
282 | int pipe; | |
283 | } drm_i915_vblank_pipe_t; | |
284 | ||
a6b54f3f MCA |
285 | /* Schedule buffer swap at given vertical blank: |
286 | */ | |
287 | typedef struct drm_i915_vblank_swap { | |
288 | drm_drawable_t drawable; | |
c60ce623 | 289 | enum drm_vblank_seq_type seqtype; |
a6b54f3f MCA |
290 | unsigned int sequence; |
291 | } drm_i915_vblank_swap_t; | |
292 | ||
dc7a9319 WZ |
293 | typedef struct drm_i915_hws_addr { |
294 | uint64_t addr; | |
295 | } drm_i915_hws_addr_t; | |
296 | ||
1da177e4 | 297 | #endif /* _I915_DRM_H_ */ |