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drm: fix MGA on non AGP systems
[deliverable/linux.git] / drivers / char / drm / mga_dma.c
CommitLineData
1da177e4
LT		 1/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
6795c985
DA		 26 */
27
28/**
29 * \file mga_dma.c
30 * DMA support for MGA G200 / G400.
31 *
32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Gareth Hughes <gareth@valinux.com>
1da177e4
LT		 36 */
37
38#include "drmP.h"
39#include "drm.h"
6795c985 40#include "drm_sarea.h"
1da177e4
LT		 41#include "mga_drm.h"
42#include "mga_drv.h"
43
44#define MGA_DEFAULT_USEC_TIMEOUT 10000
45#define MGA_FREELIST_DEBUG 0
46
47static int mga_do_cleanup_dma( drm_device_t *dev );
48
49/* ================================================================
50 * Engine control
51 */
52
53int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
54{
55 u32 status = 0;
56 int i;
57 DRM_DEBUG( "\n" );
58
59 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
60 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
61 if ( status == MGA_ENDPRDMASTS ) {
62 MGA_WRITE8( MGA_CRTC_INDEX, 0 );
63 return 0;
64 }
65 DRM_UDELAY( 1 );
66 }
67
68#if MGA_DMA_DEBUG
69 DRM_ERROR( "failed!\n" );
70 DRM_INFO( " status=0x%08x\n", status );
71#endif
72 return DRM_ERR(EBUSY);
73}
74
75static int mga_do_dma_reset( drm_mga_private_t *dev_priv )
76{
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
79
80 DRM_DEBUG( "\n" );
81
82 /* The primary DMA stream should look like new right about now.
83 */
84 primary->tail = 0;
85 primary->space = primary->size;
86 primary->last_flush = 0;
87
88 sarea_priv->last_wrap = 0;
89
90 /* FIXME: Reset counters, buffer ages etc...
91 */
92
93 /* FIXME: What else do we need to reinitialize? WARP stuff?
94 */
95
96 return 0;
97}
98
99/* ================================================================
100 * Primary DMA stream
101 */
102
103void mga_do_dma_flush( drm_mga_private_t *dev_priv )
104{
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
106 u32 head, tail;
107 u32 status = 0;
108 int i;
109 DMA_LOCALS;
110 DRM_DEBUG( "\n" );
111
112 /* We need to wait so that we can do an safe flush */
113 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
114 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
115 if ( status == MGA_ENDPRDMASTS ) break;
116 DRM_UDELAY( 1 );
117 }
118
119 if ( primary->tail == primary->last_flush ) {
120 DRM_DEBUG( " bailing out...\n" );
121 return;
122 }
123
124 tail = primary->tail + dev_priv->primary->offset;
125
126 /* We need to pad the stream between flushes, as the card
127 * actually (partially?) reads the first of these commands.
128 * See page 4-16 in the G400 manual, middle of the page or so.
129 */
130 BEGIN_DMA( 1 );
131
132 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
133 MGA_DMAPAD, 0x00000000,
134 MGA_DMAPAD, 0x00000000,
135 MGA_DMAPAD, 0x00000000 );
136
137 ADVANCE_DMA();
138
139 primary->last_flush = primary->tail;
140
141 head = MGA_READ( MGA_PRIMADDRESS );
142
143 if ( head <= tail ) {
144 primary->space = primary->size - primary->tail;
145 } else {
146 primary->space = head - tail;
147 }
148
149 DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset );
150 DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset );
151 DRM_DEBUG( " space = 0x%06x\n", primary->space );
152
153 mga_flush_write_combine();
6795c985 154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
1da177e4
LT		 155
156 DRM_DEBUG( "done.\n" );
157}
158
159void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
160{
161 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
162 u32 head, tail;
163 DMA_LOCALS;
164 DRM_DEBUG( "\n" );
165
166 BEGIN_DMA_WRAP();
167
168 DMA_BLOCK( MGA_DMAPAD, 0x00000000,
169 MGA_DMAPAD, 0x00000000,
170 MGA_DMAPAD, 0x00000000,
171 MGA_DMAPAD, 0x00000000 );
172
173 ADVANCE_DMA();
174
175 tail = primary->tail + dev_priv->primary->offset;
176
177 primary->tail = 0;
178 primary->last_flush = 0;
179 primary->last_wrap++;
180
181 head = MGA_READ( MGA_PRIMADDRESS );
182
183 if ( head == dev_priv->primary->offset ) {
184 primary->space = primary->size;
185 } else {
186 primary->space = head - dev_priv->primary->offset;
187 }
188
189 DRM_DEBUG( " head = 0x%06lx\n",
190 head - dev_priv->primary->offset );
191 DRM_DEBUG( " tail = 0x%06x\n", primary->tail );
192 DRM_DEBUG( " wrap = %d\n", primary->last_wrap );
193 DRM_DEBUG( " space = 0x%06x\n", primary->space );
194
195 mga_flush_write_combine();
6795c985 196 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
1da177e4
LT		 197
198 set_bit( 0, &primary->wrapped );
199 DRM_DEBUG( "done.\n" );
200}
201
202void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
203{
204 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
205 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 u32 head = dev_priv->primary->offset;
207 DRM_DEBUG( "\n" );
208
209 sarea_priv->last_wrap++;
210 DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap );
211
212 mga_flush_write_combine();
213 MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
214
215 clear_bit( 0, &primary->wrapped );
216 DRM_DEBUG( "done.\n" );
217}
218
219
220/* ================================================================
221 * Freelist management
222 */
223
224#define MGA_BUFFER_USED ~0
225#define MGA_BUFFER_FREE 0
226
227#if MGA_FREELIST_DEBUG
228static void mga_freelist_print( drm_device_t *dev )
229{
230 drm_mga_private_t *dev_priv = dev->dev_private;
231 drm_mga_freelist_t *entry;
232
233 DRM_INFO( "\n" );
234 DRM_INFO( "current dispatch: last=0x%x done=0x%x\n",
235 dev_priv->sarea_priv->last_dispatch,
236 (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) -
237 dev_priv->primary->offset) );
238 DRM_INFO( "current freelist:\n" );
239
240 for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
241 DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n",
242 entry, entry->buf->idx, entry->age.head,
243 entry->age.head - dev_priv->primary->offset );
244 }
245 DRM_INFO( "\n" );
246}
247#endif
248
249static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
250{
251 drm_device_dma_t *dma = dev->dma;
252 drm_buf_t *buf;
253 drm_mga_buf_priv_t *buf_priv;
254 drm_mga_freelist_t *entry;
255 int i;
256 DRM_DEBUG( "count=%d\n", dma->buf_count );
257
258 dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t),
259 DRM_MEM_DRIVER );
260 if ( dev_priv->head == NULL )
261 return DRM_ERR(ENOMEM);
262
263 memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) );
264 SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 );
265
266 for ( i = 0 ; i < dma->buf_count ; i++ ) {
267 buf = dma->buflist[i];
268 buf_priv = buf->dev_private;
269
270 entry = drm_alloc( sizeof(drm_mga_freelist_t),
271 DRM_MEM_DRIVER );
272 if ( entry == NULL )
273 return DRM_ERR(ENOMEM);
274
275 memset( entry, 0, sizeof(drm_mga_freelist_t) );
276
277 entry->next = dev_priv->head->next;
278 entry->prev = dev_priv->head;
279 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
280 entry->buf = buf;
281
282 if ( dev_priv->head->next != NULL )
283 dev_priv->head->next->prev = entry;
284 if ( entry->next == NULL )
285 dev_priv->tail = entry;
286
287 buf_priv->list_entry = entry;
288 buf_priv->discard = 0;
289 buf_priv->dispatched = 0;
290
291 dev_priv->head->next = entry;
292 }
293
294 return 0;
295}
296
297static void mga_freelist_cleanup( drm_device_t *dev )
298{
299 drm_mga_private_t *dev_priv = dev->dev_private;
300 drm_mga_freelist_t *entry;
301 drm_mga_freelist_t *next;
302 DRM_DEBUG( "\n" );
303
304 entry = dev_priv->head;
305 while ( entry ) {
306 next = entry->next;
307 drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER );
308 entry = next;
309 }
310
311 dev_priv->head = dev_priv->tail = NULL;
312}
313
314#if 0
315/* FIXME: Still needed?
316 */
317static void mga_freelist_reset( drm_device_t *dev )
318{
319 drm_device_dma_t *dma = dev->dma;
320 drm_buf_t *buf;
321 drm_mga_buf_priv_t *buf_priv;
322 int i;
323
324 for ( i = 0 ; i < dma->buf_count ; i++ ) {
325 buf = dma->buflist[i];
326 buf_priv = buf->dev_private;
327 SET_AGE( &buf_priv->list_entry->age,
328 MGA_BUFFER_FREE, 0 );
329 }
330}
331#endif
332
333static drm_buf_t *mga_freelist_get( drm_device_t *dev )
334{
335 drm_mga_private_t *dev_priv = dev->dev_private;
336 drm_mga_freelist_t *next;
337 drm_mga_freelist_t *prev;
338 drm_mga_freelist_t *tail = dev_priv->tail;
339 u32 head, wrap;
340 DRM_DEBUG( "\n" );
341
342 head = MGA_READ( MGA_PRIMADDRESS );
343 wrap = dev_priv->sarea_priv->last_wrap;
344
345 DRM_DEBUG( " tail=0x%06lx %d\n",
346 tail->age.head ?
347 tail->age.head - dev_priv->primary->offset : 0,
348 tail->age.wrap );
349 DRM_DEBUG( " head=0x%06lx %d\n",
350 head - dev_priv->primary->offset, wrap );
351
352 if ( TEST_AGE( &tail->age, head, wrap ) ) {
353 prev = dev_priv->tail->prev;
354 next = dev_priv->tail;
355 prev->next = NULL;
356 next->prev = next->next = NULL;
357 dev_priv->tail = prev;
358 SET_AGE( &next->age, MGA_BUFFER_USED, 0 );
359 return next->buf;
360 }
361
362 DRM_DEBUG( "returning NULL!\n" );
363 return NULL;
364}
365
366int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
367{
368 drm_mga_private_t *dev_priv = dev->dev_private;
369 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
370 drm_mga_freelist_t *head, *entry, *prev;
371
372 DRM_DEBUG( "age=0x%06lx wrap=%d\n",
373 buf_priv->list_entry->age.head -
374 dev_priv->primary->offset,
375 buf_priv->list_entry->age.wrap );
376
377 entry = buf_priv->list_entry;
378 head = dev_priv->head;
379
380 if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
381 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
382 prev = dev_priv->tail;
383 prev->next = entry;
384 entry->prev = prev;
385 entry->next = NULL;
386 } else {
387 prev = head->next;
388 head->next = entry;
389 prev->prev = entry;
390 entry->prev = head;
391 entry->next = prev;
392 }
393
394 return 0;
395}
396
397
398/* ================================================================
399 * DMA initialization, cleanup
400 */
401
6795c985
DA		 402
403int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
404{
405 drm_mga_private_t * dev_priv;
406
407 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
408 if (!dev_priv)
409 return DRM_ERR(ENOMEM);
410
411 dev->dev_private = (void *)dev_priv;
412 memset(dev_priv, 0, sizeof(drm_mga_private_t));
413
414 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
415 dev_priv->chipset = flags;
416
417 return 0;
418}
419
908f9c48 420#if __OS_HAS_AGP
6795c985
DA		 421/**
422 * Bootstrap the driver for AGP DMA.
423 *
424 * \todo
425 * Investigate whether there is any benifit to storing the WARP microcode in
426 * AGP memory. If not, the microcode may as well always be put in PCI
427 * memory.
428 *
429 * \todo
430 * This routine needs to set dma_bs->agp_mode to the mode actually configured
431 * in the hardware. Looking just at the Linux AGP driver code, I don't see
432 * an easy way to determine this.
433 *
434 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
435 */
436static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
437 drm_mga_dma_bootstrap_t * dma_bs)
438{
439 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private;
440 const unsigned int warp_size = mga_warp_microcode_size(dev_priv);
441 int err;
442 unsigned offset;
443 const unsigned secondary_size = dma_bs->secondary_bin_count
444 * dma_bs->secondary_bin_size;
445 const unsigned agp_size = (dma_bs->agp_size << 20);
446 drm_buf_desc_t req;
447 drm_agp_mode_t mode;
448 drm_agp_info_t info;
449
450
451 /* Acquire AGP. */
452 err = drm_agp_acquire(dev);
453 if (err) {
454 DRM_ERROR("Unable to acquire AGP\n");
455 return err;
456 }
457
458 err = drm_agp_info(dev, &info);
459 if (err) {
460 DRM_ERROR("Unable to get AGP info\n");
461 return err;
462 }
463
464 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
465 err = drm_agp_enable(dev, mode);
466 if (err) {
467 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
468 return err;
469 }
470
471
472 /* In addition to the usual AGP mode configuration, the G200 AGP cards
473 * need to have the AGP mode "manually" set.
474 */
475
476 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
477 if (mode.mode & 0x02) {
478 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
479 }
480 else {
481 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
482 }
483 }
484
485
486 /* Allocate and bind AGP memory. */
487 dev_priv->agp_pages = agp_size / PAGE_SIZE;
488 dev_priv->agp_mem = drm_alloc_agp( dev, dev_priv->agp_pages, 0 );
489 if (dev_priv->agp_mem == NULL) {
490 dev_priv->agp_pages = 0;
491 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
492 dma_bs->agp_size);
493 return DRM_ERR(ENOMEM);
494 }
495
496 err = drm_bind_agp( dev_priv->agp_mem, 0 );
497 if (err) {
498 DRM_ERROR("Unable to bind AGP memory\n");
499 return err;
500 }
501
502 offset = 0;
503 err = drm_addmap( dev, offset, warp_size,
504 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->warp );
505 if (err) {
506 DRM_ERROR("Unable to map WARP microcode\n");
507 return err;
508 }
509
510 offset += warp_size;
511 err = drm_addmap( dev, offset, dma_bs->primary_size,
512 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary );
513 if (err) {
514 DRM_ERROR("Unable to map primary DMA region\n");
515 return err;
516 }
517
518 offset += dma_bs->primary_size;
519 err = drm_addmap( dev, offset, secondary_size,
520 _DRM_AGP, 0, & dev->agp_buffer_map );
521 if (err) {
522 DRM_ERROR("Unable to map secondary DMA region\n");
523 return err;
524 }
525
526 (void) memset( &req, 0, sizeof(req) );
527 req.count = dma_bs->secondary_bin_count;
528 req.size = dma_bs->secondary_bin_size;
529 req.flags = _DRM_AGP_BUFFER;
530 req.agp_start = offset;
531
532 err = drm_addbufs_agp( dev, & req );
533 if (err) {
534 DRM_ERROR("Unable to add secondary DMA buffers\n");
535 return err;
536 }
537
538 offset += secondary_size;
539 err = drm_addmap( dev, offset, agp_size - offset,
540 _DRM_AGP, 0, & dev_priv->agp_textures );
541 if (err) {
542 DRM_ERROR("Unable to map AGP texture region\n");
543 return err;
544 }
545
546 drm_core_ioremap(dev_priv->warp, dev);
547 drm_core_ioremap(dev_priv->primary, dev);
548 drm_core_ioremap(dev->agp_buffer_map, dev);
549
550 if (!dev_priv->warp->handle ||
551 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
552 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
553 dev_priv->warp->handle, dev_priv->primary->handle,
554 dev->agp_buffer_map->handle);
555 return DRM_ERR(ENOMEM);
556 }
557
558 dev_priv->dma_access = MGA_PAGPXFER;
559 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
560
561 DRM_INFO("Initialized card for AGP DMA.\n");
562 return 0;
563}
908f9c48
DA		 564#else
565static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
566 drm_mga_dma_bootstrap_t * dma_bs)
567{
568 return -EINVAL;
569}
570#endif
6795c985
DA		 571
572/**
573 * Bootstrap the driver for PCI DMA.
574 *
575 * \todo
576 * The algorithm for decreasing the size of the primary DMA buffer could be
577 * better. The size should be rounded up to the nearest page size, then
578 * decrease the request size by a single page each pass through the loop.
579 *
580 * \todo
581 * Determine whether the maximum address passed to drm_pci_alloc is correct.
582 * The same goes for drm_addbufs_pci.
583 *
584 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
585 */
586static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
587 drm_mga_dma_bootstrap_t * dma_bs)
588{
589 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private;
590 const unsigned int warp_size = mga_warp_microcode_size(dev_priv);
591 unsigned int primary_size;
592 unsigned int bin_count;
593 int err;
594 drm_buf_desc_t req;
595
596
597 if (dev->dma == NULL) {
598 DRM_ERROR("dev->dma is NULL\n");
599 return DRM_ERR(EFAULT);
600 }
601
602 /* The proper alignment is 0x100 for this mapping */
603 err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
604 _DRM_READ_ONLY, &dev_priv->warp);
605 if (err != 0) {
606 DRM_ERROR("Unable to create mapping for WARP microcode\n");
607 return err;
608 }
609
610 /* Other than the bottom two bits being used to encode other
611 * information, there don't appear to be any restrictions on the
612 * alignment of the primary or secondary DMA buffers.
613 */
614
615 for ( primary_size = dma_bs->primary_size
616 ; primary_size != 0
617 ; primary_size >>= 1 ) {
618 /* The proper alignment for this mapping is 0x04 */
619 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
620 _DRM_READ_ONLY, &dev_priv->primary);
621 if (!err)
622 break;
623 }
624
625 if (err != 0) {
626 DRM_ERROR("Unable to allocate primary DMA region\n");
627 return DRM_ERR(ENOMEM);
628 }
629
630 if (dev_priv->primary->size != dma_bs->primary_size) {
631 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
632 dma_bs->primary_size,
633 (unsigned) dev_priv->primary->size);
634 dma_bs->primary_size = dev_priv->primary->size;
635 }
636
637 for ( bin_count = dma_bs->secondary_bin_count
638 ; bin_count > 0
639 ; bin_count-- ) {
640 (void) memset( &req, 0, sizeof(req) );
641 req.count = bin_count;
642 req.size = dma_bs->secondary_bin_size;
643
644 err = drm_addbufs_pci( dev, & req );
645 if (!err) {
646 break;
647 }
648 }
649
650 if (bin_count == 0) {
651 DRM_ERROR("Unable to add secondary DMA buffers\n");
652 return err;
653 }
654
655 if (bin_count != dma_bs->secondary_bin_count) {
656 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
657 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
658
659 dma_bs->secondary_bin_count = bin_count;
660 }
661
662 dev_priv->dma_access = 0;
663 dev_priv->wagp_enable = 0;
664
665 dma_bs->agp_mode = 0;
666
667 DRM_INFO("Initialized card for PCI DMA.\n");
668 return 0;
669}
670
671
672static int mga_do_dma_bootstrap(drm_device_t * dev,
673 drm_mga_dma_bootstrap_t * dma_bs)
674{
675 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
676 int err;
677 drm_mga_private_t * const dev_priv =
678 (drm_mga_private_t *) dev->dev_private;
679
680
681 dev_priv->used_new_dma_init = 1;
682
683 /* The first steps are the same for both PCI and AGP based DMA. Map
684 * the cards MMIO registers and map a status page.
685 */
686 err = drm_addmap( dev, dev_priv->mmio_base, dev_priv->mmio_size,
687 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio );
688 if (err) {
689 DRM_ERROR("Unable to map MMIO region\n");
690 return err;
691 }
692
693
694 err = drm_addmap( dev, 0, SAREA_MAX, _DRM_SHM,
695 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
696 & dev_priv->status );
697 if (err) {
698 DRM_ERROR("Unable to map status region\n");
699 return err;
700 }
701
702
703 /* The DMA initialization procedure is slightly different for PCI and
704 * AGP cards. AGP cards just allocate a large block of AGP memory and
705 * carve off portions of it for internal uses. The remaining memory
706 * is returned to user-mode to be used for AGP textures.
707 */
6795c985
DA		 708 if (is_agp) {
709 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
710 }
711
712 /* If we attempted to initialize the card for AGP DMA but failed,
713 * clean-up any mess that may have been created.
714 */
715
716 if (err) {
717 mga_do_cleanup_dma(dev);
718 }
719
720
721 /* Not only do we want to try and initialized PCI cards for PCI DMA,
722 * but we also try to initialized AGP cards that could not be
723 * initialized for AGP DMA. This covers the case where we have an AGP
724 * card in a system with an unsupported AGP chipset. In that case the
725 * card will be detected as AGP, but we won't be able to allocate any
726 * AGP memory, etc.
727 */
728
729 if (!is_agp || err) {
730 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
731 }
732
733
734 return err;
735}
736
737int mga_dma_bootstrap(DRM_IOCTL_ARGS)
738{
739 DRM_DEVICE;
740 drm_mga_dma_bootstrap_t bootstrap;
741 int err;
742
743
744 DRM_COPY_FROM_USER_IOCTL(bootstrap,
745 (drm_mga_dma_bootstrap_t __user *) data,
746 sizeof(bootstrap));
747
748 err = mga_do_dma_bootstrap(dev, & bootstrap);
749 if (! err) {
750 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
751 const drm_mga_private_t * const dev_priv =
752 (drm_mga_private_t *) dev->dev_private;
753
754 if (dev_priv->agp_textures != NULL) {
755 bootstrap.texture_handle = dev_priv->agp_textures->offset;
756 bootstrap.texture_size = dev_priv->agp_textures->size;
757 }
758 else {
759 bootstrap.texture_handle = 0;
760 bootstrap.texture_size = 0;
761 }
762
763 bootstrap.agp_mode = modes[ bootstrap.agp_mode & 0x07 ];
764 if (DRM_COPY_TO_USER( (void __user *) data, & bootstrap,
765 sizeof(bootstrap))) {
766 err = DRM_ERR(EFAULT);
767 }
768 }
769 else {
770 mga_do_cleanup_dma(dev);
771 }
772
773 return err;
774}
775
1da177e4
LT		 776static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
777{
778 drm_mga_private_t *dev_priv;
779 int ret;
780 DRM_DEBUG( "\n" );
781
1da177e4 782
6795c985 783 dev_priv = dev->dev_private;
1da177e4 784
6795c985 785 if (init->sgram) {
1da177e4
LT		 786 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
787 } else {
788 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
789 }
790 dev_priv->maccess = init->maccess;
791
792 dev_priv->fb_cpp = init->fb_cpp;
793 dev_priv->front_offset = init->front_offset;
794 dev_priv->front_pitch = init->front_pitch;
795 dev_priv->back_offset = init->back_offset;
796 dev_priv->back_pitch = init->back_pitch;
797
798 dev_priv->depth_cpp = init->depth_cpp;
799 dev_priv->depth_offset = init->depth_offset;
800 dev_priv->depth_pitch = init->depth_pitch;
801
802 /* FIXME: Need to support AGP textures...
803 */
804 dev_priv->texture_offset = init->texture_offset[0];
805 dev_priv->texture_size = init->texture_size[0];
806
807 DRM_GETSAREA();
808
6795c985
DA		 809 if (!dev_priv->sarea) {
810 DRM_ERROR("failed to find sarea!\n");
1da177e4
LT		 811 return DRM_ERR(EINVAL);
812 }
813
6795c985
DA		 814 if (! dev_priv->used_new_dma_init) {
815 dev_priv->status = drm_core_findmap(dev, init->status_offset);
816 if (!dev_priv->status) {
817 DRM_ERROR("failed to find status page!\n");
818 return DRM_ERR(EINVAL);
819 }
820 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
821 if (!dev_priv->mmio) {
822 DRM_ERROR("failed to find mmio region!\n");
823 return DRM_ERR(EINVAL);
824 }
825 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
826 if (!dev_priv->warp) {
827 DRM_ERROR("failed to find warp microcode region!\n");
828 return DRM_ERR(EINVAL);
829 }
830 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
831 if (!dev_priv->primary) {
832 DRM_ERROR("failed to find primary dma region!\n");
833 return DRM_ERR(EINVAL);
834 }
d1f2b55a 835 dev->agp_buffer_token = init->buffers_offset;
6795c985
DA		 836 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
837 if (!dev->agp_buffer_map) {
838 DRM_ERROR("failed to find dma buffer region!\n");
839 return DRM_ERR(EINVAL);
840 }
841
842 drm_core_ioremap(dev_priv->warp, dev);
843 drm_core_ioremap(dev_priv->primary, dev);
844 drm_core_ioremap(dev->agp_buffer_map, dev);
1da177e4
LT		 845 }
846
847 dev_priv->sarea_priv =
848 (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle +
849 init->sarea_priv_offset);
850
6795c985
DA		 851 if (!dev_priv->warp->handle ||
852 !dev_priv->primary->handle ||
853 ((dev_priv->dma_access != 0) &&
854 ((dev->agp_buffer_map == NULL) ||
855 (dev->agp_buffer_map->handle == NULL)))) {
856 DRM_ERROR("failed to ioremap agp regions!\n");
1da177e4
LT		 857 return DRM_ERR(ENOMEM);
858 }
859
6795c985
DA		 860 ret = mga_warp_install_microcode(dev_priv);
861 if (ret < 0) {
862 DRM_ERROR("failed to install WARP ucode!\n");
1da177e4
LT		 863 return ret;
864 }
865
6795c985
DA		 866 ret = mga_warp_init(dev_priv);
867 if (ret < 0) {
868 DRM_ERROR("failed to init WARP engine!\n");
1da177e4
LT		 869 return ret;
870 }
871
872 dev_priv->prim.status = (u32 *)dev_priv->status->handle;
873
874 mga_do_wait_for_idle( dev_priv );
875
876 /* Init the primary DMA registers.
877 */
878 MGA_WRITE( MGA_PRIMADDRESS,
879 dev_priv->primary->offset | MGA_DMA_GENERAL );
880#if 0
881 MGA_WRITE( MGA_PRIMPTR,
882 virt_to_bus((void *)dev_priv->prim.status) |
883 MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
884 MGA_PRIMPTREN1 ); /* DWGSYNC */
885#endif
886
887 dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
888 dev_priv->prim.end = ((u8 *)dev_priv->primary->handle
889 + dev_priv->primary->size);
890 dev_priv->prim.size = dev_priv->primary->size;
891
892 dev_priv->prim.tail = 0;
893 dev_priv->prim.space = dev_priv->prim.size;
894 dev_priv->prim.wrapped = 0;
895
896 dev_priv->prim.last_flush = 0;
897 dev_priv->prim.last_wrap = 0;
898
899 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
900
901 dev_priv->prim.status[0] = dev_priv->primary->offset;
902 dev_priv->prim.status[1] = 0;
903
904 dev_priv->sarea_priv->last_wrap = 0;
905 dev_priv->sarea_priv->last_frame.head = 0;
906 dev_priv->sarea_priv->last_frame.wrap = 0;
907
6795c985
DA		 908 if (mga_freelist_init(dev, dev_priv) < 0) {
909 DRM_ERROR("could not initialize freelist\n");
1da177e4
LT		 910 return DRM_ERR(ENOMEM);
911 }
912
1da177e4
LT		 913 return 0;
914}
915
916static int mga_do_cleanup_dma( drm_device_t *dev )
917{
6795c985
DA		 918 int err = 0;
919 DRM_DEBUG("\n");
1da177e4
LT		 920
921 /* Make sure interrupts are disabled here because the uninstall ioctl
922 * may not have been called from userspace and after dev_private
923 * is freed, it's too late.
924 */
925 if ( dev->irq_enabled ) drm_irq_uninstall(dev);
926
927 if ( dev->dev_private ) {
928 drm_mga_private_t *dev_priv = dev->dev_private;
929
6795c985
DA		 930 if ((dev_priv->warp != NULL)
931 && (dev_priv->mmio->type != _DRM_CONSISTENT))
932 drm_core_ioremapfree(dev_priv->warp, dev);
933
934 if ((dev_priv->primary != NULL)
935 && (dev_priv->primary->type != _DRM_CONSISTENT))
936 drm_core_ioremapfree(dev_priv->primary, dev);
1da177e4 937
6795c985
DA		 938 if (dev->agp_buffer_map != NULL)
939 drm_core_ioremapfree(dev->agp_buffer_map, dev);
940
941 if (dev_priv->used_new_dma_init) {
908f9c48 942#if __OS_HAS_AGP
6795c985
DA		 943 if (dev_priv->agp_mem != NULL) {
944 dev_priv->agp_textures = NULL;
945 drm_unbind_agp(dev_priv->agp_mem);
946
947 drm_free_agp(dev_priv->agp_mem, dev_priv->agp_pages);
948 dev_priv->agp_pages = 0;
949 dev_priv->agp_mem = NULL;
950 }
951
952 if ((dev->agp != NULL) && dev->agp->acquired) {
953 err = drm_agp_release(dev);
954 }
908f9c48 955#endif
6795c985 956 dev_priv->used_new_dma_init = 0;
1da177e4
LT		 957 }
958
6795c985
DA		 959 dev_priv->warp = NULL;
960 dev_priv->primary = NULL;
961 dev_priv->mmio = NULL;
962 dev_priv->status = NULL;
963 dev_priv->sarea = NULL;
964 dev_priv->sarea_priv = NULL;
965 dev->agp_buffer_map = NULL;
966
967 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
968 dev_priv->warp_pipe = 0;
969 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
970
971 if (dev_priv->head != NULL) {
972 mga_freelist_cleanup(dev);
973 }
1da177e4
LT		 974 }
975
908f9c48 976 return err;
1da177e4
LT		 977}
978
979int mga_dma_init( DRM_IOCTL_ARGS )
980{
981 DRM_DEVICE;
982 drm_mga_init_t init;
6795c985 983 int err;
1da177e4
LT		 984
985 LOCK_TEST_WITH_RETURN( dev, filp );
986
6795c985
DA		 987 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
988 sizeof(init));
1da177e4
LT		 989
990 switch ( init.func ) {
991 case MGA_INIT_DMA:
6795c985
DA		 992 err = mga_do_init_dma(dev, &init);
993 if (err) {
994 (void) mga_do_cleanup_dma(dev);
995 }
996 return err;
1da177e4
LT		 997 case MGA_CLEANUP_DMA:
998 return mga_do_cleanup_dma( dev );
999 }
1000
1001 return DRM_ERR(EINVAL);
1002}
1003
1004
1005/* ================================================================
1006 * Primary DMA stream management
1007 */
1008
1009int mga_dma_flush( DRM_IOCTL_ARGS )
1010{
1011 DRM_DEVICE;
1012 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
1013 drm_lock_t lock;
1014
1015 LOCK_TEST_WITH_RETURN( dev, filp );
1016
1017 DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) );
1018
1019 DRM_DEBUG( "%s%s%s\n",
1020 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1021 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1022 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" );
1023
1024 WRAP_WAIT_WITH_RETURN( dev_priv );
1025
1026 if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) {
1027 mga_do_dma_flush( dev_priv );
1028 }
1029
1030 if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
1031#if MGA_DMA_DEBUG
1032 int ret = mga_do_wait_for_idle( dev_priv );
1033 if ( ret < 0 )
1034 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ );
1035 return ret;
1036#else
1037 return mga_do_wait_for_idle( dev_priv );
1038#endif
1039 } else {
1040 return 0;
1041 }
1042}
1043
1044int mga_dma_reset( DRM_IOCTL_ARGS )
1045{
1046 DRM_DEVICE;
1047 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
1048
1049 LOCK_TEST_WITH_RETURN( dev, filp );
1050
1051 return mga_do_dma_reset( dev_priv );
1052}
1053
1054
1055/* ================================================================
1056 * DMA buffer management
1057 */
1058
1059static int mga_dma_get_buffers( DRMFILE filp,
1060 drm_device_t *dev, drm_dma_t *d )
1061{
1062 drm_buf_t *buf;
1063 int i;
1064
1065 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1066 buf = mga_freelist_get( dev );
1067 if ( !buf ) return DRM_ERR(EAGAIN);
1068
1069 buf->filp = filp;
1070
1071 if ( DRM_COPY_TO_USER( &d->request_indices[i],
1072 &buf->idx, sizeof(buf->idx) ) )
1073 return DRM_ERR(EFAULT);
1074 if ( DRM_COPY_TO_USER( &d->request_sizes[i],
1075 &buf->total, sizeof(buf->total) ) )
1076 return DRM_ERR(EFAULT);
1077
1078 d->granted_count++;
1079 }
1080 return 0;
1081}
1082
1083int mga_dma_buffers( DRM_IOCTL_ARGS )
1084{
1085 DRM_DEVICE;
1086 drm_device_dma_t *dma = dev->dma;
1087 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
1088 drm_dma_t __user *argp = (void __user *)data;
1089 drm_dma_t d;
1090 int ret = 0;
1091
1092 LOCK_TEST_WITH_RETURN( dev, filp );
1093
1094 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
1095
1096 /* Please don't send us buffers.
1097 */
1098 if ( d.send_count != 0 ) {
1099 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1100 DRM_CURRENTPID, d.send_count );
1101 return DRM_ERR(EINVAL);
1102 }
1103
1104 /* We'll send you buffers.
1105 */
1106 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1107 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1108 DRM_CURRENTPID, d.request_count, dma->buf_count );
1109 return DRM_ERR(EINVAL);
1110 }
1111
1112 WRAP_TEST_WITH_RETURN( dev_priv );
1113
1114 d.granted_count = 0;
1115
1116 if ( d.request_count ) {
1117 ret = mga_dma_get_buffers( filp, dev, &d );
1118 }
1119
1120 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
1121
1122 return ret;
1123}
1124
6795c985
DA		 1125/**
1126 * Called just before the module is unloaded.
1127 */
1128int mga_driver_postcleanup(drm_device_t * dev)
1129{
1130 drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1131 dev->dev_private = NULL;
1132
1133 return 0;
1134}
1135
1136/**
1137 * Called when the last opener of the device is closed.
1138 */
1139void mga_driver_pretakedown(drm_device_t * dev)
1da177e4
LT		 1140{
1141 mga_do_cleanup_dma( dev );
1142}
1143
1144int mga_driver_dma_quiescent(drm_device_t *dev)
1145{
1146 drm_mga_private_t *dev_priv = dev->dev_private;
1147 return mga_do_wait_for_idle( dev_priv );
1148}
Linux kernel - Deliverables
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