[deliverable/linux.git] / drivers / char / drm / mga_drm.h

/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jeff Hartmann <jhartmann@valinux.com>
 *    Keith Whitwell <keith@tungstengraphics.com>
 *
 * Rewritten by:
 *    Gareth Hughes <gareth@valinux.com>
 */

#ifndef __MGA_DRM_H__
#define __MGA_DRM_H__

/* WARNING: If you change any of these defines, make sure to change the
 * defines in the Xserver file (mga_sarea.h)
 */

#ifndef __MGA_SAREA_DEFINES__
#define __MGA_SAREA_DEFINES__

/* WARP pipe flags
 */
#define MGA_F			0x1		/* fog */
#define MGA_A			0x2		/* alpha */
#define MGA_S			0x4		/* specular */
#define MGA_T2			0x8		/* multitexture */

#define MGA_WARP_TGZ		0
#define MGA_WARP_TGZF		(MGA_F)
#define MGA_WARP_TGZA		(MGA_A)
#define MGA_WARP_TGZAF		(MGA_F|MGA_A)
#define MGA_WARP_TGZS		(MGA_S)
#define MGA_WARP_TGZSF		(MGA_S|MGA_F)
#define MGA_WARP_TGZSA		(MGA_S|MGA_A)
#define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
#define MGA_WARP_T2GZ		(MGA_T2)
#define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
#define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
#define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
#define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
#define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
#define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
#define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)

#define MGA_MAX_G200_PIPES	8		/* no multitex */
#define MGA_MAX_G400_PIPES	16
#define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
#define MGA_WARP_UCODE_SIZE	32768		/* in bytes */

#define MGA_CARD_TYPE_G200	1
#define MGA_CARD_TYPE_G400	2
#define MGA_CARD_TYPE_G450	3       /* not currently used */
#define MGA_CARD_TYPE_G550	4

#define MGA_FRONT		0x1
#define MGA_BACK		0x2
#define MGA_DEPTH		0x4

/* What needs to be changed for the current vertex dma buffer?
 */
#define MGA_UPLOAD_CONTEXT	0x1
#define MGA_UPLOAD_TEX0		0x2
#define MGA_UPLOAD_TEX1		0x4
#define MGA_UPLOAD_PIPE		0x8
#define MGA_UPLOAD_TEX0IMAGE	0x10 /* handled client-side */
#define MGA_UPLOAD_TEX1IMAGE	0x20 /* handled client-side */
#define MGA_UPLOAD_2D		0x40
#define MGA_WAIT_AGE		0x80 /* handled client-side */
#define MGA_UPLOAD_CLIPRECTS	0x100 /* handled client-side */
#if 0
#define MGA_DMA_FLUSH		0x200 /* set when someone gets the lock
					 quiescent */
#endif

/* 32 buffers of 64k each, total 2 meg.
 */
#define MGA_BUFFER_SIZE		(1 << 16)
#define MGA_NUM_BUFFERS		128

/* Keep these small for testing.
 */
#define MGA_NR_SAREA_CLIPRECTS	8

/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
 * regions, subject to a minimum region size of (1<<16) == 64k.
 *
 * Clients may subdivide regions internally, but when sharing between
 * clients, the region size is the minimum granularity.
 */

#define MGA_CARD_HEAP			0
#define MGA_AGP_HEAP			1
#define MGA_NR_TEX_HEAPS		2
#define MGA_NR_TEX_REGIONS		16
#define MGA_LOG_MIN_TEX_REGION_SIZE	16

#define  DRM_MGA_IDLE_RETRY          2048

#endif /* __MGA_SAREA_DEFINES__ */


/* Setup registers for 3D context
 */
typedef struct {
	unsigned int dstorg;
	unsigned int maccess;
	unsigned int plnwt;
	unsigned int dwgctl;
	unsigned int alphactrl;
	unsigned int fogcolor;
	unsigned int wflag;
	unsigned int tdualstage0;
	unsigned int tdualstage1;
	unsigned int fcol;
	unsigned int stencil;
	unsigned int stencilctl;
} drm_mga_context_regs_t;

/* Setup registers for 2D, X server
 */
typedef struct {
	unsigned int pitch;
} drm_mga_server_regs_t;

/* Setup registers for each texture unit
 */
typedef struct {
	unsigned int texctl;
	unsigned int texctl2;
	unsigned int texfilter;
	unsigned int texbordercol;
	unsigned int texorg;
	unsigned int texwidth;
	unsigned int texheight;
	unsigned int texorg1;
	unsigned int texorg2;
	unsigned int texorg3;
	unsigned int texorg4;
} drm_mga_texture_regs_t;

/* General aging mechanism
 */
typedef struct {
	unsigned int head;		/* Position of head pointer          */
	unsigned int wrap;		/* Primary DMA wrap count            */
} drm_mga_age_t;

typedef struct _drm_mga_sarea {
	/* The channel for communication of state information to the kernel
	 * on firing a vertex dma buffer.
	 */
   	drm_mga_context_regs_t context_state;
   	drm_mga_server_regs_t server_state;
   	drm_mga_texture_regs_t tex_state[2];
   	unsigned int warp_pipe;
   	unsigned int dirty;
   	unsigned int vertsize;

	/* The current cliprects, or a subset thereof.
	 */
   	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
   	unsigned int nbox;

	/* Information about the most recently used 3d drawable.  The
	 * client fills in the req_* fields, the server fills in the
	 * exported_ fields and puts the cliprects into boxes, above.
	 *
	 * The client clears the exported_drawable field before
	 * clobbering the boxes data.
	 */
        unsigned int req_drawable;	 /* the X drawable id */
	unsigned int req_draw_buffer;	 /* MGA_FRONT or MGA_BACK */

        unsigned int exported_drawable;
	unsigned int exported_index;
        unsigned int exported_stamp;
        unsigned int exported_buffers;
        unsigned int exported_nfront;
        unsigned int exported_nback;
	int exported_back_x, exported_front_x, exported_w;
	int exported_back_y, exported_front_y, exported_h;
   	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];

	/* Counters for aging textures and for client-side throttling.
	 */
	unsigned int status[4];
	unsigned int last_wrap;

	drm_mga_age_t last_frame;
        unsigned int last_enqueue;	/* last time a buffer was enqueued */
	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
	unsigned int last_quiescent;     /*  */

	/* LRU lists for texture memory in agp space and on the card.
	 */
	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
	unsigned int texAge[MGA_NR_TEX_HEAPS];

	/* Mechanism to validate card state.
	 */
   	int ctxOwner;
} drm_mga_sarea_t;


/* MGA specific ioctls
 * The device specific ioctl range is 0x40 to 0x79.
 */
#define DRM_MGA_INIT     0x00
#define DRM_MGA_FLUSH    0x01
#define DRM_MGA_RESET    0x02
#define DRM_MGA_SWAP     0x03
#define DRM_MGA_CLEAR    0x04
#define DRM_MGA_VERTEX   0x05
#define DRM_MGA_INDICES  0x06
#define DRM_MGA_ILOAD    0x07
#define DRM_MGA_BLIT     0x08
#define DRM_MGA_GETPARAM 0x09

/* 3.2:
 * ioctls for operating on fences.
 */
#define DRM_MGA_SET_FENCE      0x0a
#define DRM_MGA_WAIT_FENCE     0x0b
#define DRM_MGA_DMA_BOOTSTRAP  0x0c


#define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
#define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
#define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
#define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
#define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
#define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
#define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
#define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
#define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)

typedef struct _drm_mga_warp_index {
   	int installed;
   	unsigned long phys_addr;
   	int size;
} drm_mga_warp_index_t;

typedef struct drm_mga_init {
   	enum {
	   	MGA_INIT_DMA    = 0x01,
	       	MGA_CLEANUP_DMA = 0x02
	} func;

   	unsigned long sarea_priv_offset;

	int chipset;
   	int sgram;

	unsigned int maccess;

   	unsigned int fb_cpp;
	unsigned int front_offset, front_pitch;
   	unsigned int back_offset, back_pitch;

   	unsigned int depth_cpp;
   	unsigned int depth_offset, depth_pitch;

   	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
   	unsigned int texture_size[MGA_NR_TEX_HEAPS];

	unsigned long fb_offset;
	unsigned long mmio_offset;
	unsigned long status_offset;
	unsigned long warp_offset;
	unsigned long primary_offset;
	unsigned long buffers_offset;
} drm_mga_init_t;

typedef struct drm_mga_dma_bootstrap {
	/**
	 * \name AGP texture region
	 * 
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
	 * be filled in with the actual AGP texture settings.
	 * 
	 * \warning
	 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
	 * is zero, it means that PCI memory (most likely through the use of
	 * an IOMMU) is being used for "AGP" textures.
	 */
	/*@{*/
	unsigned long texture_handle; /**< Handle used to map AGP textures. */
	uint32_t     texture_size;    /**< Size of the AGP texture region. */
	/*@}*/


	/**
	 * Requested size of the primary DMA region.
	 * 
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	 * filled in with the actual AGP mode.  If AGP was not available
	 */
	uint32_t primary_size;


	/**
	 * Requested number of secondary DMA buffers.
	 * 
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	 * filled in with the actual number of secondary DMA buffers
	 * allocated.  Particularly when PCI DMA is used, this may be
	 * (subtantially) less than the number requested.
	 */
	uint32_t secondary_bin_count;
	
	
	/**
	 * Requested size of each secondary DMA buffer.
	 * 
	 * While the kernel \b is free to reduce
	 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
	 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
	 */
	uint32_t secondary_bin_size;


	/**
	 * Bit-wise mask of AGPSTAT2_* values.  Currently only \c AGPSTAT2_1X,
	 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported.  If this value is
	 * zero, it means that PCI DMA should be used, even if AGP is
	 * possible.
	 * 
	 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	 * filled in with the actual AGP mode.  If AGP was not available
	 * (i.e., PCI DMA was used), this value will be zero.
	 */
	uint32_t agp_mode;


	/**
	 * Desired AGP GART size, measured in megabytes.
	 */
	uint8_t agp_size;
} drm_mga_dma_bootstrap_t;

typedef struct drm_mga_clear {
	unsigned int flags;
	unsigned int clear_color;
	unsigned int clear_depth;
	unsigned int color_mask;
	unsigned int depth_mask;
} drm_mga_clear_t;

typedef struct drm_mga_vertex {
   	int idx;			/* buffer to queue */
	int used;			/* bytes in use */
	int discard;			/* client finished with buffer?  */
} drm_mga_vertex_t;

typedef struct drm_mga_indices {
   	int idx;			/* buffer to queue */
	unsigned int start;
	unsigned int end;
	int discard;			/* client finished with buffer?  */
} drm_mga_indices_t;

typedef struct drm_mga_iload {
	int idx;
	unsigned int dstorg;
	unsigned int length;
} drm_mga_iload_t;

typedef struct _drm_mga_blit {
	unsigned int planemask;
	unsigned int srcorg;
	unsigned int dstorg;
	int src_pitch, dst_pitch;
	int delta_sx, delta_sy;
	int delta_dx, delta_dy;
	int height, ydir;		/* flip image vertically */
	int source_pitch, dest_pitch;
} drm_mga_blit_t;

/* 3.1: An ioctl to get parameters that aren't available to the 3d
 * client any other way.  
 */
#define MGA_PARAM_IRQ_NR            1

/* 3.2: Query the actual card type.  The DDX only distinguishes between
 * G200 chips and non-G200 chips, which it calls G400.  It turns out that
 * there are some very sublte differences between the G4x0 chips and the G550
 * chips.  Using this parameter query, a client-side driver can detect the
 * difference between a G4x0 and a G550.
 */
#define MGA_PARAM_CARD_TYPE         2

typedef struct drm_mga_getparam {
	int param;
	void __user *value;
} drm_mga_getparam_t;

#endif
Commit	Line	Data
1da177e4 LT	1	/* mga_drm.h -- Public header for the Matrox g200/g400 driver -- linux-c --
	2	* Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
	3	*
	4	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
	5	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
	6	* All rights reserved.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice (including the next
	16	* paragraph) shall be included in all copies or substantial portions of the
	17	* Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	23	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	24	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	25	* OTHER DEALINGS IN THE SOFTWARE.
	26	*
	27	* Authors:
	28	* Jeff Hartmann <jhartmann@valinux.com>
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	*
	31	* Rewritten by:
	32	* Gareth Hughes <gareth@valinux.com>
	33	*/
	34
	35	#ifndef __MGA_DRM_H__
	36	#define __MGA_DRM_H__
	37
	38	/* WARNING: If you change any of these defines, make sure to change the
	39	* defines in the Xserver file (mga_sarea.h)
	40	*/
	41
	42	#ifndef __MGA_SAREA_DEFINES__
	43	#define __MGA_SAREA_DEFINES__
	44
	45	/* WARP pipe flags
	46	*/
	47	#define MGA_F 0x1 /* fog */
	48	#define MGA_A 0x2 /* alpha */
	49	#define MGA_S 0x4 /* specular */
	50	#define MGA_T2 0x8 /* multitexture */
	51
	52	#define MGA_WARP_TGZ 0
	53	#define MGA_WARP_TGZF (MGA_F)
	54	#define MGA_WARP_TGZA (MGA_A)
	55	#define MGA_WARP_TGZAF (MGA_F\|MGA_A)
	56	#define MGA_WARP_TGZS (MGA_S)
	57	#define MGA_WARP_TGZSF (MGA_S\|MGA_F)
	58	#define MGA_WARP_TGZSA (MGA_S\|MGA_A)
	59	#define MGA_WARP_TGZSAF (MGA_S\|MGA_F\|MGA_A)
	60	#define MGA_WARP_T2GZ (MGA_T2)
	61	#define MGA_WARP_T2GZF (MGA_T2\|MGA_F)
	62	#define MGA_WARP_T2GZA (MGA_T2\|MGA_A)
	63	#define MGA_WARP_T2GZAF (MGA_T2\|MGA_A\|MGA_F)
	64	#define MGA_WARP_T2GZS (MGA_T2\|MGA_S)
65	#define MGA_WARP_T2GZSF (MGA_T2\|MGA_S\|MGA_F)
66	#define MGA_WARP_T2GZSA (MGA_T2\|MGA_S\|MGA_A)
67	#define MGA_WARP_T2GZSAF (MGA_T2\|MGA_S\|MGA_F\|MGA_A)
68
69	#define MGA_MAX_G200_PIPES 8 /* no multitex */
70	#define MGA_MAX_G400_PIPES 16
71	#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
72	#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
73
74	#define MGA_CARD_TYPE_G200 1
75	#define MGA_CARD_TYPE_G400 2
93f453f3 DA	76	#define MGA_CARD_TYPE_G450 3 /* not currently used */
93f453f3 DA	77	#define MGA_CARD_TYPE_G550 4
1da177e4 LT	78
	79	#define MGA_FRONT 0x1
	80	#define MGA_BACK 0x2
	81	#define MGA_DEPTH 0x4
	82
	83	/* What needs to be changed for the current vertex dma buffer?
	84	*/
	85	#define MGA_UPLOAD_CONTEXT 0x1
	86	#define MGA_UPLOAD_TEX0 0x2
	87	#define MGA_UPLOAD_TEX1 0x4
	88	#define MGA_UPLOAD_PIPE 0x8
	89	#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
	90	#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
	91	#define MGA_UPLOAD_2D 0x40
	92	#define MGA_WAIT_AGE 0x80 /* handled client-side */
	93	#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
	94	#if 0
	95	#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
	96	quiescent */
	97	#endif
	98
	99	/* 32 buffers of 64k each, total 2 meg.
	100	*/
	101	#define MGA_BUFFER_SIZE (1 << 16)
	102	#define MGA_NUM_BUFFERS 128
	103
	104	/* Keep these small for testing.
	105	*/
	106	#define MGA_NR_SAREA_CLIPRECTS 8
	107
	108	/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
	109	* regions, subject to a minimum region size of (1<<16) == 64k.
	110	*
	111	* Clients may subdivide regions internally, but when sharing between
	112	* clients, the region size is the minimum granularity.
	113	*/
	114
	115	#define MGA_CARD_HEAP 0
	116	#define MGA_AGP_HEAP 1
	117	#define MGA_NR_TEX_HEAPS 2
	118	#define MGA_NR_TEX_REGIONS 16
	119	#define MGA_LOG_MIN_TEX_REGION_SIZE 16
	120
	121	#define DRM_MGA_IDLE_RETRY 2048
	122
	123	#endif /* __MGA_SAREA_DEFINES__ */
	124
	125
	126	/* Setup registers for 3D context
	127	*/
	128	typedef struct {
	129	unsigned int dstorg;
	130	unsigned int maccess;
	131	unsigned int plnwt;
	132	unsigned int dwgctl;
	133	unsigned int alphactrl;
	134	unsigned int fogcolor;
	135	unsigned int wflag;
	136	unsigned int tdualstage0;
	137	unsigned int tdualstage1;
	138	unsigned int fcol;
	139	unsigned int stencil;
	140	unsigned int stencilctl;
	141	} drm_mga_context_regs_t;
142
143	/* Setup registers for 2D, X server
144	*/
145	typedef struct {
146	unsigned int pitch;
147	} drm_mga_server_regs_t;
148
149	/* Setup registers for each texture unit
150	*/
151	typedef struct {
152	unsigned int texctl;
153	unsigned int texctl2;
154	unsigned int texfilter;
155	unsigned int texbordercol;
156	unsigned int texorg;
157	unsigned int texwidth;
158	unsigned int texheight;
159	unsigned int texorg1;
160	unsigned int texorg2;
161	unsigned int texorg3;
162	unsigned int texorg4;
163	} drm_mga_texture_regs_t;
164
165	/* General aging mechanism
166	*/
167	typedef struct {
168	unsigned int head; /* Position of head pointer */
169	unsigned int wrap; /* Primary DMA wrap count */
170	} drm_mga_age_t;
171
172	typedef struct _drm_mga_sarea {
173	/* The channel for communication of state information to the kernel
174	* on firing a vertex dma buffer.
175	*/
176	drm_mga_context_regs_t context_state;
177	drm_mga_server_regs_t server_state;
178	drm_mga_texture_regs_t tex_state[2];
179	unsigned int warp_pipe;
180	unsigned int dirty;
181	unsigned int vertsize;
182
183	/* The current cliprects, or a subset thereof.
184	*/
185	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
186	unsigned int nbox;
187
188	/* Information about the most recently used 3d drawable. The
189	* client fills in the req_* fields, the server fills in the
190	* exported_ fields and puts the cliprects into boxes, above.
191	*
192	* The client clears the exported_drawable field before
193	* clobbering the boxes data.
194	*/
195	unsigned int req_drawable; /* the X drawable id */
196	unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
197
198	unsigned int exported_drawable;
199	unsigned int exported_index;
200	unsigned int exported_stamp;
201	unsigned int exported_buffers;
202	unsigned int exported_nfront;
203	unsigned int exported_nback;
204	int exported_back_x, exported_front_x, exported_w;
205	int exported_back_y, exported_front_y, exported_h;
206	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
207
208	/* Counters for aging textures and for client-side throttling.
209	*/
210	unsigned int status[4];
211	unsigned int last_wrap;
212
213	drm_mga_age_t last_frame;
214	unsigned int last_enqueue; /* last time a buffer was enqueued */
215	unsigned int last_dispatch; /* age of the most recently dispatched buffer */
216	unsigned int last_quiescent; /* */
217
218	/* LRU lists for texture memory in agp space and on the card.
219	*/
220	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
221	unsigned int texAge[MGA_NR_TEX_HEAPS];
222
223	/* Mechanism to validate card state.
224	*/
225	int ctxOwner;
226	} drm_mga_sarea_t;
227
228
1da177e4 LT	229	/* MGA specific ioctls
	230	* The device specific ioctl range is 0x40 to 0x79.
	231	*/
	232	#define DRM_MGA_INIT 0x00
	233	#define DRM_MGA_FLUSH 0x01
	234	#define DRM_MGA_RESET 0x02
	235	#define DRM_MGA_SWAP 0x03
	236	#define DRM_MGA_CLEAR 0x04
	237	#define DRM_MGA_VERTEX 0x05
	238	#define DRM_MGA_INDICES 0x06
	239	#define DRM_MGA_ILOAD 0x07
	240	#define DRM_MGA_BLIT 0x08
	241	#define DRM_MGA_GETPARAM 0x09
	242
6795c985 DA	243	/* 3.2:
	244	* ioctls for operating on fences.
	245	*/
	246	#define DRM_MGA_SET_FENCE 0x0a
	247	#define DRM_MGA_WAIT_FENCE 0x0b
	248	#define DRM_MGA_DMA_BOOTSTRAP 0x0c
	249
	250
1da177e4 LT	251	#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
	252	#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
	253	#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
	254	#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
	255	#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
	256	#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
	257	#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
	258	#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
	259	#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
	260	#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
6795c985 DA	261	#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
	262	#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
	263	#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
1da177e4 LT	264
	265	typedef struct _drm_mga_warp_index {
	266	int installed;
	267	unsigned long phys_addr;
	268	int size;
	269	} drm_mga_warp_index_t;
	270
	271	typedef struct drm_mga_init {
	272	enum {
	273	MGA_INIT_DMA = 0x01,
	274	MGA_CLEANUP_DMA = 0x02
	275	} func;
	276
	277	unsigned long sarea_priv_offset;
	278
	279	int chipset;
	280	int sgram;
	281
	282	unsigned int maccess;
	283
	284	unsigned int fb_cpp;
	285	unsigned int front_offset, front_pitch;
	286	unsigned int back_offset, back_pitch;
	287
	288	unsigned int depth_cpp;
	289	unsigned int depth_offset, depth_pitch;
	290
	291	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
	292	unsigned int texture_size[MGA_NR_TEX_HEAPS];
	293
	294	unsigned long fb_offset;
	295	unsigned long mmio_offset;
	296	unsigned long status_offset;
	297	unsigned long warp_offset;
	298	unsigned long primary_offset;
	299	unsigned long buffers_offset;
	300	} drm_mga_init_t;
	301
6795c985 DA	302	typedef struct drm_mga_dma_bootstrap {
	303	/**
	304	* \name AGP texture region
	305	*
	306	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
	307	* be filled in with the actual AGP texture settings.
	308	*
	309	* \warning
	310	* If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
	311	* is zero, it means that PCI memory (most likely through the use of
	312	* an IOMMU) is being used for "AGP" textures.
	313	*/
	314	/@{/
d1f2b55a	315	unsigned long texture_handle; /*< Handle used to map AGP textures. /
6795c985 DA	316	uint32_t texture_size; /*< Size of the AGP texture region. /
	317	/@}/
	318
	319
	320	/**
	321	* Requested size of the primary DMA region.
	322	*
	323	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	324	* filled in with the actual AGP mode. If AGP was not available
	325	*/
	326	uint32_t primary_size;
	327
	328
	329	/**
	330	* Requested number of secondary DMA buffers.
	331	*
	332	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	333	* filled in with the actual number of secondary DMA buffers
	334	* allocated. Particularly when PCI DMA is used, this may be
	335	* (subtantially) less than the number requested.
	336	*/
	337	uint32_t secondary_bin_count;
	338
	339
	340	/**
	341	* Requested size of each secondary DMA buffer.
	342	*
	343	* While the kernel \b is free to reduce
	344	* dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
	345	* to reduce dma_mga_dma_bootstrap::secondary_bin_size.
	346	*/
	347	uint32_t secondary_bin_size;
	348
	349
	350	/**
	351	* Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
	352	* \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
	353	* zero, it means that PCI DMA should be used, even if AGP is
	354	* possible.
	355	*
	356	* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
	357	* filled in with the actual AGP mode. If AGP was not available
	358	* (i.e., PCI DMA was used), this value will be zero.
	359	*/
	360	uint32_t agp_mode;
	361
	362
	363	/**
	364	* Desired AGP GART size, measured in megabytes.
	365	*/
	366	uint8_t agp_size;
	367	} drm_mga_dma_bootstrap_t;
1da177e4 LT	368
	369	typedef struct drm_mga_clear {
	370	unsigned int flags;
	371	unsigned int clear_color;
	372	unsigned int clear_depth;
	373	unsigned int color_mask;
	374	unsigned int depth_mask;
	375	} drm_mga_clear_t;
	376
	377	typedef struct drm_mga_vertex {
	378	int idx; /* buffer to queue */
	379	int used; /* bytes in use */
	380	int discard; /* client finished with buffer? */
	381	} drm_mga_vertex_t;
	382
	383	typedef struct drm_mga_indices {
	384	int idx; /* buffer to queue */
	385	unsigned int start;
	386	unsigned int end;
	387	int discard; /* client finished with buffer? */
	388	} drm_mga_indices_t;
	389
	390	typedef struct drm_mga_iload {
	391	int idx;
	392	unsigned int dstorg;
	393	unsigned int length;
	394	} drm_mga_iload_t;
	395
	396	typedef struct _drm_mga_blit {
	397	unsigned int planemask;
	398	unsigned int srcorg;
	399	unsigned int dstorg;
	400	int src_pitch, dst_pitch;
	401	int delta_sx, delta_sy;
	402	int delta_dx, delta_dy;
	403	int height, ydir; /* flip image vertically */
	404	int source_pitch, dest_pitch;
	405	} drm_mga_blit_t;
	406
	407	/* 3.1: An ioctl to get parameters that aren't available to the 3d
	408	* client any other way.
	409	*/
	410	#define MGA_PARAM_IRQ_NR 1
	411
6795c985 DA	412	/* 3.2: Query the actual card type. The DDX only distinguishes between
	413	* G200 chips and non-G200 chips, which it calls G400. It turns out that
	414	* there are some very sublte differences between the G4x0 chips and the G550
	415	* chips. Using this parameter query, a client-side driver can detect the
	416	* difference between a G4x0 and a G550.
	417	*/
	418	#define MGA_PARAM_CARD_TYPE 2
	419
1da177e4 LT	420	typedef struct drm_mga_getparam {
	421	int param;
	422	void __user *value;
	423	} drm_mga_getparam_t;
	424
	425	#endif