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drm/radeon: init pipe setup in kernel code.
[deliverable/linux.git] / drivers / char / drm / radeon_drm.h
CommitLineData
1da177e4
LT		 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (radeon_sarea.h)
38 */
39#ifndef __RADEON_SAREA_DEFINES__
40#define __RADEON_SAREA_DEFINES__
41
42/* Old style state flags, required for sarea interface (1.1 and 1.2
43 * clears) and 1.2 drm_vertex2 ioctl.
44 */
45#define RADEON_UPLOAD_CONTEXT 0x00000001
46#define RADEON_UPLOAD_VERTFMT 0x00000002
47#define RADEON_UPLOAD_LINE 0x00000004
48#define RADEON_UPLOAD_BUMPMAP 0x00000008
49#define RADEON_UPLOAD_MASKS 0x00000010
50#define RADEON_UPLOAD_VIEWPORT 0x00000020
51#define RADEON_UPLOAD_SETUP 0x00000040
52#define RADEON_UPLOAD_TCL 0x00000080
53#define RADEON_UPLOAD_MISC 0x00000100
54#define RADEON_UPLOAD_TEX0 0x00000200
55#define RADEON_UPLOAD_TEX1 0x00000400
56#define RADEON_UPLOAD_TEX2 0x00000800
57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
b5e89ed5 60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
1da177e4 61#define RADEON_REQUIRE_QUIESCENCE 0x00010000
b5e89ed5 62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
1da177e4
LT		 63#define RADEON_UPLOAD_ALL 0x003effff
64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
65
1da177e4
LT		 66/* New style per-packet identifiers for use in cmd_buffer ioctl with
67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
68 * state bits and the packet size:
69 */
b5e89ed5
DA		 70#define RADEON_EMIT_PP_MISC 0 /* context/7 */
71#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
72#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
73#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
74#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
75#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
76#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
77#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
78#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
79#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
80#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
81#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
82#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
83#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
84#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
85#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
86#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
87#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
88#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
89#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
90#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
91#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
92#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
93#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
94#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
95#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
96#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
97#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
98#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
99#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
100#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
101#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
102#define R200_EMIT_VAP_CTL 32 /* vap/1 */
103#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
104#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
105#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
106#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
107#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
108#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
109#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
110#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
111#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
112#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
113#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
114#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
115#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
116#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
117#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
118#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
119#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
120#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
121#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
122#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
123#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
124#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
125#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
126#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
127#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
128#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
129#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
130#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
1da177e4
LT		 131#define R200_EMIT_PP_CUBIC_FACES_0 61
132#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
133#define R200_EMIT_PP_CUBIC_FACES_1 63
134#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
135#define R200_EMIT_PP_CUBIC_FACES_2 65
136#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
137#define R200_EMIT_PP_CUBIC_FACES_3 67
138#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
139#define R200_EMIT_PP_CUBIC_FACES_4 69
140#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
141#define R200_EMIT_PP_CUBIC_FACES_5 71
142#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
143#define RADEON_EMIT_PP_TEX_SIZE_0 73
144#define RADEON_EMIT_PP_TEX_SIZE_1 74
145#define RADEON_EMIT_PP_TEX_SIZE_2 75
146#define R200_EMIT_RB3D_BLENDCOLOR 76
147#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
148#define RADEON_EMIT_PP_CUBIC_FACES_0 78
149#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
150#define RADEON_EMIT_PP_CUBIC_FACES_1 80
151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
152#define RADEON_EMIT_PP_CUBIC_FACES_2 82
153#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
154#define R200_EMIT_PP_TRI_PERF_CNTL 84
9d17601c
DA		 155#define R200_EMIT_PP_AFS_0 85
156#define R200_EMIT_PP_AFS_1 86
157#define R200_EMIT_ATF_TFACTOR 87
158#define R200_EMIT_PP_TXCTLALL_0 88
159#define R200_EMIT_PP_TXCTLALL_1 89
160#define R200_EMIT_PP_TXCTLALL_2 90
161#define R200_EMIT_PP_TXCTLALL_3 91
162#define R200_EMIT_PP_TXCTLALL_4 92
163#define R200_EMIT_PP_TXCTLALL_5 93
d6fece05
DA		 164#define R200_EMIT_VAP_PVS_CNTL 94
165#define RADEON_MAX_STATE_PACKETS 95
1da177e4
LT		 166
167/* Commands understood by cmd_buffer ioctl. More can be added but
168 * obviously these can't be removed or changed:
169 */
b5e89ed5
DA		 170#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
171#define RADEON_CMD_SCALARS 2 /* emit scalar data */
172#define RADEON_CMD_VECTORS 3 /* emit vector data */
173#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
174#define RADEON_CMD_PACKET3 5 /* emit hw packet */
175#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
176#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
177#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
178 * doesn't make the cpu wait, just
179 * the graphics hardware */
d6fece05 180#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
1da177e4
LT		 181
182typedef union {
183 int i;
b5e89ed5 184 struct {
1da177e4
LT		 185 unsigned char cmd_type, pad0, pad1, pad2;
186 } header;
b5e89ed5 187 struct {
1da177e4
LT		 188 unsigned char cmd_type, packet_id, pad0, pad1;
189 } packet;
b5e89ed5
DA		 190 struct {
191 unsigned char cmd_type, offset, stride, count;
1da177e4 192 } scalars;
b5e89ed5
DA		 193 struct {
194 unsigned char cmd_type, offset, stride, count;
1da177e4 195 } vectors;
d6fece05
DA		 196 struct {
197 unsigned char cmd_type, addr_lo, addr_hi, count;
198 } veclinear;
b5e89ed5
DA		 199 struct {
200 unsigned char cmd_type, buf_idx, pad0, pad1;
1da177e4 201 } dma;
b5e89ed5
DA		 202 struct {
203 unsigned char cmd_type, flags, pad0, pad1;
1da177e4
LT		 204 } wait;
205} drm_radeon_cmd_header_t;
206
207#define RADEON_WAIT_2D 0x1
208#define RADEON_WAIT_3D 0x2
209
414ed537
DA		 210/* Allowed parameters for R300_CMD_PACKET3
211 */
212#define R300_CMD_PACKET3_CLEAR 0
213#define R300_CMD_PACKET3_RAW 1
214
215/* Commands understood by cmd_buffer ioctl for R300.
216 * The interface has not been stabilized, so some of these may be removed
217 * and eventually reordered before stabilization.
218 */
b5e89ed5
DA		 219#define R300_CMD_PACKET0 1
220#define R300_CMD_VPU 2 /* emit vertex program upload */
221#define R300_CMD_PACKET3 3 /* emit a packet3 */
222#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
414ed537
DA		 223#define R300_CMD_CP_DELAY 5
224#define R300_CMD_DMA_DISCARD 6
225#define R300_CMD_WAIT 7
bc5f4523
DA		 226# define R300_WAIT_2D 0x1
227# define R300_WAIT_3D 0x2
0c76be35
DA		 228/* these two defines are DOING IT WRONG - however
229 * we have userspace which relies on using these.
230 * The wait interface is backwards compat new
231 * code should use the NEW_WAIT defines below
232 * THESE ARE NOT BIT FIELDS
233 */
bc5f4523
DA		 234# define R300_WAIT_2D_CLEAN 0x3
235# define R300_WAIT_3D_CLEAN 0x4
0c76be35
DA		 236
237# define R300_NEW_WAIT_2D_3D 0x3
238# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
239# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
241
ee4621f0 242#define R300_CMD_SCRATCH 8
414ed537
DA		 243
244typedef union {
245 unsigned int u;
246 struct {
247 unsigned char cmd_type, pad0, pad1, pad2;
248 } header;
249 struct {
250 unsigned char cmd_type, count, reglo, reghi;
251 } packet0;
252 struct {
253 unsigned char cmd_type, count, adrlo, adrhi;
254 } vpu;
255 struct {
256 unsigned char cmd_type, packet, pad0, pad1;
257 } packet3;
258 struct {
259 unsigned char cmd_type, packet;
b5e89ed5 260 unsigned short count; /* amount of packet2 to emit */
414ed537
DA		 261 } delay;
262 struct {
263 unsigned char cmd_type, buf_idx, pad0, pad1;
264 } dma;
265 struct {
b5e89ed5 266 unsigned char cmd_type, flags, pad0, pad1;
414ed537 267 } wait;
ee4621f0
DA		 268 struct {
269 unsigned char cmd_type, reg, n_bufs, flags;
270 } scratch;
414ed537 271} drm_r300_cmd_header_t;
1da177e4
LT		 272
273#define RADEON_FRONT 0x1
274#define RADEON_BACK 0x2
275#define RADEON_DEPTH 0x4
276#define RADEON_STENCIL 0x8
277#define RADEON_CLEAR_FASTZ 0x80000000
278#define RADEON_USE_HIERZ 0x40000000
279#define RADEON_USE_COMP_ZBUF 0x20000000
280
281/* Primitive types
282 */
283#define RADEON_POINTS 0x1
284#define RADEON_LINES 0x2
285#define RADEON_LINE_STRIP 0x3
286#define RADEON_TRIANGLES 0x4
287#define RADEON_TRIANGLE_FAN 0x5
288#define RADEON_TRIANGLE_STRIP 0x6
289
290/* Vertex/indirect buffer size
291 */
292#define RADEON_BUFFER_SIZE 65536
293
294/* Byte offsets for indirect buffer data
295 */
296#define RADEON_INDEX_PRIM_OFFSET 20
297
298#define RADEON_SCRATCH_REG_OFFSET 32
299
300#define RADEON_NR_SAREA_CLIPRECTS 12
301
302/* There are 2 heaps (local/GART). Each region within a heap is a
303 * minimum of 64k, and there are at most 64 of them per heap.
304 */
305#define RADEON_LOCAL_TEX_HEAP 0
306#define RADEON_GART_TEX_HEAP 1
307#define RADEON_NR_TEX_HEAPS 2
308#define RADEON_NR_TEX_REGIONS 64
309#define RADEON_LOG_TEX_GRANULARITY 16
310
311#define RADEON_MAX_TEXTURE_LEVELS 12
312#define RADEON_MAX_TEXTURE_UNITS 3
313
314#define RADEON_MAX_SURFACES 8
315
316/* Blits have strict offset rules. All blit offset must be aligned on
317 * a 1K-byte boundary.
318 */
319#define RADEON_OFFSET_SHIFT 10
320#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
321#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
322
b5e89ed5 323#endif /* __RADEON_SAREA_DEFINES__ */
1da177e4
LT		 324
325typedef struct {
326 unsigned int red;
327 unsigned int green;
328 unsigned int blue;
329 unsigned int alpha;
330} radeon_color_regs_t;
331
332typedef struct {
333 /* Context state */
b5e89ed5 334 unsigned int pp_misc; /* 0x1c14 */
1da177e4
LT		 335 unsigned int pp_fog_color;
336 unsigned int re_solid_color;
337 unsigned int rb3d_blendcntl;
338 unsigned int rb3d_depthoffset;
339 unsigned int rb3d_depthpitch;
340 unsigned int rb3d_zstencilcntl;
341
b5e89ed5 342 unsigned int pp_cntl; /* 0x1c38 */
1da177e4
LT		 343 unsigned int rb3d_cntl;
344 unsigned int rb3d_coloroffset;
345 unsigned int re_width_height;
346 unsigned int rb3d_colorpitch;
347 unsigned int se_cntl;
348
349 /* Vertex format state */
b5e89ed5 350 unsigned int se_coord_fmt; /* 0x1c50 */
1da177e4
LT		 351
352 /* Line state */
b5e89ed5 353 unsigned int re_line_pattern; /* 0x1cd0 */
1da177e4
LT		 354 unsigned int re_line_state;
355
b5e89ed5 356 unsigned int se_line_width; /* 0x1db8 */
1da177e4
LT		 357
358 /* Bumpmap state */
b5e89ed5 359 unsigned int pp_lum_matrix; /* 0x1d00 */
1da177e4 360
b5e89ed5 361 unsigned int pp_rot_matrix_0; /* 0x1d58 */
1da177e4
LT		 362 unsigned int pp_rot_matrix_1;
363
364 /* Mask state */
b5e89ed5 365 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
1da177e4
LT		 366 unsigned int rb3d_ropcntl;
367 unsigned int rb3d_planemask;
368
369 /* Viewport state */
b5e89ed5 370 unsigned int se_vport_xscale; /* 0x1d98 */
1da177e4
LT		 371 unsigned int se_vport_xoffset;
372 unsigned int se_vport_yscale;
373 unsigned int se_vport_yoffset;
374 unsigned int se_vport_zscale;
375 unsigned int se_vport_zoffset;
376
377 /* Setup state */
b5e89ed5 378 unsigned int se_cntl_status; /* 0x2140 */
1da177e4
LT		 379
380 /* Misc state */
b5e89ed5 381 unsigned int re_top_left; /* 0x26c0 */
1da177e4
LT		 382 unsigned int re_misc;
383} drm_radeon_context_regs_t;
384
385typedef struct {
386 /* Zbias state */
b5e89ed5 387 unsigned int se_zbias_factor; /* 0x1dac */
1da177e4
LT		 388 unsigned int se_zbias_constant;
389} drm_radeon_context2_regs_t;
390
1da177e4
LT		 391/* Setup registers for each texture unit
392 */
393typedef struct {
394 unsigned int pp_txfilter;
395 unsigned int pp_txformat;
396 unsigned int pp_txoffset;
397 unsigned int pp_txcblend;
398 unsigned int pp_txablend;
399 unsigned int pp_tfactor;
400 unsigned int pp_border_color;
401} drm_radeon_texture_regs_t;
402
403typedef struct {
404 unsigned int start;
405 unsigned int finish;
406 unsigned int prim:8;
407 unsigned int stateidx:8;
b5e89ed5
DA		 408 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
409 unsigned int vc_format; /* vertex format */
1da177e4
LT		 410} drm_radeon_prim_t;
411
1da177e4
LT		 412typedef struct {
413 drm_radeon_context_regs_t context;
414 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
415 drm_radeon_context2_regs_t context2;
416 unsigned int dirty;
417} drm_radeon_state_t;
418
1da177e4
LT		 419typedef struct {
420 /* The channel for communication of state information to the
421 * kernel on firing a vertex buffer with either of the
422 * obsoleted vertex/index ioctls.
423 */
424 drm_radeon_context_regs_t context_state;
425 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
426 unsigned int dirty;
427 unsigned int vertsize;
428 unsigned int vc_format;
429
430 /* The current cliprects, or a subset thereof.
431 */
c60ce623 432 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
1da177e4
LT		 433 unsigned int nbox;
434
435 /* Counters for client-side throttling of rendering clients.
436 */
437 unsigned int last_frame;
438 unsigned int last_dispatch;
439 unsigned int last_clear;
440
c60ce623 441 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
b5e89ed5 442 1];
1da177e4
LT		 443 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
444 int ctx_owner;
b5e89ed5
DA		 445 int pfState; /* number of 3d windows (0,1,2ormore) */
446 int pfCurrentPage; /* which buffer is being displayed? */
447 int crtc2_base; /* CRTC2 frame offset */
1da177e4
LT		 448 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
449} drm_radeon_sarea_t;
450
1da177e4
LT		 451/* WARNING: If you change any of these defines, make sure to change the
452 * defines in the Xserver file (xf86drmRadeon.h)
453 *
454 * KW: actually it's illegal to change any of this (backwards compatibility).
455 */
456
457/* Radeon specific ioctls
458 * The device specific ioctl range is 0x40 to 0x79.
459 */
b5e89ed5
DA		 460#define DRM_RADEON_CP_INIT 0x00
461#define DRM_RADEON_CP_START 0x01
1da177e4
LT		 462#define DRM_RADEON_CP_STOP 0x02
463#define DRM_RADEON_CP_RESET 0x03
464#define DRM_RADEON_CP_IDLE 0x04
b5e89ed5 465#define DRM_RADEON_RESET 0x05
1da177e4 466#define DRM_RADEON_FULLSCREEN 0x06
b5e89ed5
DA		 467#define DRM_RADEON_SWAP 0x07
468#define DRM_RADEON_CLEAR 0x08
1da177e4
LT		 469#define DRM_RADEON_VERTEX 0x09
470#define DRM_RADEON_INDICES 0x0A
471#define DRM_RADEON_NOT_USED
472#define DRM_RADEON_STIPPLE 0x0C
473#define DRM_RADEON_INDIRECT 0x0D
474#define DRM_RADEON_TEXTURE 0x0E
475#define DRM_RADEON_VERTEX2 0x0F
476#define DRM_RADEON_CMDBUF 0x10
477#define DRM_RADEON_GETPARAM 0x11
478#define DRM_RADEON_FLIP 0x12
479#define DRM_RADEON_ALLOC 0x13
480#define DRM_RADEON_FREE 0x14
481#define DRM_RADEON_INIT_HEAP 0x15
482#define DRM_RADEON_IRQ_EMIT 0x16
483#define DRM_RADEON_IRQ_WAIT 0x17
484#define DRM_RADEON_CP_RESUME 0x18
485#define DRM_RADEON_SETPARAM 0x19
486#define DRM_RADEON_SURF_ALLOC 0x1a
487#define DRM_RADEON_SURF_FREE 0x1b
488
489#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
490#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
491#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
492#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
493#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
494#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
495#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
496#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
497#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
498#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
499#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
500#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
501#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
502#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
503#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
504#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
505#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
506#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
507#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
508#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
509#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
510#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
511#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
512#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
513#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
514#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
515#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
516
517typedef struct drm_radeon_init {
518 enum {
b5e89ed5 519 RADEON_INIT_CP = 0x01,
1da177e4
LT		 520 RADEON_CLEANUP_CP = 0x02,
521 RADEON_INIT_R200_CP = 0x03,
522 RADEON_INIT_R300_CP = 0x04
523 } func;
524 unsigned long sarea_priv_offset;
525 int is_pci;
526 int cp_mode;
527 int gart_size;
528 int ring_size;
529 int usec_timeout;
530
531 unsigned int fb_bpp;
532 unsigned int front_offset, front_pitch;
533 unsigned int back_offset, back_pitch;
534 unsigned int depth_bpp;
535 unsigned int depth_offset, depth_pitch;
536
537 unsigned long fb_offset;
538 unsigned long mmio_offset;
539 unsigned long ring_offset;
540 unsigned long ring_rptr_offset;
541 unsigned long buffers_offset;
542 unsigned long gart_textures_offset;
543} drm_radeon_init_t;
544
545typedef struct drm_radeon_cp_stop {
546 int flush;
547 int idle;
548} drm_radeon_cp_stop_t;
549
550typedef struct drm_radeon_fullscreen {
551 enum {
b5e89ed5 552 RADEON_INIT_FULLSCREEN = 0x01,
1da177e4
LT		 553 RADEON_CLEANUP_FULLSCREEN = 0x02
554 } func;
555} drm_radeon_fullscreen_t;
556
557#define CLEAR_X1 0
558#define CLEAR_Y1 1
559#define CLEAR_X2 2
560#define CLEAR_Y2 3
561#define CLEAR_DEPTH 4
562
563typedef union drm_radeon_clear_rect {
564 float f[5];
565 unsigned int ui[5];
566} drm_radeon_clear_rect_t;
567
568typedef struct drm_radeon_clear {
569 unsigned int flags;
570 unsigned int clear_color;
571 unsigned int clear_depth;
572 unsigned int color_mask;
b5e89ed5 573 unsigned int depth_mask; /* misnamed field: should be stencil */
1da177e4
LT		 574 drm_radeon_clear_rect_t __user *depth_boxes;
575} drm_radeon_clear_t;
576
577typedef struct drm_radeon_vertex {
578 int prim;
b5e89ed5
DA		 579 int idx; /* Index of vertex buffer */
580 int count; /* Number of vertices in buffer */
581 int discard; /* Client finished with buffer? */
1da177e4
LT		 582} drm_radeon_vertex_t;
583
584typedef struct drm_radeon_indices {
585 int prim;
586 int idx;
587 int start;
588 int end;
b5e89ed5 589 int discard; /* Client finished with buffer? */
1da177e4
LT		 590} drm_radeon_indices_t;
591
592/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
593 * - allows multiple primitives and state changes in a single ioctl
594 * - supports driver change to emit native primitives
595 */
596typedef struct drm_radeon_vertex2 {
b5e89ed5
DA		 597 int idx; /* Index of vertex buffer */
598 int discard; /* Client finished with buffer? */
1da177e4
LT		 599 int nr_states;
600 drm_radeon_state_t __user *state;
601 int nr_prims;
602 drm_radeon_prim_t __user *prim;
603} drm_radeon_vertex2_t;
604
605/* v1.3 - obsoletes drm_radeon_vertex2
b5e89ed5 606 * - allows arbitarily large cliprect list
1da177e4
LT		 607 * - allows updating of tcl packet, vector and scalar state
608 * - allows memory-efficient description of state updates
b5e89ed5 609 * - allows state to be emitted without a primitive
1da177e4
LT		 610 * (for clears, ctx switches)
611 * - allows more than one dma buffer to be referenced per ioctl
612 * - supports tcl driver
613 * - may be extended in future versions with new cmd types, packets
614 */
615typedef struct drm_radeon_cmd_buffer {
616 int bufsz;
617 char __user *buf;
618 int nbox;
c60ce623 619 struct drm_clip_rect __user *boxes;
1da177e4
LT		 620} drm_radeon_cmd_buffer_t;
621
622typedef struct drm_radeon_tex_image {
b5e89ed5 623 unsigned int x, y; /* Blit coordinates */
1da177e4
LT		 624 unsigned int width, height;
625 const void __user *data;
626} drm_radeon_tex_image_t;
627
628typedef struct drm_radeon_texture {
629 unsigned int offset;
630 int pitch;
631 int format;
b5e89ed5 632 int width; /* Texture image coordinates */
1da177e4
LT		 633 int height;
634 drm_radeon_tex_image_t __user *image;
635} drm_radeon_texture_t;
636
637typedef struct drm_radeon_stipple {
638 unsigned int __user *mask;
639} drm_radeon_stipple_t;
640
641typedef struct drm_radeon_indirect {
642 int idx;
643 int start;
644 int end;
645 int discard;
646} drm_radeon_indirect_t;
647
d985c108
DA		 648/* enum for card type parameters */
649#define RADEON_CARD_PCI 0
650#define RADEON_CARD_AGP 1
651#define RADEON_CARD_PCIE 2
652
1da177e4 653/* 1.3: An ioctl to get parameters that aren't available to the 3d
b5e89ed5 654 * client any other way.
1da177e4 655 */
b5e89ed5 656#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
1da177e4
LT		 657#define RADEON_PARAM_LAST_FRAME 2
658#define RADEON_PARAM_LAST_DISPATCH 3
659#define RADEON_PARAM_LAST_CLEAR 4
660/* Added with DRM version 1.6. */
661#define RADEON_PARAM_IRQ_NR 5
b5e89ed5 662#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
1da177e4 663/* Added with DRM version 1.8. */
b5e89ed5 664#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
1da177e4
LT		 665#define RADEON_PARAM_STATUS_HANDLE 8
666#define RADEON_PARAM_SAREA_HANDLE 9
667#define RADEON_PARAM_GART_TEX_HANDLE 10
668#define RADEON_PARAM_SCRATCH_OFFSET 11
d985c108 669#define RADEON_PARAM_CARD_TYPE 12
ddbee333 670#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
3d5e2c13 671#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
5b92c404 672#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
1da177e4
LT		 673
674typedef struct drm_radeon_getparam {
675 int param;
676 void __user *value;
677} drm_radeon_getparam_t;
678
679/* 1.6: Set up a memory manager for regions of shared memory:
680 */
681#define RADEON_MEM_REGION_GART 1
682#define RADEON_MEM_REGION_FB 2
683
684typedef struct drm_radeon_mem_alloc {
685 int region;
686 int alignment;
687 int size;
688 int __user *region_offset; /* offset from start of fb or GART */
689} drm_radeon_mem_alloc_t;
690
691typedef struct drm_radeon_mem_free {
692 int region;
693 int region_offset;
694} drm_radeon_mem_free_t;
695
696typedef struct drm_radeon_mem_init_heap {
697 int region;
698 int size;
b5e89ed5 699 int start;
1da177e4
LT		 700} drm_radeon_mem_init_heap_t;
701
1da177e4
LT		 702/* 1.6: Userspace can request & wait on irq's:
703 */
704typedef struct drm_radeon_irq_emit {
705 int __user *irq_seq;
706} drm_radeon_irq_emit_t;
707
708typedef struct drm_radeon_irq_wait {
709 int irq_seq;
710} drm_radeon_irq_wait_t;
711
1da177e4
LT		 712/* 1.10: Clients tell the DRM where they think the framebuffer is located in
713 * the card's address space, via a new generic ioctl to set parameters
714 */
715
716typedef struct drm_radeon_setparam {
717 unsigned int param;
b5e89ed5 718 int64_t value;
1da177e4
LT		 719} drm_radeon_setparam_t;
720
721#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
722#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
b5e89ed5 723#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
d5ea702f 724#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
f2b04cd2 725#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
ddbee333 726#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
1da177e4
LT		 727/* 1.14: Clients can allocate/free a surface
728 */
729typedef struct drm_radeon_surface_alloc {
730 unsigned int address;
731 unsigned int size;
732 unsigned int flags;
733} drm_radeon_surface_alloc_t;
734
735typedef struct drm_radeon_surface_free {
736 unsigned int address;
737} drm_radeon_surface_free_t;
738
bc5f4523
DA		 739#define DRM_RADEON_VBLANK_CRTC1 1
740#define DRM_RADEON_VBLANK_CRTC2 2
ddbee333 741
1da177e4 742#endif
Linux kernel - Deliverables
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