projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm: lindent the drm directory.
[deliverable/linux.git] / drivers / char / drm / radeon_drm.h
CommitLineData
1da177e4
LT		 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (radeon_sarea.h)
38 */
39#ifndef __RADEON_SAREA_DEFINES__
40#define __RADEON_SAREA_DEFINES__
41
42/* Old style state flags, required for sarea interface (1.1 and 1.2
43 * clears) and 1.2 drm_vertex2 ioctl.
44 */
45#define RADEON_UPLOAD_CONTEXT 0x00000001
46#define RADEON_UPLOAD_VERTFMT 0x00000002
47#define RADEON_UPLOAD_LINE 0x00000004
48#define RADEON_UPLOAD_BUMPMAP 0x00000008
49#define RADEON_UPLOAD_MASKS 0x00000010
50#define RADEON_UPLOAD_VIEWPORT 0x00000020
51#define RADEON_UPLOAD_SETUP 0x00000040
52#define RADEON_UPLOAD_TCL 0x00000080
53#define RADEON_UPLOAD_MISC 0x00000100
54#define RADEON_UPLOAD_TEX0 0x00000200
55#define RADEON_UPLOAD_TEX1 0x00000400
56#define RADEON_UPLOAD_TEX2 0x00000800
57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
b5e89ed5 60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
1da177e4 61#define RADEON_REQUIRE_QUIESCENCE 0x00010000
b5e89ed5 62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
1da177e4
LT		 63#define RADEON_UPLOAD_ALL 0x003effff
64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
65
1da177e4
LT		 66/* New style per-packet identifiers for use in cmd_buffer ioctl with
67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
68 * state bits and the packet size:
69 */
b5e89ed5
DA		 70#define RADEON_EMIT_PP_MISC 0 /* context/7 */
71#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
72#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
73#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
74#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
75#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
76#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
77#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
78#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
79#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
80#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
81#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
82#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
83#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
84#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
85#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
86#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
87#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
88#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
89#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
90#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
91#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
92#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
93#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
94#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
95#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
96#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
97#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
98#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
99#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
100#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
101#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
102#define R200_EMIT_VAP_CTL 32 /* vap/1 */
103#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
104#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
105#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
106#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
107#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
108#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
109#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
110#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
111#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
112#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
113#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
114#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
115#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
116#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
117#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
118#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
119#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
120#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
121#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
122#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
123#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
124#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
125#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
126#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
127#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
128#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
129#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
130#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
1da177e4
LT		 131#define R200_EMIT_PP_CUBIC_FACES_0 61
132#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
133#define R200_EMIT_PP_CUBIC_FACES_1 63
134#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
135#define R200_EMIT_PP_CUBIC_FACES_2 65
136#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
137#define R200_EMIT_PP_CUBIC_FACES_3 67
138#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
139#define R200_EMIT_PP_CUBIC_FACES_4 69
140#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
141#define R200_EMIT_PP_CUBIC_FACES_5 71
142#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
143#define RADEON_EMIT_PP_TEX_SIZE_0 73
144#define RADEON_EMIT_PP_TEX_SIZE_1 74
145#define RADEON_EMIT_PP_TEX_SIZE_2 75
146#define R200_EMIT_RB3D_BLENDCOLOR 76
147#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
148#define RADEON_EMIT_PP_CUBIC_FACES_0 78
149#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
150#define RADEON_EMIT_PP_CUBIC_FACES_1 80
151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
152#define RADEON_EMIT_PP_CUBIC_FACES_2 82
153#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
154#define R200_EMIT_PP_TRI_PERF_CNTL 84
9d17601c
DA		 155#define R200_EMIT_PP_AFS_0 85
156#define R200_EMIT_PP_AFS_1 86
157#define R200_EMIT_ATF_TFACTOR 87
158#define R200_EMIT_PP_TXCTLALL_0 88
159#define R200_EMIT_PP_TXCTLALL_1 89
160#define R200_EMIT_PP_TXCTLALL_2 90
161#define R200_EMIT_PP_TXCTLALL_3 91
162#define R200_EMIT_PP_TXCTLALL_4 92
163#define R200_EMIT_PP_TXCTLALL_5 93
164#define RADEON_MAX_STATE_PACKETS 94
1da177e4
LT		 165
166/* Commands understood by cmd_buffer ioctl. More can be added but
167 * obviously these can't be removed or changed:
168 */
b5e89ed5
DA		 169#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
170#define RADEON_CMD_SCALARS 2 /* emit scalar data */
171#define RADEON_CMD_VECTORS 3 /* emit vector data */
172#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
173#define RADEON_CMD_PACKET3 5 /* emit hw packet */
174#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
175#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
176#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
177 * doesn't make the cpu wait, just
178 * the graphics hardware */
1da177e4
LT		 179
180typedef union {
181 int i;
b5e89ed5 182 struct {
1da177e4
LT		 183 unsigned char cmd_type, pad0, pad1, pad2;
184 } header;
b5e89ed5 185 struct {
1da177e4
LT		 186 unsigned char cmd_type, packet_id, pad0, pad1;
187 } packet;
b5e89ed5
DA		 188 struct {
189 unsigned char cmd_type, offset, stride, count;
1da177e4 190 } scalars;
b5e89ed5
DA		 191 struct {
192 unsigned char cmd_type, offset, stride, count;
1da177e4 193 } vectors;
b5e89ed5
DA		 194 struct {
195 unsigned char cmd_type, buf_idx, pad0, pad1;
1da177e4 196 } dma;
b5e89ed5
DA		 197 struct {
198 unsigned char cmd_type, flags, pad0, pad1;
1da177e4
LT		 199 } wait;
200} drm_radeon_cmd_header_t;
201
202#define RADEON_WAIT_2D 0x1
203#define RADEON_WAIT_3D 0x2
204
414ed537
DA		 205/* Allowed parameters for R300_CMD_PACKET3
206 */
207#define R300_CMD_PACKET3_CLEAR 0
208#define R300_CMD_PACKET3_RAW 1
209
210/* Commands understood by cmd_buffer ioctl for R300.
211 * The interface has not been stabilized, so some of these may be removed
212 * and eventually reordered before stabilization.
213 */
b5e89ed5
DA		 214#define R300_CMD_PACKET0 1
215#define R300_CMD_VPU 2 /* emit vertex program upload */
216#define R300_CMD_PACKET3 3 /* emit a packet3 */
217#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
414ed537
DA		 218#define R300_CMD_CP_DELAY 5
219#define R300_CMD_DMA_DISCARD 6
220#define R300_CMD_WAIT 7
221# define R300_WAIT_2D 0x1
222# define R300_WAIT_3D 0x2
223# define R300_WAIT_2D_CLEAN 0x3
224# define R300_WAIT_3D_CLEAN 0x4
225
226typedef union {
227 unsigned int u;
228 struct {
229 unsigned char cmd_type, pad0, pad1, pad2;
230 } header;
231 struct {
232 unsigned char cmd_type, count, reglo, reghi;
233 } packet0;
234 struct {
235 unsigned char cmd_type, count, adrlo, adrhi;
236 } vpu;
237 struct {
238 unsigned char cmd_type, packet, pad0, pad1;
239 } packet3;
240 struct {
241 unsigned char cmd_type, packet;
b5e89ed5 242 unsigned short count; /* amount of packet2 to emit */
414ed537
DA		 243 } delay;
244 struct {
245 unsigned char cmd_type, buf_idx, pad0, pad1;
246 } dma;
247 struct {
b5e89ed5 248 unsigned char cmd_type, flags, pad0, pad1;
414ed537
DA		 249 } wait;
250} drm_r300_cmd_header_t;
1da177e4
LT		 251
252#define RADEON_FRONT 0x1
253#define RADEON_BACK 0x2
254#define RADEON_DEPTH 0x4
255#define RADEON_STENCIL 0x8
256#define RADEON_CLEAR_FASTZ 0x80000000
257#define RADEON_USE_HIERZ 0x40000000
258#define RADEON_USE_COMP_ZBUF 0x20000000
259
260/* Primitive types
261 */
262#define RADEON_POINTS 0x1
263#define RADEON_LINES 0x2
264#define RADEON_LINE_STRIP 0x3
265#define RADEON_TRIANGLES 0x4
266#define RADEON_TRIANGLE_FAN 0x5
267#define RADEON_TRIANGLE_STRIP 0x6
268
269/* Vertex/indirect buffer size
270 */
271#define RADEON_BUFFER_SIZE 65536
272
273/* Byte offsets for indirect buffer data
274 */
275#define RADEON_INDEX_PRIM_OFFSET 20
276
277#define RADEON_SCRATCH_REG_OFFSET 32
278
279#define RADEON_NR_SAREA_CLIPRECTS 12
280
281/* There are 2 heaps (local/GART). Each region within a heap is a
282 * minimum of 64k, and there are at most 64 of them per heap.
283 */
284#define RADEON_LOCAL_TEX_HEAP 0
285#define RADEON_GART_TEX_HEAP 1
286#define RADEON_NR_TEX_HEAPS 2
287#define RADEON_NR_TEX_REGIONS 64
288#define RADEON_LOG_TEX_GRANULARITY 16
289
290#define RADEON_MAX_TEXTURE_LEVELS 12
291#define RADEON_MAX_TEXTURE_UNITS 3
292
293#define RADEON_MAX_SURFACES 8
294
295/* Blits have strict offset rules. All blit offset must be aligned on
296 * a 1K-byte boundary.
297 */
298#define RADEON_OFFSET_SHIFT 10
299#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
300#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
301
b5e89ed5 302#endif /* __RADEON_SAREA_DEFINES__ */
1da177e4
LT		 303
304typedef struct {
305 unsigned int red;
306 unsigned int green;
307 unsigned int blue;
308 unsigned int alpha;
309} radeon_color_regs_t;
310
311typedef struct {
312 /* Context state */
b5e89ed5 313 unsigned int pp_misc; /* 0x1c14 */
1da177e4
LT		 314 unsigned int pp_fog_color;
315 unsigned int re_solid_color;
316 unsigned int rb3d_blendcntl;
317 unsigned int rb3d_depthoffset;
318 unsigned int rb3d_depthpitch;
319 unsigned int rb3d_zstencilcntl;
320
b5e89ed5 321 unsigned int pp_cntl; /* 0x1c38 */
1da177e4
LT		 322 unsigned int rb3d_cntl;
323 unsigned int rb3d_coloroffset;
324 unsigned int re_width_height;
325 unsigned int rb3d_colorpitch;
326 unsigned int se_cntl;
327
328 /* Vertex format state */
b5e89ed5 329 unsigned int se_coord_fmt; /* 0x1c50 */
1da177e4
LT		 330
331 /* Line state */
b5e89ed5 332 unsigned int re_line_pattern; /* 0x1cd0 */
1da177e4
LT		 333 unsigned int re_line_state;
334
b5e89ed5 335 unsigned int se_line_width; /* 0x1db8 */
1da177e4
LT		 336
337 /* Bumpmap state */
b5e89ed5 338 unsigned int pp_lum_matrix; /* 0x1d00 */
1da177e4 339
b5e89ed5 340 unsigned int pp_rot_matrix_0; /* 0x1d58 */
1da177e4
LT		 341 unsigned int pp_rot_matrix_1;
342
343 /* Mask state */
b5e89ed5 344 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
1da177e4
LT		 345 unsigned int rb3d_ropcntl;
346 unsigned int rb3d_planemask;
347
348 /* Viewport state */
b5e89ed5 349 unsigned int se_vport_xscale; /* 0x1d98 */
1da177e4
LT		 350 unsigned int se_vport_xoffset;
351 unsigned int se_vport_yscale;
352 unsigned int se_vport_yoffset;
353 unsigned int se_vport_zscale;
354 unsigned int se_vport_zoffset;
355
356 /* Setup state */
b5e89ed5 357 unsigned int se_cntl_status; /* 0x2140 */
1da177e4
LT		 358
359 /* Misc state */
b5e89ed5 360 unsigned int re_top_left; /* 0x26c0 */
1da177e4
LT		 361 unsigned int re_misc;
362} drm_radeon_context_regs_t;
363
364typedef struct {
365 /* Zbias state */
b5e89ed5 366 unsigned int se_zbias_factor; /* 0x1dac */
1da177e4
LT		 367 unsigned int se_zbias_constant;
368} drm_radeon_context2_regs_t;
369
1da177e4
LT		 370/* Setup registers for each texture unit
371 */
372typedef struct {
373 unsigned int pp_txfilter;
374 unsigned int pp_txformat;
375 unsigned int pp_txoffset;
376 unsigned int pp_txcblend;
377 unsigned int pp_txablend;
378 unsigned int pp_tfactor;
379 unsigned int pp_border_color;
380} drm_radeon_texture_regs_t;
381
382typedef struct {
383 unsigned int start;
384 unsigned int finish;
385 unsigned int prim:8;
386 unsigned int stateidx:8;
b5e89ed5
DA		 387 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
388 unsigned int vc_format; /* vertex format */
1da177e4
LT		 389} drm_radeon_prim_t;
390
1da177e4
LT		 391typedef struct {
392 drm_radeon_context_regs_t context;
393 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
394 drm_radeon_context2_regs_t context2;
395 unsigned int dirty;
396} drm_radeon_state_t;
397
1da177e4
LT		 398typedef struct {
399 /* The channel for communication of state information to the
400 * kernel on firing a vertex buffer with either of the
401 * obsoleted vertex/index ioctls.
402 */
403 drm_radeon_context_regs_t context_state;
404 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
405 unsigned int dirty;
406 unsigned int vertsize;
407 unsigned int vc_format;
408
409 /* The current cliprects, or a subset thereof.
410 */
411 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
412 unsigned int nbox;
413
414 /* Counters for client-side throttling of rendering clients.
415 */
416 unsigned int last_frame;
417 unsigned int last_dispatch;
418 unsigned int last_clear;
419
b5e89ed5
DA		 420 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
421 1];
1da177e4
LT		 422 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
423 int ctx_owner;
b5e89ed5
DA		 424 int pfState; /* number of 3d windows (0,1,2ormore) */
425 int pfCurrentPage; /* which buffer is being displayed? */
426 int crtc2_base; /* CRTC2 frame offset */
1da177e4
LT		 427 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
428} drm_radeon_sarea_t;
429
1da177e4
LT		 430/* WARNING: If you change any of these defines, make sure to change the
431 * defines in the Xserver file (xf86drmRadeon.h)
432 *
433 * KW: actually it's illegal to change any of this (backwards compatibility).
434 */
435
436/* Radeon specific ioctls
437 * The device specific ioctl range is 0x40 to 0x79.
438 */
b5e89ed5
DA		 439#define DRM_RADEON_CP_INIT 0x00
440#define DRM_RADEON_CP_START 0x01
1da177e4
LT		 441#define DRM_RADEON_CP_STOP 0x02
442#define DRM_RADEON_CP_RESET 0x03
443#define DRM_RADEON_CP_IDLE 0x04
b5e89ed5 444#define DRM_RADEON_RESET 0x05
1da177e4 445#define DRM_RADEON_FULLSCREEN 0x06
b5e89ed5
DA		 446#define DRM_RADEON_SWAP 0x07
447#define DRM_RADEON_CLEAR 0x08
1da177e4
LT		 448#define DRM_RADEON_VERTEX 0x09
449#define DRM_RADEON_INDICES 0x0A
450#define DRM_RADEON_NOT_USED
451#define DRM_RADEON_STIPPLE 0x0C
452#define DRM_RADEON_INDIRECT 0x0D
453#define DRM_RADEON_TEXTURE 0x0E
454#define DRM_RADEON_VERTEX2 0x0F
455#define DRM_RADEON_CMDBUF 0x10
456#define DRM_RADEON_GETPARAM 0x11
457#define DRM_RADEON_FLIP 0x12
458#define DRM_RADEON_ALLOC 0x13
459#define DRM_RADEON_FREE 0x14
460#define DRM_RADEON_INIT_HEAP 0x15
461#define DRM_RADEON_IRQ_EMIT 0x16
462#define DRM_RADEON_IRQ_WAIT 0x17
463#define DRM_RADEON_CP_RESUME 0x18
464#define DRM_RADEON_SETPARAM 0x19
465#define DRM_RADEON_SURF_ALLOC 0x1a
466#define DRM_RADEON_SURF_FREE 0x1b
467
468#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
469#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
470#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
471#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
472#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
473#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
474#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
475#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
476#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
477#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
478#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
479#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
480#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
481#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
482#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
483#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
484#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
485#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
486#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
487#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
488#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
489#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
490#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
491#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
492#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
493#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
494#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
495
496typedef struct drm_radeon_init {
497 enum {
b5e89ed5 498 RADEON_INIT_CP = 0x01,
1da177e4
LT		 499 RADEON_CLEANUP_CP = 0x02,
500 RADEON_INIT_R200_CP = 0x03,
501 RADEON_INIT_R300_CP = 0x04
502 } func;
503 unsigned long sarea_priv_offset;
504 int is_pci;
505 int cp_mode;
506 int gart_size;
507 int ring_size;
508 int usec_timeout;
509
510 unsigned int fb_bpp;
511 unsigned int front_offset, front_pitch;
512 unsigned int back_offset, back_pitch;
513 unsigned int depth_bpp;
514 unsigned int depth_offset, depth_pitch;
515
516 unsigned long fb_offset;
517 unsigned long mmio_offset;
518 unsigned long ring_offset;
519 unsigned long ring_rptr_offset;
520 unsigned long buffers_offset;
521 unsigned long gart_textures_offset;
522} drm_radeon_init_t;
523
524typedef struct drm_radeon_cp_stop {
525 int flush;
526 int idle;
527} drm_radeon_cp_stop_t;
528
529typedef struct drm_radeon_fullscreen {
530 enum {
b5e89ed5 531 RADEON_INIT_FULLSCREEN = 0x01,
1da177e4
LT		 532 RADEON_CLEANUP_FULLSCREEN = 0x02
533 } func;
534} drm_radeon_fullscreen_t;
535
536#define CLEAR_X1 0
537#define CLEAR_Y1 1
538#define CLEAR_X2 2
539#define CLEAR_Y2 3
540#define CLEAR_DEPTH 4
541
542typedef union drm_radeon_clear_rect {
543 float f[5];
544 unsigned int ui[5];
545} drm_radeon_clear_rect_t;
546
547typedef struct drm_radeon_clear {
548 unsigned int flags;
549 unsigned int clear_color;
550 unsigned int clear_depth;
551 unsigned int color_mask;
b5e89ed5 552 unsigned int depth_mask; /* misnamed field: should be stencil */
1da177e4
LT		 553 drm_radeon_clear_rect_t __user *depth_boxes;
554} drm_radeon_clear_t;
555
556typedef struct drm_radeon_vertex {
557 int prim;
b5e89ed5
DA		 558 int idx; /* Index of vertex buffer */
559 int count; /* Number of vertices in buffer */
560 int discard; /* Client finished with buffer? */
1da177e4
LT		 561} drm_radeon_vertex_t;
562
563typedef struct drm_radeon_indices {
564 int prim;
565 int idx;
566 int start;
567 int end;
b5e89ed5 568 int discard; /* Client finished with buffer? */
1da177e4
LT		 569} drm_radeon_indices_t;
570
571/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
572 * - allows multiple primitives and state changes in a single ioctl
573 * - supports driver change to emit native primitives
574 */
575typedef struct drm_radeon_vertex2 {
b5e89ed5
DA		 576 int idx; /* Index of vertex buffer */
577 int discard; /* Client finished with buffer? */
1da177e4
LT		 578 int nr_states;
579 drm_radeon_state_t __user *state;
580 int nr_prims;
581 drm_radeon_prim_t __user *prim;
582} drm_radeon_vertex2_t;
583
584/* v1.3 - obsoletes drm_radeon_vertex2
b5e89ed5 585 * - allows arbitarily large cliprect list
1da177e4
LT		 586 * - allows updating of tcl packet, vector and scalar state
587 * - allows memory-efficient description of state updates
b5e89ed5 588 * - allows state to be emitted without a primitive
1da177e4
LT		 589 * (for clears, ctx switches)
590 * - allows more than one dma buffer to be referenced per ioctl
591 * - supports tcl driver
592 * - may be extended in future versions with new cmd types, packets
593 */
594typedef struct drm_radeon_cmd_buffer {
595 int bufsz;
596 char __user *buf;
597 int nbox;
598 drm_clip_rect_t __user *boxes;
599} drm_radeon_cmd_buffer_t;
600
601typedef struct drm_radeon_tex_image {
b5e89ed5 602 unsigned int x, y; /* Blit coordinates */
1da177e4
LT		 603 unsigned int width, height;
604 const void __user *data;
605} drm_radeon_tex_image_t;
606
607typedef struct drm_radeon_texture {
608 unsigned int offset;
609 int pitch;
610 int format;
b5e89ed5 611 int width; /* Texture image coordinates */
1da177e4
LT		 612 int height;
613 drm_radeon_tex_image_t __user *image;
614} drm_radeon_texture_t;
615
616typedef struct drm_radeon_stipple {
617 unsigned int __user *mask;
618} drm_radeon_stipple_t;
619
620typedef struct drm_radeon_indirect {
621 int idx;
622 int start;
623 int end;
624 int discard;
625} drm_radeon_indirect_t;
626
1da177e4 627/* 1.3: An ioctl to get parameters that aren't available to the 3d
b5e89ed5 628 * client any other way.
1da177e4 629 */
b5e89ed5 630#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
1da177e4
LT		 631#define RADEON_PARAM_LAST_FRAME 2
632#define RADEON_PARAM_LAST_DISPATCH 3
633#define RADEON_PARAM_LAST_CLEAR 4
634/* Added with DRM version 1.6. */
635#define RADEON_PARAM_IRQ_NR 5
b5e89ed5 636#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
1da177e4 637/* Added with DRM version 1.8. */
b5e89ed5 638#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
1da177e4
LT		 639#define RADEON_PARAM_STATUS_HANDLE 8
640#define RADEON_PARAM_SAREA_HANDLE 9
641#define RADEON_PARAM_GART_TEX_HANDLE 10
642#define RADEON_PARAM_SCRATCH_OFFSET 11
643
644typedef struct drm_radeon_getparam {
645 int param;
646 void __user *value;
647} drm_radeon_getparam_t;
648
649/* 1.6: Set up a memory manager for regions of shared memory:
650 */
651#define RADEON_MEM_REGION_GART 1
652#define RADEON_MEM_REGION_FB 2
653
654typedef struct drm_radeon_mem_alloc {
655 int region;
656 int alignment;
657 int size;
658 int __user *region_offset; /* offset from start of fb or GART */
659} drm_radeon_mem_alloc_t;
660
661typedef struct drm_radeon_mem_free {
662 int region;
663 int region_offset;
664} drm_radeon_mem_free_t;
665
666typedef struct drm_radeon_mem_init_heap {
667 int region;
668 int size;
b5e89ed5 669 int start;
1da177e4
LT		 670} drm_radeon_mem_init_heap_t;
671
1da177e4
LT		 672/* 1.6: Userspace can request & wait on irq's:
673 */
674typedef struct drm_radeon_irq_emit {
675 int __user *irq_seq;
676} drm_radeon_irq_emit_t;
677
678typedef struct drm_radeon_irq_wait {
679 int irq_seq;
680} drm_radeon_irq_wait_t;
681
1da177e4
LT		 682/* 1.10: Clients tell the DRM where they think the framebuffer is located in
683 * the card's address space, via a new generic ioctl to set parameters
684 */
685
686typedef struct drm_radeon_setparam {
687 unsigned int param;
b5e89ed5 688 int64_t value;
1da177e4
LT		 689} drm_radeon_setparam_t;
690
691#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
692#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
b5e89ed5 693#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
1da177e4
LT		 694
695/* 1.14: Clients can allocate/free a surface
696 */
697typedef struct drm_radeon_surface_alloc {
698 unsigned int address;
699 unsigned int size;
700 unsigned int flags;
701} drm_radeon_surface_alloc_t;
702
703typedef struct drm_radeon_surface_free {
704 unsigned int address;
705} drm_radeon_surface_free_t;
706
707#endif
Linux kernel - Deliverables
This page took 0.07043 seconds and 5 git commands to generate.