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[PATCH] tpm: remove pci dependency
[deliverable/linux.git] / drivers / char / drm / radeon_drv.h
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1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20050311"
42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading)
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
1da177e4
LT		 86 */
87#define DRIVER_MAJOR 1
414ed537 88#define DRIVER_MINOR 17
1da177e4
LT		 89#define DRIVER_PATCHLEVEL 0
90
91#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
92#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
93
94/*
95 * Radeon chip families
96 */
97enum radeon_family {
98 CHIP_R100,
99 CHIP_RS100,
100 CHIP_RV100,
101 CHIP_R200,
102 CHIP_RV200,
103 CHIP_RS200,
104 CHIP_R250,
105 CHIP_RS250,
106 CHIP_RV250,
107 CHIP_RV280,
108 CHIP_R300,
109 CHIP_RS300,
414ed537 110 CHIP_R350,
1da177e4 111 CHIP_RV350,
414ed537 112 CHIP_R420,
1da177e4
LT		 113 CHIP_LAST,
114};
115
116enum radeon_cp_microcode_version {
117 UCODE_R100,
118 UCODE_R200,
119 UCODE_R300,
120};
121
122/*
123 * Chip flags
124 */
125enum radeon_chip_flags {
126 CHIP_FAMILY_MASK = 0x0000ffffUL,
127 CHIP_FLAGS_MASK = 0xffff0000UL,
128 CHIP_IS_MOBILITY = 0x00010000UL,
129 CHIP_IS_IGP = 0x00020000UL,
130 CHIP_SINGLE_CRTC = 0x00040000UL,
131 CHIP_IS_AGP = 0x00080000UL,
132 CHIP_HAS_HIERZ = 0x00100000UL,
133};
134
135typedef struct drm_radeon_freelist {
136 unsigned int age;
137 drm_buf_t *buf;
138 struct drm_radeon_freelist *next;
139 struct drm_radeon_freelist *prev;
140} drm_radeon_freelist_t;
141
142typedef struct drm_radeon_ring_buffer {
143 u32 *start;
144 u32 *end;
145 int size;
146 int size_l2qw;
147
148 u32 tail;
149 u32 tail_mask;
150 int space;
151
152 int high_mark;
153} drm_radeon_ring_buffer_t;
154
155typedef struct drm_radeon_depth_clear_t {
156 u32 rb3d_cntl;
157 u32 rb3d_zstencilcntl;
158 u32 se_cntl;
159} drm_radeon_depth_clear_t;
160
161struct drm_radeon_driver_file_fields {
162 int64_t radeon_fb_delta;
163};
164
165struct mem_block {
166 struct mem_block *next;
167 struct mem_block *prev;
168 int start;
169 int size;
170 DRMFILE filp; /* 0: free, -1: heap, other: real files */
171};
172
173struct radeon_surface {
174 int refcount;
175 u32 lower;
176 u32 upper;
177 u32 flags;
178};
179
180struct radeon_virt_surface {
181 int surface_index;
182 u32 lower;
183 u32 upper;
184 u32 flags;
185 DRMFILE filp;
186};
187
188typedef struct drm_radeon_private {
189 drm_radeon_ring_buffer_t ring;
190 drm_radeon_sarea_t *sarea_priv;
191
192 u32 fb_location;
193
194 int gart_size;
195 u32 gart_vm_start;
196 unsigned long gart_buffers_offset;
197
198 int cp_mode;
199 int cp_running;
200
201 drm_radeon_freelist_t *head;
202 drm_radeon_freelist_t *tail;
203 int last_buf;
204 volatile u32 *scratch;
205 int writeback_works;
206
207 int usec_timeout;
208
209 int microcode_version;
210
211 int is_pci;
212 unsigned long phys_pci_gart;
213 dma_addr_t bus_pci_gart;
214
215 struct {
216 u32 boxes;
217 int freelist_timeouts;
218 int freelist_loops;
219 int requested_bufs;
220 int last_frame_reads;
221 int last_clear_reads;
222 int clears;
223 int texture_uploads;
224 } stats;
225
226 int do_boxes;
227 int page_flipping;
228 int current_page;
229
230 u32 color_fmt;
231 unsigned int front_offset;
232 unsigned int front_pitch;
233 unsigned int back_offset;
234 unsigned int back_pitch;
235
236 u32 depth_fmt;
237 unsigned int depth_offset;
238 unsigned int depth_pitch;
239
240 u32 front_pitch_offset;
241 u32 back_pitch_offset;
242 u32 depth_pitch_offset;
243
244 drm_radeon_depth_clear_t depth_clear;
245
246 unsigned long fb_offset;
247 unsigned long mmio_offset;
248 unsigned long ring_offset;
249 unsigned long ring_rptr_offset;
250 unsigned long buffers_offset;
251 unsigned long gart_textures_offset;
252
253 drm_local_map_t *sarea;
254 drm_local_map_t *mmio;
255 drm_local_map_t *cp_ring;
256 drm_local_map_t *ring_rptr;
257 drm_local_map_t *gart_textures;
258
259 struct mem_block *gart_heap;
260 struct mem_block *fb_heap;
261
262 /* SW interrupt */
263 wait_queue_head_t swi_queue;
264 atomic_t swi_emitted;
265
266 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
267 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
268
269 /* starting from here on, data is preserved accross an open */
270 uint32_t flags; /* see radeon_chip_flags */
271} drm_radeon_private_t;
272
273typedef struct drm_radeon_buf_priv {
274 u32 age;
275} drm_radeon_buf_priv_t;
276
277 /* radeon_cp.c */
278extern int radeon_cp_init( DRM_IOCTL_ARGS );
279extern int radeon_cp_start( DRM_IOCTL_ARGS );
280extern int radeon_cp_stop( DRM_IOCTL_ARGS );
281extern int radeon_cp_reset( DRM_IOCTL_ARGS );
282extern int radeon_cp_idle( DRM_IOCTL_ARGS );
283extern int radeon_cp_resume( DRM_IOCTL_ARGS );
284extern int radeon_engine_reset( DRM_IOCTL_ARGS );
285extern int radeon_fullscreen( DRM_IOCTL_ARGS );
286extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
287
288extern void radeon_freelist_reset( drm_device_t *dev );
289extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
290
291extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
292
293extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
294
295extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 296extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 297extern int radeon_driver_postcleanup(struct drm_device *dev);
298
299extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
300extern int radeon_mem_free( DRM_IOCTL_ARGS );
301extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
302extern void radeon_mem_takedown( struct mem_block **heap );
303extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
304
305 /* radeon_irq.c */
306extern int radeon_irq_emit( DRM_IOCTL_ARGS );
307extern int radeon_irq_wait( DRM_IOCTL_ARGS );
308
309extern void radeon_do_release(drm_device_t *dev);
310extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
311extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS );
312extern void radeon_driver_irq_preinstall( drm_device_t *dev );
313extern void radeon_driver_irq_postinstall( drm_device_t *dev );
314extern void radeon_driver_irq_uninstall( drm_device_t *dev );
315extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp);
316extern void radeon_driver_pretakedown(drm_device_t *dev);
317extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv);
318extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv);
319
320extern int radeon_preinit( struct drm_device *dev, unsigned long flags );
321extern int radeon_postinit( struct drm_device *dev, unsigned long flags );
322extern int radeon_postcleanup( struct drm_device *dev );
323
9a186645
DA		 324extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
325 unsigned long arg);
326
414ed537
DA		 327
328/* r300_cmdbuf.c */
329extern void r300_init_reg_flags(void);
330
331extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
332 drm_file_t* filp_priv,
333 drm_radeon_cmd_buffer_t* cmdbuf);
334
1da177e4
LT		 335/* Flags for stats.boxes
336 */
337#define RADEON_BOX_DMA_IDLE 0x1
338#define RADEON_BOX_RING_FULL 0x2
339#define RADEON_BOX_FLIP 0x4
340#define RADEON_BOX_WAIT_IDLE 0x8
341#define RADEON_BOX_TEXTURE_LOAD 0x10
342
343
344
345/* Register definitions, register access macros and drmAddMap constants
346 * for Radeon kernel driver.
347 */
348
349#define RADEON_AGP_COMMAND 0x0f60
350#define RADEON_AUX_SCISSOR_CNTL 0x26f0
351# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
352# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
353# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
354# define RADEON_SCISSOR_0_ENABLE (1 << 28)
355# define RADEON_SCISSOR_1_ENABLE (1 << 29)
356# define RADEON_SCISSOR_2_ENABLE (1 << 30)
357
358#define RADEON_BUS_CNTL 0x0030
359# define RADEON_BUS_MASTER_DIS (1 << 6)
360
361#define RADEON_CLOCK_CNTL_DATA 0x000c
362# define RADEON_PLL_WR_EN (1 << 7)
363#define RADEON_CLOCK_CNTL_INDEX 0x0008
364#define RADEON_CONFIG_APER_SIZE 0x0108
365#define RADEON_CRTC_OFFSET 0x0224
366#define RADEON_CRTC_OFFSET_CNTL 0x0228
367# define RADEON_CRTC_TILE_EN (1 << 15)
368# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
369#define RADEON_CRTC2_OFFSET 0x0324
370#define RADEON_CRTC2_OFFSET_CNTL 0x0328
371
414ed537
DA		 372#define RADEON_MPP_TB_CONFIG 0x01c0
373#define RADEON_MEM_CNTL 0x0140
374#define RADEON_MEM_SDRAM_MODE_REG 0x0158
375#define RADEON_AGP_BASE 0x0170
376
1da177e4
LT		 377#define RADEON_RB3D_COLOROFFSET 0x1c40
378#define RADEON_RB3D_COLORPITCH 0x1c48
379
380#define RADEON_DP_GUI_MASTER_CNTL 0x146c
381# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
382# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
383# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
384# define RADEON_GMC_BRUSH_NONE (15 << 4)
385# define RADEON_GMC_DST_16BPP (4 << 8)
386# define RADEON_GMC_DST_24BPP (5 << 8)
387# define RADEON_GMC_DST_32BPP (6 << 8)
388# define RADEON_GMC_DST_DATATYPE_SHIFT 8
389# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
390# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
391# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
392# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
393# define RADEON_GMC_WR_MSK_DIS (1 << 30)
394# define RADEON_ROP3_S 0x00cc0000
395# define RADEON_ROP3_P 0x00f00000
396#define RADEON_DP_WRITE_MASK 0x16cc
397#define RADEON_DST_PITCH_OFFSET 0x142c
398#define RADEON_DST_PITCH_OFFSET_C 0x1c80
399# define RADEON_DST_TILE_LINEAR (0 << 30)
400# define RADEON_DST_TILE_MACRO (1 << 30)
401# define RADEON_DST_TILE_MICRO (2 << 30)
402# define RADEON_DST_TILE_BOTH (3 << 30)
403
404#define RADEON_SCRATCH_REG0 0x15e0
405#define RADEON_SCRATCH_REG1 0x15e4
406#define RADEON_SCRATCH_REG2 0x15e8
407#define RADEON_SCRATCH_REG3 0x15ec
408#define RADEON_SCRATCH_REG4 0x15f0
409#define RADEON_SCRATCH_REG5 0x15f4
410#define RADEON_SCRATCH_UMSK 0x0770
411#define RADEON_SCRATCH_ADDR 0x0774
412
413#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
414
415#define GET_SCRATCH( x ) (dev_priv->writeback_works \
416 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
417 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
418
419
420#define RADEON_GEN_INT_CNTL 0x0040
421# define RADEON_CRTC_VBLANK_MASK (1 << 0)
422# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
423# define RADEON_SW_INT_ENABLE (1 << 25)
424
425#define RADEON_GEN_INT_STATUS 0x0044
426# define RADEON_CRTC_VBLANK_STAT (1 << 0)
427# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
428# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
429# define RADEON_SW_INT_TEST (1 << 25)
430# define RADEON_SW_INT_TEST_ACK (1 << 25)
431# define RADEON_SW_INT_FIRE (1 << 26)
432
433#define RADEON_HOST_PATH_CNTL 0x0130
434# define RADEON_HDP_SOFT_RESET (1 << 26)
435# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
436# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
437
438#define RADEON_ISYNC_CNTL 0x1724
439# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
440# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
441# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
442# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
443# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
444# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
445
446#define RADEON_RBBM_GUICNTL 0x172c
447# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
448# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
449# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
450# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
451
452#define RADEON_MC_AGP_LOCATION 0x014c
453#define RADEON_MC_FB_LOCATION 0x0148
454#define RADEON_MCLK_CNTL 0x0012
455# define RADEON_FORCEON_MCLKA (1 << 16)
456# define RADEON_FORCEON_MCLKB (1 << 17)
457# define RADEON_FORCEON_YCLKA (1 << 18)
458# define RADEON_FORCEON_YCLKB (1 << 19)
459# define RADEON_FORCEON_MC (1 << 20)
460# define RADEON_FORCEON_AIC (1 << 21)
461
462#define RADEON_PP_BORDER_COLOR_0 0x1d40
463#define RADEON_PP_BORDER_COLOR_1 0x1d44
464#define RADEON_PP_BORDER_COLOR_2 0x1d48
465#define RADEON_PP_CNTL 0x1c38
466# define RADEON_SCISSOR_ENABLE (1 << 1)
467#define RADEON_PP_LUM_MATRIX 0x1d00
468#define RADEON_PP_MISC 0x1c14
469#define RADEON_PP_ROT_MATRIX_0 0x1d58
470#define RADEON_PP_TXFILTER_0 0x1c54
471#define RADEON_PP_TXOFFSET_0 0x1c5c
472#define RADEON_PP_TXFILTER_1 0x1c6c
473#define RADEON_PP_TXFILTER_2 0x1c84
474
475#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
476# define RADEON_RB2D_DC_FLUSH (3 << 0)
477# define RADEON_RB2D_DC_FREE (3 << 2)
478# define RADEON_RB2D_DC_FLUSH_ALL 0xf
479# define RADEON_RB2D_DC_BUSY (1 << 31)
480#define RADEON_RB3D_CNTL 0x1c3c
481# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
482# define RADEON_PLANE_MASK_ENABLE (1 << 1)
483# define RADEON_DITHER_ENABLE (1 << 2)
484# define RADEON_ROUND_ENABLE (1 << 3)
485# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
486# define RADEON_DITHER_INIT (1 << 5)
487# define RADEON_ROP_ENABLE (1 << 6)
488# define RADEON_STENCIL_ENABLE (1 << 7)
489# define RADEON_Z_ENABLE (1 << 8)
490# define RADEON_ZBLOCK16 (1 << 15)
491#define RADEON_RB3D_DEPTHOFFSET 0x1c24
492#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
493#define RADEON_RB3D_DEPTHPITCH 0x1c28
494#define RADEON_RB3D_PLANEMASK 0x1d84
495#define RADEON_RB3D_STENCILREFMASK 0x1d7c
496#define RADEON_RB3D_ZCACHE_MODE 0x3250
497#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
498# define RADEON_RB3D_ZC_FLUSH (1 << 0)
499# define RADEON_RB3D_ZC_FREE (1 << 2)
500# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
501# define RADEON_RB3D_ZC_BUSY (1 << 31)
502#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
503# define RADEON_Z_TEST_MASK (7 << 4)
504# define RADEON_Z_TEST_ALWAYS (7 << 4)
505# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
506# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
507# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
508# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
509# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
510# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
511# define RADEON_FORCE_Z_DIRTY (1 << 29)
512# define RADEON_Z_WRITE_ENABLE (1 << 30)
513# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
514#define RADEON_RBBM_SOFT_RESET 0x00f0
515# define RADEON_SOFT_RESET_CP (1 << 0)
516# define RADEON_SOFT_RESET_HI (1 << 1)
517# define RADEON_SOFT_RESET_SE (1 << 2)
518# define RADEON_SOFT_RESET_RE (1 << 3)
519# define RADEON_SOFT_RESET_PP (1 << 4)
520# define RADEON_SOFT_RESET_E2 (1 << 5)
521# define RADEON_SOFT_RESET_RB (1 << 6)
522# define RADEON_SOFT_RESET_HDP (1 << 7)
523#define RADEON_RBBM_STATUS 0x0e40
524# define RADEON_RBBM_FIFOCNT_MASK 0x007f
525# define RADEON_RBBM_ACTIVE (1 << 31)
526#define RADEON_RE_LINE_PATTERN 0x1cd0
527#define RADEON_RE_MISC 0x26c4
528#define RADEON_RE_TOP_LEFT 0x26c0
529#define RADEON_RE_WIDTH_HEIGHT 0x1c44
530#define RADEON_RE_STIPPLE_ADDR 0x1cc8
531#define RADEON_RE_STIPPLE_DATA 0x1ccc
532
533#define RADEON_SCISSOR_TL_0 0x1cd8
534#define RADEON_SCISSOR_BR_0 0x1cdc
535#define RADEON_SCISSOR_TL_1 0x1ce0
536#define RADEON_SCISSOR_BR_1 0x1ce4
537#define RADEON_SCISSOR_TL_2 0x1ce8
538#define RADEON_SCISSOR_BR_2 0x1cec
539#define RADEON_SE_COORD_FMT 0x1c50
540#define RADEON_SE_CNTL 0x1c4c
541# define RADEON_FFACE_CULL_CW (0 << 0)
542# define RADEON_BFACE_SOLID (3 << 1)
543# define RADEON_FFACE_SOLID (3 << 3)
544# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
545# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
546# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
547# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
548# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
549# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
550# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
551# define RADEON_FOG_SHADE_FLAT (1 << 14)
552# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
553# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
554# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
555# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
556# define RADEON_ROUND_MODE_TRUNC (0 << 28)
557# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
558#define RADEON_SE_CNTL_STATUS 0x2140
559#define RADEON_SE_LINE_WIDTH 0x1db8
560#define RADEON_SE_VPORT_XSCALE 0x1d98
561#define RADEON_SE_ZBIAS_FACTOR 0x1db0
562#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
563#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
564#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
565# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
566# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
567#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
568#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
569# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
570#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
571#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
572#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
573#define RADEON_SURFACE_CNTL 0x0b00
574# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
575# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
576# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
577# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
578# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
579# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
580# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
581# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
582# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
583#define RADEON_SURFACE0_INFO 0x0b0c
584# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
585# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
586# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
587# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
588# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
589# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
590#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
591#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
592# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
593#define RADEON_SURFACE1_INFO 0x0b1c
594#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
595#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
596#define RADEON_SURFACE2_INFO 0x0b2c
597#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
598#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
599#define RADEON_SURFACE3_INFO 0x0b3c
600#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
601#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
602#define RADEON_SURFACE4_INFO 0x0b4c
603#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
604#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
605#define RADEON_SURFACE5_INFO 0x0b5c
606#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
607#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
608#define RADEON_SURFACE6_INFO 0x0b6c
609#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
610#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
611#define RADEON_SURFACE7_INFO 0x0b7c
612#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
613#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
614#define RADEON_SW_SEMAPHORE 0x013c
615
616#define RADEON_WAIT_UNTIL 0x1720
617# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
618# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
619# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
620# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
621
622#define RADEON_RB3D_ZMASKOFFSET 0x3234
623#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
624# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
625# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
626
627
628/* CP registers */
629#define RADEON_CP_ME_RAM_ADDR 0x07d4
630#define RADEON_CP_ME_RAM_RADDR 0x07d8
631#define RADEON_CP_ME_RAM_DATAH 0x07dc
632#define RADEON_CP_ME_RAM_DATAL 0x07e0
633
634#define RADEON_CP_RB_BASE 0x0700
635#define RADEON_CP_RB_CNTL 0x0704
636# define RADEON_BUF_SWAP_32BIT (2 << 16)
637#define RADEON_CP_RB_RPTR_ADDR 0x070c
638#define RADEON_CP_RB_RPTR 0x0710
639#define RADEON_CP_RB_WPTR 0x0714
640
641#define RADEON_CP_RB_WPTR_DELAY 0x0718
642# define RADEON_PRE_WRITE_TIMER_SHIFT 0
643# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
644
645#define RADEON_CP_IB_BASE 0x0738
646
647#define RADEON_CP_CSQ_CNTL 0x0740
648# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
649# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
650# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
651# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
652# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
653# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
654# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
655
656#define RADEON_AIC_CNTL 0x01d0
657# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
658#define RADEON_AIC_STAT 0x01d4
659#define RADEON_AIC_PT_BASE 0x01d8
660#define RADEON_AIC_LO_ADDR 0x01dc
661#define RADEON_AIC_HI_ADDR 0x01e0
662#define RADEON_AIC_TLB_ADDR 0x01e4
663#define RADEON_AIC_TLB_DATA 0x01e8
664
665/* CP command packets */
666#define RADEON_CP_PACKET0 0x00000000
667# define RADEON_ONE_REG_WR (1 << 15)
668#define RADEON_CP_PACKET1 0x40000000
669#define RADEON_CP_PACKET2 0x80000000
670#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 671# define RADEON_CP_NOP 0x00001000
672# define RADEON_CP_NEXT_CHAR 0x00001900
673# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
674# define RADEON_CP_SET_SCISSORS 0x00001E00
675 /* GEN_INDX_PRIM is unsupported starting with R300 */
1da177e4
LT		 676# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
677# define RADEON_WAIT_FOR_IDLE 0x00002600
678# define RADEON_3D_DRAW_VBUF 0x00002800
679# define RADEON_3D_DRAW_IMMD 0x00002900
680# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 681# define RADEON_CP_LOAD_PALETTE 0x00002C00
1da177e4
LT		 682# define RADEON_3D_LOAD_VBPNTR 0x00002F00
683# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
684# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
685# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 686# define RADEON_CP_INDX_BUFFER 0x00003300
687# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
688# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
689# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 690# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 691# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1da177e4
LT		 692# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
693# define RADEON_CNTL_PAINT_MULTI 0x00009A00
694# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
695# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
696
697#define RADEON_CP_PACKET_MASK 0xC0000000
698#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
699#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
700#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
701#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
702
703#define RADEON_VTX_Z_PRESENT (1 << 31)
704#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
705
706#define RADEON_PRIM_TYPE_NONE (0 << 0)
707#define RADEON_PRIM_TYPE_POINT (1 << 0)
708#define RADEON_PRIM_TYPE_LINE (2 << 0)
709#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
710#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
711#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
712#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
713#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
714#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
715#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
716#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
717#define RADEON_PRIM_TYPE_MASK 0xf
718#define RADEON_PRIM_WALK_IND (1 << 4)
719#define RADEON_PRIM_WALK_LIST (2 << 4)
720#define RADEON_PRIM_WALK_RING (3 << 4)
721#define RADEON_COLOR_ORDER_BGRA (0 << 6)
722#define RADEON_COLOR_ORDER_RGBA (1 << 6)
723#define RADEON_MAOS_ENABLE (1 << 7)
724#define RADEON_VTX_FMT_R128_MODE (0 << 8)
725#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
726#define RADEON_NUM_VERTICES_SHIFT 16
727
728#define RADEON_COLOR_FORMAT_CI8 2
729#define RADEON_COLOR_FORMAT_ARGB1555 3
730#define RADEON_COLOR_FORMAT_RGB565 4
731#define RADEON_COLOR_FORMAT_ARGB8888 6
732#define RADEON_COLOR_FORMAT_RGB332 7
733#define RADEON_COLOR_FORMAT_RGB8 9
734#define RADEON_COLOR_FORMAT_ARGB4444 15
735
736#define RADEON_TXFORMAT_I8 0
737#define RADEON_TXFORMAT_AI88 1
738#define RADEON_TXFORMAT_RGB332 2
739#define RADEON_TXFORMAT_ARGB1555 3
740#define RADEON_TXFORMAT_RGB565 4
741#define RADEON_TXFORMAT_ARGB4444 5
742#define RADEON_TXFORMAT_ARGB8888 6
743#define RADEON_TXFORMAT_RGBA8888 7
744#define RADEON_TXFORMAT_Y8 8
745#define RADEON_TXFORMAT_VYUY422 10
746#define RADEON_TXFORMAT_YVYU422 11
747#define RADEON_TXFORMAT_DXT1 12
748#define RADEON_TXFORMAT_DXT23 14
749#define RADEON_TXFORMAT_DXT45 15
750
751#define R200_PP_TXCBLEND_0 0x2f00
752#define R200_PP_TXCBLEND_1 0x2f10
753#define R200_PP_TXCBLEND_2 0x2f20
754#define R200_PP_TXCBLEND_3 0x2f30
755#define R200_PP_TXCBLEND_4 0x2f40
756#define R200_PP_TXCBLEND_5 0x2f50
757#define R200_PP_TXCBLEND_6 0x2f60
758#define R200_PP_TXCBLEND_7 0x2f70
759#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
760#define R200_PP_TFACTOR_0 0x2ee0
761#define R200_SE_VTX_FMT_0 0x2088
762#define R200_SE_VAP_CNTL 0x2080
763#define R200_SE_TCL_MATRIX_SEL_0 0x2230
764#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
765#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
766#define R200_PP_TXFILTER_5 0x2ca0
767#define R200_PP_TXFILTER_4 0x2c80
768#define R200_PP_TXFILTER_3 0x2c60
769#define R200_PP_TXFILTER_2 0x2c40
770#define R200_PP_TXFILTER_1 0x2c20
771#define R200_PP_TXFILTER_0 0x2c00
772#define R200_PP_TXOFFSET_5 0x2d78
773#define R200_PP_TXOFFSET_4 0x2d60
774#define R200_PP_TXOFFSET_3 0x2d48
775#define R200_PP_TXOFFSET_2 0x2d30
776#define R200_PP_TXOFFSET_1 0x2d18
777#define R200_PP_TXOFFSET_0 0x2d00
778
779#define R200_PP_CUBIC_FACES_0 0x2c18
780#define R200_PP_CUBIC_FACES_1 0x2c38
781#define R200_PP_CUBIC_FACES_2 0x2c58
782#define R200_PP_CUBIC_FACES_3 0x2c78
783#define R200_PP_CUBIC_FACES_4 0x2c98
784#define R200_PP_CUBIC_FACES_5 0x2cb8
785#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
786#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
787#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
788#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
789#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
790#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
791#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
792#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
793#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
794#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
795#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
796#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
797#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
798#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
799#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
800#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
801#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
802#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
803#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
804#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
805#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
806#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
807#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
808#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
809#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
810#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
811#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
812#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
813#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
814#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
815
816#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
817#define R200_SE_VTE_CNTL 0x20b0
818#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
819#define R200_PP_TAM_DEBUG3 0x2d9c
820#define R200_PP_CNTL_X 0x2cc4
821#define R200_SE_VAP_CNTL_STATUS 0x2140
822#define R200_RE_SCISSOR_TL_0 0x1cd8
823#define R200_RE_SCISSOR_TL_1 0x1ce0
824#define R200_RE_SCISSOR_TL_2 0x1ce8
825#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
826#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
827#define R200_SE_VTX_STATE_CNTL 0x2180
828#define R200_RE_POINTSIZE 0x2648
829#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
830
831#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
832#define RADEON_PP_TEX_SIZE_1 0x1d0c
833#define RADEON_PP_TEX_SIZE_2 0x1d14
834
835#define RADEON_PP_CUBIC_FACES_0 0x1d24
836#define RADEON_PP_CUBIC_FACES_1 0x1d28
837#define RADEON_PP_CUBIC_FACES_2 0x1d2c
838#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
839#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
840#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
841
842#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
843#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
844#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
845#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
846#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
847#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
848#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
849#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
850#define R200_3D_DRAW_IMMD_2 0xC0003500
851#define R200_SE_VTX_FMT_1 0x208c
852#define R200_RE_CNTL 0x1c50
853
854#define R200_RB3D_BLENDCOLOR 0x3218
855
856#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
857
858#define R200_PP_TRI_PERF 0x2cf8
859
860/* Constants */
861#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
862
863#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
864#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
865#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
866#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
867#define RADEON_LAST_DISPATCH 1
868
869#define RADEON_MAX_VB_AGE 0x7fffffff
870#define RADEON_MAX_VB_VERTS (0xffff)
871
872#define RADEON_RING_HIGH_MARK 128
873
874#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
875#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
876#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
877#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
878
879#define RADEON_WRITE_PLL( addr, val ) \
880do { \
881 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
882 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
883 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
884} while (0)
885
886#define CP_PACKET0( reg, n ) \
887 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
888#define CP_PACKET0_TABLE( reg, n ) \
889 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
890#define CP_PACKET1( reg0, reg1 ) \
891 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
892#define CP_PACKET2() \
893 (RADEON_CP_PACKET2)
894#define CP_PACKET3( pkt, n ) \
895 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
896
897
898/* ================================================================
899 * Engine control helper macros
900 */
901
902#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
903 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
904 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
905 RADEON_WAIT_HOST_IDLECLEAN) ); \
906} while (0)
907
908#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
909 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
910 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
911 RADEON_WAIT_HOST_IDLECLEAN) ); \
912} while (0)
913
914#define RADEON_WAIT_UNTIL_IDLE() do { \
915 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
916 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
917 RADEON_WAIT_3D_IDLECLEAN | \
918 RADEON_WAIT_HOST_IDLECLEAN) ); \
919} while (0)
920
921#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
922 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
923 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
924} while (0)
925
926#define RADEON_FLUSH_CACHE() do { \
927 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
928 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
929} while (0)
930
931#define RADEON_PURGE_CACHE() do { \
932 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
933 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
934} while (0)
935
936#define RADEON_FLUSH_ZCACHE() do { \
937 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
938 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
939} while (0)
940
941#define RADEON_PURGE_ZCACHE() do { \
942 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
943 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
944} while (0)
945
946
947/* ================================================================
948 * Misc helper macros
949 */
950
951/* Perfbox functionality only.
952 */
953#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
954do { \
955 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
956 u32 head = GET_RING_HEAD( dev_priv ); \
957 if (head == dev_priv->ring.tail) \
958 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
959 } \
960} while (0)
961
962#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
963do { \
964 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
965 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
966 int __ret = radeon_do_cp_idle( dev_priv ); \
967 if ( __ret ) return __ret; \
968 sarea_priv->last_dispatch = 0; \
969 radeon_freelist_reset( dev ); \
970 } \
971} while (0)
972
973#define RADEON_DISPATCH_AGE( age ) do { \
974 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
975 OUT_RING( age ); \
976} while (0)
977
978#define RADEON_FRAME_AGE( age ) do { \
979 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
980 OUT_RING( age ); \
981} while (0)
982
983#define RADEON_CLEAR_AGE( age ) do { \
984 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
985 OUT_RING( age ); \
986} while (0)
987
988
989/* ================================================================
990 * Ring control
991 */
992
993#define RADEON_VERBOSE 0
994
995#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
996
997#define BEGIN_RING( n ) do { \
998 if ( RADEON_VERBOSE ) { \
999 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1000 n, __FUNCTION__ ); \
1001 } \
1002 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1003 COMMIT_RING(); \
1004 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1005 } \
1006 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1007 ring = dev_priv->ring.start; \
1008 write = dev_priv->ring.tail; \
1009 mask = dev_priv->ring.tail_mask; \
1010} while (0)
1011
1012#define ADVANCE_RING() do { \
1013 if ( RADEON_VERBOSE ) { \
1014 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1015 write, dev_priv->ring.tail ); \
1016 } \
1017 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1018 DRM_ERROR( \
1019 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1020 ((dev_priv->ring.tail + _nr) & mask), \
1021 write, __LINE__); \
1022 } else \
1023 dev_priv->ring.tail = write; \
1024} while (0)
1025
1026#define COMMIT_RING() do { \
1027 /* Flush writes to ring */ \
1028 DRM_MEMORYBARRIER(); \
1029 GET_RING_HEAD( dev_priv ); \
1030 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1031 /* read from PCI bus to ensure correct posting */ \
1032 RADEON_READ( RADEON_CP_RB_RPTR ); \
1033} while (0)
1034
1035#define OUT_RING( x ) do { \
1036 if ( RADEON_VERBOSE ) { \
1037 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1038 (unsigned int)(x), write ); \
1039 } \
1040 ring[write++] = (x); \
1041 write &= mask; \
1042} while (0)
1043
1044#define OUT_RING_REG( reg, val ) do { \
1045 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1046 OUT_RING( val ); \
1047} while (0)
1048
1049
1050#define OUT_RING_TABLE( tab, sz ) do { \
1051 int _size = (sz); \
1052 int *_tab = (int *)(tab); \
1053 \
1054 if (write + _size > mask) { \
1055 int _i = (mask+1) - write; \
1056 _size -= _i; \
1057 while (_i > 0 ) { \
1058 *(int *)(ring + write) = *_tab++; \
1059 write++; \
1060 _i--; \
1061 } \
1062 write = 0; \
1063 _tab += _i; \
1064 } \
1065 \
1066 while (_size > 0) { \
1067 *(ring + write) = *_tab++; \
1068 write++; \
1069 _size--; \
1070 } \
1071 write &= mask; \
1072} while (0)
1073
1074
1075#endif /* __RADEON_DRV_H__ */
Linux kernel - Deliverables
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