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drm: lindent the drm directory.
[deliverable/linux.git] / drivers / char / drm / radeon_drv.h
CommitLineData
1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
ea98a92f 41#define DRIVER_DATE "20050911"
1da177e4
LT		 42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 71 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading)
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 90 * 1.19- Add support for gart table in FB memory and PCIE r300
1da177e4
LT		 91 */
92#define DRIVER_MAJOR 1
ea98a92f 93#define DRIVER_MINOR 19
1da177e4
LT		 94#define DRIVER_PATCHLEVEL 0
95
96#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
97#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
98
99/*
100 * Radeon chip families
101 */
102enum radeon_family {
103 CHIP_R100,
104 CHIP_RS100,
105 CHIP_RV100,
106 CHIP_R200,
107 CHIP_RV200,
108 CHIP_RS200,
109 CHIP_R250,
110 CHIP_RS250,
111 CHIP_RV250,
112 CHIP_RV280,
113 CHIP_R300,
114 CHIP_RS300,
414ed537 115 CHIP_R350,
1da177e4 116 CHIP_RV350,
414ed537 117 CHIP_R420,
1da177e4
LT		 118 CHIP_LAST,
119};
120
121enum radeon_cp_microcode_version {
122 UCODE_R100,
123 UCODE_R200,
124 UCODE_R300,
125};
126
127/*
128 * Chip flags
129 */
130enum radeon_chip_flags {
131 CHIP_FAMILY_MASK = 0x0000ffffUL,
132 CHIP_FLAGS_MASK = 0xffff0000UL,
133 CHIP_IS_MOBILITY = 0x00010000UL,
134 CHIP_IS_IGP = 0x00020000UL,
135 CHIP_SINGLE_CRTC = 0x00040000UL,
136 CHIP_IS_AGP = 0x00080000UL,
b5e89ed5 137 CHIP_HAS_HIERZ = 0x00100000UL,
ea98a92f 138 CHIP_IS_PCIE = 0x00200000UL,
1da177e4
LT		 139};
140
141typedef struct drm_radeon_freelist {
b5e89ed5
DA		 142 unsigned int age;
143 drm_buf_t *buf;
144 struct drm_radeon_freelist *next;
145 struct drm_radeon_freelist *prev;
1da177e4
LT		 146} drm_radeon_freelist_t;
147
148typedef struct drm_radeon_ring_buffer {
149 u32 *start;
150 u32 *end;
151 int size;
152 int size_l2qw;
153
154 u32 tail;
155 u32 tail_mask;
156 int space;
157
158 int high_mark;
159} drm_radeon_ring_buffer_t;
160
161typedef struct drm_radeon_depth_clear_t {
162 u32 rb3d_cntl;
163 u32 rb3d_zstencilcntl;
164 u32 se_cntl;
165} drm_radeon_depth_clear_t;
166
167struct drm_radeon_driver_file_fields {
168 int64_t radeon_fb_delta;
169};
170
171struct mem_block {
172 struct mem_block *next;
173 struct mem_block *prev;
174 int start;
175 int size;
176 DRMFILE filp; /* 0: free, -1: heap, other: real files */
177};
178
179struct radeon_surface {
180 int refcount;
181 u32 lower;
182 u32 upper;
183 u32 flags;
184};
185
186struct radeon_virt_surface {
187 int surface_index;
188 u32 lower;
189 u32 upper;
190 u32 flags;
191 DRMFILE filp;
192};
193
194typedef struct drm_radeon_private {
195 drm_radeon_ring_buffer_t ring;
196 drm_radeon_sarea_t *sarea_priv;
197
198 u32 fb_location;
199
200 int gart_size;
201 u32 gart_vm_start;
202 unsigned long gart_buffers_offset;
203
204 int cp_mode;
205 int cp_running;
206
b5e89ed5
DA		 207 drm_radeon_freelist_t *head;
208 drm_radeon_freelist_t *tail;
1da177e4
LT		 209 int last_buf;
210 volatile u32 *scratch;
211 int writeback_works;
212
213 int usec_timeout;
214
215 int microcode_version;
216
217 int is_pci;
1da177e4
LT		 218
219 struct {
220 u32 boxes;
221 int freelist_timeouts;
222 int freelist_loops;
223 int requested_bufs;
224 int last_frame_reads;
225 int last_clear_reads;
226 int clears;
227 int texture_uploads;
228 } stats;
229
230 int do_boxes;
231 int page_flipping;
232 int current_page;
233
234 u32 color_fmt;
235 unsigned int front_offset;
236 unsigned int front_pitch;
237 unsigned int back_offset;
238 unsigned int back_pitch;
239
240 u32 depth_fmt;
241 unsigned int depth_offset;
242 unsigned int depth_pitch;
243
244 u32 front_pitch_offset;
245 u32 back_pitch_offset;
246 u32 depth_pitch_offset;
247
248 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 249
1da177e4
LT		 250 unsigned long fb_offset;
251 unsigned long mmio_offset;
252 unsigned long ring_offset;
253 unsigned long ring_rptr_offset;
254 unsigned long buffers_offset;
255 unsigned long gart_textures_offset;
256
257 drm_local_map_t *sarea;
258 drm_local_map_t *mmio;
259 drm_local_map_t *cp_ring;
260 drm_local_map_t *ring_rptr;
261 drm_local_map_t *gart_textures;
262
263 struct mem_block *gart_heap;
264 struct mem_block *fb_heap;
265
266 /* SW interrupt */
b5e89ed5
DA		 267 wait_queue_head_t swi_queue;
268 atomic_t swi_emitted;
1da177e4
LT		 269
270 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 271 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 272
b5e89ed5
DA		 273 unsigned long pcigart_offset;
274 drm_ati_pcigart_info gart_info;
ea98a92f 275
1da177e4
LT		 276 /* starting from here on, data is preserved accross an open */
277 uint32_t flags; /* see radeon_chip_flags */
278} drm_radeon_private_t;
279
280typedef struct drm_radeon_buf_priv {
281 u32 age;
282} drm_radeon_buf_priv_t;
283
284 /* radeon_cp.c */
b5e89ed5
DA		 285extern int radeon_cp_init(DRM_IOCTL_ARGS);
286extern int radeon_cp_start(DRM_IOCTL_ARGS);
287extern int radeon_cp_stop(DRM_IOCTL_ARGS);
288extern int radeon_cp_reset(DRM_IOCTL_ARGS);
289extern int radeon_cp_idle(DRM_IOCTL_ARGS);
290extern int radeon_cp_resume(DRM_IOCTL_ARGS);
291extern int radeon_engine_reset(DRM_IOCTL_ARGS);
292extern int radeon_fullscreen(DRM_IOCTL_ARGS);
293extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
1da177e4 294
b5e89ed5
DA		 295extern void radeon_freelist_reset(drm_device_t * dev);
296extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
1da177e4 297
b5e89ed5 298extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 299
b5e89ed5 300extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 301
302extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 303extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 304extern int radeon_driver_postcleanup(struct drm_device *dev);
305
b5e89ed5
DA		 306extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
307extern int radeon_mem_free(DRM_IOCTL_ARGS);
308extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
309extern void radeon_mem_takedown(struct mem_block **heap);
310extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
1da177e4
LT		 311
312 /* radeon_irq.c */
b5e89ed5
DA		 313extern int radeon_irq_emit(DRM_IOCTL_ARGS);
314extern int radeon_irq_wait(DRM_IOCTL_ARGS);
315
316extern void radeon_do_release(drm_device_t * dev);
317extern int radeon_driver_vblank_wait(drm_device_t * dev,
318 unsigned int *sequence);
319extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
320extern void radeon_driver_irq_preinstall(drm_device_t * dev);
321extern void radeon_driver_irq_postinstall(drm_device_t * dev);
322extern void radeon_driver_irq_uninstall(drm_device_t * dev);
323extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp);
324extern void radeon_driver_pretakedown(drm_device_t * dev);
325extern int radeon_driver_open_helper(drm_device_t * dev,
326 drm_file_t * filp_priv);
327extern void radeon_driver_free_filp_priv(drm_device_t * dev,
328 drm_file_t * filp_priv);
329
330extern int radeon_preinit(struct drm_device *dev, unsigned long flags);
331extern int radeon_postinit(struct drm_device *dev, unsigned long flags);
332extern int radeon_postcleanup(struct drm_device *dev);
1da177e4 333
9a186645
DA		 334extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
335 unsigned long arg);
336
414ed537
DA		 337/* r300_cmdbuf.c */
338extern void r300_init_reg_flags(void);
339
b5e89ed5
DA		 340extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
341 drm_file_t * filp_priv,
342 drm_radeon_cmd_buffer_t * cmdbuf);
414ed537 343
1da177e4
LT		 344/* Flags for stats.boxes
345 */
346#define RADEON_BOX_DMA_IDLE 0x1
347#define RADEON_BOX_RING_FULL 0x2
348#define RADEON_BOX_FLIP 0x4
349#define RADEON_BOX_WAIT_IDLE 0x8
350#define RADEON_BOX_TEXTURE_LOAD 0x10
351
1da177e4
LT		 352/* Register definitions, register access macros and drmAddMap constants
353 * for Radeon kernel driver.
354 */
355
356#define RADEON_AGP_COMMAND 0x0f60
357#define RADEON_AUX_SCISSOR_CNTL 0x26f0
358# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
359# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
360# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
361# define RADEON_SCISSOR_0_ENABLE (1 << 28)
362# define RADEON_SCISSOR_1_ENABLE (1 << 29)
363# define RADEON_SCISSOR_2_ENABLE (1 << 30)
364
365#define RADEON_BUS_CNTL 0x0030
366# define RADEON_BUS_MASTER_DIS (1 << 6)
367
368#define RADEON_CLOCK_CNTL_DATA 0x000c
369# define RADEON_PLL_WR_EN (1 << 7)
370#define RADEON_CLOCK_CNTL_INDEX 0x0008
371#define RADEON_CONFIG_APER_SIZE 0x0108
372#define RADEON_CRTC_OFFSET 0x0224
373#define RADEON_CRTC_OFFSET_CNTL 0x0228
374# define RADEON_CRTC_TILE_EN (1 << 15)
375# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
376#define RADEON_CRTC2_OFFSET 0x0324
377#define RADEON_CRTC2_OFFSET_CNTL 0x0328
378
ea98a92f
DA		 379#define RADEON_PCIE_INDEX 0x0030
380#define RADEON_PCIE_DATA 0x0034
381#define RADEON_PCIE_TX_GART_CNTL 0x10
382# define RADEON_PCIE_TX_GART_EN (1 << 0)
383# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
384# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
385# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
386# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
387# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
388# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
389# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
390#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
391#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
392#define RADEON_PCIE_TX_GART_BASE 0x13
393#define RADEON_PCIE_TX_GART_START_LO 0x14
394#define RADEON_PCIE_TX_GART_START_HI 0x15
395#define RADEON_PCIE_TX_GART_END_LO 0x16
396#define RADEON_PCIE_TX_GART_END_HI 0x17
397
414ed537
DA		 398#define RADEON_MPP_TB_CONFIG 0x01c0
399#define RADEON_MEM_CNTL 0x0140
400#define RADEON_MEM_SDRAM_MODE_REG 0x0158
401#define RADEON_AGP_BASE 0x0170
402
1da177e4
LT		 403#define RADEON_RB3D_COLOROFFSET 0x1c40
404#define RADEON_RB3D_COLORPITCH 0x1c48
405
406#define RADEON_DP_GUI_MASTER_CNTL 0x146c
407# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
408# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
409# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
410# define RADEON_GMC_BRUSH_NONE (15 << 4)
411# define RADEON_GMC_DST_16BPP (4 << 8)
412# define RADEON_GMC_DST_24BPP (5 << 8)
413# define RADEON_GMC_DST_32BPP (6 << 8)
414# define RADEON_GMC_DST_DATATYPE_SHIFT 8
415# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
416# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
417# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
418# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
419# define RADEON_GMC_WR_MSK_DIS (1 << 30)
420# define RADEON_ROP3_S 0x00cc0000
421# define RADEON_ROP3_P 0x00f00000
422#define RADEON_DP_WRITE_MASK 0x16cc
423#define RADEON_DST_PITCH_OFFSET 0x142c
424#define RADEON_DST_PITCH_OFFSET_C 0x1c80
425# define RADEON_DST_TILE_LINEAR (0 << 30)
426# define RADEON_DST_TILE_MACRO (1 << 30)
427# define RADEON_DST_TILE_MICRO (2 << 30)
428# define RADEON_DST_TILE_BOTH (3 << 30)
429
430#define RADEON_SCRATCH_REG0 0x15e0
431#define RADEON_SCRATCH_REG1 0x15e4
432#define RADEON_SCRATCH_REG2 0x15e8
433#define RADEON_SCRATCH_REG3 0x15ec
434#define RADEON_SCRATCH_REG4 0x15f0
435#define RADEON_SCRATCH_REG5 0x15f4
436#define RADEON_SCRATCH_UMSK 0x0770
437#define RADEON_SCRATCH_ADDR 0x0774
438
439#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
440
441#define GET_SCRATCH( x ) (dev_priv->writeback_works \
442 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
443 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
444
1da177e4
LT		 445#define RADEON_GEN_INT_CNTL 0x0040
446# define RADEON_CRTC_VBLANK_MASK (1 << 0)
447# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
448# define RADEON_SW_INT_ENABLE (1 << 25)
449
450#define RADEON_GEN_INT_STATUS 0x0044
451# define RADEON_CRTC_VBLANK_STAT (1 << 0)
452# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
453# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
454# define RADEON_SW_INT_TEST (1 << 25)
455# define RADEON_SW_INT_TEST_ACK (1 << 25)
456# define RADEON_SW_INT_FIRE (1 << 26)
457
458#define RADEON_HOST_PATH_CNTL 0x0130
459# define RADEON_HDP_SOFT_RESET (1 << 26)
460# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
461# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
462
463#define RADEON_ISYNC_CNTL 0x1724
464# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
465# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
466# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
467# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
468# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
469# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
470
471#define RADEON_RBBM_GUICNTL 0x172c
472# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
473# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
474# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
475# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
476
477#define RADEON_MC_AGP_LOCATION 0x014c
478#define RADEON_MC_FB_LOCATION 0x0148
479#define RADEON_MCLK_CNTL 0x0012
480# define RADEON_FORCEON_MCLKA (1 << 16)
481# define RADEON_FORCEON_MCLKB (1 << 17)
482# define RADEON_FORCEON_YCLKA (1 << 18)
483# define RADEON_FORCEON_YCLKB (1 << 19)
484# define RADEON_FORCEON_MC (1 << 20)
485# define RADEON_FORCEON_AIC (1 << 21)
486
487#define RADEON_PP_BORDER_COLOR_0 0x1d40
488#define RADEON_PP_BORDER_COLOR_1 0x1d44
489#define RADEON_PP_BORDER_COLOR_2 0x1d48
490#define RADEON_PP_CNTL 0x1c38
491# define RADEON_SCISSOR_ENABLE (1 << 1)
492#define RADEON_PP_LUM_MATRIX 0x1d00
493#define RADEON_PP_MISC 0x1c14
494#define RADEON_PP_ROT_MATRIX_0 0x1d58
495#define RADEON_PP_TXFILTER_0 0x1c54
496#define RADEON_PP_TXOFFSET_0 0x1c5c
497#define RADEON_PP_TXFILTER_1 0x1c6c
498#define RADEON_PP_TXFILTER_2 0x1c84
499
500#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
501# define RADEON_RB2D_DC_FLUSH (3 << 0)
502# define RADEON_RB2D_DC_FREE (3 << 2)
503# define RADEON_RB2D_DC_FLUSH_ALL 0xf
504# define RADEON_RB2D_DC_BUSY (1 << 31)
505#define RADEON_RB3D_CNTL 0x1c3c
506# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
507# define RADEON_PLANE_MASK_ENABLE (1 << 1)
508# define RADEON_DITHER_ENABLE (1 << 2)
509# define RADEON_ROUND_ENABLE (1 << 3)
510# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
511# define RADEON_DITHER_INIT (1 << 5)
512# define RADEON_ROP_ENABLE (1 << 6)
513# define RADEON_STENCIL_ENABLE (1 << 7)
514# define RADEON_Z_ENABLE (1 << 8)
515# define RADEON_ZBLOCK16 (1 << 15)
516#define RADEON_RB3D_DEPTHOFFSET 0x1c24
517#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
518#define RADEON_RB3D_DEPTHPITCH 0x1c28
519#define RADEON_RB3D_PLANEMASK 0x1d84
520#define RADEON_RB3D_STENCILREFMASK 0x1d7c
521#define RADEON_RB3D_ZCACHE_MODE 0x3250
522#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
523# define RADEON_RB3D_ZC_FLUSH (1 << 0)
524# define RADEON_RB3D_ZC_FREE (1 << 2)
525# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
526# define RADEON_RB3D_ZC_BUSY (1 << 31)
527#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
528# define RADEON_Z_TEST_MASK (7 << 4)
529# define RADEON_Z_TEST_ALWAYS (7 << 4)
530# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
531# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
532# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
533# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
534# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
535# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
536# define RADEON_FORCE_Z_DIRTY (1 << 29)
537# define RADEON_Z_WRITE_ENABLE (1 << 30)
538# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
539#define RADEON_RBBM_SOFT_RESET 0x00f0
540# define RADEON_SOFT_RESET_CP (1 << 0)
541# define RADEON_SOFT_RESET_HI (1 << 1)
542# define RADEON_SOFT_RESET_SE (1 << 2)
543# define RADEON_SOFT_RESET_RE (1 << 3)
544# define RADEON_SOFT_RESET_PP (1 << 4)
545# define RADEON_SOFT_RESET_E2 (1 << 5)
546# define RADEON_SOFT_RESET_RB (1 << 6)
547# define RADEON_SOFT_RESET_HDP (1 << 7)
548#define RADEON_RBBM_STATUS 0x0e40
549# define RADEON_RBBM_FIFOCNT_MASK 0x007f
550# define RADEON_RBBM_ACTIVE (1 << 31)
551#define RADEON_RE_LINE_PATTERN 0x1cd0
552#define RADEON_RE_MISC 0x26c4
553#define RADEON_RE_TOP_LEFT 0x26c0
554#define RADEON_RE_WIDTH_HEIGHT 0x1c44
555#define RADEON_RE_STIPPLE_ADDR 0x1cc8
556#define RADEON_RE_STIPPLE_DATA 0x1ccc
557
558#define RADEON_SCISSOR_TL_0 0x1cd8
559#define RADEON_SCISSOR_BR_0 0x1cdc
560#define RADEON_SCISSOR_TL_1 0x1ce0
561#define RADEON_SCISSOR_BR_1 0x1ce4
562#define RADEON_SCISSOR_TL_2 0x1ce8
563#define RADEON_SCISSOR_BR_2 0x1cec
564#define RADEON_SE_COORD_FMT 0x1c50
565#define RADEON_SE_CNTL 0x1c4c
566# define RADEON_FFACE_CULL_CW (0 << 0)
567# define RADEON_BFACE_SOLID (3 << 1)
568# define RADEON_FFACE_SOLID (3 << 3)
569# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
570# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
571# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
572# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
573# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
574# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
575# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
576# define RADEON_FOG_SHADE_FLAT (1 << 14)
577# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
578# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
579# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
580# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
581# define RADEON_ROUND_MODE_TRUNC (0 << 28)
582# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
583#define RADEON_SE_CNTL_STATUS 0x2140
584#define RADEON_SE_LINE_WIDTH 0x1db8
585#define RADEON_SE_VPORT_XSCALE 0x1d98
586#define RADEON_SE_ZBIAS_FACTOR 0x1db0
587#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
588#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
589#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
590# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
591# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
592#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
593#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
594# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
595#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
596#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
597#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
598#define RADEON_SURFACE_CNTL 0x0b00
599# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
600# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
601# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
602# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
603# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
604# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
605# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
606# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
607# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
608#define RADEON_SURFACE0_INFO 0x0b0c
609# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
610# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
611# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
612# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
613# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
614# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
615#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
616#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
617# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
618#define RADEON_SURFACE1_INFO 0x0b1c
619#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
620#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
621#define RADEON_SURFACE2_INFO 0x0b2c
622#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
623#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
624#define RADEON_SURFACE3_INFO 0x0b3c
625#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
626#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
627#define RADEON_SURFACE4_INFO 0x0b4c
628#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
629#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
630#define RADEON_SURFACE5_INFO 0x0b5c
631#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
632#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
633#define RADEON_SURFACE6_INFO 0x0b6c
634#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
635#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
636#define RADEON_SURFACE7_INFO 0x0b7c
637#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
638#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
639#define RADEON_SW_SEMAPHORE 0x013c
640
641#define RADEON_WAIT_UNTIL 0x1720
642# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
643# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
644# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
645# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
646
647#define RADEON_RB3D_ZMASKOFFSET 0x3234
648#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
649# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
650# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
651
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LT		 652/* CP registers */
653#define RADEON_CP_ME_RAM_ADDR 0x07d4
654#define RADEON_CP_ME_RAM_RADDR 0x07d8
655#define RADEON_CP_ME_RAM_DATAH 0x07dc
656#define RADEON_CP_ME_RAM_DATAL 0x07e0
657
658#define RADEON_CP_RB_BASE 0x0700
659#define RADEON_CP_RB_CNTL 0x0704
660# define RADEON_BUF_SWAP_32BIT (2 << 16)
661#define RADEON_CP_RB_RPTR_ADDR 0x070c
662#define RADEON_CP_RB_RPTR 0x0710
663#define RADEON_CP_RB_WPTR 0x0714
664
665#define RADEON_CP_RB_WPTR_DELAY 0x0718
666# define RADEON_PRE_WRITE_TIMER_SHIFT 0
667# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
668
669#define RADEON_CP_IB_BASE 0x0738
670
671#define RADEON_CP_CSQ_CNTL 0x0740
672# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
673# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
674# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
675# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
676# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
677# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
678# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
679
680#define RADEON_AIC_CNTL 0x01d0
681# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
682#define RADEON_AIC_STAT 0x01d4
683#define RADEON_AIC_PT_BASE 0x01d8
684#define RADEON_AIC_LO_ADDR 0x01dc
685#define RADEON_AIC_HI_ADDR 0x01e0
686#define RADEON_AIC_TLB_ADDR 0x01e4
687#define RADEON_AIC_TLB_DATA 0x01e8
688
689/* CP command packets */
690#define RADEON_CP_PACKET0 0x00000000
691# define RADEON_ONE_REG_WR (1 << 15)
692#define RADEON_CP_PACKET1 0x40000000
693#define RADEON_CP_PACKET2 0x80000000
694#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 695# define RADEON_CP_NOP 0x00001000
696# define RADEON_CP_NEXT_CHAR 0x00001900
697# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
698# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 699 /* GEN_INDX_PRIM is unsupported starting with R300 */
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LT		 700# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
701# define RADEON_WAIT_FOR_IDLE 0x00002600
702# define RADEON_3D_DRAW_VBUF 0x00002800
703# define RADEON_3D_DRAW_IMMD 0x00002900
704# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 705# define RADEON_CP_LOAD_PALETTE 0x00002C00
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LT		 706# define RADEON_3D_LOAD_VBPNTR 0x00002F00
707# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
708# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
709# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 710# define RADEON_CP_INDX_BUFFER 0x00003300
711# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
712# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
713# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 714# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 715# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
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LT		 716# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
717# define RADEON_CNTL_PAINT_MULTI 0x00009A00
718# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
719# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
720
721#define RADEON_CP_PACKET_MASK 0xC0000000
722#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
723#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
724#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
725#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
726
727#define RADEON_VTX_Z_PRESENT (1 << 31)
728#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
729
730#define RADEON_PRIM_TYPE_NONE (0 << 0)
731#define RADEON_PRIM_TYPE_POINT (1 << 0)
732#define RADEON_PRIM_TYPE_LINE (2 << 0)
733#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
734#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
735#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
736#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
737#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
738#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
739#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
740#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
741#define RADEON_PRIM_TYPE_MASK 0xf
742#define RADEON_PRIM_WALK_IND (1 << 4)
743#define RADEON_PRIM_WALK_LIST (2 << 4)
744#define RADEON_PRIM_WALK_RING (3 << 4)
745#define RADEON_COLOR_ORDER_BGRA (0 << 6)
746#define RADEON_COLOR_ORDER_RGBA (1 << 6)
747#define RADEON_MAOS_ENABLE (1 << 7)
748#define RADEON_VTX_FMT_R128_MODE (0 << 8)
749#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
750#define RADEON_NUM_VERTICES_SHIFT 16
751
752#define RADEON_COLOR_FORMAT_CI8 2
753#define RADEON_COLOR_FORMAT_ARGB1555 3
754#define RADEON_COLOR_FORMAT_RGB565 4
755#define RADEON_COLOR_FORMAT_ARGB8888 6
756#define RADEON_COLOR_FORMAT_RGB332 7
757#define RADEON_COLOR_FORMAT_RGB8 9
758#define RADEON_COLOR_FORMAT_ARGB4444 15
759
760#define RADEON_TXFORMAT_I8 0
761#define RADEON_TXFORMAT_AI88 1
762#define RADEON_TXFORMAT_RGB332 2
763#define RADEON_TXFORMAT_ARGB1555 3
764#define RADEON_TXFORMAT_RGB565 4
765#define RADEON_TXFORMAT_ARGB4444 5
766#define RADEON_TXFORMAT_ARGB8888 6
767#define RADEON_TXFORMAT_RGBA8888 7
768#define RADEON_TXFORMAT_Y8 8
769#define RADEON_TXFORMAT_VYUY422 10
770#define RADEON_TXFORMAT_YVYU422 11
771#define RADEON_TXFORMAT_DXT1 12
772#define RADEON_TXFORMAT_DXT23 14
773#define RADEON_TXFORMAT_DXT45 15
774
775#define R200_PP_TXCBLEND_0 0x2f00
776#define R200_PP_TXCBLEND_1 0x2f10
777#define R200_PP_TXCBLEND_2 0x2f20
778#define R200_PP_TXCBLEND_3 0x2f30
779#define R200_PP_TXCBLEND_4 0x2f40
780#define R200_PP_TXCBLEND_5 0x2f50
781#define R200_PP_TXCBLEND_6 0x2f60
782#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 783#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1da177e4
LT		 784#define R200_PP_TFACTOR_0 0x2ee0
785#define R200_SE_VTX_FMT_0 0x2088
786#define R200_SE_VAP_CNTL 0x2080
787#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 788#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
789#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
790#define R200_PP_TXFILTER_5 0x2ca0
791#define R200_PP_TXFILTER_4 0x2c80
792#define R200_PP_TXFILTER_3 0x2c60
793#define R200_PP_TXFILTER_2 0x2c40
794#define R200_PP_TXFILTER_1 0x2c20
795#define R200_PP_TXFILTER_0 0x2c00
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LT		 796#define R200_PP_TXOFFSET_5 0x2d78
797#define R200_PP_TXOFFSET_4 0x2d60
798#define R200_PP_TXOFFSET_3 0x2d48
799#define R200_PP_TXOFFSET_2 0x2d30
800#define R200_PP_TXOFFSET_1 0x2d18
801#define R200_PP_TXOFFSET_0 0x2d00
802
803#define R200_PP_CUBIC_FACES_0 0x2c18
804#define R200_PP_CUBIC_FACES_1 0x2c38
805#define R200_PP_CUBIC_FACES_2 0x2c58
806#define R200_PP_CUBIC_FACES_3 0x2c78
807#define R200_PP_CUBIC_FACES_4 0x2c98
808#define R200_PP_CUBIC_FACES_5 0x2cb8
809#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
810#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
811#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
812#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
813#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
814#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
815#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
816#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
817#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
818#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
819#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
820#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
821#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
822#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
823#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
824#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
825#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
826#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
827#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
828#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
829#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
830#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
831#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
832#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
833#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
834#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
835#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
836#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
837#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
838#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
839
840#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
841#define R200_SE_VTE_CNTL 0x20b0
842#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
843#define R200_PP_TAM_DEBUG3 0x2d9c
844#define R200_PP_CNTL_X 0x2cc4
845#define R200_SE_VAP_CNTL_STATUS 0x2140
846#define R200_RE_SCISSOR_TL_0 0x1cd8
847#define R200_RE_SCISSOR_TL_1 0x1ce0
848#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 849#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1da177e4
LT		 850#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
851#define R200_SE_VTX_STATE_CNTL 0x2180
852#define R200_RE_POINTSIZE 0x2648
853#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
854
b5e89ed5 855#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
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LT		 856#define RADEON_PP_TEX_SIZE_1 0x1d0c
857#define RADEON_PP_TEX_SIZE_2 0x1d14
858
859#define RADEON_PP_CUBIC_FACES_0 0x1d24
860#define RADEON_PP_CUBIC_FACES_1 0x1d28
861#define RADEON_PP_CUBIC_FACES_2 0x1d2c
862#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
863#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
864#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
865
866#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
867#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
868#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
869#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
870#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
871#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
872#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
873#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
874#define R200_3D_DRAW_IMMD_2 0xC0003500
875#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 876#define R200_RE_CNTL 0x1c50
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LT		 877
878#define R200_RB3D_BLENDCOLOR 0x3218
879
880#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
881
882#define R200_PP_TRI_PERF 0x2cf8
883
9d17601c 884#define R200_PP_AFS_0 0x2f80
b5e89ed5 885#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 886
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LT		 887/* Constants */
888#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
889
890#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
891#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
892#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
893#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
894#define RADEON_LAST_DISPATCH 1
895
896#define RADEON_MAX_VB_AGE 0x7fffffff
897#define RADEON_MAX_VB_VERTS (0xffff)
898
899#define RADEON_RING_HIGH_MARK 128
900
ea98a92f
DA		 901#define RADEON_PCIGART_TABLE_SIZE (32*1024)
902
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LT		 903#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
904#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
905#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
906#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
907
908#define RADEON_WRITE_PLL( addr, val ) \
909do { \
910 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
911 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
912 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
913} while (0)
914
ea98a92f
DA		 915#define RADEON_WRITE_PCIE( addr, val ) \
916do { \
917 RADEON_WRITE8( RADEON_PCIE_INDEX, \
918 ((addr) & 0xff)); \
919 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
920} while (0)
921
1da177e4
LT		 922#define CP_PACKET0( reg, n ) \
923 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
924#define CP_PACKET0_TABLE( reg, n ) \
925 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
926#define CP_PACKET1( reg0, reg1 ) \
927 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
928#define CP_PACKET2() \
929 (RADEON_CP_PACKET2)
930#define CP_PACKET3( pkt, n ) \
931 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
932
1da177e4
LT		 933/* ================================================================
934 * Engine control helper macros
935 */
936
937#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
938 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
939 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
940 RADEON_WAIT_HOST_IDLECLEAN) ); \
941} while (0)
942
943#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
944 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
945 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
946 RADEON_WAIT_HOST_IDLECLEAN) ); \
947} while (0)
948
949#define RADEON_WAIT_UNTIL_IDLE() do { \
950 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
951 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
952 RADEON_WAIT_3D_IDLECLEAN | \
953 RADEON_WAIT_HOST_IDLECLEAN) ); \
954} while (0)
955
956#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
957 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
958 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
959} while (0)
960
961#define RADEON_FLUSH_CACHE() do { \
962 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
963 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
964} while (0)
965
966#define RADEON_PURGE_CACHE() do { \
967 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
968 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
969} while (0)
970
971#define RADEON_FLUSH_ZCACHE() do { \
972 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
973 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
974} while (0)
975
976#define RADEON_PURGE_ZCACHE() do { \
977 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
978 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
979} while (0)
980
1da177e4
LT		 981/* ================================================================
982 * Misc helper macros
983 */
984
b5e89ed5 985/* Perfbox functionality only.
1da177e4
LT		 986 */
987#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
988do { \
989 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
990 u32 head = GET_RING_HEAD( dev_priv ); \
991 if (head == dev_priv->ring.tail) \
992 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
993 } \
994} while (0)
995
996#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
997do { \
998 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
999 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1000 int __ret = radeon_do_cp_idle( dev_priv ); \
1001 if ( __ret ) return __ret; \
1002 sarea_priv->last_dispatch = 0; \
1003 radeon_freelist_reset( dev ); \
1004 } \
1005} while (0)
1006
1007#define RADEON_DISPATCH_AGE( age ) do { \
1008 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1009 OUT_RING( age ); \
1010} while (0)
1011
1012#define RADEON_FRAME_AGE( age ) do { \
1013 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1014 OUT_RING( age ); \
1015} while (0)
1016
1017#define RADEON_CLEAR_AGE( age ) do { \
1018 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1019 OUT_RING( age ); \
1020} while (0)
1021
1da177e4
LT		 1022/* ================================================================
1023 * Ring control
1024 */
1025
1026#define RADEON_VERBOSE 0
1027
1028#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1029
1030#define BEGIN_RING( n ) do { \
1031 if ( RADEON_VERBOSE ) { \
1032 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1033 n, __FUNCTION__ ); \
1034 } \
1035 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1036 COMMIT_RING(); \
1037 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1038 } \
1039 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1040 ring = dev_priv->ring.start; \
1041 write = dev_priv->ring.tail; \
1042 mask = dev_priv->ring.tail_mask; \
1043} while (0)
1044
1045#define ADVANCE_RING() do { \
1046 if ( RADEON_VERBOSE ) { \
1047 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1048 write, dev_priv->ring.tail ); \
1049 } \
1050 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1051 DRM_ERROR( \
1052 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1053 ((dev_priv->ring.tail + _nr) & mask), \
1054 write, __LINE__); \
1055 } else \
1056 dev_priv->ring.tail = write; \
1057} while (0)
1058
1059#define COMMIT_RING() do { \
1060 /* Flush writes to ring */ \
1061 DRM_MEMORYBARRIER(); \
1062 GET_RING_HEAD( dev_priv ); \
1063 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1064 /* read from PCI bus to ensure correct posting */ \
1065 RADEON_READ( RADEON_CP_RB_RPTR ); \
1066} while (0)
1067
1068#define OUT_RING( x ) do { \
1069 if ( RADEON_VERBOSE ) { \
1070 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1071 (unsigned int)(x), write ); \
1072 } \
1073 ring[write++] = (x); \
1074 write &= mask; \
1075} while (0)
1076
1077#define OUT_RING_REG( reg, val ) do { \
1078 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1079 OUT_RING( val ); \
1080} while (0)
1081
1da177e4
LT		 1082#define OUT_RING_TABLE( tab, sz ) do { \
1083 int _size = (sz); \
1084 int *_tab = (int *)(tab); \
1085 \
1086 if (write + _size > mask) { \
1087 int _i = (mask+1) - write; \
1088 _size -= _i; \
1089 while (_i > 0 ) { \
1090 *(int *)(ring + write) = *_tab++; \
1091 write++; \
1092 _i--; \
1093 } \
1094 write = 0; \
1095 _tab += _i; \
1096 } \
1097 \
1098 while (_size > 0) { \
1099 *(ring + write) = *_tab++; \
1100 write++; \
1101 _size--; \
1102 } \
1103 write &= mask; \
1104} while (0)
1105
b5e89ed5 1106#endif /* __RADEON_DRV_H__ */
Linux kernel - Deliverables
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