Commit | Line | Data |
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22f579c6 | 1 | /* via_dma.c -- DMA support for the VIA Unichrome/Pro |
b5e89ed5 | 2 | * |
22f579c6 DA |
3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. | |
7 | * All Rights Reserved. | |
b5e89ed5 | 8 | * |
22f579c6 DA |
9 | * Copyright 2004 The Unichrome project. |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the | |
20 | * next paragraph) shall be included in all copies or substantial portions | |
21 | * of the Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
b5e89ed5 DA |
26 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
27 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
28 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
22f579c6 DA |
29 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
30 | * | |
b5e89ed5 DA |
31 | * Authors: |
32 | * Tungsten Graphics, | |
33 | * Erdi Chen, | |
22f579c6 DA |
34 | * Thomas Hellstrom. |
35 | */ | |
36 | ||
37 | #include "drmP.h" | |
38 | #include "drm.h" | |
39 | #include "via_drm.h" | |
40 | #include "via_drv.h" | |
41 | #include "via_3d_reg.h" | |
42 | ||
43 | #define CMDBUF_ALIGNMENT_SIZE (0x100) | |
44 | #define CMDBUF_ALIGNMENT_MASK (0x0ff) | |
45 | ||
46 | /* defines for VIA 3D registers */ | |
47 | #define VIA_REG_STATUS 0x400 | |
48 | #define VIA_REG_TRANSET 0x43C | |
49 | #define VIA_REG_TRANSPACE 0x440 | |
50 | ||
51 | /* VIA_REG_STATUS(0x400): Engine Status */ | |
52 | #define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ | |
53 | #define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ | |
54 | #define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ | |
55 | #define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ | |
56 | ||
57 | #define SetReg2DAGP(nReg, nData) { \ | |
58 | *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \ | |
59 | *((uint32_t *)(vb) + 1) = (nData); \ | |
60 | vb = ((uint32_t *)vb) + 2; \ | |
61 | dev_priv->dma_low +=8; \ | |
62 | } | |
63 | ||
b5e89ed5 | 64 | #define via_flush_write_combine() DRM_MEMORYBARRIER() |
22f579c6 DA |
65 | |
66 | #define VIA_OUT_RING_QW(w1,w2) \ | |
67 | *vb++ = (w1); \ | |
68 | *vb++ = (w2); \ | |
b5e89ed5 | 69 | dev_priv->dma_low += 8; |
22f579c6 DA |
70 | |
71 | static void via_cmdbuf_start(drm_via_private_t * dev_priv); | |
72 | static void via_cmdbuf_pause(drm_via_private_t * dev_priv); | |
73 | static void via_cmdbuf_reset(drm_via_private_t * dev_priv); | |
74 | static void via_cmdbuf_rewind(drm_via_private_t * dev_priv); | |
75 | static int via_wait_idle(drm_via_private_t * dev_priv); | |
b5e89ed5 | 76 | static void via_pad_cache(drm_via_private_t * dev_priv, int qwords); |
22f579c6 DA |
77 | |
78 | /* | |
79 | * Free space in command buffer. | |
80 | */ | |
81 | ||
b5e89ed5 | 82 | static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv) |
22f579c6 | 83 | { |
b5e89ed5 | 84 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
22f579c6 | 85 | uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; |
b5e89ed5 DA |
86 | |
87 | return ((hw_addr <= dev_priv->dma_low) ? | |
88 | (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : | |
22f579c6 DA |
89 | (hw_addr - dev_priv->dma_low)); |
90 | } | |
91 | ||
92 | /* | |
93 | * How much does the command regulator lag behind? | |
94 | */ | |
95 | ||
b5e89ed5 | 96 | static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv) |
22f579c6 | 97 | { |
b5e89ed5 | 98 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
22f579c6 | 99 | uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; |
b5e89ed5 DA |
100 | |
101 | return ((hw_addr <= dev_priv->dma_low) ? | |
102 | (dev_priv->dma_low - hw_addr) : | |
22f579c6 DA |
103 | (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); |
104 | } | |
105 | ||
106 | /* | |
107 | * Check that the given size fits in the buffer, otherwise wait. | |
108 | */ | |
109 | ||
110 | static inline int | |
111 | via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size) | |
112 | { | |
113 | uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
114 | uint32_t cur_addr, hw_addr, next_addr; | |
115 | volatile uint32_t *hw_addr_ptr; | |
116 | uint32_t count; | |
117 | hw_addr_ptr = dev_priv->hw_addr_ptr; | |
118 | cur_addr = dev_priv->dma_low; | |
b5e89ed5 | 119 | next_addr = cur_addr + size + 512 * 1024; |
22f579c6 DA |
120 | count = 1000000; |
121 | do { | |
b5e89ed5 | 122 | hw_addr = *hw_addr_ptr - agp_base; |
22f579c6 | 123 | if (count-- == 0) { |
b5e89ed5 DA |
124 | DRM_ERROR |
125 | ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n", | |
126 | hw_addr, cur_addr, next_addr); | |
22f579c6 DA |
127 | return -1; |
128 | } | |
129 | } while ((cur_addr < hw_addr) && (next_addr >= hw_addr)); | |
130 | return 0; | |
131 | } | |
132 | ||
22f579c6 DA |
133 | /* |
134 | * Checks whether buffer head has reach the end. Rewind the ring buffer | |
135 | * when necessary. | |
136 | * | |
137 | * Returns virtual pointer to ring buffer. | |
138 | */ | |
139 | ||
140 | static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, | |
141 | unsigned int size) | |
142 | { | |
b5e89ed5 DA |
143 | if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) > |
144 | dev_priv->dma_high) { | |
22f579c6 DA |
145 | via_cmdbuf_rewind(dev_priv); |
146 | } | |
147 | if (via_cmdbuf_wait(dev_priv, size) != 0) { | |
148 | return NULL; | |
149 | } | |
150 | ||
151 | return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); | |
152 | } | |
153 | ||
154 | int via_dma_cleanup(drm_device_t * dev) | |
155 | { | |
156 | if (dev->dev_private) { | |
157 | drm_via_private_t *dev_priv = | |
b5e89ed5 | 158 | (drm_via_private_t *) dev->dev_private; |
22f579c6 DA |
159 | |
160 | if (dev_priv->ring.virtual_start) { | |
161 | via_cmdbuf_reset(dev_priv); | |
162 | ||
163 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
164 | dev_priv->ring.virtual_start = NULL; | |
165 | } | |
166 | ||
167 | } | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | static int via_initialize(drm_device_t * dev, | |
173 | drm_via_private_t * dev_priv, | |
174 | drm_via_dma_init_t * init) | |
175 | { | |
176 | if (!dev_priv || !dev_priv->mmio) { | |
177 | DRM_ERROR("via_dma_init called before via_map_init\n"); | |
178 | return DRM_ERR(EFAULT); | |
179 | } | |
180 | ||
181 | if (dev_priv->ring.virtual_start != NULL) { | |
182 | DRM_ERROR("%s called again without calling cleanup\n", | |
183 | __FUNCTION__); | |
184 | return DRM_ERR(EFAULT); | |
185 | } | |
186 | ||
187 | if (!dev->agp || !dev->agp->base) { | |
b5e89ed5 | 188 | DRM_ERROR("%s called with no agp memory available\n", |
22f579c6 DA |
189 | __FUNCTION__); |
190 | return DRM_ERR(EFAULT); | |
191 | } | |
192 | ||
193 | dev_priv->ring.map.offset = dev->agp->base + init->offset; | |
194 | dev_priv->ring.map.size = init->size; | |
195 | dev_priv->ring.map.type = 0; | |
196 | dev_priv->ring.map.flags = 0; | |
197 | dev_priv->ring.map.mtrr = 0; | |
198 | ||
199 | drm_core_ioremap(&dev_priv->ring.map, dev); | |
200 | ||
201 | if (dev_priv->ring.map.handle == NULL) { | |
202 | via_dma_cleanup(dev); | |
203 | DRM_ERROR("can not ioremap virtual address for" | |
204 | " ring buffer\n"); | |
205 | return DRM_ERR(ENOMEM); | |
206 | } | |
207 | ||
208 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
209 | ||
210 | dev_priv->dma_ptr = dev_priv->ring.virtual_start; | |
211 | dev_priv->dma_low = 0; | |
212 | dev_priv->dma_high = init->size; | |
213 | dev_priv->dma_wrap = init->size; | |
214 | dev_priv->dma_offset = init->offset; | |
215 | dev_priv->last_pause_ptr = NULL; | |
92514243 DA |
216 | dev_priv->hw_addr_ptr = |
217 | (volatile uint32_t *)((char *)dev_priv->mmio->handle + | |
218 | init->reg_pause_addr); | |
22f579c6 DA |
219 | |
220 | via_cmdbuf_start(dev_priv); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
ce60fe02 | 225 | static int via_dma_init(DRM_IOCTL_ARGS) |
22f579c6 DA |
226 | { |
227 | DRM_DEVICE; | |
228 | drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; | |
229 | drm_via_dma_init_t init; | |
230 | int retcode = 0; | |
231 | ||
bbaf3641 | 232 | DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data, |
22f579c6 DA |
233 | sizeof(init)); |
234 | ||
235 | switch (init.func) { | |
236 | case VIA_INIT_DMA: | |
92514243 | 237 | if (!DRM_SUSER(DRM_CURPROC)) |
22f579c6 DA |
238 | retcode = DRM_ERR(EPERM); |
239 | else | |
240 | retcode = via_initialize(dev, dev_priv, &init); | |
241 | break; | |
242 | case VIA_CLEANUP_DMA: | |
92514243 | 243 | if (!DRM_SUSER(DRM_CURPROC)) |
22f579c6 DA |
244 | retcode = DRM_ERR(EPERM); |
245 | else | |
246 | retcode = via_dma_cleanup(dev); | |
247 | break; | |
b5e89ed5 DA |
248 | case VIA_DMA_INITIALIZED: |
249 | retcode = (dev_priv->ring.virtual_start != NULL) ? | |
250 | 0 : DRM_ERR(EFAULT); | |
251 | break; | |
22f579c6 DA |
252 | default: |
253 | retcode = DRM_ERR(EINVAL); | |
254 | break; | |
255 | } | |
256 | ||
257 | return retcode; | |
258 | } | |
259 | ||
22f579c6 DA |
260 | static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) |
261 | { | |
262 | drm_via_private_t *dev_priv; | |
263 | uint32_t *vb; | |
264 | int ret; | |
265 | ||
266 | dev_priv = (drm_via_private_t *) dev->dev_private; | |
267 | ||
268 | if (dev_priv->ring.virtual_start == NULL) { | |
269 | DRM_ERROR("%s called without initializing AGP ring buffer.\n", | |
270 | __FUNCTION__); | |
271 | return DRM_ERR(EFAULT); | |
272 | } | |
273 | ||
274 | if (cmd->size > VIA_PCI_BUF_SIZE) { | |
275 | return DRM_ERR(ENOMEM); | |
b5e89ed5 | 276 | } |
22f579c6 DA |
277 | |
278 | if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) | |
279 | return DRM_ERR(EFAULT); | |
280 | ||
281 | /* | |
282 | * Running this function on AGP memory is dead slow. Therefore | |
283 | * we run it on a temporary cacheable system memory buffer and | |
284 | * copy it to AGP memory when ready. | |
285 | */ | |
286 | ||
b5e89ed5 DA |
287 | if ((ret = |
288 | via_verify_command_stream((uint32_t *) dev_priv->pci_buf, | |
289 | cmd->size, dev, 1))) { | |
22f579c6 DA |
290 | return ret; |
291 | } | |
b5e89ed5 | 292 | |
22f579c6 DA |
293 | vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); |
294 | if (vb == NULL) { | |
295 | return DRM_ERR(EAGAIN); | |
296 | } | |
297 | ||
298 | memcpy(vb, dev_priv->pci_buf, cmd->size); | |
b5e89ed5 | 299 | |
22f579c6 DA |
300 | dev_priv->dma_low += cmd->size; |
301 | ||
302 | /* | |
303 | * Small submissions somehow stalls the CPU. (AGP cache effects?) | |
304 | * pad to greater size. | |
305 | */ | |
306 | ||
307 | if (cmd->size < 0x100) | |
b5e89ed5 | 308 | via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3); |
22f579c6 DA |
309 | via_cmdbuf_pause(dev_priv); |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | int via_driver_dma_quiescent(drm_device_t * dev) | |
315 | { | |
316 | drm_via_private_t *dev_priv = dev->dev_private; | |
317 | ||
318 | if (!via_wait_idle(dev_priv)) { | |
319 | return DRM_ERR(EBUSY); | |
320 | } | |
321 | return 0; | |
322 | } | |
323 | ||
ce60fe02 | 324 | static int via_flush_ioctl(DRM_IOCTL_ARGS) |
22f579c6 DA |
325 | { |
326 | DRM_DEVICE; | |
327 | ||
b5e89ed5 | 328 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 DA |
329 | |
330 | return via_driver_dma_quiescent(dev); | |
331 | } | |
332 | ||
ce60fe02 | 333 | static int via_cmdbuffer(DRM_IOCTL_ARGS) |
22f579c6 DA |
334 | { |
335 | DRM_DEVICE; | |
336 | drm_via_cmdbuffer_t cmdbuf; | |
337 | int ret; | |
338 | ||
b5e89ed5 | 339 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 | 340 | |
bbaf3641 | 341 | DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, |
22f579c6 DA |
342 | sizeof(cmdbuf)); |
343 | ||
344 | DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size); | |
345 | ||
346 | ret = via_dispatch_cmdbuffer(dev, &cmdbuf); | |
347 | if (ret) { | |
348 | return ret; | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
22f579c6 DA |
354 | static int via_dispatch_pci_cmdbuffer(drm_device_t * dev, |
355 | drm_via_cmdbuffer_t * cmd) | |
356 | { | |
357 | drm_via_private_t *dev_priv = dev->dev_private; | |
358 | int ret; | |
359 | ||
360 | if (cmd->size > VIA_PCI_BUF_SIZE) { | |
361 | return DRM_ERR(ENOMEM); | |
b5e89ed5 | 362 | } |
22f579c6 DA |
363 | if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) |
364 | return DRM_ERR(EFAULT); | |
b5e89ed5 DA |
365 | |
366 | if ((ret = | |
367 | via_verify_command_stream((uint32_t *) dev_priv->pci_buf, | |
368 | cmd->size, dev, 0))) { | |
22f579c6 DA |
369 | return ret; |
370 | } | |
b5e89ed5 DA |
371 | |
372 | ret = | |
373 | via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, | |
374 | cmd->size); | |
22f579c6 DA |
375 | return ret; |
376 | } | |
377 | ||
ce60fe02 | 378 | static int via_pci_cmdbuffer(DRM_IOCTL_ARGS) |
22f579c6 DA |
379 | { |
380 | DRM_DEVICE; | |
381 | drm_via_cmdbuffer_t cmdbuf; | |
382 | int ret; | |
383 | ||
b5e89ed5 | 384 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 | 385 | |
bbaf3641 | 386 | DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, |
22f579c6 DA |
387 | sizeof(cmdbuf)); |
388 | ||
389 | DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf, | |
390 | cmdbuf.size); | |
391 | ||
392 | ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf); | |
393 | if (ret) { | |
394 | return ret; | |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
22f579c6 DA |
400 | static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv, |
401 | uint32_t * vb, int qw_count) | |
402 | { | |
b5e89ed5 | 403 | for (; qw_count > 0; --qw_count) { |
22f579c6 DA |
404 | VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY); |
405 | } | |
406 | return vb; | |
407 | } | |
408 | ||
22f579c6 DA |
409 | /* |
410 | * This function is used internally by ring buffer mangement code. | |
411 | * | |
412 | * Returns virtual pointer to ring buffer. | |
413 | */ | |
414 | static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv) | |
415 | { | |
416 | return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); | |
417 | } | |
418 | ||
419 | /* | |
420 | * Hooks a segment of data into the tail of the ring-buffer by | |
421 | * modifying the pause address stored in the buffer itself. If | |
422 | * the regulator has already paused, restart it. | |
423 | */ | |
b5e89ed5 | 424 | static int via_hook_segment(drm_via_private_t * dev_priv, |
22f579c6 DA |
425 | uint32_t pause_addr_hi, uint32_t pause_addr_lo, |
426 | int no_pci_fire) | |
427 | { | |
428 | int paused, count; | |
429 | volatile uint32_t *paused_at = dev_priv->last_pause_ptr; | |
430 | ||
431 | via_flush_write_combine(); | |
b5e89ed5 | 432 | while (!*(via_get_dma(dev_priv) - 1)) ; |
22f579c6 DA |
433 | *dev_priv->last_pause_ptr = pause_addr_lo; |
434 | via_flush_write_combine(); | |
435 | ||
436 | /* | |
437 | * The below statement is inserted to really force the flush. | |
438 | * Not sure it is needed. | |
439 | */ | |
440 | ||
b5e89ed5 | 441 | while (!*dev_priv->last_pause_ptr) ; |
22f579c6 | 442 | dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; |
b5e89ed5 | 443 | while (!*dev_priv->last_pause_ptr) ; |
22f579c6 DA |
444 | |
445 | paused = 0; | |
b5e89ed5 | 446 | count = 20; |
22f579c6 | 447 | |
b5e89ed5 | 448 | while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--) ; |
22f579c6 DA |
449 | if ((count <= 8) && (count >= 0)) { |
450 | uint32_t rgtr, ptr; | |
451 | rgtr = *(dev_priv->hw_addr_ptr); | |
92514243 DA |
452 | ptr = ((volatile char *)dev_priv->last_pause_ptr - |
453 | dev_priv->dma_ptr) + dev_priv->dma_offset + | |
454 | (uint32_t) dev_priv->agpAddr + 4 - CMDBUF_ALIGNMENT_SIZE; | |
22f579c6 | 455 | if (rgtr <= ptr) { |
b5e89ed5 DA |
456 | DRM_ERROR |
457 | ("Command regulator\npaused at count %d, address %x, " | |
458 | "while current pause address is %x.\n" | |
459 | "Please mail this message to " | |
460 | "<unichrome-devel@lists.sourceforge.net>\n", count, | |
461 | rgtr, ptr); | |
22f579c6 DA |
462 | } |
463 | } | |
b5e89ed5 | 464 | |
22f579c6 | 465 | if (paused && !no_pci_fire) { |
b5e89ed5 | 466 | uint32_t rgtr, ptr; |
22f579c6 DA |
467 | uint32_t ptr_low; |
468 | ||
469 | count = 1000000; | |
b5e89ed5 DA |
470 | while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) |
471 | && count--) ; | |
472 | ||
22f579c6 | 473 | rgtr = *(dev_priv->hw_addr_ptr); |
92514243 | 474 | ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + |
b5e89ed5 | 475 | dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; |
22f579c6 | 476 | |
b5e89ed5 DA |
477 | ptr_low = (ptr > 3 * CMDBUF_ALIGNMENT_SIZE) ? |
478 | ptr - 3 * CMDBUF_ALIGNMENT_SIZE : 0; | |
22f579c6 DA |
479 | if (rgtr <= ptr && rgtr >= ptr_low) { |
480 | VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); | |
481 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); | |
482 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); | |
b5e89ed5 | 483 | } |
22f579c6 DA |
484 | } |
485 | return paused; | |
486 | } | |
487 | ||
22f579c6 DA |
488 | static int via_wait_idle(drm_via_private_t * dev_priv) |
489 | { | |
490 | int count = 10000000; | |
491 | while (count-- && (VIA_READ(VIA_REG_STATUS) & | |
492 | (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | | |
493 | VIA_3D_ENG_BUSY))) ; | |
494 | return count; | |
495 | } | |
496 | ||
497 | static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type, | |
b5e89ed5 DA |
498 | uint32_t addr, uint32_t * cmd_addr_hi, |
499 | uint32_t * cmd_addr_lo, int skip_wait) | |
22f579c6 DA |
500 | { |
501 | uint32_t agp_base; | |
502 | uint32_t cmd_addr, addr_lo, addr_hi; | |
503 | uint32_t *vb; | |
504 | uint32_t qw_pad_count; | |
505 | ||
506 | if (!skip_wait) | |
b5e89ed5 | 507 | via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE); |
22f579c6 DA |
508 | |
509 | vb = via_get_dma(dev_priv); | |
b5e89ed5 DA |
510 | VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) | |
511 | (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16); | |
22f579c6 DA |
512 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; |
513 | qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) - | |
b5e89ed5 | 514 | ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); |
22f579c6 | 515 | |
b5e89ed5 DA |
516 | cmd_addr = (addr) ? addr : |
517 | agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3); | |
22f579c6 DA |
518 | addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) | |
519 | (cmd_addr & HC_HAGPBpL_MASK)); | |
520 | addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24)); | |
521 | ||
522 | vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1); | |
b5e89ed5 | 523 | VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo); |
22f579c6 DA |
524 | return vb; |
525 | } | |
526 | ||
22f579c6 DA |
527 | static void via_cmdbuf_start(drm_via_private_t * dev_priv) |
528 | { | |
529 | uint32_t pause_addr_lo, pause_addr_hi; | |
530 | uint32_t start_addr, start_addr_lo; | |
531 | uint32_t end_addr, end_addr_lo; | |
532 | uint32_t command; | |
533 | uint32_t agp_base; | |
534 | ||
22f579c6 DA |
535 | dev_priv->dma_low = 0; |
536 | ||
537 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
538 | start_addr = agp_base; | |
539 | end_addr = agp_base + dev_priv->dma_high; | |
540 | ||
541 | start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF)); | |
542 | end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF)); | |
543 | command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) | | |
544 | ((end_addr & 0xff000000) >> 16)); | |
545 | ||
b5e89ed5 DA |
546 | dev_priv->last_pause_ptr = |
547 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, | |
548 | &pause_addr_hi, &pause_addr_lo, 1) - 1; | |
22f579c6 DA |
549 | |
550 | via_flush_write_combine(); | |
b5e89ed5 | 551 | while (!*dev_priv->last_pause_ptr) ; |
22f579c6 DA |
552 | |
553 | VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); | |
554 | VIA_WRITE(VIA_REG_TRANSPACE, command); | |
555 | VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo); | |
556 | VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo); | |
557 | ||
558 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); | |
559 | VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); | |
560 | ||
561 | VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); | |
562 | } | |
563 | ||
b5e89ed5 | 564 | static void via_pad_cache(drm_via_private_t * dev_priv, int qwords) |
22f579c6 DA |
565 | { |
566 | uint32_t *vb; | |
567 | ||
568 | via_cmdbuf_wait(dev_priv, qwords + 2); | |
569 | vb = via_get_dma(dev_priv); | |
b5e89ed5 DA |
570 | VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16); |
571 | via_align_buffer(dev_priv, vb, qwords); | |
22f579c6 DA |
572 | } |
573 | ||
574 | static inline void via_dummy_bitblt(drm_via_private_t * dev_priv) | |
575 | { | |
576 | uint32_t *vb = via_get_dma(dev_priv); | |
577 | SetReg2DAGP(0x0C, (0 | (0 << 16))); | |
578 | SetReg2DAGP(0x10, 0 | (0 << 16)); | |
b5e89ed5 | 579 | SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); |
22f579c6 DA |
580 | } |
581 | ||
22f579c6 DA |
582 | static void via_cmdbuf_jump(drm_via_private_t * dev_priv) |
583 | { | |
584 | uint32_t agp_base; | |
585 | uint32_t pause_addr_lo, pause_addr_hi; | |
586 | uint32_t jump_addr_lo, jump_addr_hi; | |
587 | volatile uint32_t *last_pause_ptr; | |
588 | uint32_t dma_low_save1, dma_low_save2; | |
589 | ||
590 | agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; | |
b5e89ed5 | 591 | via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, |
22f579c6 | 592 | &jump_addr_lo, 0); |
22f579c6 | 593 | |
b5e89ed5 | 594 | dev_priv->dma_wrap = dev_priv->dma_low; |
22f579c6 DA |
595 | |
596 | /* | |
597 | * Wrap command buffer to the beginning. | |
598 | */ | |
599 | ||
600 | dev_priv->dma_low = 0; | |
601 | if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) { | |
602 | DRM_ERROR("via_cmdbuf_jump failed\n"); | |
603 | } | |
604 | ||
605 | via_dummy_bitblt(dev_priv); | |
b5e89ed5 | 606 | via_dummy_bitblt(dev_priv); |
22f579c6 | 607 | |
b5e89ed5 DA |
608 | last_pause_ptr = |
609 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
610 | &pause_addr_lo, 0) - 1; | |
611 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
22f579c6 DA |
612 | &pause_addr_lo, 0); |
613 | ||
614 | *last_pause_ptr = pause_addr_lo; | |
615 | dma_low_save1 = dev_priv->dma_low; | |
616 | ||
617 | /* | |
618 | * Now, set a trap that will pause the regulator if it tries to rerun the old | |
619 | * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause | |
620 | * and reissues the jump command over PCI, while the regulator has already taken the jump | |
621 | * and actually paused at the current buffer end). | |
622 | * There appears to be no other way to detect this condition, since the hw_addr_pointer | |
623 | * does not seem to get updated immediately when a jump occurs. | |
624 | */ | |
625 | ||
b5e89ed5 DA |
626 | last_pause_ptr = |
627 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
628 | &pause_addr_lo, 0) - 1; | |
629 | via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, | |
22f579c6 DA |
630 | &pause_addr_lo, 0); |
631 | *last_pause_ptr = pause_addr_lo; | |
632 | ||
633 | dma_low_save2 = dev_priv->dma_low; | |
b5e89ed5 DA |
634 | dev_priv->dma_low = dma_low_save1; |
635 | via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0); | |
22f579c6 | 636 | dev_priv->dma_low = dma_low_save2; |
b5e89ed5 | 637 | via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); |
22f579c6 DA |
638 | } |
639 | ||
22f579c6 DA |
640 | static void via_cmdbuf_rewind(drm_via_private_t * dev_priv) |
641 | { | |
b5e89ed5 | 642 | via_cmdbuf_jump(dev_priv); |
22f579c6 DA |
643 | } |
644 | ||
645 | static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type) | |
646 | { | |
647 | uint32_t pause_addr_lo, pause_addr_hi; | |
648 | ||
649 | via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0); | |
b5e89ed5 | 650 | via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); |
22f579c6 DA |
651 | } |
652 | ||
22f579c6 DA |
653 | static void via_cmdbuf_pause(drm_via_private_t * dev_priv) |
654 | { | |
655 | via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE); | |
656 | } | |
657 | ||
658 | static void via_cmdbuf_reset(drm_via_private_t * dev_priv) | |
659 | { | |
660 | via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP); | |
661 | via_wait_idle(dev_priv); | |
662 | } | |
663 | ||
664 | /* | |
665 | * User interface to the space and lag functions. | |
666 | */ | |
667 | ||
ce60fe02 | 668 | static int via_cmdbuf_size(DRM_IOCTL_ARGS) |
22f579c6 DA |
669 | { |
670 | DRM_DEVICE; | |
671 | drm_via_cmdbuf_size_t d_siz; | |
672 | int ret = 0; | |
673 | uint32_t tmp_size, count; | |
674 | drm_via_private_t *dev_priv; | |
675 | ||
676 | DRM_DEBUG("via cmdbuf_size\n"); | |
b5e89ed5 | 677 | LOCK_TEST_WITH_RETURN(dev, filp); |
22f579c6 DA |
678 | |
679 | dev_priv = (drm_via_private_t *) dev->dev_private; | |
680 | ||
681 | if (dev_priv->ring.virtual_start == NULL) { | |
682 | DRM_ERROR("%s called without initializing AGP ring buffer.\n", | |
683 | __FUNCTION__); | |
684 | return DRM_ERR(EFAULT); | |
685 | } | |
686 | ||
bbaf3641 | 687 | DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data, |
22f579c6 DA |
688 | sizeof(d_siz)); |
689 | ||
22f579c6 DA |
690 | count = 1000000; |
691 | tmp_size = d_siz.size; | |
b5e89ed5 | 692 | switch (d_siz.func) { |
22f579c6 | 693 | case VIA_CMDBUF_SPACE: |
b5e89ed5 DA |
694 | while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size) |
695 | && count--) { | |
22f579c6 DA |
696 | if (!d_siz.wait) { |
697 | break; | |
698 | } | |
699 | } | |
700 | if (!count) { | |
701 | DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n"); | |
702 | ret = DRM_ERR(EAGAIN); | |
703 | } | |
704 | break; | |
705 | case VIA_CMDBUF_LAG: | |
b5e89ed5 DA |
706 | while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size) |
707 | && count--) { | |
22f579c6 DA |
708 | if (!d_siz.wait) { |
709 | break; | |
710 | } | |
711 | } | |
712 | if (!count) { | |
713 | DRM_ERROR("VIA_CMDBUF_LAG timed out.\n"); | |
714 | ret = DRM_ERR(EAGAIN); | |
715 | } | |
716 | break; | |
717 | default: | |
718 | ret = DRM_ERR(EFAULT); | |
719 | } | |
720 | d_siz.size = tmp_size; | |
721 | ||
bbaf3641 | 722 | DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz, |
22f579c6 DA |
723 | sizeof(d_siz)); |
724 | return ret; | |
725 | } | |
92514243 DA |
726 | |
727 | drm_ioctl_desc_t via_ioctls[] = { | |
a7a2cc31 DA |
728 | [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH}, |
729 | [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH}, | |
730 | [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER}, | |
731 | [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER}, | |
732 | [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER}, | |
733 | [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH}, | |
734 | [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH}, | |
735 | [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH}, | |
736 | [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH}, | |
737 | [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH}, | |
738 | [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH}, | |
443448d0 DA |
739 | [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH}, |
740 | [DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH}, | |
741 | [DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH} | |
92514243 DA |
742 | }; |
743 | ||
744 | int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls); |