Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
76832c28 | 2 | * Timer device implementation for SGI SN platforms. |
1da177e4 LT |
3 | * |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
76832c28 | 8 | * Copyright (c) 2001-2006 Silicon Graphics, Inc. All rights reserved. |
1da177e4 LT |
9 | * |
10 | * This driver exports an API that should be supportable by any HPET or IA-PC | |
11 | * multimedia timer. The code below is currently specific to the SGI Altix | |
12 | * SHub RTC, however. | |
13 | * | |
14 | * 11/01/01 - jbarnes - initial revision | |
15 | * 9/10/04 - Christoph Lameter - remove interrupt support for kernel inclusion | |
16 | * 10/1/04 - Christoph Lameter - provide posix clock CLOCK_SGI_CYCLE | |
17 | * 10/13/04 - Christoph Lameter, Dimitri Sivanich - provide timer interrupt | |
18 | * support via the posix timer interface | |
19 | */ | |
20 | ||
21 | #include <linux/types.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/ioctl.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/mm.h> | |
4e950f6f | 28 | #include <linux/fs.h> |
1da177e4 LT |
29 | #include <linux/mmtimer.h> |
30 | #include <linux/miscdevice.h> | |
31 | #include <linux/posix-timers.h> | |
32 | #include <linux/interrupt.h> | |
33 | ||
34 | #include <asm/uaccess.h> | |
35 | #include <asm/sn/addrs.h> | |
36 | #include <asm/sn/intr.h> | |
37 | #include <asm/sn/shub_mmr.h> | |
38 | #include <asm/sn/nodepda.h> | |
39 | #include <asm/sn/shubio.h> | |
40 | ||
41 | MODULE_AUTHOR("Jesse Barnes <jbarnes@sgi.com>"); | |
42 | MODULE_DESCRIPTION("SGI Altix RTC Timer"); | |
43 | MODULE_LICENSE("GPL"); | |
44 | ||
45 | /* name of the device, usually in /dev */ | |
46 | #define MMTIMER_NAME "mmtimer" | |
47 | #define MMTIMER_DESC "SGI Altix RTC Timer" | |
76832c28 | 48 | #define MMTIMER_VERSION "2.1" |
1da177e4 LT |
49 | |
50 | #define RTC_BITS 55 /* 55 bits for this implementation */ | |
51 | ||
52 | extern unsigned long sn_rtc_cycles_per_second; | |
53 | ||
54 | #define RTC_COUNTER_ADDR ((long *)LOCAL_MMR_ADDR(SH_RTC)) | |
55 | ||
56 | #define rtc_time() (*RTC_COUNTER_ADDR) | |
57 | ||
58 | static int mmtimer_ioctl(struct inode *inode, struct file *file, | |
59 | unsigned int cmd, unsigned long arg); | |
60 | static int mmtimer_mmap(struct file *file, struct vm_area_struct *vma); | |
61 | ||
62 | /* | |
63 | * Period in femtoseconds (10^-15 s) | |
64 | */ | |
65 | static unsigned long mmtimer_femtoperiod = 0; | |
66 | ||
62322d25 | 67 | static const struct file_operations mmtimer_fops = { |
1da177e4 LT |
68 | .owner = THIS_MODULE, |
69 | .mmap = mmtimer_mmap, | |
70 | .ioctl = mmtimer_ioctl, | |
71 | }; | |
72 | ||
73 | /* | |
74 | * We only have comparison registers RTC1-4 currently available per | |
75 | * node. RTC0 is used by SAL. | |
76 | */ | |
1da177e4 | 77 | /* Check for an RTC interrupt pending */ |
cbacdd95 | 78 | static int mmtimer_int_pending(int comparator) |
1da177e4 LT |
79 | { |
80 | if (HUB_L((unsigned long *)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)) & | |
81 | SH_EVENT_OCCURRED_RTC1_INT_MASK << comparator) | |
82 | return 1; | |
83 | else | |
84 | return 0; | |
85 | } | |
cbacdd95 | 86 | |
1da177e4 | 87 | /* Clear the RTC interrupt pending bit */ |
cbacdd95 | 88 | static void mmtimer_clr_int_pending(int comparator) |
1da177e4 LT |
89 | { |
90 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), | |
91 | SH_EVENT_OCCURRED_RTC1_INT_MASK << comparator); | |
92 | } | |
93 | ||
94 | /* Setup timer on comparator RTC1 */ | |
cbacdd95 | 95 | static void mmtimer_setup_int_0(int cpu, u64 expires) |
1da177e4 LT |
96 | { |
97 | u64 val; | |
98 | ||
99 | /* Disable interrupt */ | |
100 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_ENABLE), 0UL); | |
101 | ||
102 | /* Initialize comparator value */ | |
103 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPB), -1L); | |
104 | ||
105 | /* Clear pending bit */ | |
106 | mmtimer_clr_int_pending(0); | |
107 | ||
108 | val = ((u64)SGI_MMTIMER_VECTOR << SH_RTC1_INT_CONFIG_IDX_SHFT) | | |
cbacdd95 | 109 | ((u64)cpu_physical_id(cpu) << |
1da177e4 LT |
110 | SH_RTC1_INT_CONFIG_PID_SHFT); |
111 | ||
112 | /* Set configuration */ | |
113 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_CONFIG), val); | |
114 | ||
115 | /* Enable RTC interrupts */ | |
116 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_ENABLE), 1UL); | |
117 | ||
118 | /* Initialize comparator value */ | |
119 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPB), expires); | |
120 | ||
121 | ||
122 | } | |
123 | ||
124 | /* Setup timer on comparator RTC2 */ | |
cbacdd95 | 125 | static void mmtimer_setup_int_1(int cpu, u64 expires) |
1da177e4 LT |
126 | { |
127 | u64 val; | |
128 | ||
129 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_ENABLE), 0UL); | |
130 | ||
131 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPC), -1L); | |
132 | ||
133 | mmtimer_clr_int_pending(1); | |
134 | ||
135 | val = ((u64)SGI_MMTIMER_VECTOR << SH_RTC2_INT_CONFIG_IDX_SHFT) | | |
cbacdd95 | 136 | ((u64)cpu_physical_id(cpu) << |
1da177e4 LT |
137 | SH_RTC2_INT_CONFIG_PID_SHFT); |
138 | ||
139 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_CONFIG), val); | |
140 | ||
141 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_ENABLE), 1UL); | |
142 | ||
143 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPC), expires); | |
144 | } | |
145 | ||
146 | /* Setup timer on comparator RTC3 */ | |
cbacdd95 | 147 | static void mmtimer_setup_int_2(int cpu, u64 expires) |
1da177e4 LT |
148 | { |
149 | u64 val; | |
150 | ||
151 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_ENABLE), 0UL); | |
152 | ||
153 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPD), -1L); | |
154 | ||
155 | mmtimer_clr_int_pending(2); | |
156 | ||
157 | val = ((u64)SGI_MMTIMER_VECTOR << SH_RTC3_INT_CONFIG_IDX_SHFT) | | |
cbacdd95 | 158 | ((u64)cpu_physical_id(cpu) << |
1da177e4 LT |
159 | SH_RTC3_INT_CONFIG_PID_SHFT); |
160 | ||
161 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_CONFIG), val); | |
162 | ||
163 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_ENABLE), 1UL); | |
164 | ||
165 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPD), expires); | |
166 | } | |
167 | ||
168 | /* | |
169 | * This function must be called with interrupts disabled and preemption off | |
170 | * in order to insure that the setup succeeds in a deterministic time frame. | |
171 | * It will check if the interrupt setup succeeded. | |
172 | */ | |
cbacdd95 | 173 | static int mmtimer_setup(int cpu, int comparator, unsigned long expires) |
1da177e4 LT |
174 | { |
175 | ||
176 | switch (comparator) { | |
177 | case 0: | |
cbacdd95 | 178 | mmtimer_setup_int_0(cpu, expires); |
1da177e4 LT |
179 | break; |
180 | case 1: | |
cbacdd95 | 181 | mmtimer_setup_int_1(cpu, expires); |
1da177e4 LT |
182 | break; |
183 | case 2: | |
cbacdd95 | 184 | mmtimer_setup_int_2(cpu, expires); |
1da177e4 LT |
185 | break; |
186 | } | |
187 | /* We might've missed our expiration time */ | |
cbacdd95 | 188 | if (rtc_time() <= expires) |
1da177e4 LT |
189 | return 1; |
190 | ||
191 | /* | |
192 | * If an interrupt is already pending then its okay | |
193 | * if not then we failed | |
194 | */ | |
195 | return mmtimer_int_pending(comparator); | |
196 | } | |
197 | ||
cbacdd95 | 198 | static int mmtimer_disable_int(long nasid, int comparator) |
1da177e4 LT |
199 | { |
200 | switch (comparator) { | |
201 | case 0: | |
202 | nasid == -1 ? HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_ENABLE), | |
203 | 0UL) : REMOTE_HUB_S(nasid, SH_RTC1_INT_ENABLE, 0UL); | |
204 | break; | |
205 | case 1: | |
206 | nasid == -1 ? HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_ENABLE), | |
207 | 0UL) : REMOTE_HUB_S(nasid, SH_RTC2_INT_ENABLE, 0UL); | |
208 | break; | |
209 | case 2: | |
210 | nasid == -1 ? HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_ENABLE), | |
211 | 0UL) : REMOTE_HUB_S(nasid, SH_RTC3_INT_ENABLE, 0UL); | |
212 | break; | |
213 | default: | |
214 | return -EFAULT; | |
215 | } | |
216 | return 0; | |
217 | } | |
218 | ||
cbacdd95 | 219 | #define COMPARATOR 1 /* The comparator to use */ |
1da177e4 | 220 | |
cbacdd95 DS |
221 | #define TIMER_OFF 0xbadcabLL /* Timer is not setup */ |
222 | #define TIMER_SET 0 /* Comparator is set for this timer */ | |
223 | ||
224 | /* There is one of these for each timer */ | |
225 | struct mmtimer { | |
226 | struct rb_node list; | |
1da177e4 | 227 | struct k_itimer *timer; |
1da177e4 | 228 | int cpu; |
cbacdd95 DS |
229 | }; |
230 | ||
231 | struct mmtimer_node { | |
232 | spinlock_t lock ____cacheline_aligned; | |
233 | struct rb_root timer_head; | |
234 | struct rb_node *next; | |
1da177e4 | 235 | struct tasklet_struct tasklet; |
cbacdd95 DS |
236 | }; |
237 | static struct mmtimer_node *timers; | |
238 | ||
239 | ||
240 | /* | |
241 | * Add a new mmtimer struct to the node's mmtimer list. | |
242 | * This function assumes the struct mmtimer_node is locked. | |
243 | */ | |
244 | static void mmtimer_add_list(struct mmtimer *n) | |
245 | { | |
246 | int nodeid = n->timer->it.mmtimer.node; | |
247 | unsigned long expires = n->timer->it.mmtimer.expires; | |
248 | struct rb_node **link = &timers[nodeid].timer_head.rb_node; | |
249 | struct rb_node *parent = NULL; | |
250 | struct mmtimer *x; | |
251 | ||
252 | /* | |
253 | * Find the right place in the rbtree: | |
254 | */ | |
255 | while (*link) { | |
256 | parent = *link; | |
257 | x = rb_entry(parent, struct mmtimer, list); | |
258 | ||
259 | if (expires < x->timer->it.mmtimer.expires) | |
260 | link = &(*link)->rb_left; | |
261 | else | |
262 | link = &(*link)->rb_right; | |
263 | } | |
264 | ||
265 | /* | |
266 | * Insert the timer to the rbtree and check whether it | |
267 | * replaces the first pending timer | |
268 | */ | |
269 | rb_link_node(&n->list, parent, link); | |
270 | rb_insert_color(&n->list, &timers[nodeid].timer_head); | |
271 | ||
272 | if (!timers[nodeid].next || expires < rb_entry(timers[nodeid].next, | |
273 | struct mmtimer, list)->timer->it.mmtimer.expires) | |
274 | timers[nodeid].next = &n->list; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Set the comparator for the next timer. | |
279 | * This function assumes the struct mmtimer_node is locked. | |
280 | */ | |
281 | static void mmtimer_set_next_timer(int nodeid) | |
282 | { | |
283 | struct mmtimer_node *n = &timers[nodeid]; | |
284 | struct mmtimer *x; | |
285 | struct k_itimer *t; | |
286 | int o; | |
287 | ||
288 | restart: | |
289 | if (n->next == NULL) | |
290 | return; | |
1da177e4 | 291 | |
cbacdd95 DS |
292 | x = rb_entry(n->next, struct mmtimer, list); |
293 | t = x->timer; | |
294 | if (!t->it.mmtimer.incr) { | |
295 | /* Not an interval timer */ | |
296 | if (!mmtimer_setup(x->cpu, COMPARATOR, | |
297 | t->it.mmtimer.expires)) { | |
298 | /* Late setup, fire now */ | |
299 | tasklet_schedule(&n->tasklet); | |
300 | } | |
301 | return; | |
302 | } | |
303 | ||
304 | /* Interval timer */ | |
305 | o = 0; | |
306 | while (!mmtimer_setup(x->cpu, COMPARATOR, t->it.mmtimer.expires)) { | |
307 | unsigned long e, e1; | |
308 | struct rb_node *next; | |
309 | t->it.mmtimer.expires += t->it.mmtimer.incr << o; | |
310 | t->it_overrun += 1 << o; | |
311 | o++; | |
312 | if (o > 20) { | |
313 | printk(KERN_ALERT "mmtimer: cannot reschedule timer\n"); | |
314 | t->it.mmtimer.clock = TIMER_OFF; | |
315 | n->next = rb_next(&x->list); | |
316 | rb_erase(&x->list, &n->timer_head); | |
317 | kfree(x); | |
318 | goto restart; | |
319 | } | |
320 | ||
321 | e = t->it.mmtimer.expires; | |
322 | next = rb_next(&x->list); | |
323 | ||
324 | if (next == NULL) | |
325 | continue; | |
326 | ||
327 | e1 = rb_entry(next, struct mmtimer, list)-> | |
328 | timer->it.mmtimer.expires; | |
329 | if (e > e1) { | |
330 | n->next = next; | |
331 | rb_erase(&x->list, &n->timer_head); | |
332 | mmtimer_add_list(x); | |
333 | goto restart; | |
334 | } | |
335 | } | |
336 | } | |
1da177e4 LT |
337 | |
338 | /** | |
339 | * mmtimer_ioctl - ioctl interface for /dev/mmtimer | |
340 | * @inode: inode of the device | |
341 | * @file: file structure for the device | |
342 | * @cmd: command to execute | |
343 | * @arg: optional argument to command | |
344 | * | |
345 | * Executes the command specified by @cmd. Returns 0 for success, < 0 for | |
346 | * failure. | |
347 | * | |
348 | * Valid commands: | |
349 | * | |
350 | * %MMTIMER_GETOFFSET - Should return the offset (relative to the start | |
351 | * of the page where the registers are mapped) for the counter in question. | |
352 | * | |
353 | * %MMTIMER_GETRES - Returns the resolution of the clock in femto (10^-15) | |
354 | * seconds | |
355 | * | |
356 | * %MMTIMER_GETFREQ - Copies the frequency of the clock in Hz to the address | |
357 | * specified by @arg | |
358 | * | |
359 | * %MMTIMER_GETBITS - Returns the number of bits in the clock's counter | |
360 | * | |
361 | * %MMTIMER_MMAPAVAIL - Returns 1 if the registers can be mmap'd into userspace | |
362 | * | |
363 | * %MMTIMER_GETCOUNTER - Gets the current value in the counter and places it | |
364 | * in the address specified by @arg. | |
365 | */ | |
366 | static int mmtimer_ioctl(struct inode *inode, struct file *file, | |
367 | unsigned int cmd, unsigned long arg) | |
368 | { | |
369 | int ret = 0; | |
370 | ||
371 | switch (cmd) { | |
372 | case MMTIMER_GETOFFSET: /* offset of the counter */ | |
373 | /* | |
374 | * SN RTC registers are on their own 64k page | |
375 | */ | |
376 | if(PAGE_SIZE <= (1 << 16)) | |
377 | ret = (((long)RTC_COUNTER_ADDR) & (PAGE_SIZE-1)) / 8; | |
378 | else | |
379 | ret = -ENOSYS; | |
380 | break; | |
381 | ||
382 | case MMTIMER_GETRES: /* resolution of the clock in 10^-15 s */ | |
383 | if(copy_to_user((unsigned long __user *)arg, | |
384 | &mmtimer_femtoperiod, sizeof(unsigned long))) | |
385 | return -EFAULT; | |
386 | break; | |
387 | ||
388 | case MMTIMER_GETFREQ: /* frequency in Hz */ | |
389 | if(copy_to_user((unsigned long __user *)arg, | |
390 | &sn_rtc_cycles_per_second, | |
391 | sizeof(unsigned long))) | |
392 | return -EFAULT; | |
393 | ret = 0; | |
394 | break; | |
395 | ||
396 | case MMTIMER_GETBITS: /* number of bits in the clock */ | |
397 | ret = RTC_BITS; | |
398 | break; | |
399 | ||
400 | case MMTIMER_MMAPAVAIL: /* can we mmap the clock into userspace? */ | |
401 | ret = (PAGE_SIZE <= (1 << 16)) ? 1 : 0; | |
402 | break; | |
403 | ||
404 | case MMTIMER_GETCOUNTER: | |
405 | if(copy_to_user((unsigned long __user *)arg, | |
406 | RTC_COUNTER_ADDR, sizeof(unsigned long))) | |
407 | return -EFAULT; | |
408 | break; | |
409 | default: | |
410 | ret = -ENOSYS; | |
411 | break; | |
412 | } | |
413 | ||
414 | return ret; | |
415 | } | |
416 | ||
417 | /** | |
418 | * mmtimer_mmap - maps the clock's registers into userspace | |
419 | * @file: file structure for the device | |
420 | * @vma: VMA to map the registers into | |
421 | * | |
422 | * Calls remap_pfn_range() to map the clock's registers into | |
423 | * the calling process' address space. | |
424 | */ | |
425 | static int mmtimer_mmap(struct file *file, struct vm_area_struct *vma) | |
426 | { | |
427 | unsigned long mmtimer_addr; | |
428 | ||
429 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) | |
430 | return -EINVAL; | |
431 | ||
432 | if (vma->vm_flags & VM_WRITE) | |
433 | return -EPERM; | |
434 | ||
435 | if (PAGE_SIZE > (1 << 16)) | |
436 | return -ENOSYS; | |
437 | ||
1da177e4 LT |
438 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
439 | ||
440 | mmtimer_addr = __pa(RTC_COUNTER_ADDR); | |
441 | mmtimer_addr &= ~(PAGE_SIZE - 1); | |
442 | mmtimer_addr &= 0xfffffffffffffffUL; | |
443 | ||
444 | if (remap_pfn_range(vma, vma->vm_start, mmtimer_addr >> PAGE_SHIFT, | |
445 | PAGE_SIZE, vma->vm_page_prot)) { | |
446 | printk(KERN_ERR "remap_pfn_range failed in mmtimer.c\n"); | |
447 | return -EAGAIN; | |
448 | } | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static struct miscdevice mmtimer_miscdev = { | |
454 | SGI_MMTIMER, | |
455 | MMTIMER_NAME, | |
456 | &mmtimer_fops | |
457 | }; | |
458 | ||
459 | static struct timespec sgi_clock_offset; | |
460 | static int sgi_clock_period; | |
461 | ||
462 | /* | |
463 | * Posix Timer Interface | |
464 | */ | |
465 | ||
466 | static struct timespec sgi_clock_offset; | |
467 | static int sgi_clock_period; | |
468 | ||
469 | static int sgi_clock_get(clockid_t clockid, struct timespec *tp) | |
470 | { | |
471 | u64 nsec; | |
472 | ||
473 | nsec = rtc_time() * sgi_clock_period | |
474 | + sgi_clock_offset.tv_nsec; | |
475 | tp->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &tp->tv_nsec) | |
476 | + sgi_clock_offset.tv_sec; | |
477 | return 0; | |
478 | }; | |
479 | ||
480 | static int sgi_clock_set(clockid_t clockid, struct timespec *tp) | |
481 | { | |
482 | ||
483 | u64 nsec; | |
484 | u64 rem; | |
485 | ||
486 | nsec = rtc_time() * sgi_clock_period; | |
487 | ||
488 | sgi_clock_offset.tv_sec = tp->tv_sec - div_long_long_rem(nsec, NSEC_PER_SEC, &rem); | |
489 | ||
490 | if (rem <= tp->tv_nsec) | |
491 | sgi_clock_offset.tv_nsec = tp->tv_sec - rem; | |
492 | else { | |
493 | sgi_clock_offset.tv_nsec = tp->tv_sec + NSEC_PER_SEC - rem; | |
494 | sgi_clock_offset.tv_sec--; | |
495 | } | |
496 | return 0; | |
497 | } | |
498 | ||
1da177e4 LT |
499 | /** |
500 | * mmtimer_interrupt - timer interrupt handler | |
501 | * @irq: irq received | |
502 | * @dev_id: device the irq came from | |
1da177e4 LT |
503 | * |
504 | * Called when one of the comarators matches the counter, This | |
505 | * routine will send signals to processes that have requested | |
506 | * them. | |
507 | * | |
508 | * This interrupt is run in an interrupt context | |
509 | * by the SHUB. It is therefore safe to locally access SHub | |
510 | * registers. | |
511 | */ | |
512 | static irqreturn_t | |
7d12e780 | 513 | mmtimer_interrupt(int irq, void *dev_id) |
1da177e4 | 514 | { |
1da177e4 LT |
515 | unsigned long expires = 0; |
516 | int result = IRQ_NONE; | |
76832c28 | 517 | unsigned indx = cpu_to_node(smp_processor_id()); |
cbacdd95 | 518 | struct mmtimer *base; |
1da177e4 | 519 | |
cbacdd95 DS |
520 | spin_lock(&timers[indx].lock); |
521 | base = rb_entry(timers[indx].next, struct mmtimer, list); | |
522 | if (base == NULL) { | |
523 | spin_unlock(&timers[indx].lock); | |
524 | return result; | |
525 | } | |
526 | ||
527 | if (base->cpu == smp_processor_id()) { | |
528 | if (base->timer) | |
529 | expires = base->timer->it.mmtimer.expires; | |
530 | /* expires test won't work with shared irqs */ | |
531 | if ((mmtimer_int_pending(COMPARATOR) > 0) || | |
532 | (expires && (expires <= rtc_time()))) { | |
533 | mmtimer_clr_int_pending(COMPARATOR); | |
534 | tasklet_schedule(&timers[indx].tasklet); | |
535 | result = IRQ_HANDLED; | |
1da177e4 | 536 | } |
1da177e4 | 537 | } |
cbacdd95 | 538 | spin_unlock(&timers[indx].lock); |
1da177e4 LT |
539 | return result; |
540 | } | |
541 | ||
cbacdd95 DS |
542 | static void mmtimer_tasklet(unsigned long data) |
543 | { | |
544 | int nodeid = data; | |
545 | struct mmtimer_node *mn = &timers[nodeid]; | |
546 | struct mmtimer *x = rb_entry(mn->next, struct mmtimer, list); | |
547 | struct k_itimer *t; | |
1da177e4 LT |
548 | unsigned long flags; |
549 | ||
1da177e4 | 550 | /* Send signal and deal with periodic signals */ |
cbacdd95 DS |
551 | spin_lock_irqsave(&mn->lock, flags); |
552 | if (!mn->next) | |
1da177e4 | 553 | goto out; |
1da177e4 | 554 | |
cbacdd95 DS |
555 | x = rb_entry(mn->next, struct mmtimer, list); |
556 | t = x->timer; | |
557 | ||
558 | if (t->it.mmtimer.clock == TIMER_OFF) | |
559 | goto out; | |
560 | ||
561 | t->it_overrun = 0; | |
1da177e4 | 562 | |
cbacdd95 DS |
563 | mn->next = rb_next(&x->list); |
564 | rb_erase(&x->list, &mn->timer_head); | |
1da177e4 | 565 | |
cbacdd95 | 566 | if (posix_timer_event(t, 0) != 0) |
1da177e4 | 567 | t->it_overrun++; |
cbacdd95 | 568 | |
1da177e4 | 569 | if(t->it.mmtimer.incr) { |
cbacdd95 DS |
570 | t->it.mmtimer.expires += t->it.mmtimer.incr; |
571 | mmtimer_add_list(x); | |
1da177e4 LT |
572 | } else { |
573 | /* Ensure we don't false trigger in mmtimer_interrupt */ | |
cbacdd95 | 574 | t->it.mmtimer.clock = TIMER_OFF; |
1da177e4 | 575 | t->it.mmtimer.expires = 0; |
cbacdd95 | 576 | kfree(x); |
1da177e4 | 577 | } |
cbacdd95 DS |
578 | /* Set comparator for next timer, if there is one */ |
579 | mmtimer_set_next_timer(nodeid); | |
580 | ||
1da177e4 LT |
581 | t->it_overrun_last = t->it_overrun; |
582 | out: | |
cbacdd95 | 583 | spin_unlock_irqrestore(&mn->lock, flags); |
1da177e4 LT |
584 | } |
585 | ||
586 | static int sgi_timer_create(struct k_itimer *timer) | |
587 | { | |
588 | /* Insure that a newly created timer is off */ | |
589 | timer->it.mmtimer.clock = TIMER_OFF; | |
590 | return 0; | |
591 | } | |
592 | ||
593 | /* This does not really delete a timer. It just insures | |
594 | * that the timer is not active | |
595 | * | |
596 | * Assumption: it_lock is already held with irq's disabled | |
597 | */ | |
598 | static int sgi_timer_del(struct k_itimer *timr) | |
599 | { | |
1da177e4 | 600 | cnodeid_t nodeid = timr->it.mmtimer.node; |
1da177e4 LT |
601 | unsigned long irqflags; |
602 | ||
cbacdd95 DS |
603 | spin_lock_irqsave(&timers[nodeid].lock, irqflags); |
604 | if (timr->it.mmtimer.clock != TIMER_OFF) { | |
605 | unsigned long expires = timr->it.mmtimer.expires; | |
606 | struct rb_node *n = timers[nodeid].timer_head.rb_node; | |
607 | struct mmtimer *uninitialized_var(t); | |
608 | int r = 0; | |
609 | ||
1da177e4 LT |
610 | timr->it.mmtimer.clock = TIMER_OFF; |
611 | timr->it.mmtimer.expires = 0; | |
cbacdd95 DS |
612 | |
613 | while (n) { | |
614 | t = rb_entry(n, struct mmtimer, list); | |
615 | if (t->timer == timr) | |
616 | break; | |
617 | ||
618 | if (expires < t->timer->it.mmtimer.expires) | |
619 | n = n->rb_left; | |
620 | else | |
621 | n = n->rb_right; | |
622 | } | |
623 | ||
624 | if (!n) { | |
625 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); | |
626 | return 0; | |
627 | } | |
628 | ||
629 | if (timers[nodeid].next == n) { | |
630 | timers[nodeid].next = rb_next(n); | |
631 | r = 1; | |
632 | } | |
633 | ||
634 | rb_erase(n, &timers[nodeid].timer_head); | |
635 | kfree(t); | |
636 | ||
637 | if (r) { | |
638 | mmtimer_disable_int(cnodeid_to_nasid(nodeid), | |
639 | COMPARATOR); | |
640 | mmtimer_set_next_timer(nodeid); | |
641 | } | |
1da177e4 | 642 | } |
cbacdd95 | 643 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); |
1da177e4 LT |
644 | return 0; |
645 | } | |
646 | ||
647 | #define timespec_to_ns(x) ((x).tv_nsec + (x).tv_sec * NSEC_PER_SEC) | |
648 | #define ns_to_timespec(ts, nsec) (ts).tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &(ts).tv_nsec) | |
649 | ||
650 | /* Assumption: it_lock is already held with irq's disabled */ | |
651 | static void sgi_timer_get(struct k_itimer *timr, struct itimerspec *cur_setting) | |
652 | { | |
653 | ||
654 | if (timr->it.mmtimer.clock == TIMER_OFF) { | |
655 | cur_setting->it_interval.tv_nsec = 0; | |
656 | cur_setting->it_interval.tv_sec = 0; | |
657 | cur_setting->it_value.tv_nsec = 0; | |
658 | cur_setting->it_value.tv_sec =0; | |
659 | return; | |
660 | } | |
661 | ||
662 | ns_to_timespec(cur_setting->it_interval, timr->it.mmtimer.incr * sgi_clock_period); | |
663 | ns_to_timespec(cur_setting->it_value, (timr->it.mmtimer.expires - rtc_time())* sgi_clock_period); | |
664 | return; | |
665 | } | |
666 | ||
667 | ||
668 | static int sgi_timer_set(struct k_itimer *timr, int flags, | |
669 | struct itimerspec * new_setting, | |
670 | struct itimerspec * old_setting) | |
671 | { | |
1da177e4 LT |
672 | unsigned long when, period, irqflags; |
673 | int err = 0; | |
674 | cnodeid_t nodeid; | |
cbacdd95 DS |
675 | struct mmtimer *base; |
676 | struct rb_node *n; | |
1da177e4 LT |
677 | |
678 | if (old_setting) | |
679 | sgi_timer_get(timr, old_setting); | |
680 | ||
681 | sgi_timer_del(timr); | |
682 | when = timespec_to_ns(new_setting->it_value); | |
683 | period = timespec_to_ns(new_setting->it_interval); | |
684 | ||
685 | if (when == 0) | |
686 | /* Clear timer */ | |
687 | return 0; | |
688 | ||
cbacdd95 DS |
689 | base = kmalloc(sizeof(struct mmtimer), GFP_KERNEL); |
690 | if (base == NULL) | |
691 | return -ENOMEM; | |
692 | ||
1da177e4 LT |
693 | if (flags & TIMER_ABSTIME) { |
694 | struct timespec n; | |
695 | unsigned long now; | |
696 | ||
697 | getnstimeofday(&n); | |
698 | now = timespec_to_ns(n); | |
699 | if (when > now) | |
700 | when -= now; | |
701 | else | |
702 | /* Fire the timer immediately */ | |
703 | when = 0; | |
704 | } | |
705 | ||
706 | /* | |
707 | * Convert to sgi clock period. Need to keep rtc_time() as near as possible | |
708 | * to getnstimeofday() in order to be as faithful as possible to the time | |
709 | * specified. | |
710 | */ | |
711 | when = (when + sgi_clock_period - 1) / sgi_clock_period + rtc_time(); | |
712 | period = (period + sgi_clock_period - 1) / sgi_clock_period; | |
713 | ||
714 | /* | |
715 | * We are allocating a local SHub comparator. If we would be moved to another | |
716 | * cpu then another SHub may be local to us. Prohibit that by switching off | |
717 | * preemption. | |
718 | */ | |
719 | preempt_disable(); | |
720 | ||
55642d36 | 721 | nodeid = cpu_to_node(smp_processor_id()); |
1da177e4 | 722 | |
cbacdd95 DS |
723 | /* Lock the node timer structure */ |
724 | spin_lock_irqsave(&timers[nodeid].lock, irqflags); | |
1da177e4 | 725 | |
76832c28 DS |
726 | base->timer = timr; |
727 | base->cpu = smp_processor_id(); | |
1da177e4 | 728 | |
cbacdd95 | 729 | timr->it.mmtimer.clock = TIMER_SET; |
1da177e4 LT |
730 | timr->it.mmtimer.node = nodeid; |
731 | timr->it.mmtimer.incr = period; | |
732 | timr->it.mmtimer.expires = when; | |
733 | ||
cbacdd95 DS |
734 | n = timers[nodeid].next; |
735 | ||
736 | /* Add the new struct mmtimer to node's timer list */ | |
737 | mmtimer_add_list(base); | |
738 | ||
739 | if (timers[nodeid].next == n) { | |
740 | /* No need to reprogram comparator for now */ | |
741 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); | |
742 | preempt_enable(); | |
743 | return err; | |
1da177e4 LT |
744 | } |
745 | ||
cbacdd95 DS |
746 | /* We need to reprogram the comparator */ |
747 | if (n) | |
748 | mmtimer_disable_int(cnodeid_to_nasid(nodeid), COMPARATOR); | |
749 | ||
750 | mmtimer_set_next_timer(nodeid); | |
751 | ||
752 | /* Unlock the node timer structure */ | |
753 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); | |
1da177e4 LT |
754 | |
755 | preempt_enable(); | |
756 | ||
757 | return err; | |
758 | } | |
759 | ||
760 | static struct k_clock sgi_clock = { | |
761 | .res = 0, | |
762 | .clock_set = sgi_clock_set, | |
763 | .clock_get = sgi_clock_get, | |
764 | .timer_create = sgi_timer_create, | |
765 | .nsleep = do_posix_clock_nonanosleep, | |
766 | .timer_set = sgi_timer_set, | |
767 | .timer_del = sgi_timer_del, | |
768 | .timer_get = sgi_timer_get | |
769 | }; | |
770 | ||
771 | /** | |
772 | * mmtimer_init - device initialization routine | |
773 | * | |
774 | * Does initial setup for the mmtimer device. | |
775 | */ | |
776 | static int __init mmtimer_init(void) | |
777 | { | |
76832c28 | 778 | cnodeid_t node, maxn = -1; |
1da177e4 LT |
779 | |
780 | if (!ia64_platform_is("sn2")) | |
f032f908 | 781 | return 0; |
1da177e4 LT |
782 | |
783 | /* | |
784 | * Sanity check the cycles/sec variable | |
785 | */ | |
786 | if (sn_rtc_cycles_per_second < 100000) { | |
787 | printk(KERN_ERR "%s: unable to determine clock frequency\n", | |
788 | MMTIMER_NAME); | |
5d469ec0 | 789 | goto out1; |
1da177e4 LT |
790 | } |
791 | ||
792 | mmtimer_femtoperiod = ((unsigned long)1E15 + sn_rtc_cycles_per_second / | |
793 | 2) / sn_rtc_cycles_per_second; | |
794 | ||
0f2ed4c6 | 795 | if (request_irq(SGI_MMTIMER_VECTOR, mmtimer_interrupt, IRQF_PERCPU, MMTIMER_NAME, NULL)) { |
1da177e4 LT |
796 | printk(KERN_WARNING "%s: unable to allocate interrupt.", |
797 | MMTIMER_NAME); | |
5d469ec0 | 798 | goto out1; |
1da177e4 LT |
799 | } |
800 | ||
1da177e4 LT |
801 | if (misc_register(&mmtimer_miscdev)) { |
802 | printk(KERN_ERR "%s: failed to register device\n", | |
803 | MMTIMER_NAME); | |
5d469ec0 | 804 | goto out2; |
1da177e4 LT |
805 | } |
806 | ||
76832c28 DS |
807 | /* Get max numbered node, calculate slots needed */ |
808 | for_each_online_node(node) { | |
809 | maxn = node; | |
810 | } | |
811 | maxn++; | |
812 | ||
813 | /* Allocate list of node ptrs to mmtimer_t's */ | |
cbacdd95 | 814 | timers = kzalloc(sizeof(struct mmtimer_node)*maxn, GFP_KERNEL); |
76832c28 DS |
815 | if (timers == NULL) { |
816 | printk(KERN_ERR "%s: failed to allocate memory for device\n", | |
817 | MMTIMER_NAME); | |
5d469ec0 | 818 | goto out3; |
76832c28 DS |
819 | } |
820 | ||
cbacdd95 | 821 | /* Initialize struct mmtimer's for each online node */ |
76832c28 | 822 | for_each_online_node(node) { |
cbacdd95 DS |
823 | spin_lock_init(&timers[node].lock); |
824 | tasklet_init(&timers[node].tasklet, mmtimer_tasklet, | |
825 | (unsigned long) node); | |
76832c28 DS |
826 | } |
827 | ||
1da177e4 LT |
828 | sgi_clock_period = sgi_clock.res = NSEC_PER_SEC / sn_rtc_cycles_per_second; |
829 | register_posix_clock(CLOCK_SGI_CYCLE, &sgi_clock); | |
830 | ||
831 | printk(KERN_INFO "%s: v%s, %ld MHz\n", MMTIMER_DESC, MMTIMER_VERSION, | |
832 | sn_rtc_cycles_per_second/(unsigned long)1E6); | |
833 | ||
834 | return 0; | |
5d469ec0 | 835 | |
5d469ec0 | 836 | out3: |
cbacdd95 | 837 | kfree(timers); |
5d469ec0 NH |
838 | misc_deregister(&mmtimer_miscdev); |
839 | out2: | |
840 | free_irq(SGI_MMTIMER_VECTOR, NULL); | |
841 | out1: | |
842 | return -1; | |
1da177e4 LT |
843 | } |
844 | ||
845 | module_init(mmtimer_init); |