Commit | Line | Data |
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03718234 JS |
1 | #ifndef MOXA_H_FILE |
2 | #define MOXA_H_FILE | |
3 | ||
4 | /* | |
5 | * System Configuration | |
6 | */ | |
7 | ||
8 | #define Magic_code 0x404 | |
9 | ||
10 | /* | |
11 | * for C218 BIOS initialization | |
12 | */ | |
13 | #define C218_ConfBase 0x800 | |
14 | #define C218_status (C218_ConfBase + 0) /* BIOS running status */ | |
15 | #define C218_diag (C218_ConfBase + 2) /* diagnostic status */ | |
16 | #define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */ | |
17 | #define C218DLoad_len (C218_ConfBase + 6) /* WORD */ | |
18 | #define C218check_sum (C218_ConfBase + 8) /* BYTE */ | |
19 | #define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */ | |
20 | #define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */ | |
21 | #define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */ | |
22 | #define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */ | |
23 | #define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */ | |
24 | ||
25 | #define C218_LoadBuf 0x0F00 | |
26 | #define C218_KeyCode 0x218 | |
27 | #define CP204J_KeyCode 0x204 | |
28 | ||
29 | /* | |
30 | * for C320 BIOS initialization | |
31 | */ | |
32 | #define C320_ConfBase 0x800 | |
33 | #define C320_LoadBuf 0x0f00 | |
34 | #define STS_init 0x05 /* for C320_status */ | |
35 | ||
36 | #define C320_status C320_ConfBase + 0 /* BIOS running status */ | |
37 | #define C320_diag C320_ConfBase + 2 /* diagnostic status */ | |
38 | #define C320_key C320_ConfBase + 4 /* WORD (0320H for C320) */ | |
39 | #define C320DLoad_len C320_ConfBase + 6 /* WORD */ | |
40 | #define C320check_sum C320_ConfBase + 8 /* WORD */ | |
41 | #define C320chksum_ok C320_ConfBase + 0x0a /* WORD (1:ok) */ | |
42 | #define C320bapi_len C320_ConfBase + 0x0c /* WORD */ | |
43 | #define C320UART_no C320_ConfBase + 0x0e /* WORD */ | |
44 | ||
45 | #define C320_KeyCode 0x320 | |
46 | ||
47 | #define FixPage_addr 0x0000 /* starting addr of static page */ | |
48 | #define DynPage_addr 0x2000 /* starting addr of dynamic page */ | |
49 | #define C218_start 0x3000 /* starting addr of C218 BIOS prg */ | |
50 | #define Control_reg 0x1ff0 /* select page and reset control */ | |
51 | #define HW_reset 0x80 | |
52 | ||
53 | /* | |
54 | * Function Codes | |
55 | */ | |
56 | #define FC_CardReset 0x80 | |
57 | #define FC_ChannelReset 1 /* C320 firmware not supported */ | |
58 | #define FC_EnableCH 2 | |
59 | #define FC_DisableCH 3 | |
60 | #define FC_SetParam 4 | |
61 | #define FC_SetMode 5 | |
62 | #define FC_SetRate 6 | |
63 | #define FC_LineControl 7 | |
64 | #define FC_LineStatus 8 | |
65 | #define FC_XmitControl 9 | |
66 | #define FC_FlushQueue 10 | |
67 | #define FC_SendBreak 11 | |
68 | #define FC_StopBreak 12 | |
69 | #define FC_LoopbackON 13 | |
70 | #define FC_LoopbackOFF 14 | |
71 | #define FC_ClrIrqTable 15 | |
72 | #define FC_SendXon 16 | |
73 | #define FC_SetTermIrq 17 /* C320 firmware not supported */ | |
74 | #define FC_SetCntIrq 18 /* C320 firmware not supported */ | |
75 | #define FC_SetBreakIrq 19 | |
76 | #define FC_SetLineIrq 20 | |
77 | #define FC_SetFlowCtl 21 | |
78 | #define FC_GenIrq 22 | |
79 | #define FC_InCD180 23 | |
80 | #define FC_OutCD180 24 | |
81 | #define FC_InUARTreg 23 | |
82 | #define FC_OutUARTreg 24 | |
83 | #define FC_SetXonXoff 25 | |
84 | #define FC_OutCD180CCR 26 | |
85 | #define FC_ExtIQueue 27 | |
86 | #define FC_ExtOQueue 28 | |
87 | #define FC_ClrLineIrq 29 | |
88 | #define FC_HWFlowCtl 30 | |
89 | #define FC_GetClockRate 35 | |
90 | #define FC_SetBaud 36 | |
91 | #define FC_SetDataMode 41 | |
92 | #define FC_GetCCSR 43 | |
93 | #define FC_GetDataError 45 | |
94 | #define FC_RxControl 50 | |
95 | #define FC_ImmSend 51 | |
96 | #define FC_SetXonState 52 | |
97 | #define FC_SetXoffState 53 | |
98 | #define FC_SetRxFIFOTrig 54 | |
99 | #define FC_SetTxFIFOCnt 55 | |
100 | #define FC_UnixRate 56 | |
101 | #define FC_UnixResetTimer 57 | |
102 | ||
103 | #define RxFIFOTrig1 0 | |
104 | #define RxFIFOTrig4 1 | |
105 | #define RxFIFOTrig8 2 | |
106 | #define RxFIFOTrig14 3 | |
107 | ||
108 | /* | |
109 | * Dual-Ported RAM | |
110 | */ | |
111 | #define DRAM_global 0 | |
112 | #define INT_data (DRAM_global + 0) | |
113 | #define Config_base (DRAM_global + 0x108) | |
114 | ||
115 | #define IRQindex (INT_data + 0) | |
116 | #define IRQpending (INT_data + 4) | |
117 | #define IRQtable (INT_data + 8) | |
118 | ||
119 | /* | |
120 | * Interrupt Status | |
121 | */ | |
122 | #define IntrRx 0x01 /* receiver data O.K. */ | |
123 | #define IntrTx 0x02 /* transmit buffer empty */ | |
124 | #define IntrFunc 0x04 /* function complete */ | |
125 | #define IntrBreak 0x08 /* received break */ | |
126 | #define IntrLine 0x10 /* line status change | |
127 | for transmitter */ | |
128 | #define IntrIntr 0x20 /* received INTR code */ | |
129 | #define IntrQuit 0x40 /* received QUIT code */ | |
130 | #define IntrEOF 0x80 /* received EOF code */ | |
131 | ||
132 | #define IntrRxTrigger 0x100 /* rx data count reach tigger value */ | |
133 | #define IntrTxTrigger 0x200 /* tx data count below trigger value */ | |
134 | ||
135 | #define Magic_no (Config_base + 0) | |
136 | #define Card_model_no (Config_base + 2) | |
137 | #define Total_ports (Config_base + 4) | |
138 | #define Module_cnt (Config_base + 8) | |
139 | #define Module_no (Config_base + 10) | |
140 | #define Timer_10ms (Config_base + 14) | |
141 | #define Disable_IRQ (Config_base + 20) | |
142 | #define TMS320_PORT1 (Config_base + 22) | |
143 | #define TMS320_PORT2 (Config_base + 24) | |
144 | #define TMS320_CLOCK (Config_base + 26) | |
145 | ||
146 | /* | |
147 | * DATA BUFFER in DRAM | |
148 | */ | |
149 | #define Extern_table 0x400 /* Base address of the external table | |
150 | (24 words * 64) total 3K bytes | |
151 | (24 words * 128) total 6K bytes */ | |
152 | #define Extern_size 0x60 /* 96 bytes */ | |
153 | #define RXrptr 0x00 /* read pointer for RX buffer */ | |
154 | #define RXwptr 0x02 /* write pointer for RX buffer */ | |
155 | #define TXrptr 0x04 /* read pointer for TX buffer */ | |
156 | #define TXwptr 0x06 /* write pointer for TX buffer */ | |
157 | #define HostStat 0x08 /* IRQ flag and general flag */ | |
158 | #define FlagStat 0x0A | |
159 | #define FlowControl 0x0C /* B7 B6 B5 B4 B3 B2 B1 B0 */ | |
160 | /* x x x x | | | | */ | |
161 | /* | | | + CTS flow */ | |
162 | /* | | +--- RTS flow */ | |
163 | /* | +------ TX Xon/Xoff */ | |
164 | /* +--------- RX Xon/Xoff */ | |
165 | #define Break_cnt 0x0E /* received break count */ | |
166 | #define CD180TXirq 0x10 /* if non-0: enable TX irq */ | |
167 | #define RX_mask 0x12 | |
168 | #define TX_mask 0x14 | |
169 | #define Ofs_rxb 0x16 | |
170 | #define Ofs_txb 0x18 | |
171 | #define Page_rxb 0x1A | |
172 | #define Page_txb 0x1C | |
173 | #define EndPage_rxb 0x1E | |
174 | #define EndPage_txb 0x20 | |
175 | #define Data_error 0x22 | |
176 | #define RxTrigger 0x28 | |
177 | #define TxTrigger 0x2a | |
178 | ||
179 | #define rRXwptr 0x34 | |
180 | #define Low_water 0x36 | |
181 | ||
182 | #define FuncCode 0x40 | |
183 | #define FuncArg 0x42 | |
184 | #define FuncArg1 0x44 | |
185 | ||
186 | #define C218rx_size 0x2000 /* 8K bytes */ | |
187 | #define C218tx_size 0x8000 /* 32K bytes */ | |
188 | ||
189 | #define C218rx_mask (C218rx_size - 1) | |
190 | #define C218tx_mask (C218tx_size - 1) | |
191 | ||
192 | #define C320p8rx_size 0x2000 | |
193 | #define C320p8tx_size 0x8000 | |
194 | #define C320p8rx_mask (C320p8rx_size - 1) | |
195 | #define C320p8tx_mask (C320p8tx_size - 1) | |
196 | ||
197 | #define C320p16rx_size 0x2000 | |
198 | #define C320p16tx_size 0x4000 | |
199 | #define C320p16rx_mask (C320p16rx_size - 1) | |
200 | #define C320p16tx_mask (C320p16tx_size - 1) | |
201 | ||
202 | #define C320p24rx_size 0x2000 | |
203 | #define C320p24tx_size 0x2000 | |
204 | #define C320p24rx_mask (C320p24rx_size - 1) | |
205 | #define C320p24tx_mask (C320p24tx_size - 1) | |
206 | ||
207 | #define C320p32rx_size 0x1000 | |
208 | #define C320p32tx_size 0x1000 | |
209 | #define C320p32rx_mask (C320p32rx_size - 1) | |
210 | #define C320p32tx_mask (C320p32tx_size - 1) | |
211 | ||
212 | #define Page_size 0x2000 | |
213 | #define Page_mask (Page_size - 1) | |
214 | #define C218rx_spage 3 | |
215 | #define C218tx_spage 4 | |
216 | #define C218rx_pageno 1 | |
217 | #define C218tx_pageno 4 | |
218 | #define C218buf_pageno 5 | |
219 | ||
220 | #define C320p8rx_spage 3 | |
221 | #define C320p8tx_spage 4 | |
222 | #define C320p8rx_pgno 1 | |
223 | #define C320p8tx_pgno 4 | |
224 | #define C320p8buf_pgno 5 | |
225 | ||
226 | #define C320p16rx_spage 3 | |
227 | #define C320p16tx_spage 4 | |
228 | #define C320p16rx_pgno 1 | |
229 | #define C320p16tx_pgno 2 | |
230 | #define C320p16buf_pgno 3 | |
231 | ||
232 | #define C320p24rx_spage 3 | |
233 | #define C320p24tx_spage 4 | |
234 | #define C320p24rx_pgno 1 | |
235 | #define C320p24tx_pgno 1 | |
236 | #define C320p24buf_pgno 2 | |
237 | ||
238 | #define C320p32rx_spage 3 | |
239 | #define C320p32tx_ofs C320p32rx_size | |
240 | #define C320p32tx_spage 3 | |
241 | #define C320p32buf_pgno 1 | |
242 | ||
243 | /* | |
244 | * Host Status | |
245 | */ | |
246 | #define WakeupRx 0x01 | |
247 | #define WakeupTx 0x02 | |
248 | #define WakeupBreak 0x08 | |
249 | #define WakeupLine 0x10 | |
250 | #define WakeupIntr 0x20 | |
251 | #define WakeupQuit 0x40 | |
252 | #define WakeupEOF 0x80 /* used in VTIME control */ | |
253 | #define WakeupRxTrigger 0x100 | |
254 | #define WakeupTxTrigger 0x200 | |
255 | /* | |
256 | * Flag status | |
257 | */ | |
258 | #define Rx_over 0x01 | |
259 | #define Xoff_state 0x02 | |
260 | #define Tx_flowOff 0x04 | |
261 | #define Tx_enable 0x08 | |
262 | #define CTS_state 0x10 | |
263 | #define DSR_state 0x20 | |
264 | #define DCD_state 0x80 | |
265 | /* | |
266 | * FlowControl | |
267 | */ | |
268 | #define CTS_FlowCtl 1 | |
269 | #define RTS_FlowCtl 2 | |
270 | #define Tx_FlowCtl 4 | |
271 | #define Rx_FlowCtl 8 | |
272 | #define IXM_IXANY 0x10 | |
273 | ||
274 | #define LowWater 128 | |
275 | ||
276 | #define DTR_ON 1 | |
277 | #define RTS_ON 2 | |
278 | #define CTS_ON 1 | |
279 | #define DSR_ON 2 | |
280 | #define DCD_ON 8 | |
281 | ||
282 | /* mode definition */ | |
283 | #define MX_CS8 0x03 | |
284 | #define MX_CS7 0x02 | |
285 | #define MX_CS6 0x01 | |
286 | #define MX_CS5 0x00 | |
287 | ||
288 | #define MX_STOP1 0x00 | |
289 | #define MX_STOP15 0x04 | |
290 | #define MX_STOP2 0x08 | |
291 | ||
292 | #define MX_PARNONE 0x00 | |
293 | #define MX_PAREVEN 0x40 | |
294 | #define MX_PARODD 0xC0 | |
295 | ||
296 | #endif |