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mpc52xx_psc_spi: fix block transfer
[deliverable/linux.git] / drivers / char / mxser.c
CommitLineData
1da177e4
LT		 1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
80ff8a80
JS		 4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
5 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
1da177e4 6 *
1c45607a
JS		 7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
1da177e4
LT		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
8ea2c2ec 14 * (at your option) any later version.
1da177e4 15 *
1da177e4
LT		 16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
17 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
18 * - Fixed x86_64 cleanness
1da177e4
LT		 19 */
20
1da177e4 21#include <linux/module.h>
1da177e4
LT		 22#include <linux/errno.h>
23#include <linux/signal.h>
24#include <linux/sched.h>
25#include <linux/timer.h>
26#include <linux/interrupt.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/serial.h>
30#include <linux/serial_reg.h>
31#include <linux/major.h>
32#include <linux/string.h>
33#include <linux/fcntl.h>
34#include <linux/ptrace.h>
35#include <linux/gfp.h>
36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/delay.h>
39#include <linux/pci.h>
1977f032 40#include <linux/bitops.h>
1da177e4
LT		 41
42#include <asm/system.h>
43#include <asm/io.h>
44#include <asm/irq.h>
1da177e4
LT		 45#include <asm/uaccess.h>
46
47#include "mxser.h"
48
e129deff 49#define MXSER_VERSION "2.0.4" /* 1.12 */
1da177e4 50#define MXSERMAJOR 174
1da177e4 51
1da177e4 52#define MXSER_BOARDS 4 /* Max. boards */
1da177e4 53#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
1c45607a
JS		 54#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
55#define MXSER_ISR_PASS_LIMIT 100
1da177e4 56
1c45607a
JS		 57/*CheckIsMoxaMust return value*/
58#define MOXA_OTHER_UART 0x00
59#define MOXA_MUST_MU150_HWID 0x01
60#define MOXA_MUST_MU860_HWID 0x02
61
1da177e4
LT		 62#define WAKEUP_CHARS 256
63
64#define UART_MCR_AFE 0x20
65#define UART_LSR_SPECIAL 0x1E
66
e129deff 67#define PCI_DEVICE_ID_POS104UL 0x1044
1c45607a 68#define PCI_DEVICE_ID_CB108 0x1080
e129deff 69#define PCI_DEVICE_ID_CP102UF 0x1023
1c45607a 70#define PCI_DEVICE_ID_CB114 0x1142
80ff8a80 71#define PCI_DEVICE_ID_CP114UL 0x1143
1c45607a
JS		 72#define PCI_DEVICE_ID_CB134I 0x1341
73#define PCI_DEVICE_ID_CP138U 0x1380
1da177e4 74
1da177e4
LT		 75
76#define C168_ASIC_ID 1
77#define C104_ASIC_ID 2
78#define C102_ASIC_ID 0xB
79#define CI132_ASIC_ID 4
80#define CI134_ASIC_ID 3
81#define CI104J_ASIC_ID 5
82
1c45607a
JS		 83#define MXSER_HIGHBAUD 1
84#define MXSER_HAS2 2
1da177e4 85
8ea2c2ec 86/* This is only for PCI */
1c45607a 87static const struct {
1da177e4
LT		 88 int type;
89 int tx_fifo;
90 int rx_fifo;
91 int xmit_fifo_size;
92 int rx_high_water;
93 int rx_trigger;
94 int rx_low_water;
95 long max_baud;
1c45607a 96} Gpci_uart_info[] = {
1da177e4
LT		 97 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
98 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
99 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
100};
1c45607a 101#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
1da177e4 102
1c45607a
JS		 103struct mxser_cardinfo {
104 char *name;
105 unsigned int nports;
106 unsigned int flags;
107};
1da177e4 108
1c45607a
JS		 109static const struct mxser_cardinfo mxser_cards[] = {
110/* 0*/ { "C168 series", 8, },
111 { "C104 series", 4, },
112 { "CI-104J series", 4, },
113 { "C168H/PCI series", 8, },
114 { "C104H/PCI series", 4, },
115/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
116 { "CI-132 series", 4, MXSER_HAS2 },
117 { "CI-134 series", 4, },
118 { "CP-132 series", 2, },
119 { "CP-114 series", 4, },
120/*10*/ { "CT-114 series", 4, },
121 { "CP-102 series", 2, MXSER_HIGHBAUD },
122 { "CP-104U series", 4, },
123 { "CP-168U series", 8, },
124 { "CP-132U series", 2, },
125/*15*/ { "CP-134U series", 4, },
126 { "CP-104JU series", 4, },
127 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
128 { "CP-118U series", 8, },
129 { "CP-102UL series", 2, },
130/*20*/ { "CP-102U series", 2, },
131 { "CP-118EL series", 8, },
132 { "CP-168EL series", 8, },
133 { "CP-104EL series", 4, },
134 { "CB-108 series", 8, },
135/*25*/ { "CB-114 series", 4, },
136 { "CB-134I series", 4, },
137 { "CP-138U series", 8, },
80ff8a80 138 { "POS-104UL series", 4, },
e129deff
JS		 139 { "CP-114UL series", 4, },
140/*30*/ { "CP-102UF series", 2, }
1c45607a 141};
1da177e4 142
1c45607a
JS		 143/* driver_data correspond to the lines in the structure above
144 see also ISA probe function before you change something */
1da177e4 145static struct pci_device_id mxser_pcibrds[] = {
1c45607a
JS		 146 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
147 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
148 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
149 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
150 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
151 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
80ff8a80 169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 },
e129deff 170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 30 },
1c45607a 171 { }
1da177e4 172};
1da177e4
LT		 173MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
174
1df00924 175static unsigned long ioaddr[MXSER_BOARDS];
1da177e4 176static int ttymajor = MXSERMAJOR;
1da177e4
LT		 177
178/* Variables for insmod */
179
180MODULE_AUTHOR("Casper Yang");
181MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
1df00924
JS		 182module_param_array(ioaddr, ulong, NULL, 0);
183MODULE_PARM_DESC(ioaddr, "ISA io addresses to look for a moxa board");
8d3b33f6 184module_param(ttymajor, int, 0);
1da177e4
LT		 185MODULE_LICENSE("GPL");
186
187struct mxser_log {
188 int tick;
189 unsigned long rxcnt[MXSER_PORTS];
190 unsigned long txcnt[MXSER_PORTS];
191};
192
1da177e4
LT		 193struct mxser_mon {
194 unsigned long rxcnt;
195 unsigned long txcnt;
196 unsigned long up_rxcnt;
197 unsigned long up_txcnt;
198 int modem_status;
199 unsigned char hold_reason;
200};
201
202struct mxser_mon_ext {
203 unsigned long rx_cnt[32];
204 unsigned long tx_cnt[32];
205 unsigned long up_rxcnt[32];
206 unsigned long up_txcnt[32];
207 int modem_status[32];
208
209 long baudrate[32];
210 int databits[32];
211 int stopbits[32];
212 int parity[32];
213 int flowctrl[32];
214 int fifo[32];
215 int iftype[32];
216};
8ea2c2ec 217
1c45607a
JS		 218struct mxser_board;
219
220struct mxser_port {
0ad9e7d1 221 struct tty_port port;
1c45607a 222 struct mxser_board *board;
1c45607a
JS		 223
224 unsigned long ioaddr;
225 unsigned long opmode_ioaddr;
226 int max_baud;
1da177e4 227
1da177e4
LT		 228 int rx_high_water;
229 int rx_trigger; /* Rx fifo trigger level */
230 int rx_low_water;
231 int baud_base; /* max. speed */
1da177e4 232 int type; /* UART type */
1c45607a 233
1da177e4 234 int x_char; /* xon/xoff character */
1da177e4
LT		 235 int IER; /* Interrupt Enable Register */
236 int MCR; /* Modem control register */
1c45607a
JS		 237
238 unsigned char stop_rx;
239 unsigned char ldisc_stop_rx;
240
241 int custom_divisor;
1c45607a 242 unsigned char err_shadow;
1c45607a 243
1c45607a
JS		 244 struct async_icount icount; /* kernel counters for 4 input interrupts */
245 int timeout;
246
247 int read_status_mask;
248 int ignore_status_mask;
249 int xmit_fifo_size;
1da177e4
LT		 250 int xmit_head;
251 int xmit_tail;
252 int xmit_cnt;
1c45607a 253
606d099c 254 struct ktermios normal_termios;
1c45607a 255
1da177e4 256 struct mxser_mon mon_data;
1c45607a 257
1da177e4 258 spinlock_t slock;
1c45607a
JS		 259 wait_queue_head_t delta_msr_wait;
260};
261
262struct mxser_board {
263 unsigned int idx;
264 int irq;
265 const struct mxser_cardinfo *info;
266 unsigned long vector;
267 unsigned long vector_mask;
268
269 int chip_flag;
270 int uart_type;
271
272 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
1da177e4
LT		 273};
274
1da177e4
LT		 275struct mxser_mstatus {
276 tcflag_t cflag;
277 int cts;
278 int dsr;
279 int ri;
280 int dcd;
281};
282
1c45607a 283static struct mxser_board mxser_boards[MXSER_BOARDS];
1da177e4 284static struct tty_driver *mxvar_sdriver;
1da177e4 285static struct mxser_log mxvar_log;
1da177e4 286static int mxser_set_baud_method[MXSER_PORTS + 1];
1da177e4 287
148ff86b
CH		 288static void mxser_enable_must_enchance_mode(unsigned long baseio)
289{
290 u8 oldlcr;
291 u8 efr;
292
293 oldlcr = inb(baseio + UART_LCR);
294 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
295
296 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
297 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
298
299 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
300 outb(oldlcr, baseio + UART_LCR);
301}
302
303static void mxser_disable_must_enchance_mode(unsigned long baseio)
304{
305 u8 oldlcr;
306 u8 efr;
307
308 oldlcr = inb(baseio + UART_LCR);
309 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
310
311 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
312 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
313
314 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
315 outb(oldlcr, baseio + UART_LCR);
316}
317
318static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
319{
320 u8 oldlcr;
321 u8 efr;
322
323 oldlcr = inb(baseio + UART_LCR);
324 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
325
326 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
327 efr &= ~MOXA_MUST_EFR_BANK_MASK;
328 efr |= MOXA_MUST_EFR_BANK0;
329
330 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
331 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
332 outb(oldlcr, baseio + UART_LCR);
333}
334
335static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
336{
337 u8 oldlcr;
338 u8 efr;
339
340 oldlcr = inb(baseio + UART_LCR);
341 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
342
343 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
344 efr &= ~MOXA_MUST_EFR_BANK_MASK;
345 efr |= MOXA_MUST_EFR_BANK0;
346
347 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
348 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
349 outb(oldlcr, baseio + UART_LCR);
350}
351
352static void mxser_set_must_fifo_value(struct mxser_port *info)
353{
354 u8 oldlcr;
355 u8 efr;
356
357 oldlcr = inb(info->ioaddr + UART_LCR);
358 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
359
360 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
361 efr &= ~MOXA_MUST_EFR_BANK_MASK;
362 efr |= MOXA_MUST_EFR_BANK1;
363
364 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
365 outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
366 outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
367 outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
368 outb(oldlcr, info->ioaddr + UART_LCR);
369}
370
371static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
372{
373 u8 oldlcr;
374 u8 efr;
375
376 oldlcr = inb(baseio + UART_LCR);
377 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
378
379 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
380 efr &= ~MOXA_MUST_EFR_BANK_MASK;
381 efr |= MOXA_MUST_EFR_BANK2;
382
383 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
384 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
385 outb(oldlcr, baseio + UART_LCR);
386}
387
388static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
389{
390 u8 oldlcr;
391 u8 efr;
392
393 oldlcr = inb(baseio + UART_LCR);
394 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
395
396 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
397 efr &= ~MOXA_MUST_EFR_BANK_MASK;
398 efr |= MOXA_MUST_EFR_BANK2;
399
400 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
401 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
402 outb(oldlcr, baseio + UART_LCR);
403}
404
405static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
406{
407 u8 oldlcr;
408 u8 efr;
409
410 oldlcr = inb(baseio + UART_LCR);
411 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
412
413 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
414 efr &= ~MOXA_MUST_EFR_SF_MASK;
415
416 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
417 outb(oldlcr, baseio + UART_LCR);
418}
419
420static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
421{
422 u8 oldlcr;
423 u8 efr;
424
425 oldlcr = inb(baseio + UART_LCR);
426 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
427
428 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
429 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
430 efr |= MOXA_MUST_EFR_SF_TX1;
431
432 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
433 outb(oldlcr, baseio + UART_LCR);
434}
435
436static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
437{
438 u8 oldlcr;
439 u8 efr;
440
441 oldlcr = inb(baseio + UART_LCR);
442 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
443
444 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
445 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
446
447 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
448 outb(oldlcr, baseio + UART_LCR);
449}
450
451static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
452{
453 u8 oldlcr;
454 u8 efr;
455
456 oldlcr = inb(baseio + UART_LCR);
457 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
458
459 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
460 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
461 efr |= MOXA_MUST_EFR_SF_RX1;
462
463 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
464 outb(oldlcr, baseio + UART_LCR);
465}
466
467static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
468{
469 u8 oldlcr;
470 u8 efr;
471
472 oldlcr = inb(baseio + UART_LCR);
473 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
474
475 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
476 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
477
478 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
479 outb(oldlcr, baseio + UART_LCR);
480}
481
b8cc5549 482#ifdef CONFIG_PCI
1c45607a 483static int __devinit CheckIsMoxaMust(unsigned long io)
1da177e4
LT		 484{
485 u8 oldmcr, hwid;
486 int i;
487
488 outb(0, io + UART_LCR);
148ff86b 489 mxser_disable_must_enchance_mode(io);
1da177e4
LT		 490 oldmcr = inb(io + UART_MCR);
491 outb(0, io + UART_MCR);
148ff86b 492 mxser_set_must_xon1_value(io, 0x11);
1da177e4
LT		 493 if ((hwid = inb(io + UART_MCR)) != 0) {
494 outb(oldmcr, io + UART_MCR);
8ea2c2ec 495 return MOXA_OTHER_UART;
1da177e4
LT		 496 }
497
148ff86b 498 mxser_get_must_hardware_id(io, &hwid);
1c45607a
JS		 499 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
500 if (hwid == Gpci_uart_info[i].type)
8ea2c2ec 501 return (int)hwid;
1da177e4
LT		 502 }
503 return MOXA_OTHER_UART;
504}
b8cc5549 505#endif
1da177e4 506
1c45607a 507static void process_txrx_fifo(struct mxser_port *info)
1da177e4
LT		 508{
509 int i;
510
511 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
512 info->rx_trigger = 1;
513 info->rx_high_water = 1;
514 info->rx_low_water = 1;
515 info->xmit_fifo_size = 1;
1c45607a
JS		 516 } else
517 for (i = 0; i < UART_INFO_NUM; i++)
518 if (info->board->chip_flag == Gpci_uart_info[i].type) {
1da177e4
LT		 519 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
520 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
521 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
522 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
523 break;
524 }
1da177e4
LT		 525}
526
1c45607a 527static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
1da177e4 528{
72800df9 529 static unsigned char mxser_msr[MXSER_PORTS + 1];
1c45607a 530 unsigned char status = 0;
1da177e4 531
1c45607a 532 status = inb(baseaddr + UART_MSR);
1da177e4 533
1c45607a
JS		 534 mxser_msr[port] &= 0x0F;
535 mxser_msr[port] |= status;
536 status = mxser_msr[port];
537 if (mode)
538 mxser_msr[port] = 0;
1da177e4 539
1c45607a
JS		 540 return status;
541}
1da177e4 542
1c45607a
JS		 543static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp,
544 struct mxser_port *port)
545{
546 DECLARE_WAITQUEUE(wait, current);
547 int retval;
548 int do_clocal = 0;
549 unsigned long flags;
1da177e4 550
1c45607a
JS		 551 /*
552 * If non-blocking mode is set, or the port is not enabled,
553 * then make the check up front and then exit.
554 */
555 if ((filp->f_flags & O_NONBLOCK) ||
556 test_bit(TTY_IO_ERROR, &tty->flags)) {
0ad9e7d1 557 port->port.flags |= ASYNC_NORMAL_ACTIVE;
1c45607a
JS		 558 return 0;
559 }
1da177e4 560
1c45607a
JS		 561 if (tty->termios->c_cflag & CLOCAL)
562 do_clocal = 1;
1da177e4 563
1da177e4 564 /*
1c45607a
JS		 565 * Block waiting for the carrier detect and the line to become
566 * free (i.e., not in use by the callout). While we are in
0ad9e7d1 567 * this loop, port->port.count is dropped by one, so that
1c45607a
JS		 568 * mxser_close() knows when to free things. We restore it upon
569 * exit, either normal or abnormal.
1da177e4 570 */
1c45607a 571 retval = 0;
0ad9e7d1 572 add_wait_queue(&port->port.open_wait, &wait);
1da177e4 573
1c45607a
JS		 574 spin_lock_irqsave(&port->slock, flags);
575 if (!tty_hung_up_p(filp))
0ad9e7d1 576 port->port.count--;
1c45607a 577 spin_unlock_irqrestore(&port->slock, flags);
0ad9e7d1 578 port->port.blocked_open++;
1c45607a
JS		 579 while (1) {
580 spin_lock_irqsave(&port->slock, flags);
581 outb(inb(port->ioaddr + UART_MCR) |
582 UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR);
583 spin_unlock_irqrestore(&port->slock, flags);
584 set_current_state(TASK_INTERRUPTIBLE);
0ad9e7d1
AC		 585 if (tty_hung_up_p(filp) || !(port->port.flags & ASYNC_INITIALIZED)) {
586 if (port->port.flags & ASYNC_HUP_NOTIFY)
1c45607a
JS		 587 retval = -EAGAIN;
588 else
589 retval = -ERESTARTSYS;
590 break;
591 }
0ad9e7d1 592 if (!(port->port.flags & ASYNC_CLOSING) &&
1c45607a
JS		 593 (do_clocal ||
594 (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD)))
595 break;
596 if (signal_pending(current)) {
597 retval = -ERESTARTSYS;
598 break;
599 }
600 schedule();
1da177e4 601 }
1c45607a 602 set_current_state(TASK_RUNNING);
0ad9e7d1 603 remove_wait_queue(&port->port.open_wait, &wait);
1c45607a 604 if (!tty_hung_up_p(filp))
0ad9e7d1
AC		 605 port->port.count++;
606 port->port.blocked_open--;
1c45607a 607 if (retval)
1da177e4 608 return retval;
0ad9e7d1 609 port->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 610 return 0;
611}
612
1c45607a 613static int mxser_set_baud(struct mxser_port *info, long newspd)
1da177e4 614{
1c45607a
JS		 615 int quot = 0, baud;
616 unsigned char cval;
1da177e4 617
0ad9e7d1 618 if (!info->port.tty || !info->port.tty->termios)
1c45607a 619 return -1;
1da177e4 620
1c45607a
JS		 621 if (!(info->ioaddr))
622 return -1;
1da177e4 623
1c45607a
JS		 624 if (newspd > info->max_baud)
625 return -1;
1da177e4 626
1c45607a
JS		 627 if (newspd == 134) {
628 quot = 2 * info->baud_base / 269;
0ad9e7d1 629 tty_encode_baud_rate(info->port.tty, 134, 134);
1c45607a
JS		 630 } else if (newspd) {
631 quot = info->baud_base / newspd;
632 if (quot == 0)
633 quot = 1;
634 baud = info->baud_base/quot;
0ad9e7d1 635 tty_encode_baud_rate(info->port.tty, baud, baud);
1c45607a
JS		 636 } else {
637 quot = 0;
638 }
1da177e4 639
1c45607a
JS		 640 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
641 info->timeout += HZ / 50; /* Add .02 seconds of slop */
1da177e4 642
1c45607a
JS		 643 if (quot) {
644 info->MCR |= UART_MCR_DTR;
645 outb(info->MCR, info->ioaddr + UART_MCR);
646 } else {
647 info->MCR &= ~UART_MCR_DTR;
648 outb(info->MCR, info->ioaddr + UART_MCR);
649 return 0;
650 }
1da177e4 651
1c45607a 652 cval = inb(info->ioaddr + UART_LCR);
1da177e4 653
1c45607a 654 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
1da177e4 655
1c45607a
JS		 656 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
657 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
658 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
1da177e4 659
1c45607a 660#ifdef BOTHER
0ad9e7d1 661 if (C_BAUD(info->port.tty) == BOTHER) {
1c45607a
JS		 662 quot = info->baud_base % newspd;
663 quot *= 8;
664 if (quot % newspd > newspd / 2) {
665 quot /= newspd;
666 quot++;
667 } else
668 quot /= newspd;
669
148ff86b 670 mxser_set_must_enum_value(info->ioaddr, quot);
1c45607a
JS		 671 } else
672#endif
148ff86b 673 mxser_set_must_enum_value(info->ioaddr, 0);
1da177e4 674
8ea2c2ec 675 return 0;
1da177e4 676}
1da177e4 677
1c45607a
JS		 678/*
679 * This routine is called to set the UART divisor registers to match
680 * the specified baud rate for a serial port.
681 */
682static int mxser_change_speed(struct mxser_port *info,
683 struct ktermios *old_termios)
1da177e4 684{
1c45607a
JS		 685 unsigned cflag, cval, fcr;
686 int ret = 0;
687 unsigned char status;
1da177e4 688
0ad9e7d1 689 if (!info->port.tty || !info->port.tty->termios)
1c45607a 690 return ret;
0ad9e7d1 691 cflag = info->port.tty->termios->c_cflag;
1c45607a
JS		 692 if (!(info->ioaddr))
693 return ret;
1da177e4 694
0ad9e7d1
AC		 695 if (mxser_set_baud_method[info->port.tty->index] == 0)
696 mxser_set_baud(info, tty_get_baud_rate(info->port.tty));
1da177e4 697
1c45607a
JS		 698 /* byte size and parity */
699 switch (cflag & CSIZE) {
700 case CS5:
701 cval = 0x00;
702 break;
703 case CS6:
704 cval = 0x01;
705 break;
706 case CS7:
707 cval = 0x02;
708 break;
709 case CS8:
710 cval = 0x03;
711 break;
712 default:
713 cval = 0x00;
714 break; /* too keep GCC shut... */
715 }
716 if (cflag & CSTOPB)
717 cval |= 0x04;
718 if (cflag & PARENB)
719 cval |= UART_LCR_PARITY;
720 if (!(cflag & PARODD))
721 cval |= UART_LCR_EPAR;
722 if (cflag & CMSPAR)
723 cval |= UART_LCR_SPAR;
1da177e4 724
1c45607a
JS		 725 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
726 if (info->board->chip_flag) {
727 fcr = UART_FCR_ENABLE_FIFO;
728 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 729 mxser_set_must_fifo_value(info);
1c45607a
JS		 730 } else
731 fcr = 0;
732 } else {
733 fcr = UART_FCR_ENABLE_FIFO;
734 if (info->board->chip_flag) {
735 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 736 mxser_set_must_fifo_value(info);
1c45607a
JS		 737 } else {
738 switch (info->rx_trigger) {
739 case 1:
740 fcr |= UART_FCR_TRIGGER_1;
741 break;
742 case 4:
743 fcr |= UART_FCR_TRIGGER_4;
744 break;
745 case 8:
746 fcr |= UART_FCR_TRIGGER_8;
747 break;
748 default:
749 fcr |= UART_FCR_TRIGGER_14;
750 break;
751 }
1da177e4 752 }
1da177e4
LT		 753 }
754
1c45607a
JS		 755 /* CTS flow control flag and modem status interrupts */
756 info->IER &= ~UART_IER_MSI;
757 info->MCR &= ~UART_MCR_AFE;
758 if (cflag & CRTSCTS) {
0ad9e7d1 759 info->port.flags |= ASYNC_CTS_FLOW;
1c45607a
JS		 760 info->IER |= UART_IER_MSI;
761 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
762 info->MCR |= UART_MCR_AFE;
763 } else {
764 status = inb(info->ioaddr + UART_MSR);
0ad9e7d1 765 if (info->port.tty->hw_stopped) {
1c45607a 766 if (status & UART_MSR_CTS) {
0ad9e7d1 767 info->port.tty->hw_stopped = 0;
1c45607a
JS		 768 if (info->type != PORT_16550A &&
769 !info->board->chip_flag) {
770 outb(info->IER & ~UART_IER_THRI,
771 info->ioaddr +
772 UART_IER);
773 info->IER |= UART_IER_THRI;
774 outb(info->IER, info->ioaddr +
775 UART_IER);
776 }
0ad9e7d1 777 tty_wakeup(info->port.tty);
1c45607a
JS		 778 }
779 } else {
780 if (!(status & UART_MSR_CTS)) {
0ad9e7d1 781 info->port.tty->hw_stopped = 1;
1c45607a
JS		 782 if ((info->type != PORT_16550A) &&
783 (!info->board->chip_flag)) {
784 info->IER &= ~UART_IER_THRI;
785 outb(info->IER, info->ioaddr +
786 UART_IER);
787 }
788 }
789 }
1da177e4 790 }
1c45607a 791 } else {
0ad9e7d1 792 info->port.flags &= ~ASYNC_CTS_FLOW;
1c45607a
JS		 793 }
794 outb(info->MCR, info->ioaddr + UART_MCR);
795 if (cflag & CLOCAL) {
0ad9e7d1 796 info->port.flags &= ~ASYNC_CHECK_CD;
1c45607a 797 } else {
0ad9e7d1 798 info->port.flags |= ASYNC_CHECK_CD;
1c45607a
JS		 799 info->IER |= UART_IER_MSI;
800 }
801 outb(info->IER, info->ioaddr + UART_IER);
802
803 /*
804 * Set up parity check flag
805 */
806 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
0ad9e7d1 807 if (I_INPCK(info->port.tty))
1c45607a 808 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
0ad9e7d1 809 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1c45607a 810 info->read_status_mask |= UART_LSR_BI;
1da177e4 811
1c45607a 812 info->ignore_status_mask = 0;
1da177e4 813
0ad9e7d1 814 if (I_IGNBRK(info->port.tty)) {
1c45607a
JS		 815 info->ignore_status_mask |= UART_LSR_BI;
816 info->read_status_mask |= UART_LSR_BI;
8ea2c2ec 817 /*
1c45607a
JS		 818 * If we're ignore parity and break indicators, ignore
819 * overruns too. (For real raw support).
8ea2c2ec 820 */
0ad9e7d1 821 if (I_IGNPAR(info->port.tty)) {
1c45607a
JS		 822 info->ignore_status_mask |=
823 UART_LSR_OE |
824 UART_LSR_PE |
825 UART_LSR_FE;
826 info->read_status_mask |=
827 UART_LSR_OE |
828 UART_LSR_PE |
829 UART_LSR_FE;
830 }
1da177e4 831 }
1c45607a 832 if (info->board->chip_flag) {
0ad9e7d1
AC		 833 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(info->port.tty));
834 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(info->port.tty));
835 if (I_IXON(info->port.tty)) {
148ff86b
CH		 836 mxser_enable_must_rx_software_flow_control(
837 info->ioaddr);
1c45607a 838 } else {
148ff86b
CH		 839 mxser_disable_must_rx_software_flow_control(
840 info->ioaddr);
1da177e4 841 }
0ad9e7d1 842 if (I_IXOFF(info->port.tty)) {
148ff86b
CH		 843 mxser_enable_must_tx_software_flow_control(
844 info->ioaddr);
1c45607a 845 } else {
148ff86b
CH		 846 mxser_disable_must_tx_software_flow_control(
847 info->ioaddr);
1da177e4
LT		 848 }
849 }
1da177e4 850
1da177e4 851
1c45607a
JS		 852 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
853 outb(cval, info->ioaddr + UART_LCR);
1da177e4 854
1c45607a 855 return ret;
1da177e4
LT		 856}
857
1c45607a 858static void mxser_check_modem_status(struct mxser_port *port, int status)
1da177e4 859{
1c45607a
JS		 860 /* update input line counters */
861 if (status & UART_MSR_TERI)
862 port->icount.rng++;
863 if (status & UART_MSR_DDSR)
864 port->icount.dsr++;
865 if (status & UART_MSR_DDCD)
866 port->icount.dcd++;
867 if (status & UART_MSR_DCTS)
868 port->icount.cts++;
869 port->mon_data.modem_status = status;
870 wake_up_interruptible(&port->delta_msr_wait);
1da177e4 871
0ad9e7d1 872 if ((port->port.flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
1c45607a 873 if (status & UART_MSR_DCD)
0ad9e7d1 874 wake_up_interruptible(&port->port.open_wait);
1c45607a 875 }
1da177e4 876
0ad9e7d1
AC		 877 if (port->port.flags & ASYNC_CTS_FLOW) {
878 if (port->port.tty->hw_stopped) {
1c45607a 879 if (status & UART_MSR_CTS) {
0ad9e7d1 880 port->port.tty->hw_stopped = 0;
1c45607a
JS		 881
882 if ((port->type != PORT_16550A) &&
883 (!port->board->chip_flag)) {
884 outb(port->IER & ~UART_IER_THRI,
885 port->ioaddr + UART_IER);
886 port->IER |= UART_IER_THRI;
887 outb(port->IER, port->ioaddr +
888 UART_IER);
889 }
0ad9e7d1 890 tty_wakeup(port->port.tty);
1c45607a
JS		 891 }
892 } else {
893 if (!(status & UART_MSR_CTS)) {
0ad9e7d1 894 port->port.tty->hw_stopped = 1;
1c45607a
JS		 895 if (port->type != PORT_16550A &&
896 !port->board->chip_flag) {
897 port->IER &= ~UART_IER_THRI;
898 outb(port->IER, port->ioaddr +
899 UART_IER);
900 }
901 }
902 }
1da177e4
LT		 903 }
904}
905
1c45607a 906static int mxser_startup(struct mxser_port *info)
1da177e4 907{
1c45607a
JS		 908 unsigned long page;
909 unsigned long flags;
1da177e4 910
1c45607a
JS		 911 page = __get_free_page(GFP_KERNEL);
912 if (!page)
913 return -ENOMEM;
1da177e4 914
1c45607a 915 spin_lock_irqsave(&info->slock, flags);
1da177e4 916
0ad9e7d1 917 if (info->port.flags & ASYNC_INITIALIZED) {
1c45607a
JS		 918 free_page(page);
919 spin_unlock_irqrestore(&info->slock, flags);
920 return 0;
921 }
6f08b72c 922
1c45607a 923 if (!info->ioaddr || !info->type) {
0ad9e7d1
AC		 924 if (info->port.tty)
925 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a
JS		 926 free_page(page);
927 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 928 return 0;
1c45607a 929 }
0ad9e7d1 930 if (info->port.xmit_buf)
1c45607a
JS		 931 free_page(page);
932 else
0ad9e7d1 933 info->port.xmit_buf = (unsigned char *) page;
1da177e4 934
1da177e4 935 /*
1c45607a
JS		 936 * Clear the FIFO buffers and disable them
937 * (they will be reenabled in mxser_change_speed())
1da177e4 938 */
1c45607a
JS		 939 if (info->board->chip_flag)
940 outb((UART_FCR_CLEAR_RCVR |
941 UART_FCR_CLEAR_XMIT |
942 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
943 else
944 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
945 info->ioaddr + UART_FCR);
1da177e4 946
1c45607a
JS		 947 /*
948 * At this point there's no way the LSR could still be 0xFF;
949 * if it is, then bail out, because there's likely no UART
950 * here.
951 */
952 if (inb(info->ioaddr + UART_LSR) == 0xff) {
953 spin_unlock_irqrestore(&info->slock, flags);
954 if (capable(CAP_SYS_ADMIN)) {
0ad9e7d1
AC		 955 if (info->port.tty)
956 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a
JS		 957 return 0;
958 } else
959 return -ENODEV;
960 }
1da177e4 961
1c45607a
JS		 962 /*
963 * Clear the interrupt registers.
964 */
965 (void) inb(info->ioaddr + UART_LSR);
966 (void) inb(info->ioaddr + UART_RX);
967 (void) inb(info->ioaddr + UART_IIR);
968 (void) inb(info->ioaddr + UART_MSR);
969
970 /*
971 * Now, initialize the UART
972 */
973 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
974 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
975 outb(info->MCR, info->ioaddr + UART_MCR);
976
977 /*
978 * Finally, enable interrupts
979 */
980 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
981
982 if (info->board->chip_flag)
983 info->IER |= MOXA_MUST_IER_EGDAI;
984 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
985
986 /*
987 * And clear the interrupt registers again for luck.
988 */
989 (void) inb(info->ioaddr + UART_LSR);
990 (void) inb(info->ioaddr + UART_RX);
991 (void) inb(info->ioaddr + UART_IIR);
992 (void) inb(info->ioaddr + UART_MSR);
993
0ad9e7d1
AC		 994 if (info->port.tty)
995 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a
JS		 996 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
997
998 /*
999 * and set the speed of the serial port
1000 */
1001 mxser_change_speed(info, NULL);
0ad9e7d1 1002 info->port.flags |= ASYNC_INITIALIZED;
1c45607a
JS		 1003 spin_unlock_irqrestore(&info->slock, flags);
1004
1005 return 0;
1006}
1007
1008/*
1009 * This routine will shutdown a serial port; interrupts maybe disabled, and
1010 * DTR is dropped if the hangup on close termio flag is on.
1011 */
1012static void mxser_shutdown(struct mxser_port *info)
1013{
1014 unsigned long flags;
1015
0ad9e7d1 1016 if (!(info->port.flags & ASYNC_INITIALIZED))
1c45607a
JS		 1017 return;
1018
1019 spin_lock_irqsave(&info->slock, flags);
1020
1021 /*
1022 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
1023 * here so the queue might never be waken up
1024 */
1025 wake_up_interruptible(&info->delta_msr_wait);
1026
1027 /*
1028 * Free the IRQ, if necessary
1029 */
0ad9e7d1
AC		 1030 if (info->port.xmit_buf) {
1031 free_page((unsigned long) info->port.xmit_buf);
1032 info->port.xmit_buf = NULL;
1da177e4
LT		 1033 }
1034
1c45607a
JS		 1035 info->IER = 0;
1036 outb(0x00, info->ioaddr + UART_IER);
1037
0ad9e7d1 1038 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL))
1c45607a
JS		 1039 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
1040 outb(info->MCR, info->ioaddr + UART_MCR);
1041
1042 /* clear Rx/Tx FIFO's */
1043 if (info->board->chip_flag)
1044 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
1045 MOXA_MUST_FCR_GDA_MODE_ENABLE,
1046 info->ioaddr + UART_FCR);
1047 else
1048 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1049 info->ioaddr + UART_FCR);
1050
1051 /* read data port to reset things */
1052 (void) inb(info->ioaddr + UART_RX);
1053
0ad9e7d1
AC		 1054 if (info->port.tty)
1055 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a 1056
0ad9e7d1 1057 info->port.flags &= ~ASYNC_INITIALIZED;
1c45607a
JS		 1058
1059 if (info->board->chip_flag)
1060 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
1061
1062 spin_unlock_irqrestore(&info->slock, flags);
1063}
1064
1065/*
1066 * This routine is called whenever a serial port is opened. It
1067 * enables interrupts for a serial port, linking in its async structure into
1068 * the IRQ chain. It also performs the serial-specific
1069 * initialization for the tty structure.
1070 */
1071static int mxser_open(struct tty_struct *tty, struct file *filp)
1072{
1073 struct mxser_port *info;
1074 unsigned long flags;
1075 int retval, line;
1076
1077 line = tty->index;
1078 if (line == MXSER_PORTS)
1079 return 0;
1080 if (line < 0 || line > MXSER_PORTS)
1081 return -ENODEV;
1082 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1083 if (!info->ioaddr)
1084 return -ENODEV;
1085
1086 tty->driver_data = info;
0ad9e7d1 1087 info->port.tty = tty;
8ea2c2ec 1088 /*
1c45607a
JS		 1089 * Start up serial port
1090 */
1091 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1092 info->port.count++;
1c45607a
JS		 1093 spin_unlock_irqrestore(&info->slock, flags);
1094 retval = mxser_startup(info);
1095 if (retval)
1096 return retval;
1097
1098 retval = mxser_block_til_ready(tty, filp, info);
1099 if (retval)
1100 return retval;
1da177e4 1101
8cddd707 1102 /* unmark here for very high baud rate (ex. 921600 bps) used */
1da177e4
LT		 1103 tty->low_latency = 1;
1104 return 0;
1105}
1106
978e595f
AC		 1107static void mxser_flush_buffer(struct tty_struct *tty)
1108{
1109 struct mxser_port *info = tty->driver_data;
1110 char fcr;
1111 unsigned long flags;
1112
1113
1114 spin_lock_irqsave(&info->slock, flags);
1115 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1116
1117 fcr = inb(info->ioaddr + UART_FCR);
1118 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1119 info->ioaddr + UART_FCR);
1120 outb(fcr, info->ioaddr + UART_FCR);
1121
1122 spin_unlock_irqrestore(&info->slock, flags);
1123
1124 tty_wakeup(tty);
1125}
1126
1127
1da177e4
LT		 1128/*
1129 * This routine is called when the serial port gets closed. First, we
1130 * wait for the last remaining data to be sent. Then, we unlink its
1131 * async structure from the interrupt chain if necessary, and we free
1132 * that IRQ if nothing is left in the chain.
1133 */
1134static void mxser_close(struct tty_struct *tty, struct file *filp)
1135{
1c45607a 1136 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1137
1138 unsigned long timeout;
1139 unsigned long flags;
1da177e4
LT		 1140
1141 if (tty->index == MXSER_PORTS)
1142 return;
1143 if (!info)
6f08b72c 1144 return;
1da177e4
LT		 1145
1146 spin_lock_irqsave(&info->slock, flags);
1147
1148 if (tty_hung_up_p(filp)) {
1149 spin_unlock_irqrestore(&info->slock, flags);
1150 return;
1151 }
0ad9e7d1 1152 if ((tty->count == 1) && (info->port.count != 1)) {
1da177e4
LT		 1153 /*
1154 * Uh, oh. tty->count is 1, which means that the tty
0ad9e7d1 1155 * structure will be freed. Info->port.count should always
1da177e4
LT		 1156 * be one in these conditions. If it's greater than
1157 * one, we've got real problems, since it means the
1158 * serial port won't be shutdown.
1159 */
8ea2c2ec 1160 printk(KERN_ERR "mxser_close: bad serial port count; "
0ad9e7d1
AC		 1161 "tty->count is 1, info->port.count is %d\n", info->port.count);
1162 info->port.count = 1;
1da177e4 1163 }
0ad9e7d1 1164 if (--info->port.count < 0) {
8ea2c2ec 1165 printk(KERN_ERR "mxser_close: bad serial port count for "
0ad9e7d1
AC		 1166 "ttys%d: %d\n", tty->index, info->port.count);
1167 info->port.count = 0;
1da177e4 1168 }
0ad9e7d1 1169 if (info->port.count) {
1da177e4
LT		 1170 spin_unlock_irqrestore(&info->slock, flags);
1171 return;
1172 }
0ad9e7d1 1173 info->port.flags |= ASYNC_CLOSING;
1da177e4
LT		 1174 spin_unlock_irqrestore(&info->slock, flags);
1175 /*
1176 * Save the termios structure, since this port may have
1177 * separate termios for callout and dialin.
1178 */
0ad9e7d1 1179 if (info->port.flags & ASYNC_NORMAL_ACTIVE)
1da177e4
LT		 1180 info->normal_termios = *tty->termios;
1181 /*
1182 * Now we wait for the transmit buffer to clear; and we notify
1183 * the line discipline to only process XON/XOFF characters.
1184 */
1185 tty->closing = 1;
44b7d1b3
AC		 1186 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
1187 tty_wait_until_sent(tty, info->port.closing_wait);
1da177e4
LT		 1188 /*
1189 * At this point we stop accepting input. To do this, we
1190 * disable the receive line status interrupts, and tell the
1191 * interrupt driver to stop checking the data ready bit in the
1192 * line status register.
1193 */
1194 info->IER &= ~UART_IER_RLSI;
1c45607a 1195 if (info->board->chip_flag)
1da177e4 1196 info->IER &= ~MOXA_MUST_RECV_ISR;
1c45607a 1197
0ad9e7d1 1198 if (info->port.flags & ASYNC_INITIALIZED) {
1c45607a 1199 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1200 /*
1201 * Before we drop DTR, make sure the UART transmitter
1202 * has completely drained; this is especially
1203 * important if there is a transmit FIFO!
1204 */
1205 timeout = jiffies + HZ;
1c45607a 1206 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
da4cd8df 1207 schedule_timeout_interruptible(5);
1da177e4
LT		 1208 if (time_after(jiffies, timeout))
1209 break;
1210 }
1211 }
1212 mxser_shutdown(info);
1213
978e595f 1214 mxser_flush_buffer(tty);
1c45607a
JS		 1215 tty_ldisc_flush(tty);
1216
1da177e4 1217 tty->closing = 0;
0ad9e7d1
AC		 1218 info->port.tty = NULL;
1219 if (info->port.blocked_open) {
44b7d1b3
AC		 1220 if (info->port.close_delay)
1221 schedule_timeout_interruptible(info->port.close_delay);
0ad9e7d1 1222 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1223 }
1224
0ad9e7d1 1225 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
1da177e4
LT		 1226}
1227
1228static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1229{
1230 int c, total = 0;
1c45607a 1231 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1232 unsigned long flags;
1233
0ad9e7d1 1234 if (!info->port.xmit_buf)
8ea2c2ec 1235 return 0;
1da177e4
LT		 1236
1237 while (1) {
8ea2c2ec
JJ		 1238 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1239 SERIAL_XMIT_SIZE - info->xmit_head));
1da177e4
LT		 1240 if (c <= 0)
1241 break;
1242
0ad9e7d1 1243 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1da177e4 1244 spin_lock_irqsave(&info->slock, flags);
8ea2c2ec
JJ		 1245 info->xmit_head = (info->xmit_head + c) &
1246 (SERIAL_XMIT_SIZE - 1);
1da177e4
LT		 1247 info->xmit_cnt += c;
1248 spin_unlock_irqrestore(&info->slock, flags);
1249
1250 buf += c;
1251 count -= c;
1252 total += c;
1da177e4
LT		 1253 }
1254
1c45607a 1255 if (info->xmit_cnt && !tty->stopped) {
8ea2c2ec
JJ		 1256 if (!tty->hw_stopped ||
1257 (info->type == PORT_16550A) ||
1c45607a 1258 (info->board->chip_flag)) {
1da177e4 1259 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 1260 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1261 UART_IER);
1da177e4 1262 info->IER |= UART_IER_THRI;
1c45607a 1263 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1264 spin_unlock_irqrestore(&info->slock, flags);
1265 }
1266 }
1267 return total;
1268}
1269
0be2eade 1270static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1271{
1c45607a 1272 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1273 unsigned long flags;
1274
0ad9e7d1 1275 if (!info->port.xmit_buf)
0be2eade 1276 return 0;
1da177e4
LT		 1277
1278 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
0be2eade 1279 return 0;
1da177e4
LT		 1280
1281 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1282 info->port.xmit_buf[info->xmit_head++] = ch;
1da177e4
LT		 1283 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1284 info->xmit_cnt++;
1285 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 1286 if (!tty->stopped) {
8ea2c2ec
JJ		 1287 if (!tty->hw_stopped ||
1288 (info->type == PORT_16550A) ||
1c45607a 1289 info->board->chip_flag) {
1da177e4 1290 spin_lock_irqsave(&info->slock, flags);
1c45607a 1291 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1292 info->IER |= UART_IER_THRI;
1c45607a 1293 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1294 spin_unlock_irqrestore(&info->slock, flags);
1295 }
1296 }
0be2eade 1297 return 1;
1da177e4
LT		 1298}
1299
1300
1301static void mxser_flush_chars(struct tty_struct *tty)
1302{
1c45607a 1303 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1304 unsigned long flags;
1305
ace7dd96
JS		 1306 if (info->xmit_cnt <= 0 || tty->stopped || !info->port.xmit_buf ||
1307 (tty->hw_stopped && info->type != PORT_16550A &&
1308 !info->board->chip_flag))
1da177e4
LT		 1309 return;
1310
1311 spin_lock_irqsave(&info->slock, flags);
1312
1c45607a 1313 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1314 info->IER |= UART_IER_THRI;
1c45607a 1315 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1316
1317 spin_unlock_irqrestore(&info->slock, flags);
1318}
1319
1320static int mxser_write_room(struct tty_struct *tty)
1321{
1c45607a 1322 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1323 int ret;
1324
1325 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
ace7dd96 1326 return ret < 0 ? 0 : ret;
1da177e4
LT		 1327}
1328
1329static int mxser_chars_in_buffer(struct tty_struct *tty)
1330{
1c45607a 1331 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1332 return info->xmit_cnt;
1333}
1334
1c45607a
JS		 1335/*
1336 * ------------------------------------------------------------
1337 * friends of mxser_ioctl()
1338 * ------------------------------------------------------------
1339 */
1340static int mxser_get_serial_info(struct mxser_port *info,
1341 struct serial_struct __user *retinfo)
1342{
1343 struct serial_struct tmp = {
1344 .type = info->type,
0ad9e7d1 1345 .line = info->port.tty->index,
1c45607a
JS		 1346 .port = info->ioaddr,
1347 .irq = info->board->irq,
0ad9e7d1 1348 .flags = info->port.flags,
1c45607a 1349 .baud_base = info->baud_base,
44b7d1b3
AC		 1350 .close_delay = info->port.close_delay,
1351 .closing_wait = info->port.closing_wait,
1c45607a
JS		 1352 .custom_divisor = info->custom_divisor,
1353 .hub6 = 0
1354 };
1355 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1356 return -EFAULT;
1357 return 0;
1358}
1359
1360static int mxser_set_serial_info(struct mxser_port *info,
1361 struct serial_struct __user *new_info)
1da177e4 1362{
1c45607a 1363 struct serial_struct new_serial;
80ff8a80 1364 speed_t baud;
1c45607a
JS		 1365 unsigned long sl_flags;
1366 unsigned int flags;
1367 int retval = 0;
1da177e4 1368
1c45607a 1369 if (!new_info || !info->ioaddr)
80ff8a80 1370 return -ENODEV;
1c45607a
JS		 1371 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1372 return -EFAULT;
1da177e4 1373
80ff8a80
JS		 1374 if (new_serial.irq != info->board->irq ||
1375 new_serial.port != info->ioaddr)
1376 return -EINVAL;
1da177e4 1377
0ad9e7d1 1378 flags = info->port.flags & ASYNC_SPD_MASK;
1da177e4 1379
1c45607a
JS		 1380 if (!capable(CAP_SYS_ADMIN)) {
1381 if ((new_serial.baud_base != info->baud_base) ||
44b7d1b3 1382 (new_serial.close_delay != info->port.close_delay) ||
0ad9e7d1 1383 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK)))
1c45607a 1384 return -EPERM;
0ad9e7d1 1385 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1c45607a
JS		 1386 (new_serial.flags & ASYNC_USR_MASK));
1387 } else {
1da177e4 1388 /*
1c45607a
JS		 1389 * OK, past this point, all the error checking has been done.
1390 * At this point, we start making changes.....
1da177e4 1391 */
0ad9e7d1 1392 info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) |
1c45607a 1393 (new_serial.flags & ASYNC_FLAGS));
44b7d1b3
AC		 1394 info->port.close_delay = new_serial.close_delay * HZ / 100;
1395 info->port.closing_wait = new_serial.closing_wait * HZ / 100;
0ad9e7d1
AC		 1396 info->port.tty->low_latency =
1397 (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
0ad9e7d1 1398 if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
80ff8a80
JS		 1399 (new_serial.baud_base != info->baud_base ||
1400 new_serial.custom_divisor !=
1401 info->custom_divisor)) {
1402 baud = new_serial.baud_base / new_serial.custom_divisor;
0ad9e7d1 1403 tty_encode_baud_rate(info->port.tty, baud, baud);
80ff8a80 1404 }
1c45607a 1405 }
fc83815c 1406
1c45607a 1407 info->type = new_serial.type;
1da177e4 1408
1c45607a
JS		 1409 process_txrx_fifo(info);
1410
0ad9e7d1
AC		 1411 if (info->port.flags & ASYNC_INITIALIZED) {
1412 if (flags != (info->port.flags & ASYNC_SPD_MASK)) {
1c45607a
JS		 1413 spin_lock_irqsave(&info->slock, sl_flags);
1414 mxser_change_speed(info, NULL);
1415 spin_unlock_irqrestore(&info->slock, sl_flags);
1da177e4 1416 }
1c45607a
JS		 1417 } else
1418 retval = mxser_startup(info);
1da177e4 1419
1c45607a
JS		 1420 return retval;
1421}
1da177e4 1422
1c45607a
JS		 1423/*
1424 * mxser_get_lsr_info - get line status register info
1425 *
1426 * Purpose: Let user call ioctl() to get info when the UART physically
1427 * is emptied. On bus types like RS485, the transmitter must
1428 * release the bus after transmitting. This must be done when
1429 * the transmit shift register is empty, not be done when the
1430 * transmit holding register is empty. This functionality
1431 * allows an RS485 driver to be written in user space.
1432 */
1433static int mxser_get_lsr_info(struct mxser_port *info,
1434 unsigned int __user *value)
1435{
1436 unsigned char status;
1437 unsigned int result;
1438 unsigned long flags;
1da177e4 1439
1c45607a
JS		 1440 spin_lock_irqsave(&info->slock, flags);
1441 status = inb(info->ioaddr + UART_LSR);
1442 spin_unlock_irqrestore(&info->slock, flags);
1443 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1444 return put_user(result, value);
1445}
1da177e4 1446
1c45607a
JS		 1447static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
1448{
1449 struct mxser_port *info = tty->driver_data;
1450 unsigned char control, status;
1451 unsigned long flags;
1da177e4 1452
8ea2c2ec 1453
1c45607a
JS		 1454 if (tty->index == MXSER_PORTS)
1455 return -ENOIOCTLCMD;
1456 if (test_bit(TTY_IO_ERROR, &tty->flags))
1457 return -EIO;
1da177e4 1458
1c45607a 1459 control = info->MCR;
1da177e4 1460
1c45607a
JS		 1461 spin_lock_irqsave(&info->slock, flags);
1462 status = inb(info->ioaddr + UART_MSR);
1463 if (status & UART_MSR_ANY_DELTA)
1464 mxser_check_modem_status(info, status);
1465 spin_unlock_irqrestore(&info->slock, flags);
1466 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1467 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1468 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1469 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1470 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1471 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1472}
1da177e4 1473
1c45607a
JS		 1474static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1475 unsigned int set, unsigned int clear)
1476{
1477 struct mxser_port *info = tty->driver_data;
1478 unsigned long flags;
1da177e4 1479
1da177e4 1480
1c45607a
JS		 1481 if (tty->index == MXSER_PORTS)
1482 return -ENOIOCTLCMD;
1483 if (test_bit(TTY_IO_ERROR, &tty->flags))
1484 return -EIO;
1da177e4 1485
1c45607a 1486 spin_lock_irqsave(&info->slock, flags);
1da177e4 1487
1c45607a
JS		 1488 if (set & TIOCM_RTS)
1489 info->MCR |= UART_MCR_RTS;
1490 if (set & TIOCM_DTR)
1491 info->MCR |= UART_MCR_DTR;
1da177e4 1492
1c45607a
JS		 1493 if (clear & TIOCM_RTS)
1494 info->MCR &= ~UART_MCR_RTS;
1495 if (clear & TIOCM_DTR)
1496 info->MCR &= ~UART_MCR_DTR;
8ea2c2ec 1497
1c45607a
JS		 1498 outb(info->MCR, info->ioaddr + UART_MCR);
1499 spin_unlock_irqrestore(&info->slock, flags);
1500 return 0;
1501}
1da177e4 1502
1c45607a
JS		 1503static int __init mxser_program_mode(int port)
1504{
1505 int id, i, j, n;
1506
1507 outb(0, port);
1508 outb(0, port);
1509 outb(0, port);
1510 (void)inb(port);
1511 (void)inb(port);
1512 outb(0, port);
1513 (void)inb(port);
1514
1515 id = inb(port + 1) & 0x1F;
1516 if ((id != C168_ASIC_ID) &&
1517 (id != C104_ASIC_ID) &&
1518 (id != C102_ASIC_ID) &&
1519 (id != CI132_ASIC_ID) &&
1520 (id != CI134_ASIC_ID) &&
1521 (id != CI104J_ASIC_ID))
1522 return -1;
1523 for (i = 0, j = 0; i < 4; i++) {
1524 n = inb(port + 2);
1525 if (n == 'M') {
1526 j = 1;
1527 } else if ((j == 1) && (n == 1)) {
1528 j = 2;
1529 break;
1530 } else
1531 j = 0;
1da177e4 1532 }
1c45607a
JS		 1533 if (j != 2)
1534 id = -2;
1535 return id;
1da177e4
LT		 1536}
1537
1c45607a
JS		 1538static void __init mxser_normal_mode(int port)
1539{
1540 int i, n;
1541
1542 outb(0xA5, port + 1);
1543 outb(0x80, port + 3);
1544 outb(12, port + 0); /* 9600 bps */
1545 outb(0, port + 1);
1546 outb(0x03, port + 3); /* 8 data bits */
1547 outb(0x13, port + 4); /* loop back mode */
1548 for (i = 0; i < 16; i++) {
1549 n = inb(port + 5);
1550 if ((n & 0x61) == 0x60)
1551 break;
1552 if ((n & 1) == 1)
1553 (void)inb(port);
1554 }
1555 outb(0x00, port + 4);
1556}
1557
1558#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1559#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1560#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1561#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1562#define EN_CCMD 0x000 /* Chip's command register */
1563#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1564#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1565#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1566#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1567#define EN0_DCFG 0x00E /* Data configuration reg WR */
1568#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1569#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1570#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1571static int __init mxser_read_register(int port, unsigned short *regs)
1572{
1573 int i, k, value, id;
1574 unsigned int j;
1575
1576 id = mxser_program_mode(port);
1577 if (id < 0)
1578 return id;
1579 for (i = 0; i < 14; i++) {
1580 k = (i & 0x3F) | 0x180;
1581 for (j = 0x100; j > 0; j >>= 1) {
1582 outb(CHIP_CS, port);
1583 if (k & j) {
1584 outb(CHIP_CS | CHIP_DO, port);
1585 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1586 } else {
1587 outb(CHIP_CS, port);
1588 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1589 }
1590 }
1591 (void)inb(port);
1592 value = 0;
1593 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1594 outb(CHIP_CS, port);
1595 outb(CHIP_CS | CHIP_SK, port);
1596 if (inb(port) & CHIP_DI)
1597 value |= j;
1598 }
1599 regs[i] = value;
1600 outb(0, port);
1601 }
1602 mxser_normal_mode(port);
1603 return id;
1604}
1da177e4
LT		 1605
1606static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1607{
1c45607a
JS		 1608 struct mxser_port *port;
1609 int result, status;
1610 unsigned int i, j;
9d6d162d 1611 int ret = 0;
1da177e4
LT		 1612
1613 switch (cmd) {
1da177e4 1614 case MOXA_GET_MAJOR:
41aee9a1
JS		 1615 printk(KERN_WARNING "mxser: '%s' uses deprecated ioctl %x, fix "
1616 "your userspace\n", current->comm, cmd);
1c45607a 1617 return put_user(ttymajor, (int __user *)argp);
1da177e4
LT		 1618
1619 case MOXA_CHKPORTENABLE:
1620 result = 0;
9d6d162d 1621 lock_kernel();
1c45607a
JS		 1622 for (i = 0; i < MXSER_BOARDS; i++)
1623 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1624 if (mxser_boards[i].ports[j].ioaddr)
1625 result |= (1 << i);
9d6d162d 1626 unlock_kernel();
8ea2c2ec 1627 return put_user(result, (unsigned long __user *)argp);
1da177e4 1628 case MOXA_GETDATACOUNT:
9d6d162d 1629 lock_kernel();
1da177e4 1630 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
9d6d162d
AC		 1631 ret = -EFAULT;
1632 unlock_kernel();
1633 return ret;
72800df9
JS		 1634 case MOXA_GETMSTATUS: {
1635 struct mxser_mstatus ms, __user *msu = argp;
9d6d162d 1636 lock_kernel();
1c45607a
JS		 1637 for (i = 0; i < MXSER_BOARDS; i++)
1638 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1639 port = &mxser_boards[i].ports[j];
72800df9 1640 memset(&ms, 0, sizeof(ms));
1c45607a 1641
72800df9
JS		 1642 if (!port->ioaddr)
1643 goto copy;
1da177e4 1644
0ad9e7d1 1645 if (!port->port.tty || !port->port.tty->termios)
72800df9 1646 ms.cflag = port->normal_termios.c_cflag;
1c45607a 1647 else
72800df9 1648 ms.cflag = port->port.tty->termios->c_cflag;
1da177e4 1649
1c45607a 1650 status = inb(port->ioaddr + UART_MSR);
72800df9
JS		 1651 if (status & UART_MSR_DCD)
1652 ms.dcd = 1;
1653 if (status & UART_MSR_DSR)
1654 ms.dsr = 1;
1655 if (status & UART_MSR_CTS)
1656 ms.cts = 1;
1657 copy:
1658 if (copy_to_user(msu, &ms, sizeof(ms))) {
1659 unlock_kernel();
1660 return -EFAULT;
1661 }
1662 msu++;
1c45607a 1663 }
9d6d162d 1664 unlock_kernel();
1da177e4 1665 return 0;
72800df9 1666 }
8ea2c2ec 1667 case MOXA_ASPP_MON_EXT: {
72800df9
JS		 1668 struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
1669 unsigned int cflag, iflag, p;
1670 u8 opmode;
1671
1672 me = kzalloc(sizeof(*me), GFP_KERNEL);
1673 if (!me)
1674 return -ENOMEM;
1c45607a 1675
9d6d162d 1676 lock_kernel();
72800df9
JS		 1677 for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
1678 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
1679 if (p >= ARRAY_SIZE(me->rx_cnt)) {
1680 i = MXSER_BOARDS;
1681 break;
1682 }
1c45607a
JS		 1683 port = &mxser_boards[i].ports[j];
1684 if (!port->ioaddr)
1da177e4
LT		 1685 continue;
1686
72800df9 1687 status = mxser_get_msr(port->ioaddr, 0, p);
1c45607a 1688
1da177e4 1689 if (status & UART_MSR_TERI)
1c45607a 1690 port->icount.rng++;
1da177e4 1691 if (status & UART_MSR_DDSR)
1c45607a 1692 port->icount.dsr++;
1da177e4 1693 if (status & UART_MSR_DDCD)
1c45607a 1694 port->icount.dcd++;
1da177e4 1695 if (status & UART_MSR_DCTS)
1c45607a
JS		 1696 port->icount.cts++;
1697
1698 port->mon_data.modem_status = status;
72800df9
JS		 1699 me->rx_cnt[p] = port->mon_data.rxcnt;
1700 me->tx_cnt[p] = port->mon_data.txcnt;
1701 me->up_rxcnt[p] = port->mon_data.up_rxcnt;
1702 me->up_txcnt[p] = port->mon_data.up_txcnt;
1703 me->modem_status[p] =
1c45607a 1704 port->mon_data.modem_status;
72800df9 1705 me->baudrate[p] = tty_get_baud_rate(port->port.tty);
1c45607a 1706
0ad9e7d1 1707 if (!port->port.tty || !port->port.tty->termios) {
1c45607a
JS		 1708 cflag = port->normal_termios.c_cflag;
1709 iflag = port->normal_termios.c_iflag;
1da177e4 1710 } else {
0ad9e7d1
AC		 1711 cflag = port->port.tty->termios->c_cflag;
1712 iflag = port->port.tty->termios->c_iflag;
1da177e4
LT		 1713 }
1714
72800df9
JS		 1715 me->databits[p] = cflag & CSIZE;
1716 me->stopbits[p] = cflag & CSTOPB;
1717 me->parity[p] = cflag & (PARENB | PARODD |
1718 CMSPAR);
1da177e4
LT		 1719
1720 if (cflag & CRTSCTS)
72800df9 1721 me->flowctrl[p] |= 0x03;
1da177e4
LT		 1722
1723 if (iflag & (IXON | IXOFF))
72800df9 1724 me->flowctrl[p] |= 0x0C;
1da177e4 1725
1c45607a 1726 if (port->type == PORT_16550A)
72800df9 1727 me->fifo[p] = 1;
1da177e4 1728
72800df9
JS		 1729 opmode = inb(port->opmode_ioaddr) >>
1730 ((p % 4) * 2);
1da177e4 1731 opmode &= OP_MODE_MASK;
72800df9 1732 me->iftype[p] = opmode;
1da177e4 1733 }
9d6d162d
AC		 1734 }
1735 unlock_kernel();
72800df9
JS		 1736 if (copy_to_user(argp, me, sizeof(*me)))
1737 ret = -EFAULT;
1738 kfree(me);
1739 return ret;
9d6d162d
AC		 1740 }
1741 default:
1da177e4
LT		 1742 return -ENOIOCTLCMD;
1743 }
1744 return 0;
1745}
1746
1c45607a
JS		 1747static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1748 struct async_icount *cprev)
1da177e4 1749{
1c45607a
JS		 1750 struct async_icount cnow;
1751 unsigned long flags;
1752 int ret;
1da177e4 1753
1c45607a
JS		 1754 spin_lock_irqsave(&info->slock, flags);
1755 cnow = info->icount; /* atomic copy */
1756 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 1757
1c45607a
JS		 1758 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1759 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1760 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1761 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1da177e4 1762
1c45607a
JS		 1763 *cprev = cnow;
1764
1765 return ret;
1766}
1767
1768static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1769 unsigned int cmd, unsigned long arg)
1da177e4 1770{
1c45607a
JS		 1771 struct mxser_port *info = tty->driver_data;
1772 struct async_icount cnow;
1c45607a
JS		 1773 unsigned long flags;
1774 void __user *argp = (void __user *)arg;
1775 int retval;
1da177e4 1776
1c45607a
JS		 1777 if (tty->index == MXSER_PORTS)
1778 return mxser_ioctl_special(cmd, argp);
1da177e4 1779
1c45607a
JS		 1780 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1781 int p;
1782 unsigned long opmode;
1783 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1784 int shiftbit;
1785 unsigned char val, mask;
1da177e4 1786
1c45607a
JS		 1787 p = tty->index % 4;
1788 if (cmd == MOXA_SET_OP_MODE) {
1789 if (get_user(opmode, (int __user *) argp))
1790 return -EFAULT;
1791 if (opmode != RS232_MODE &&
1792 opmode != RS485_2WIRE_MODE &&
1793 opmode != RS422_MODE &&
1794 opmode != RS485_4WIRE_MODE)
1795 return -EFAULT;
9d6d162d 1796 lock_kernel();
1c45607a
JS		 1797 mask = ModeMask[p];
1798 shiftbit = p * 2;
1799 val = inb(info->opmode_ioaddr);
1800 val &= mask;
1801 val |= (opmode << shiftbit);
1802 outb(val, info->opmode_ioaddr);
9d6d162d 1803 unlock_kernel();
1c45607a 1804 } else {
9d6d162d 1805 lock_kernel();
1c45607a
JS		 1806 shiftbit = p * 2;
1807 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1808 opmode &= OP_MODE_MASK;
9d6d162d 1809 unlock_kernel();
1c45607a
JS		 1810 if (put_user(opmode, (int __user *)argp))
1811 return -EFAULT;
1812 }
1813 return 0;
1814 }
1815
1816 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT &&
1817 test_bit(TTY_IO_ERROR, &tty->flags))
1818 return -EIO;
1819
1820 switch (cmd) {
1c45607a 1821 case TIOCGSERIAL:
9d6d162d
AC		 1822 lock_kernel();
1823 retval = mxser_get_serial_info(info, argp);
1824 unlock_kernel();
1825 return retval;
1c45607a 1826 case TIOCSSERIAL:
9d6d162d
AC		 1827 lock_kernel();
1828 retval = mxser_set_serial_info(info, argp);
1829 unlock_kernel();
1830 return retval;
1c45607a 1831 case TIOCSERGETLSR: /* Get line status register */
9d6d162d 1832 return mxser_get_lsr_info(info, argp);
1c45607a
JS		 1833 /*
1834 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1835 * - mask passed in arg for lines of interest
1836 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1837 * Caller should use TIOCGICOUNT to see which one it was
1838 */
1839 case TIOCMIWAIT:
1840 spin_lock_irqsave(&info->slock, flags);
1841 cnow = info->icount; /* note the counters on entry */
1842 spin_unlock_irqrestore(&info->slock, flags);
1843
1844 return wait_event_interruptible(info->delta_msr_wait,
1845 mxser_cflags_changed(info, arg, &cnow));
1846 /*
1847 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1848 * Return: write counters to the user passed counter struct
1849 * NB: both 1->0 and 0->1 transitions are counted except for
1850 * RI where only 0->1 is counted.
1851 */
41aee9a1
JS		 1852 case TIOCGICOUNT: {
1853 struct serial_icounter_struct icnt = { 0 };
1c45607a
JS		 1854 spin_lock_irqsave(&info->slock, flags);
1855 cnow = info->icount;
1856 spin_unlock_irqrestore(&info->slock, flags);
41aee9a1
JS		 1857
1858 icnt.frame = cnow.frame;
1859 icnt.brk = cnow.brk;
1860 icnt.overrun = cnow.overrun;
1861 icnt.buf_overrun = cnow.buf_overrun;
1862 icnt.parity = cnow.parity;
1863 icnt.rx = cnow.rx;
1864 icnt.tx = cnow.tx;
1865 icnt.cts = cnow.cts;
1866 icnt.dsr = cnow.dsr;
1867 icnt.rng = cnow.rng;
1868 icnt.dcd = cnow.dcd;
1869
1870 return copy_to_user(argp, &icnt, sizeof(icnt)) ? -EFAULT : 0;
1871 }
1c45607a
JS		 1872 case MOXA_HighSpeedOn:
1873 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1874 case MOXA_SDS_RSTICOUNTER:
9d6d162d 1875 lock_kernel();
1c45607a
JS		 1876 info->mon_data.rxcnt = 0;
1877 info->mon_data.txcnt = 0;
9d6d162d 1878 unlock_kernel();
1c45607a
JS		 1879 return 0;
1880
1881 case MOXA_ASPP_OQUEUE:{
1882 int len, lsr;
1883
9d6d162d 1884 lock_kernel();
1c45607a 1885 len = mxser_chars_in_buffer(tty);
1c45607a 1886 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT;
1c45607a 1887 len += (lsr ? 0 : 1);
9d6d162d 1888 unlock_kernel();
1c45607a
JS		 1889
1890 return put_user(len, (int __user *)argp);
1891 }
1892 case MOXA_ASPP_MON: {
1893 int mcr, status;
1894
9d6d162d 1895 lock_kernel();
1c45607a
JS		 1896 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1897 mxser_check_modem_status(info, status);
1898
1899 mcr = inb(info->ioaddr + UART_MCR);
1900 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1901 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1902 else
1903 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1904
1905 if (mcr & MOXA_MUST_MCR_TX_XON)
1906 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1907 else
1908 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1909
0ad9e7d1 1910 if (info->port.tty->hw_stopped)
1c45607a
JS		 1911 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1912 else
1913 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
9d6d162d 1914 unlock_kernel();
1c45607a
JS		 1915 if (copy_to_user(argp, &info->mon_data,
1916 sizeof(struct mxser_mon)))
1917 return -EFAULT;
1918
1919 return 0;
1920 }
1921 case MOXA_ASPP_LSTATUS: {
1922 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1923 return -EFAULT;
1924
1925 info->err_shadow = 0;
1926 return 0;
1927 }
1928 case MOXA_SET_BAUD_METHOD: {
1929 int method;
1930
1931 if (get_user(method, (int __user *)argp))
1932 return -EFAULT;
1933 mxser_set_baud_method[tty->index] = method;
1934 return put_user(method, (int __user *)argp);
1935 }
1936 default:
1937 return -ENOIOCTLCMD;
1938 }
1939 return 0;
1940}
1941
1942static void mxser_stoprx(struct tty_struct *tty)
1943{
1944 struct mxser_port *info = tty->driver_data;
1945
1946 info->ldisc_stop_rx = 1;
1947 if (I_IXOFF(tty)) {
1948 if (info->board->chip_flag) {
1949 info->IER &= ~MOXA_MUST_RECV_ISR;
1950 outb(info->IER, info->ioaddr + UART_IER);
1951 } else {
1952 info->x_char = STOP_CHAR(tty);
1953 outb(0, info->ioaddr + UART_IER);
1954 info->IER |= UART_IER_THRI;
1955 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1956 }
1957 }
1958
0ad9e7d1 1959 if (info->port.tty->termios->c_cflag & CRTSCTS) {
1c45607a
JS		 1960 info->MCR &= ~UART_MCR_RTS;
1961 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1962 }
1963}
1964
1965/*
1966 * This routine is called by the upper-layer tty layer to signal that
1967 * incoming characters should be throttled.
1968 */
1969static void mxser_throttle(struct tty_struct *tty)
1970{
1da177e4 1971 mxser_stoprx(tty);
1da177e4
LT		 1972}
1973
1974static void mxser_unthrottle(struct tty_struct *tty)
1975{
1c45607a 1976 struct mxser_port *info = tty->driver_data;
1da177e4 1977
1c45607a
JS		 1978 /* startrx */
1979 info->ldisc_stop_rx = 0;
1980 if (I_IXOFF(tty)) {
1981 if (info->x_char)
1982 info->x_char = 0;
1983 else {
1984 if (info->board->chip_flag) {
1985 info->IER |= MOXA_MUST_RECV_ISR;
1986 outb(info->IER, info->ioaddr + UART_IER);
1987 } else {
1988 info->x_char = START_CHAR(tty);
1989 outb(0, info->ioaddr + UART_IER);
1990 info->IER |= UART_IER_THRI;
1991 outb(info->IER, info->ioaddr + UART_IER);
1992 }
1da177e4 1993 }
1c45607a 1994 }
1da177e4 1995
0ad9e7d1 1996 if (info->port.tty->termios->c_cflag & CRTSCTS) {
1c45607a
JS		 1997 info->MCR |= UART_MCR_RTS;
1998 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1999 }
2000}
2001
2002/*
2003 * mxser_stop() and mxser_start()
2004 *
2005 * This routines are called before setting or resetting tty->stopped.
2006 * They enable or disable transmitter interrupts, as necessary.
2007 */
2008static void mxser_stop(struct tty_struct *tty)
2009{
1c45607a 2010 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2011 unsigned long flags;
2012
2013 spin_lock_irqsave(&info->slock, flags);
2014 if (info->IER & UART_IER_THRI) {
2015 info->IER &= ~UART_IER_THRI;
1c45607a 2016 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 2017 }
2018 spin_unlock_irqrestore(&info->slock, flags);
2019}
2020
2021static void mxser_start(struct tty_struct *tty)
2022{
1c45607a 2023 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2024 unsigned long flags;
2025
2026 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 2027 if (info->xmit_cnt && info->port.xmit_buf) {
1c45607a 2028 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 2029 info->IER |= UART_IER_THRI;
1c45607a 2030 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 2031 }
2032 spin_unlock_irqrestore(&info->slock, flags);
2033}
2034
1c45607a
JS		 2035static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
2036{
2037 struct mxser_port *info = tty->driver_data;
2038 unsigned long flags;
2039
2040 spin_lock_irqsave(&info->slock, flags);
2041 mxser_change_speed(info, old_termios);
2042 spin_unlock_irqrestore(&info->slock, flags);
2043
2044 if ((old_termios->c_cflag & CRTSCTS) &&
2045 !(tty->termios->c_cflag & CRTSCTS)) {
2046 tty->hw_stopped = 0;
2047 mxser_start(tty);
2048 }
2049
2050 /* Handle sw stopped */
2051 if ((old_termios->c_iflag & IXON) &&
2052 !(tty->termios->c_iflag & IXON)) {
2053 tty->stopped = 0;
2054
2055 if (info->board->chip_flag) {
2056 spin_lock_irqsave(&info->slock, flags);
148ff86b
CH		 2057 mxser_disable_must_rx_software_flow_control(
2058 info->ioaddr);
1c45607a
JS		 2059 spin_unlock_irqrestore(&info->slock, flags);
2060 }
2061
2062 mxser_start(tty);
2063 }
2064}
2065
1da177e4
LT		 2066/*
2067 * mxser_wait_until_sent() --- wait until the transmitter is empty
2068 */
2069static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
2070{
1c45607a 2071 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2072 unsigned long orig_jiffies, char_time;
2073 int lsr;
2074
2075 if (info->type == PORT_UNKNOWN)
2076 return;
2077
2078 if (info->xmit_fifo_size == 0)
2079 return; /* Just in case.... */
2080
2081 orig_jiffies = jiffies;
2082 /*
2083 * Set the check interval to be 1/5 of the estimated time to
2084 * send a single character, and make it at least 1. The check
2085 * interval should also be less than the timeout.
2086 *
2087 * Note: we have to use pretty tight timings here to satisfy
2088 * the NIST-PCTS.
2089 */
2090 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
2091 char_time = char_time / 5;
2092 if (char_time == 0)
2093 char_time = 1;
2094 if (timeout && timeout < char_time)
2095 char_time = timeout;
2096 /*
2097 * If the transmitter hasn't cleared in twice the approximate
2098 * amount of time to send the entire FIFO, it probably won't
2099 * ever clear. This assumes the UART isn't doing flow
2100 * control, which is currently the case. Hence, if it ever
2101 * takes longer than info->timeout, this is probably due to a
2102 * UART bug of some kind. So, we clamp the timeout parameter at
2103 * 2*info->timeout.
2104 */
2105 if (!timeout || timeout > 2 * info->timeout)
2106 timeout = 2 * info->timeout;
2107#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8ea2c2ec
JJ		 2108 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
2109 timeout, char_time);
1da177e4
LT		 2110 printk("jiff=%lu...", jiffies);
2111#endif
978e595f 2112 lock_kernel();
1c45607a 2113 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
1da177e4
LT		 2114#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2115 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
2116#endif
da4cd8df 2117 schedule_timeout_interruptible(char_time);
1da177e4 2118 if (signal_pending(current))
1c45607a
JS		 2119 break;
2120 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2121 break;
1da177e4 2122 }
1c45607a 2123 set_current_state(TASK_RUNNING);
978e595f 2124 unlock_kernel();
1da177e4 2125
1c45607a
JS		 2126#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2127 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
2128#endif
2129}
1da177e4 2130
1c45607a
JS		 2131/*
2132 * This routine is called by tty_hangup() when a hangup is signaled.
2133 */
2134static void mxser_hangup(struct tty_struct *tty)
2135{
2136 struct mxser_port *info = tty->driver_data;
1da177e4 2137
1c45607a
JS		 2138 mxser_flush_buffer(tty);
2139 mxser_shutdown(info);
0ad9e7d1
AC		 2140 info->port.count = 0;
2141 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
2142 info->port.tty = NULL;
2143 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 2144}
2145
1c45607a
JS		 2146/*
2147 * mxser_rs_break() --- routine which turns the break handling on or off
2148 */
9e98966c 2149static int mxser_rs_break(struct tty_struct *tty, int break_state)
1da177e4 2150{
1c45607a 2151 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2152 unsigned long flags;
2153
1c45607a
JS		 2154 spin_lock_irqsave(&info->slock, flags);
2155 if (break_state == -1)
2156 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2157 info->ioaddr + UART_LCR);
2158 else
2159 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2160 info->ioaddr + UART_LCR);
2161 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 2162 return 0;
1c45607a 2163}
1da177e4 2164
1c45607a
JS		 2165static void mxser_receive_chars(struct mxser_port *port, int *status)
2166{
0ad9e7d1 2167 struct tty_struct *tty = port->port.tty;
1c45607a
JS		 2168 unsigned char ch, gdl;
2169 int ignored = 0;
2170 int cnt = 0;
2171 int recv_room;
2172 int max = 256;
1da177e4 2173
1c45607a
JS		 2174 recv_room = tty->receive_room;
2175 if ((recv_room == 0) && (!port->ldisc_stop_rx))
2176 mxser_stoprx(tty);
1da177e4 2177
1c45607a 2178 if (port->board->chip_flag != MOXA_OTHER_UART) {
1da177e4 2179
1c45607a
JS		 2180 if (*status & UART_LSR_SPECIAL)
2181 goto intr_old;
2182 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2183 (*status & MOXA_MUST_LSR_RERR))
2184 goto intr_old;
2185 if (*status & MOXA_MUST_LSR_RERR)
2186 goto intr_old;
1da177e4 2187
1c45607a
JS		 2188 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2189
2190 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2191 gdl &= MOXA_MUST_GDL_MASK;
2192 if (gdl >= recv_room) {
2193 if (!port->ldisc_stop_rx)
2194 mxser_stoprx(tty);
2195 }
2196 while (gdl--) {
2197 ch = inb(port->ioaddr + UART_RX);
2198 tty_insert_flip_char(tty, ch, 0);
2199 cnt++;
2200 }
2201 goto end_intr;
1da177e4 2202 }
1c45607a
JS		 2203intr_old:
2204
2205 do {
2206 if (max-- < 0)
2207 break;
1da177e4 2208
1c45607a
JS		 2209 ch = inb(port->ioaddr + UART_RX);
2210 if (port->board->chip_flag && (*status & UART_LSR_OE))
2211 outb(0x23, port->ioaddr + UART_FCR);
2212 *status &= port->read_status_mask;
2213 if (*status & port->ignore_status_mask) {
2214 if (++ignored > 100)
2215 break;
2216 } else {
2217 char flag = 0;
2218 if (*status & UART_LSR_SPECIAL) {
2219 if (*status & UART_LSR_BI) {
2220 flag = TTY_BREAK;
2221 port->icount.brk++;
1da177e4 2222
0ad9e7d1 2223 if (port->port.flags & ASYNC_SAK)
1c45607a
JS		 2224 do_SAK(tty);
2225 } else if (*status & UART_LSR_PE) {
2226 flag = TTY_PARITY;
2227 port->icount.parity++;
2228 } else if (*status & UART_LSR_FE) {
2229 flag = TTY_FRAME;
2230 port->icount.frame++;
2231 } else if (*status & UART_LSR_OE) {
2232 flag = TTY_OVERRUN;
2233 port->icount.overrun++;
2234 } else
2235 flag = TTY_BREAK;
2236 }
2237 tty_insert_flip_char(tty, ch, flag);
2238 cnt++;
2239 if (cnt >= recv_room) {
2240 if (!port->ldisc_stop_rx)
2241 mxser_stoprx(tty);
2242 break;
2243 }
1da177e4 2244
1c45607a 2245 }
1da177e4 2246
1c45607a
JS		 2247 if (port->board->chip_flag)
2248 break;
1da177e4 2249
1c45607a
JS		 2250 *status = inb(port->ioaddr + UART_LSR);
2251 } while (*status & UART_LSR_DR);
1da177e4 2252
1c45607a 2253end_intr:
0ad9e7d1 2254 mxvar_log.rxcnt[port->port.tty->index] += cnt;
1c45607a
JS		 2255 port->mon_data.rxcnt += cnt;
2256 port->mon_data.up_rxcnt += cnt;
1da177e4 2257
1c45607a
JS		 2258 /*
2259 * We are called from an interrupt context with &port->slock
2260 * being held. Drop it temporarily in order to prevent
2261 * recursive locking.
2262 */
2263 spin_unlock(&port->slock);
2264 tty_flip_buffer_push(tty);
2265 spin_lock(&port->slock);
1da177e4
LT		 2266}
2267
1c45607a 2268static void mxser_transmit_chars(struct mxser_port *port)
1da177e4 2269{
1c45607a 2270 int count, cnt;
1da177e4 2271
1c45607a
JS		 2272 if (port->x_char) {
2273 outb(port->x_char, port->ioaddr + UART_TX);
2274 port->x_char = 0;
0ad9e7d1 2275 mxvar_log.txcnt[port->port.tty->index]++;
1c45607a
JS		 2276 port->mon_data.txcnt++;
2277 port->mon_data.up_txcnt++;
2278 port->icount.tx++;
2279 return;
2280 }
1da177e4 2281
0ad9e7d1 2282 if (port->port.xmit_buf == NULL)
1c45607a 2283 return;
1da177e4 2284
0ad9e7d1
AC		 2285 if ((port->xmit_cnt <= 0) || port->port.tty->stopped ||
2286 (port->port.tty->hw_stopped &&
1c45607a
JS		 2287 (port->type != PORT_16550A) &&
2288 (!port->board->chip_flag))) {
2289 port->IER &= ~UART_IER_THRI;
2290 outb(port->IER, port->ioaddr + UART_IER);
2291 return;
1da177e4
LT		 2292 }
2293
1c45607a
JS		 2294 cnt = port->xmit_cnt;
2295 count = port->xmit_fifo_size;
2296 do {
0ad9e7d1 2297 outb(port->port.xmit_buf[port->xmit_tail++],
1c45607a
JS		 2298 port->ioaddr + UART_TX);
2299 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2300 if (--port->xmit_cnt <= 0)
2301 break;
2302 } while (--count > 0);
0ad9e7d1 2303 mxvar_log.txcnt[port->port.tty->index] += (cnt - port->xmit_cnt);
1da177e4 2304
1c45607a
JS		 2305 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2306 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2307 port->icount.tx += (cnt - port->xmit_cnt);
1da177e4 2308
1c45607a 2309 if (port->xmit_cnt < WAKEUP_CHARS)
0ad9e7d1 2310 tty_wakeup(port->port.tty);
1c45607a
JS		 2311
2312 if (port->xmit_cnt <= 0) {
2313 port->IER &= ~UART_IER_THRI;
2314 outb(port->IER, port->ioaddr + UART_IER);
1da177e4 2315 }
1da177e4
LT		 2316}
2317
2318/*
1c45607a 2319 * This is the serial driver's generic interrupt routine
1da177e4 2320 */
1c45607a 2321static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1da177e4 2322{
1c45607a
JS		 2323 int status, iir, i;
2324 struct mxser_board *brd = NULL;
2325 struct mxser_port *port;
2326 int max, irqbits, bits, msr;
2327 unsigned int int_cnt, pass_counter = 0;
2328 int handled = IRQ_NONE;
1da177e4 2329
1c45607a
JS		 2330 for (i = 0; i < MXSER_BOARDS; i++)
2331 if (dev_id == &mxser_boards[i]) {
2332 brd = dev_id;
2333 break;
2334 }
1da177e4 2335
1c45607a
JS		 2336 if (i == MXSER_BOARDS)
2337 goto irq_stop;
2338 if (brd == NULL)
2339 goto irq_stop;
2340 max = brd->info->nports;
2341 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2342 irqbits = inb(brd->vector) & brd->vector_mask;
2343 if (irqbits == brd->vector_mask)
2344 break;
1da177e4 2345
1c45607a
JS		 2346 handled = IRQ_HANDLED;
2347 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2348 if (irqbits == brd->vector_mask)
2349 break;
2350 if (bits & irqbits)
2351 continue;
2352 port = &brd->ports[i];
2353
2354 int_cnt = 0;
2355 spin_lock(&port->slock);
2356 do {
2357 iir = inb(port->ioaddr + UART_IIR);
2358 if (iir & UART_IIR_NO_INT)
2359 break;
2360 iir &= MOXA_MUST_IIR_MASK;
0ad9e7d1
AC		 2361 if (!port->port.tty ||
2362 (port->port.flags & ASYNC_CLOSING) ||
2363 !(port->port.flags &
1c45607a
JS		 2364 ASYNC_INITIALIZED)) {
2365 status = inb(port->ioaddr + UART_LSR);
2366 outb(0x27, port->ioaddr + UART_FCR);
2367 inb(port->ioaddr + UART_MSR);
2368 break;
2369 }
1da177e4 2370
1c45607a
JS		 2371 status = inb(port->ioaddr + UART_LSR);
2372
2373 if (status & UART_LSR_PE)
2374 port->err_shadow |= NPPI_NOTIFY_PARITY;
2375 if (status & UART_LSR_FE)
2376 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2377 if (status & UART_LSR_OE)
2378 port->err_shadow |=
2379 NPPI_NOTIFY_HW_OVERRUN;
2380 if (status & UART_LSR_BI)
2381 port->err_shadow |= NPPI_NOTIFY_BREAK;
2382
2383 if (port->board->chip_flag) {
2384 if (iir == MOXA_MUST_IIR_GDA ||
2385 iir == MOXA_MUST_IIR_RDA ||
2386 iir == MOXA_MUST_IIR_RTO ||
2387 iir == MOXA_MUST_IIR_LSR)
2388 mxser_receive_chars(port,
2389 &status);
2390
2391 } else {
2392 status &= port->read_status_mask;
2393 if (status & UART_LSR_DR)
2394 mxser_receive_chars(port,
2395 &status);
2396 }
2397 msr = inb(port->ioaddr + UART_MSR);
2398 if (msr & UART_MSR_ANY_DELTA)
2399 mxser_check_modem_status(port, msr);
2400
2401 if (port->board->chip_flag) {
2402 if (iir == 0x02 && (status &
2403 UART_LSR_THRE))
2404 mxser_transmit_chars(port);
2405 } else {
2406 if (status & UART_LSR_THRE)
2407 mxser_transmit_chars(port);
2408 }
2409 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2410 spin_unlock(&port->slock);
2411 }
2412 }
1da177e4 2413
1c45607a
JS		 2414irq_stop:
2415 return handled;
2416}
1da177e4 2417
1c45607a
JS		 2418static const struct tty_operations mxser_ops = {
2419 .open = mxser_open,
2420 .close = mxser_close,
2421 .write = mxser_write,
2422 .put_char = mxser_put_char,
2423 .flush_chars = mxser_flush_chars,
2424 .write_room = mxser_write_room,
2425 .chars_in_buffer = mxser_chars_in_buffer,
2426 .flush_buffer = mxser_flush_buffer,
2427 .ioctl = mxser_ioctl,
2428 .throttle = mxser_throttle,
2429 .unthrottle = mxser_unthrottle,
2430 .set_termios = mxser_set_termios,
2431 .stop = mxser_stop,
2432 .start = mxser_start,
2433 .hangup = mxser_hangup,
2434 .break_ctl = mxser_rs_break,
2435 .wait_until_sent = mxser_wait_until_sent,
2436 .tiocmget = mxser_tiocmget,
2437 .tiocmset = mxser_tiocmset,
2438};
1da177e4 2439
1c45607a
JS		 2440/*
2441 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2442 */
1da177e4 2443
1c45607a
JS		 2444static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev,
2445 unsigned int irq)
2446{
2447 if (irq)
2448 free_irq(brd->irq, brd);
2449 if (pdev != NULL) { /* PCI */
2450#ifdef CONFIG_PCI
2451 pci_release_region(pdev, 2);
2452 pci_release_region(pdev, 3);
2453#endif
2454 } else {
2455 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2456 release_region(brd->vector, 1);
2457 }
1da177e4
LT		 2458}
2459
1c45607a
JS		 2460static int __devinit mxser_initbrd(struct mxser_board *brd,
2461 struct pci_dev *pdev)
1da177e4 2462{
1c45607a
JS		 2463 struct mxser_port *info;
2464 unsigned int i;
2465 int retval;
1da177e4 2466
83766bc6
JS		 2467 printk(KERN_INFO "mxser: max. baud rate = %d bps\n",
2468 brd->ports[0].max_baud);
1da177e4 2469
1c45607a
JS		 2470 for (i = 0; i < brd->info->nports; i++) {
2471 info = &brd->ports[i];
44b7d1b3 2472 tty_port_init(&info->port);
1c45607a
JS		 2473 info->board = brd;
2474 info->stop_rx = 0;
2475 info->ldisc_stop_rx = 0;
1da177e4 2476
1c45607a
JS		 2477 /* Enhance mode enabled here */
2478 if (brd->chip_flag != MOXA_OTHER_UART)
148ff86b 2479 mxser_enable_must_enchance_mode(info->ioaddr);
1da177e4 2480
0ad9e7d1 2481 info->port.flags = ASYNC_SHARE_IRQ;
1c45607a 2482 info->type = brd->uart_type;
1da177e4 2483
1c45607a 2484 process_txrx_fifo(info);
1da177e4 2485
1c45607a 2486 info->custom_divisor = info->baud_base * 16;
44b7d1b3
AC		 2487 info->port.close_delay = 5 * HZ / 10;
2488 info->port.closing_wait = 30 * HZ;
1c45607a 2489 info->normal_termios = mxvar_sdriver->init_termios;
1c45607a
JS		 2490 init_waitqueue_head(&info->delta_msr_wait);
2491 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2492 info->err_shadow = 0;
2493 spin_lock_init(&info->slock);
1da177e4 2494
1c45607a
JS		 2495 /* before set INT ISR, disable all int */
2496 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2497 info->ioaddr + UART_IER);
2498 }
1da177e4 2499
1c45607a
JS		 2500 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2501 brd);
2502 if (retval) {
2503 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2504 "conflict with another device.\n",
2505 brd->info->name, brd->irq);
2506 /* We hold resources, we need to release them. */
2507 mxser_release_res(brd, pdev, 0);
2508 }
2509 return retval;
2510}
1da177e4 2511
1c45607a 2512static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
1da177e4
LT		 2513{
2514 int id, i, bits;
2515 unsigned short regs[16], irq;
2516 unsigned char scratch, scratch2;
2517
1c45607a 2518 brd->chip_flag = MOXA_OTHER_UART;
1da177e4
LT		 2519
2520 id = mxser_read_register(cap, regs);
1c45607a
JS		 2521 switch (id) {
2522 case C168_ASIC_ID:
2523 brd->info = &mxser_cards[0];
2524 break;
2525 case C104_ASIC_ID:
2526 brd->info = &mxser_cards[1];
2527 break;
2528 case CI104J_ASIC_ID:
2529 brd->info = &mxser_cards[2];
2530 break;
2531 case C102_ASIC_ID:
2532 brd->info = &mxser_cards[5];
2533 break;
2534 case CI132_ASIC_ID:
2535 brd->info = &mxser_cards[6];
2536 break;
2537 case CI134_ASIC_ID:
2538 brd->info = &mxser_cards[7];
2539 break;
2540 default:
8ea2c2ec 2541 return 0;
1c45607a 2542 }
1da177e4
LT		 2543
2544 irq = 0;
1c45607a
JS		 2545 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2546 Flag-hack checks if configuration should be read as 2-port here. */
2547 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
1da177e4
LT		 2548 irq = regs[9] & 0xF000;
2549 irq = irq | (irq >> 4);
2550 if (irq != (regs[9] & 0xFF00))
83766bc6 2551 goto err_irqconflict;
1c45607a 2552 } else if (brd->info->nports == 4) {
1da177e4
LT		 2553 irq = regs[9] & 0xF000;
2554 irq = irq | (irq >> 4);
2555 irq = irq | (irq >> 8);
2556 if (irq != regs[9])
83766bc6 2557 goto err_irqconflict;
1c45607a 2558 } else if (brd->info->nports == 8) {
1da177e4
LT		 2559 irq = regs[9] & 0xF000;
2560 irq = irq | (irq >> 4);
2561 irq = irq | (irq >> 8);
2562 if ((irq != regs[9]) || (irq != regs[10]))
83766bc6 2563 goto err_irqconflict;
1da177e4
LT		 2564 }
2565
83766bc6
JS		 2566 if (!irq) {
2567 printk(KERN_ERR "mxser: interrupt number unset\n");
2568 return -EIO;
2569 }
1c45607a 2570 brd->irq = ((int)(irq & 0xF000) >> 12);
1da177e4 2571 for (i = 0; i < 8; i++)
1c45607a 2572 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
83766bc6
JS		 2573 if ((regs[12] & 0x80) == 0) {
2574 printk(KERN_ERR "mxser: invalid interrupt vector\n");
2575 return -EIO;
2576 }
1c45607a 2577 brd->vector = (int)regs[11]; /* interrupt vector */
1da177e4 2578 if (id == 1)
1c45607a 2579 brd->vector_mask = 0x00FF;
1da177e4 2580 else
1c45607a 2581 brd->vector_mask = 0x000F;
1da177e4
LT		 2582 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2583 if (regs[12] & bits) {
1c45607a
JS		 2584 brd->ports[i].baud_base = 921600;
2585 brd->ports[i].max_baud = 921600;
1da177e4 2586 } else {
1c45607a
JS		 2587 brd->ports[i].baud_base = 115200;
2588 brd->ports[i].max_baud = 115200;
1da177e4
LT		 2589 }
2590 }
2591 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2592 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2593 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2594 outb(scratch2, cap + UART_LCR);
2595 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2596 scratch = inb(cap + UART_IIR);
2597
2598 if (scratch & 0xC0)
1c45607a 2599 brd->uart_type = PORT_16550A;
1da177e4 2600 else
1c45607a
JS		 2601 brd->uart_type = PORT_16450;
2602 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
83766bc6
JS		 2603 "mxser(IO)")) {
2604 printk(KERN_ERR "mxser: can't request ports I/O region: "
2605 "0x%.8lx-0x%.8lx\n",
2606 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2607 8 * brd->info->nports - 1);
2608 return -EIO;
2609 }
1c45607a
JS		 2610 if (!request_region(brd->vector, 1, "mxser(vector)")) {
2611 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
83766bc6
JS		 2612 printk(KERN_ERR "mxser: can't request interrupt vector region: "
2613 "0x%.8lx-0x%.8lx\n",
2614 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2615 8 * brd->info->nports - 1);
2616 return -EIO;
1c45607a
JS		 2617 }
2618 return brd->info->nports;
83766bc6
JS		 2619
2620err_irqconflict:
2621 printk(KERN_ERR "mxser: invalid interrupt number\n");
2622 return -EIO;
1da177e4
LT		 2623}
2624
1c45607a
JS		 2625static int __devinit mxser_probe(struct pci_dev *pdev,
2626 const struct pci_device_id *ent)
1da177e4 2627{
1c45607a
JS		 2628#ifdef CONFIG_PCI
2629 struct mxser_board *brd;
2630 unsigned int i, j;
2631 unsigned long ioaddress;
2632 int retval = -EINVAL;
1da177e4 2633
1c45607a
JS		 2634 for (i = 0; i < MXSER_BOARDS; i++)
2635 if (mxser_boards[i].info == NULL)
2636 break;
2637
2638 if (i >= MXSER_BOARDS) {
83766bc6
JS		 2639 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
2640 "not configured\n", MXSER_BOARDS);
1c45607a
JS		 2641 goto err;
2642 }
2643
2644 brd = &mxser_boards[i];
2645 brd->idx = i * MXSER_PORTS_PER_BOARD;
83766bc6 2646 dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
1c45607a
JS		 2647 mxser_cards[ent->driver_data].name,
2648 pdev->bus->number, PCI_SLOT(pdev->devfn));
2649
2650 retval = pci_enable_device(pdev);
2651 if (retval) {
83766bc6 2652 dev_err(&pdev->dev, "PCI enable failed\n");
1c45607a
JS		 2653 goto err;
2654 }
2655
2656 /* io address */
2657 ioaddress = pci_resource_start(pdev, 2);
2658 retval = pci_request_region(pdev, 2, "mxser(IO)");
2659 if (retval)
2660 goto err;
2661
2662 brd->info = &mxser_cards[ent->driver_data];
2663 for (i = 0; i < brd->info->nports; i++)
2664 brd->ports[i].ioaddr = ioaddress + 8 * i;
2665
2666 /* vector */
2667 ioaddress = pci_resource_start(pdev, 3);
2668 retval = pci_request_region(pdev, 3, "mxser(vector)");
2669 if (retval)
2670 goto err_relio;
2671 brd->vector = ioaddress;
2672
2673 /* irq */
2674 brd->irq = pdev->irq;
2675
2676 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2677 brd->uart_type = PORT_16550A;
2678 brd->vector_mask = 0;
2679
2680 for (i = 0; i < brd->info->nports; i++) {
2681 for (j = 0; j < UART_INFO_NUM; j++) {
2682 if (Gpci_uart_info[j].type == brd->chip_flag) {
2683 brd->ports[i].max_baud =
2684 Gpci_uart_info[j].max_baud;
2685
2686 /* exception....CP-102 */
2687 if (brd->info->flags & MXSER_HIGHBAUD)
2688 brd->ports[i].max_baud = 921600;
2689 break;
1da177e4
LT		 2690 }
2691 }
1c45607a
JS		 2692 }
2693
2694 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2695 for (i = 0; i < brd->info->nports; i++) {
2696 if (i < 4)
2697 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2698 else
2699 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
1da177e4 2700 }
1c45607a
JS		 2701 outb(0, ioaddress + 4); /* default set to RS232 mode */
2702 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
1da177e4 2703 }
1c45607a
JS		 2704
2705 for (i = 0; i < brd->info->nports; i++) {
2706 brd->vector_mask |= (1 << i);
2707 brd->ports[i].baud_base = 921600;
2708 }
2709
2710 /* mxser_initbrd will hook ISR. */
2711 retval = mxser_initbrd(brd, pdev);
2712 if (retval)
2713 goto err_null;
2714
2715 for (i = 0; i < brd->info->nports; i++)
2716 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2717
2718 pci_set_drvdata(pdev, brd);
2719
2720 return 0;
2721err_relio:
2722 pci_release_region(pdev, 2);
2723err_null:
2724 brd->info = NULL;
2725err:
2726 return retval;
2727#else
2728 return -ENODEV;
2729#endif
1da177e4
LT		 2730}
2731
1c45607a 2732static void __devexit mxser_remove(struct pci_dev *pdev)
1da177e4 2733{
1c45607a
JS		 2734 struct mxser_board *brd = pci_get_drvdata(pdev);
2735 unsigned int i;
1da177e4 2736
1c45607a
JS		 2737 for (i = 0; i < brd->info->nports; i++)
2738 tty_unregister_device(mxvar_sdriver, brd->idx + i);
1da177e4 2739
1c45607a
JS		 2740 mxser_release_res(brd, pdev, 1);
2741 brd->info = NULL;
1da177e4
LT		 2742}
2743
1c45607a
JS		 2744static struct pci_driver mxser_driver = {
2745 .name = "mxser",
2746 .id_table = mxser_pcibrds,
2747 .probe = mxser_probe,
2748 .remove = __devexit_p(mxser_remove)
2749};
2750
2751static int __init mxser_module_init(void)
1da177e4 2752{
1c45607a 2753 struct mxser_board *brd;
1df00924
JS		 2754 unsigned int b, i, m;
2755 int retval;
1da177e4 2756
1c45607a
JS		 2757 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2758 if (!mxvar_sdriver)
2759 return -ENOMEM;
2760
2761 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2762 MXSER_VERSION);
2763
2764 /* Initialize the tty_driver structure */
2765 mxvar_sdriver->owner = THIS_MODULE;
2766 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
2767 mxvar_sdriver->name = "ttyMI";
2768 mxvar_sdriver->major = ttymajor;
2769 mxvar_sdriver->minor_start = 0;
2770 mxvar_sdriver->num = MXSER_PORTS + 1;
2771 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2772 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2773 mxvar_sdriver->init_termios = tty_std_termios;
2774 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2775 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2776 tty_set_operations(mxvar_sdriver, &mxser_ops);
2777
2778 retval = tty_register_driver(mxvar_sdriver);
2779 if (retval) {
2780 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2781 "tty driver !\n");
2782 goto err_put;
1da177e4 2783 }
1c45607a 2784
1c45607a 2785 /* Start finding ISA boards here */
1df00924
JS		 2786 for (m = 0, b = 0; b < MXSER_BOARDS; b++) {
2787 if (!ioaddr[b])
2788 continue;
2789
2790 brd = &mxser_boards[m];
2791 retval = mxser_get_ISA_conf(!ioaddr[b], brd);
2792 if (retval <= 0) {
2793 brd->info = NULL;
2794 continue;
2795 }
1c45607a 2796
1df00924
JS		 2797 printk(KERN_INFO "mxser: found MOXA %s board (CAP=0x%lx)\n",
2798 brd->info->name, ioaddr[b]);
83766bc6 2799
1df00924
JS		 2800 /* mxser_initbrd will hook ISR. */
2801 if (mxser_initbrd(brd, NULL) < 0) {
2802 brd->info = NULL;
2803 continue;
2804 }
1c45607a 2805
1df00924
JS		 2806 brd->idx = m * MXSER_PORTS_PER_BOARD;
2807 for (i = 0; i < brd->info->nports; i++)
2808 tty_register_device(mxvar_sdriver, brd->idx + i, NULL);
1c45607a 2809
1df00924
JS		 2810 m++;
2811 }
1c45607a
JS		 2812
2813 retval = pci_register_driver(&mxser_driver);
2814 if (retval) {
83766bc6 2815 printk(KERN_ERR "mxser: can't register pci driver\n");
1c45607a
JS		 2816 if (!m) {
2817 retval = -ENODEV;
2818 goto err_unr;
2819 } /* else: we have some ISA cards under control */
2820 }
2821
1c45607a
JS		 2822 return 0;
2823err_unr:
2824 tty_unregister_driver(mxvar_sdriver);
2825err_put:
2826 put_tty_driver(mxvar_sdriver);
2827 return retval;
2828}
2829
2830static void __exit mxser_module_exit(void)
2831{
2832 unsigned int i, j;
2833
1c45607a
JS		 2834 pci_unregister_driver(&mxser_driver);
2835
2836 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2837 if (mxser_boards[i].info != NULL)
2838 for (j = 0; j < mxser_boards[i].info->nports; j++)
2839 tty_unregister_device(mxvar_sdriver,
2840 mxser_boards[i].idx + j);
2841 tty_unregister_driver(mxvar_sdriver);
2842 put_tty_driver(mxvar_sdriver);
2843
2844 for (i = 0; i < MXSER_BOARDS; i++)
2845 if (mxser_boards[i].info != NULL)
2846 mxser_release_res(&mxser_boards[i], NULL, 1);
1da177e4
LT		 2847}
2848
2849module_init(mxser_module_init);
2850module_exit(mxser_module_exit);
Linux kernel - Deliverables
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