[deliverable/linux.git] / drivers / char / mxser.h

#ifndef _MXSER_H
#define _MXSER_H

/*
 *	Semi-public control interfaces
 */
 
/*
 *	MOXA ioctls
 */

#define MOXA			0x400
#define MOXA_GETDATACOUNT	(MOXA + 23)
#define	MOXA_GET_CONF		(MOXA + 35)
#define MOXA_DIAGNOSE		(MOXA + 50)
#define MOXA_CHKPORTENABLE	(MOXA + 60)
#define MOXA_HighSpeedOn	(MOXA + 61)
#define MOXA_GET_MAJOR		(MOXA + 63)
#define MOXA_GET_CUMAJOR	(MOXA + 64)
#define MOXA_GETMSTATUS		(MOXA + 65)
#define MOXA_SET_OP_MODE	(MOXA + 66)
#define MOXA_GET_OP_MODE	(MOXA + 67)

#define RS232_MODE		0
#define RS485_2WIRE_MODE	1
#define RS422_MODE		2
#define RS485_4WIRE_MODE	3
#define OP_MODE_MASK		3
// above add by Victor Yu. 01-05-2004

#define TTY_THRESHOLD_THROTTLE  128

#define HI_WATER		768

// added by James. 03-11-2004.
#define MOXA_SDS_GETICOUNTER  	(MOXA + 68)
#define MOXA_SDS_RSTICOUNTER  	(MOXA + 69)
// (above) added by James.

#define MOXA_ASPP_OQUEUE  	(MOXA + 70)
#define MOXA_ASPP_SETBAUD 	(MOXA + 71)
#define MOXA_ASPP_GETBAUD 	(MOXA + 72)
#define MOXA_ASPP_MON     	(MOXA + 73)
#define MOXA_ASPP_LSTATUS 	(MOXA + 74)
#define MOXA_ASPP_MON_EXT 	(MOXA + 75)
#define MOXA_SET_BAUD_METHOD	(MOXA + 76)


/* --------------------------------------------------- */

#define NPPI_NOTIFY_PARITY	0x01
#define NPPI_NOTIFY_FRAMING	0x02
#define NPPI_NOTIFY_HW_OVERRUN	0x04
#define NPPI_NOTIFY_SW_OVERRUN	0x08
#define NPPI_NOTIFY_BREAK	0x10

#define NPPI_NOTIFY_CTSHOLD         0x01	// Tx hold by CTS low
#define NPPI_NOTIFY_DSRHOLD         0x02	// Tx hold by DSR low
#define NPPI_NOTIFY_XOFFHOLD        0x08	// Tx hold by Xoff received
#define NPPI_NOTIFY_XOFFXENT        0x10	// Xoff Sent

//CheckIsMoxaMust return value
#define MOXA_OTHER_UART			0x00
#define MOXA_MUST_MU150_HWID		0x01
#define MOXA_MUST_MU860_HWID		0x02

// follow just for Moxa Must chip define.
//
// when LCR register (offset 0x03) write following value,
// the Must chip will enter enchance mode. And write value
// on EFR (offset 0x02) bit 6,7 to change bank.
#define MOXA_MUST_ENTER_ENCHANCE	0xBF

// when enhance mode enable, access on general bank register
#define MOXA_MUST_GDL_REGISTER		0x07
#define MOXA_MUST_GDL_MASK		0x7F
#define MOXA_MUST_GDL_HAS_BAD_DATA	0x80

#define MOXA_MUST_LSR_RERR		0x80	// error in receive FIFO
// enchance register bank select and enchance mode setting register
// when LCR register equal to 0xBF
#define MOXA_MUST_EFR_REGISTER		0x02
// enchance mode enable
#define MOXA_MUST_EFR_EFRB_ENABLE	0x10
// enchance reister bank set 0, 1, 2
#define MOXA_MUST_EFR_BANK0		0x00
#define MOXA_MUST_EFR_BANK1		0x40
#define MOXA_MUST_EFR_BANK2		0x80
#define MOXA_MUST_EFR_BANK3		0xC0
#define MOXA_MUST_EFR_BANK_MASK		0xC0

// set XON1 value register, when LCR=0xBF and change to bank0
#define MOXA_MUST_XON1_REGISTER		0x04

// set XON2 value register, when LCR=0xBF and change to bank0
#define MOXA_MUST_XON2_REGISTER		0x05

// set XOFF1 value register, when LCR=0xBF and change to bank0
#define MOXA_MUST_XOFF1_REGISTER	0x06

// set XOFF2 value register, when LCR=0xBF and change to bank0
#define MOXA_MUST_XOFF2_REGISTER	0x07

#define MOXA_MUST_RBRTL_REGISTER	0x04
#define MOXA_MUST_RBRTH_REGISTER	0x05
#define MOXA_MUST_RBRTI_REGISTER	0x06
#define MOXA_MUST_THRTL_REGISTER	0x07
#define MOXA_MUST_ENUM_REGISTER		0x04
#define MOXA_MUST_HWID_REGISTER		0x05
#define MOXA_MUST_ECR_REGISTER		0x06
#define MOXA_MUST_CSR_REGISTER		0x07

// good data mode enable
#define MOXA_MUST_FCR_GDA_MODE_ENABLE	0x20
// only good data put into RxFIFO
#define MOXA_MUST_FCR_GDA_ONLY_ENABLE	0x10

// enable CTS interrupt
#define MOXA_MUST_IER_ECTSI		0x80
// enable RTS interrupt
#define MOXA_MUST_IER_ERTSI		0x40
// enable Xon/Xoff interrupt
#define MOXA_MUST_IER_XINT		0x20
// enable GDA interrupt
#define MOXA_MUST_IER_EGDAI		0x10

#define MOXA_MUST_RECV_ISR		(UART_IER_RDI | MOXA_MUST_IER_EGDAI)

// GDA interrupt pending
#define MOXA_MUST_IIR_GDA		0x1C
#define MOXA_MUST_IIR_RDA		0x04
#define MOXA_MUST_IIR_RTO		0x0C
#define MOXA_MUST_IIR_LSR		0x06

// recieved Xon/Xoff or specical interrupt pending
#define MOXA_MUST_IIR_XSC		0x10

// RTS/CTS change state interrupt pending
#define MOXA_MUST_IIR_RTSCTS		0x20
#define MOXA_MUST_IIR_MASK		0x3E

#define MOXA_MUST_MCR_XON_FLAG		0x40
#define MOXA_MUST_MCR_XON_ANY		0x80
#define MOXA_MUST_MCR_TX_XON		0x08


// software flow control on chip mask value
#define MOXA_MUST_EFR_SF_MASK		0x0F
// send Xon1/Xoff1
#define MOXA_MUST_EFR_SF_TX1		0x08
// send Xon2/Xoff2
#define MOXA_MUST_EFR_SF_TX2		0x04
// send Xon1,Xon2/Xoff1,Xoff2
#define MOXA_MUST_EFR_SF_TX12		0x0C
// don't send Xon/Xoff
#define MOXA_MUST_EFR_SF_TX_NO		0x00
// Tx software flow control mask
#define MOXA_MUST_EFR_SF_TX_MASK	0x0C
// don't receive Xon/Xoff
#define MOXA_MUST_EFR_SF_RX_NO		0x00
// receive Xon1/Xoff1
#define MOXA_MUST_EFR_SF_RX1		0x02
// receive Xon2/Xoff2
#define MOXA_MUST_EFR_SF_RX2		0x01
// receive Xon1,Xon2/Xoff1,Xoff2
#define MOXA_MUST_EFR_SF_RX12		0x03
// Rx software flow control mask
#define MOXA_MUST_EFR_SF_RX_MASK	0x03

//#define MOXA_MUST_MIN_XOFFLIMIT               66
//#define MOXA_MUST_MIN_XONLIMIT                20
//#define ID1_RX_TRIG                   120


#define CHECK_MOXA_MUST_XOFFLIMIT(info) { 	\
	if ( (info)->IsMoxaMustChipFlag && 	\
	 (info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) {	\
		(info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT;	\
		(info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT;	\
	}	\
}

#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr |= MOXA_MUST_EFR_EFRB_ENABLE;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK0;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK0;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK0;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK0;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

//#define MOXA_MUST_RBRL_VALUE  4
#define SET_MOXA_MUST_FIFO_VALUE(info) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((info)->base+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR);	\
	__efr = inb((info)->base+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK1;	\
	outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER);	\
	outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER);	\
	outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER);	\
	outb(__oldlcr, (info)->base+UART_LCR);	\
}


#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK2;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;	\
	__efr |= MOXA_MUST_EFR_BANK2;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	*pId = inb((baseio)+MOXA_MUST_HWID_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_MASK;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_MASK;	\
	__efr |= MOXA_MUST_EFR_SF_TX1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK;	\
	__efr |= MOXA_MUST_EFR_SF_TX1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_MASK;	\
	__efr |= MOXA_MUST_EFR_SF_RX1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK;	\
	__efr |= MOXA_MUST_EFR_SF_RX1;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK;	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) {	\
	u8	__oldlcr, __efr;	\
	__oldlcr = inb((baseio)+UART_LCR);	\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_SF_MASK;	\
	__efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1);	\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);	\
}

#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) {	\
	u8	__oldmcr;	\
	__oldmcr = inb((baseio)+UART_MCR);	\
	__oldmcr |= MOXA_MUST_MCR_XON_ANY;	\
	outb(__oldmcr, (baseio)+UART_MCR);	\
}

#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) {	\
	u8	__oldmcr;	\
	__oldmcr = inb((baseio)+UART_MCR);	\
	__oldmcr &= ~MOXA_MUST_MCR_XON_ANY;	\
	outb(__oldmcr, (baseio)+UART_MCR);	\
}

#define READ_MOXA_MUST_GDL(baseio)	inb((baseio)+MOXA_MUST_GDL_REGISTER)

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef _MXSER_H
	2	#define _MXSER_H
	3
	4	/*
	5	* Semi-public control interfaces
	6	*/
	7
	8	/*
	9	* MOXA ioctls
	10	*/
	11
	12	#define MOXA 0x400
	13	#define MOXA_GETDATACOUNT (MOXA + 23)
	14	#define MOXA_GET_CONF (MOXA + 35)
	15	#define MOXA_DIAGNOSE (MOXA + 50)
	16	#define MOXA_CHKPORTENABLE (MOXA + 60)
	17	#define MOXA_HighSpeedOn (MOXA + 61)
	18	#define MOXA_GET_MAJOR (MOXA + 63)
	19	#define MOXA_GET_CUMAJOR (MOXA + 64)
	20	#define MOXA_GETMSTATUS (MOXA + 65)
	21	#define MOXA_SET_OP_MODE (MOXA + 66)
	22	#define MOXA_GET_OP_MODE (MOXA + 67)
	23
	24	#define RS232_MODE 0
	25	#define RS485_2WIRE_MODE 1
	26	#define RS422_MODE 2
	27	#define RS485_4WIRE_MODE 3
	28	#define OP_MODE_MASK 3
	29	// above add by Victor Yu. 01-05-2004
	30
	31	#define TTY_THRESHOLD_THROTTLE 128
	32
7f748bbd	33	#define HI_WATER 768
1da177e4 LT	34
	35	// added by James. 03-11-2004.
	36	#define MOXA_SDS_GETICOUNTER (MOXA + 68)
	37	#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
	38	// (above) added by James.
	39
	40	#define MOXA_ASPP_OQUEUE (MOXA + 70)
	41	#define MOXA_ASPP_SETBAUD (MOXA + 71)
	42	#define MOXA_ASPP_GETBAUD (MOXA + 72)
	43	#define MOXA_ASPP_MON (MOXA + 73)
	44	#define MOXA_ASPP_LSTATUS (MOXA + 74)
	45	#define MOXA_ASPP_MON_EXT (MOXA + 75)
	46	#define MOXA_SET_BAUD_METHOD (MOXA + 76)
	47
	48
	49	/* --------------------------------------------------- */
	50
	51	#define NPPI_NOTIFY_PARITY 0x01
	52	#define NPPI_NOTIFY_FRAMING 0x02
	53	#define NPPI_NOTIFY_HW_OVERRUN 0x04
	54	#define NPPI_NOTIFY_SW_OVERRUN 0x08
	55	#define NPPI_NOTIFY_BREAK 0x10
	56
	57	#define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low
	58	#define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low
	59	#define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received
	60	#define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent
	61
	62	//CheckIsMoxaMust return value
	63	#define MOXA_OTHER_UART 0x00
	64	#define MOXA_MUST_MU150_HWID 0x01
	65	#define MOXA_MUST_MU860_HWID 0x02
	66
	67	// follow just for Moxa Must chip define.
	68	//
	69	// when LCR register (offset 0x03) write following value,
	70	// the Must chip will enter enchance mode. And write value
	71	// on EFR (offset 0x02) bit 6,7 to change bank.
	72	#define MOXA_MUST_ENTER_ENCHANCE 0xBF
	73
	74	// when enhance mode enable, access on general bank register
	75	#define MOXA_MUST_GDL_REGISTER 0x07
	76	#define MOXA_MUST_GDL_MASK 0x7F
	77	#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
	78
	79	#define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO
	80	// enchance register bank select and enchance mode setting register
	81	// when LCR register equal to 0xBF
	82	#define MOXA_MUST_EFR_REGISTER 0x02
	83	// enchance mode enable
	84	#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
	85	// enchance reister bank set 0, 1, 2
	86	#define MOXA_MUST_EFR_BANK0 0x00
	87	#define MOXA_MUST_EFR_BANK1 0x40
	88	#define MOXA_MUST_EFR_BANK2 0x80
	89	#define MOXA_MUST_EFR_BANK3 0xC0
	90	#define MOXA_MUST_EFR_BANK_MASK 0xC0
	91
	92	// set XON1 value register, when LCR=0xBF and change to bank0
	93	#define MOXA_MUST_XON1_REGISTER 0x04
	94
	95	// set XON2 value register, when LCR=0xBF and change to bank0
	96	#define MOXA_MUST_XON2_REGISTER 0x05
	97
98	// set XOFF1 value register, when LCR=0xBF and change to bank0
99	#define MOXA_MUST_XOFF1_REGISTER 0x06
100
101	// set XOFF2 value register, when LCR=0xBF and change to bank0
102	#define MOXA_MUST_XOFF2_REGISTER 0x07
103
104	#define MOXA_MUST_RBRTL_REGISTER 0x04
105	#define MOXA_MUST_RBRTH_REGISTER 0x05
106	#define MOXA_MUST_RBRTI_REGISTER 0x06
107	#define MOXA_MUST_THRTL_REGISTER 0x07
108	#define MOXA_MUST_ENUM_REGISTER 0x04
109	#define MOXA_MUST_HWID_REGISTER 0x05
110	#define MOXA_MUST_ECR_REGISTER 0x06
111	#define MOXA_MUST_CSR_REGISTER 0x07
112
113	// good data mode enable
114	#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
115	// only good data put into RxFIFO
116	#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
117
118	// enable CTS interrupt
119	#define MOXA_MUST_IER_ECTSI 0x80
7f927fcc	120	// enable RTS interrupt
1da177e4 LT	121	#define MOXA_MUST_IER_ERTSI 0x40
	122	// enable Xon/Xoff interrupt
	123	#define MOXA_MUST_IER_XINT 0x20
	124	// enable GDA interrupt
	125	#define MOXA_MUST_IER_EGDAI 0x10
	126
	127	#define MOXA_MUST_RECV_ISR (UART_IER_RDI \| MOXA_MUST_IER_EGDAI)
	128
	129	// GDA interrupt pending
	130	#define MOXA_MUST_IIR_GDA 0x1C
	131	#define MOXA_MUST_IIR_RDA 0x04
	132	#define MOXA_MUST_IIR_RTO 0x0C
	133	#define MOXA_MUST_IIR_LSR 0x06
	134
	135	// recieved Xon/Xoff or specical interrupt pending
	136	#define MOXA_MUST_IIR_XSC 0x10
	137
	138	// RTS/CTS change state interrupt pending
	139	#define MOXA_MUST_IIR_RTSCTS 0x20
	140	#define MOXA_MUST_IIR_MASK 0x3E
	141
	142	#define MOXA_MUST_MCR_XON_FLAG 0x40
	143	#define MOXA_MUST_MCR_XON_ANY 0x80
	144	#define MOXA_MUST_MCR_TX_XON 0x08
	145
	146
	147	// software flow control on chip mask value
	148	#define MOXA_MUST_EFR_SF_MASK 0x0F
	149	// send Xon1/Xoff1
	150	#define MOXA_MUST_EFR_SF_TX1 0x08
	151	// send Xon2/Xoff2
	152	#define MOXA_MUST_EFR_SF_TX2 0x04
	153	// send Xon1,Xon2/Xoff1,Xoff2
	154	#define MOXA_MUST_EFR_SF_TX12 0x0C
	155	// don't send Xon/Xoff
	156	#define MOXA_MUST_EFR_SF_TX_NO 0x00
	157	// Tx software flow control mask
	158	#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
	159	// don't receive Xon/Xoff
	160	#define MOXA_MUST_EFR_SF_RX_NO 0x00
	161	// receive Xon1/Xoff1
	162	#define MOXA_MUST_EFR_SF_RX1 0x02
	163	// receive Xon2/Xoff2
	164	#define MOXA_MUST_EFR_SF_RX2 0x01
	165	// receive Xon1,Xon2/Xoff1,Xoff2
	166	#define MOXA_MUST_EFR_SF_RX12 0x03
	167	// Rx software flow control mask
	168	#define MOXA_MUST_EFR_SF_RX_MASK 0x03
	169
	170	//#define MOXA_MUST_MIN_XOFFLIMIT 66
	171	//#define MOXA_MUST_MIN_XONLIMIT 20
	172	//#define ID1_RX_TRIG 120
	173
	174
	175	#define CHECK_MOXA_MUST_XOFFLIMIT(info) { \
	176	if ( (info)->IsMoxaMustChipFlag && \
	177	(info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \
	178	(info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \
	179	(info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \
	180	} \
	181	}
	182
	183	#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
	184	u8 __oldlcr, __efr; \
185	__oldlcr = inb((baseio)+UART_LCR); \
186	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
187	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
188	__efr \|= MOXA_MUST_EFR_EFRB_ENABLE; \
189	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
190	outb(__oldlcr, (baseio)+UART_LCR); \
191	}
192
193	#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
194	u8 __oldlcr, __efr; \
195	__oldlcr = inb((baseio)+UART_LCR); \
196	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
197	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
198	__efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
199	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
200	outb(__oldlcr, (baseio)+UART_LCR); \
201	}
202
203	#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \
204	u8 __oldlcr, __efr; \
205	__oldlcr = inb((baseio)+UART_LCR); \
206	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
207	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
208	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
209	__efr \|= MOXA_MUST_EFR_BANK0; \
210	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
211	outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
212	outb(__oldlcr, (baseio)+UART_LCR); \
213	}
214
215	#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \
216	u8 __oldlcr, __efr; \
217	__oldlcr = inb((baseio)+UART_LCR); \
218	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
219	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
220	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
221	__efr \|= MOXA_MUST_EFR_BANK0; \
222	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
223	outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \
224	outb(__oldlcr, (baseio)+UART_LCR); \
225	}
226
227	#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \
228	u8 __oldlcr, __efr; \
229	__oldlcr = inb((baseio)+UART_LCR); \
230	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
231	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
232	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
233	__efr \|= MOXA_MUST_EFR_BANK0; \
234	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
235	outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
236	outb(__oldlcr, (baseio)+UART_LCR); \
237	}
238
239	#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \
240	u8 __oldlcr, __efr; \
241	__oldlcr = inb((baseio)+UART_LCR); \
242	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
243	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
244	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
245	__efr \|= MOXA_MUST_EFR_BANK0; \
246	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
247	outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \
248	outb(__oldlcr, (baseio)+UART_LCR); \
249	}
250
251	#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \
252	u8 __oldlcr, __efr; \
253	__oldlcr = inb((baseio)+UART_LCR); \
254	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
255	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
256	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
257	__efr \|= MOXA_MUST_EFR_BANK1; \
258	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
259	outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \
260	outb(__oldlcr, (baseio)+UART_LCR); \
261	}
262
263	#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \
264	u8 __oldlcr, __efr; \
265	__oldlcr = inb((baseio)+UART_LCR); \
266	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
267	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
268	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
269	__efr \|= MOXA_MUST_EFR_BANK1; \
270	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
271	outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \
272	outb(__oldlcr, (baseio)+UART_LCR); \
273	}
274
275	#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \
276	u8 __oldlcr, __efr; \
277	__oldlcr = inb((baseio)+UART_LCR); \
278	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
279	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
280	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
281	__efr \|= MOXA_MUST_EFR_BANK1; \
282	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
283	outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \
284	outb(__oldlcr, (baseio)+UART_LCR); \
285	}
286
287	#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \
288	u8 __oldlcr, __efr; \
289	__oldlcr = inb((baseio)+UART_LCR); \
290	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
291	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
292	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
293	__efr \|= MOXA_MUST_EFR_BANK1; \
294	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
295	outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \
296	outb(__oldlcr, (baseio)+UART_LCR); \
297	}
298
299	//#define MOXA_MUST_RBRL_VALUE 4
300	#define SET_MOXA_MUST_FIFO_VALUE(info) { \
301	u8 __oldlcr, __efr; \
302	__oldlcr = inb((info)->base+UART_LCR); \
303	outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR); \
304	__efr = inb((info)->base+MOXA_MUST_EFR_REGISTER); \
305	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
306	__efr \|= MOXA_MUST_EFR_BANK1; \
307	outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER); \
308	outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER); \
309	outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER); \
310	outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER); \
311	outb(__oldlcr, (info)->base+UART_LCR); \
312	}
313
314
315
316	#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \
317	u8 __oldlcr, __efr; \
318	__oldlcr = inb((baseio)+UART_LCR); \
319	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
320	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
321	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
322	__efr \|= MOXA_MUST_EFR_BANK2; \
323	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
324	outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
325	outb(__oldlcr, (baseio)+UART_LCR); \
326	}
327
328	#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \
329	u8 __oldlcr, __efr; \
330	__oldlcr = inb((baseio)+UART_LCR); \
331	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
332	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
333	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
334	__efr \|= MOXA_MUST_EFR_BANK2; \
335	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
336	*pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
337	outb(__oldlcr, (baseio)+UART_LCR); \
338	}
339
340	#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \
341	u8 __oldlcr, __efr; \
342	__oldlcr = inb((baseio)+UART_LCR); \
343	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
344	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
345	__efr &= ~MOXA_MUST_EFR_SF_MASK; \
346	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
347	outb(__oldlcr, (baseio)+UART_LCR); \
348	}
349
350	#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
351	u8 __oldlcr, __efr; \
352	__oldlcr = inb((baseio)+UART_LCR); \
353	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
354	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
355	__efr &= ~MOXA_MUST_EFR_SF_MASK; \
356	__efr \|= MOXA_MUST_EFR_SF_TX1; \
357	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
358	outb(__oldlcr, (baseio)+UART_LCR); \
359	}
360
361	#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
362	u8 __oldlcr, __efr; \
363	__oldlcr = inb((baseio)+UART_LCR); \
364	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
365	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
366	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
367	__efr \|= MOXA_MUST_EFR_SF_TX1; \
368	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
369	outb(__oldlcr, (baseio)+UART_LCR); \
370	}
371
372	#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
373	u8 __oldlcr, __efr; \
374	__oldlcr = inb((baseio)+UART_LCR); \
375	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
376	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
377	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
378	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
379	outb(__oldlcr, (baseio)+UART_LCR); \
380	}
381
382	#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
383	u8 __oldlcr, __efr; \
384	__oldlcr = inb((baseio)+UART_LCR); \
385	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
386	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
387	__efr &= ~MOXA_MUST_EFR_SF_MASK; \
388	__efr \|= MOXA_MUST_EFR_SF_RX1; \
389	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
390	outb(__oldlcr, (baseio)+UART_LCR); \
391	}
392
393	#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
394	u8 __oldlcr, __efr; \
395	__oldlcr = inb((baseio)+UART_LCR); \
396	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
397	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
398	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
399	__efr \|= MOXA_MUST_EFR_SF_RX1; \
400	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
401	outb(__oldlcr, (baseio)+UART_LCR); \
402	}
403
404	#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
405	u8 __oldlcr, __efr; \
406	__oldlcr = inb((baseio)+UART_LCR); \
407	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
408	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
409	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
410	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
411	outb(__oldlcr, (baseio)+UART_LCR); \
412	}
413
414	#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
415	u8 __oldlcr, __efr; \
416	__oldlcr = inb((baseio)+UART_LCR); \
417	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
418	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
419	__efr &= ~MOXA_MUST_EFR_SF_MASK; \
420	__efr \|= (MOXA_MUST_EFR_SF_RX1\|MOXA_MUST_EFR_SF_TX1); \
421	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
422	outb(__oldlcr, (baseio)+UART_LCR); \
423	}
424
425	#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
426	u8 __oldmcr; \
427	__oldmcr = inb((baseio)+UART_MCR); \
428	__oldmcr \|= MOXA_MUST_MCR_XON_ANY; \
429	outb(__oldmcr, (baseio)+UART_MCR); \
430	}
431
432	#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
433	u8 __oldmcr; \
434	__oldmcr = inb((baseio)+UART_MCR); \
435	__oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \
436	outb(__oldmcr, (baseio)+UART_MCR); \
437	}
438
439	#define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER)
440
1da177e4	441	#endif