[deliverable/linux.git] / drivers / char / mxser.h

#ifndef _MXSER_H
#define _MXSER_H

/*
 *	Semi-public control interfaces
 */

/*
 *	MOXA ioctls
 */

#define MOXA			0x400
#define MOXA_GETDATACOUNT	(MOXA + 23)
#define MOXA_DIAGNOSE		(MOXA + 50)
#define MOXA_CHKPORTENABLE	(MOXA + 60)
#define MOXA_HighSpeedOn	(MOXA + 61)
#define MOXA_GET_MAJOR		(MOXA + 63)
#define MOXA_GETMSTATUS		(MOXA + 65)
#define MOXA_SET_OP_MODE	(MOXA + 66)
#define MOXA_GET_OP_MODE	(MOXA + 67)

#define RS232_MODE		0
#define RS485_2WIRE_MODE	1
#define RS422_MODE		2
#define RS485_4WIRE_MODE	3
#define OP_MODE_MASK		3

#define MOXA_SDS_RSTICOUNTER	(MOXA + 69)
#define MOXA_ASPP_OQUEUE  	(MOXA + 70)
#define MOXA_ASPP_MON     	(MOXA + 73)
#define MOXA_ASPP_LSTATUS 	(MOXA + 74)
#define MOXA_ASPP_MON_EXT 	(MOXA + 75)
#define MOXA_SET_BAUD_METHOD	(MOXA + 76)

/* --------------------------------------------------- */

#define NPPI_NOTIFY_PARITY	0x01
#define NPPI_NOTIFY_FRAMING	0x02
#define NPPI_NOTIFY_HW_OVERRUN	0x04
#define NPPI_NOTIFY_SW_OVERRUN	0x08
#define NPPI_NOTIFY_BREAK	0x10

#define NPPI_NOTIFY_CTSHOLD         0x01	/* Tx hold by CTS low */
#define NPPI_NOTIFY_DSRHOLD         0x02	/* Tx hold by DSR low */
#define NPPI_NOTIFY_XOFFHOLD        0x08	/* Tx hold by Xoff received */
#define NPPI_NOTIFY_XOFFXENT        0x10	/* Xoff Sent */

/* follow just for Moxa Must chip define. */
/* */
/* when LCR register (offset 0x03) write following value, */
/* the Must chip will enter enchance mode. And write value */
/* on EFR (offset 0x02) bit 6,7 to change bank. */
#define MOXA_MUST_ENTER_ENCHANCE	0xBF

/* when enhance mode enable, access on general bank register */
#define MOXA_MUST_GDL_REGISTER		0x07
#define MOXA_MUST_GDL_MASK		0x7F
#define MOXA_MUST_GDL_HAS_BAD_DATA	0x80

#define MOXA_MUST_LSR_RERR		0x80	/* error in receive FIFO */
/* enchance register bank select and enchance mode setting register */
/* when LCR register equal to 0xBF */
#define MOXA_MUST_EFR_REGISTER		0x02
/* enchance mode enable */
#define MOXA_MUST_EFR_EFRB_ENABLE	0x10
/* enchance reister bank set 0, 1, 2 */
#define MOXA_MUST_EFR_BANK0		0x00
#define MOXA_MUST_EFR_BANK1		0x40
#define MOXA_MUST_EFR_BANK2		0x80
#define MOXA_MUST_EFR_BANK3		0xC0
#define MOXA_MUST_EFR_BANK_MASK		0xC0

/* set XON1 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XON1_REGISTER		0x04

/* set XON2 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XON2_REGISTER		0x05

/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XOFF1_REGISTER	0x06

/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
#define MOXA_MUST_XOFF2_REGISTER	0x07

#define MOXA_MUST_RBRTL_REGISTER	0x04
#define MOXA_MUST_RBRTH_REGISTER	0x05
#define MOXA_MUST_RBRTI_REGISTER	0x06
#define MOXA_MUST_THRTL_REGISTER	0x07
#define MOXA_MUST_ENUM_REGISTER		0x04
#define MOXA_MUST_HWID_REGISTER		0x05
#define MOXA_MUST_ECR_REGISTER		0x06
#define MOXA_MUST_CSR_REGISTER		0x07

/* good data mode enable */
#define MOXA_MUST_FCR_GDA_MODE_ENABLE	0x20
/* only good data put into RxFIFO */
#define MOXA_MUST_FCR_GDA_ONLY_ENABLE	0x10

/* enable CTS interrupt */
#define MOXA_MUST_IER_ECTSI		0x80
/* enable RTS interrupt */
#define MOXA_MUST_IER_ERTSI		0x40
/* enable Xon/Xoff interrupt */
#define MOXA_MUST_IER_XINT		0x20
/* enable GDA interrupt */
#define MOXA_MUST_IER_EGDAI		0x10

#define MOXA_MUST_RECV_ISR		(UART_IER_RDI | MOXA_MUST_IER_EGDAI)

/* GDA interrupt pending */
#define MOXA_MUST_IIR_GDA		0x1C
#define MOXA_MUST_IIR_RDA		0x04
#define MOXA_MUST_IIR_RTO		0x0C
#define MOXA_MUST_IIR_LSR		0x06

/* recieved Xon/Xoff or specical interrupt pending */
#define MOXA_MUST_IIR_XSC		0x10

/* RTS/CTS change state interrupt pending */
#define MOXA_MUST_IIR_RTSCTS		0x20
#define MOXA_MUST_IIR_MASK		0x3E

#define MOXA_MUST_MCR_XON_FLAG		0x40
#define MOXA_MUST_MCR_XON_ANY		0x80
#define MOXA_MUST_MCR_TX_XON		0x08

/* software flow control on chip mask value */
#define MOXA_MUST_EFR_SF_MASK		0x0F
/* send Xon1/Xoff1 */
#define MOXA_MUST_EFR_SF_TX1		0x08
/* send Xon2/Xoff2 */
#define MOXA_MUST_EFR_SF_TX2		0x04
/* send Xon1,Xon2/Xoff1,Xoff2 */
#define MOXA_MUST_EFR_SF_TX12		0x0C
/* don't send Xon/Xoff */
#define MOXA_MUST_EFR_SF_TX_NO		0x00
/* Tx software flow control mask */
#define MOXA_MUST_EFR_SF_TX_MASK	0x0C
/* don't receive Xon/Xoff */
#define MOXA_MUST_EFR_SF_RX_NO		0x00
/* receive Xon1/Xoff1 */
#define MOXA_MUST_EFR_SF_RX1		0x02
/* receive Xon2/Xoff2 */
#define MOXA_MUST_EFR_SF_RX2		0x01
/* receive Xon1,Xon2/Xoff1,Xoff2 */
#define MOXA_MUST_EFR_SF_RX12		0x03
/* Rx software flow control mask */
#define MOXA_MUST_EFR_SF_RX_MASK	0x03

#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { 		\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr |= MOXA_MUST_EFR_EFRB_ENABLE;			\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do {		\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;			\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do {		\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;			\
	__efr |= MOXA_MUST_EFR_BANK0;				\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do {		\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;			\
	__efr |= MOXA_MUST_EFR_BANK0;				\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define SET_MOXA_MUST_FIFO_VALUE(info) do {			\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((info)->ioaddr+UART_LCR);		\
	outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
	__efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER);	\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;			\
	__efr |= MOXA_MUST_EFR_BANK1;				\
	outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER);	\
	outb((u8)((info)->rx_high_water), (info)->ioaddr+	\
			MOXA_MUST_RBRTH_REGISTER);		\
	outb((u8)((info)->rx_trigger), (info)->ioaddr+		\
			MOXA_MUST_RBRTI_REGISTER);		\
	outb((u8)((info)->rx_low_water), (info)->ioaddr+	\
			MOXA_MUST_RBRTL_REGISTER);		\
	outb(__oldlcr, (info)->ioaddr+UART_LCR);		\
} while (0)

#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do {		\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;			\
	__efr |= MOXA_MUST_EFR_BANK2;				\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER);	\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do {		\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_BANK_MASK;			\
	__efr |= MOXA_MUST_EFR_BANK2;				\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	*pId = inb((baseio)+MOXA_MUST_HWID_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do {	\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_SF_MASK;			\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do {	\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK;			\
	__efr |= MOXA_MUST_EFR_SF_TX1;				\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do {	\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK;			\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do {	\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK;			\
	__efr |= MOXA_MUST_EFR_SF_RX1;				\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do {	\
	u8	__oldlcr, __efr;				\
	__oldlcr = inb((baseio)+UART_LCR);			\
	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR);	\
	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER);		\
	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK;			\
	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER);		\
	outb(__oldlcr, (baseio)+UART_LCR);			\
} while (0)

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef _MXSER_H
	2	#define _MXSER_H
	3
	4	/*
	5	* Semi-public control interfaces
	6	*/
1c45607a	7
1da177e4 LT	8	/*
	9	* MOXA ioctls
	10	*/
	11
	12	#define MOXA 0x400
	13	#define MOXA_GETDATACOUNT (MOXA + 23)
1da177e4 LT	14	#define MOXA_DIAGNOSE (MOXA + 50)
	15	#define MOXA_CHKPORTENABLE (MOXA + 60)
	16	#define MOXA_HighSpeedOn (MOXA + 61)
	17	#define MOXA_GET_MAJOR (MOXA + 63)
1da177e4 LT	18	#define MOXA_GETMSTATUS (MOXA + 65)
	19	#define MOXA_SET_OP_MODE (MOXA + 66)
	20	#define MOXA_GET_OP_MODE (MOXA + 67)
	21
	22	#define RS232_MODE 0
	23	#define RS485_2WIRE_MODE 1
	24	#define RS422_MODE 2
	25	#define RS485_4WIRE_MODE 3
	26	#define OP_MODE_MASK 3
1da177e4	27
1c45607a	28	#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
1da177e4	29	#define MOXA_ASPP_OQUEUE (MOXA + 70)
1da177e4 LT	30	#define MOXA_ASPP_MON (MOXA + 73)
	31	#define MOXA_ASPP_LSTATUS (MOXA + 74)
	32	#define MOXA_ASPP_MON_EXT (MOXA + 75)
	33	#define MOXA_SET_BAUD_METHOD (MOXA + 76)
	34
1da177e4 LT	35	/* --------------------------------------------------- */
	36
	37	#define NPPI_NOTIFY_PARITY 0x01
	38	#define NPPI_NOTIFY_FRAMING 0x02
	39	#define NPPI_NOTIFY_HW_OVERRUN 0x04
	40	#define NPPI_NOTIFY_SW_OVERRUN 0x08
	41	#define NPPI_NOTIFY_BREAK 0x10
	42
1c45607a JS	43	#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
	44	#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
	45	#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
	46	#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
	47
	48	/* follow just for Moxa Must chip define. */
	49	/* */
	50	/* when LCR register (offset 0x03) write following value, */
	51	/* the Must chip will enter enchance mode. And write value */
	52	/* on EFR (offset 0x02) bit 6,7 to change bank. */
1da177e4 LT	53	#define MOXA_MUST_ENTER_ENCHANCE 0xBF
1da177e4 LT	54
1c45607a	55	/* when enhance mode enable, access on general bank register */
1da177e4 LT	56	#define MOXA_MUST_GDL_REGISTER 0x07
	57	#define MOXA_MUST_GDL_MASK 0x7F
	58	#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
	59
1c45607a JS	60	#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
	61	/* enchance register bank select and enchance mode setting register */
	62	/* when LCR register equal to 0xBF */
1da177e4	63	#define MOXA_MUST_EFR_REGISTER 0x02
1c45607a	64	/* enchance mode enable */
1da177e4	65	#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
1c45607a	66	/* enchance reister bank set 0, 1, 2 */
1da177e4 LT	67	#define MOXA_MUST_EFR_BANK0 0x00
	68	#define MOXA_MUST_EFR_BANK1 0x40
	69	#define MOXA_MUST_EFR_BANK2 0x80
	70	#define MOXA_MUST_EFR_BANK3 0xC0
	71	#define MOXA_MUST_EFR_BANK_MASK 0xC0
	72
1c45607a	73	/* set XON1 value register, when LCR=0xBF and change to bank0 */
1da177e4 LT	74	#define MOXA_MUST_XON1_REGISTER 0x04
1da177e4 LT	75
1c45607a	76	/* set XON2 value register, when LCR=0xBF and change to bank0 */
1da177e4 LT	77	#define MOXA_MUST_XON2_REGISTER 0x05
1da177e4 LT	78
1c45607a	79	/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
1da177e4 LT	80	#define MOXA_MUST_XOFF1_REGISTER 0x06
1da177e4 LT	81
1c45607a	82	/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
1da177e4 LT	83	#define MOXA_MUST_XOFF2_REGISTER 0x07
	84
	85	#define MOXA_MUST_RBRTL_REGISTER 0x04
	86	#define MOXA_MUST_RBRTH_REGISTER 0x05
	87	#define MOXA_MUST_RBRTI_REGISTER 0x06
	88	#define MOXA_MUST_THRTL_REGISTER 0x07
	89	#define MOXA_MUST_ENUM_REGISTER 0x04
	90	#define MOXA_MUST_HWID_REGISTER 0x05
	91	#define MOXA_MUST_ECR_REGISTER 0x06
	92	#define MOXA_MUST_CSR_REGISTER 0x07
	93
1c45607a	94	/* good data mode enable */
1da177e4	95	#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
1c45607a	96	/* only good data put into RxFIFO */
1da177e4 LT	97	#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
1da177e4 LT	98
1c45607a	99	/* enable CTS interrupt */
1da177e4	100	#define MOXA_MUST_IER_ECTSI 0x80
1c45607a	101	/* enable RTS interrupt */
1da177e4	102	#define MOXA_MUST_IER_ERTSI 0x40
1c45607a	103	/* enable Xon/Xoff interrupt */
1da177e4	104	#define MOXA_MUST_IER_XINT 0x20
1c45607a	105	/* enable GDA interrupt */
1da177e4 LT	106	#define MOXA_MUST_IER_EGDAI 0x10
	107
	108	#define MOXA_MUST_RECV_ISR (UART_IER_RDI \| MOXA_MUST_IER_EGDAI)
	109
1c45607a	110	/* GDA interrupt pending */
1da177e4 LT	111	#define MOXA_MUST_IIR_GDA 0x1C
	112	#define MOXA_MUST_IIR_RDA 0x04
	113	#define MOXA_MUST_IIR_RTO 0x0C
	114	#define MOXA_MUST_IIR_LSR 0x06
	115
1c45607a	116	/* recieved Xon/Xoff or specical interrupt pending */
1da177e4 LT	117	#define MOXA_MUST_IIR_XSC 0x10
1da177e4 LT	118
1c45607a	119	/* RTS/CTS change state interrupt pending */
1da177e4 LT	120	#define MOXA_MUST_IIR_RTSCTS 0x20
	121	#define MOXA_MUST_IIR_MASK 0x3E
	122
	123	#define MOXA_MUST_MCR_XON_FLAG 0x40
	124	#define MOXA_MUST_MCR_XON_ANY 0x80
	125	#define MOXA_MUST_MCR_TX_XON 0x08
	126
1c45607a	127	/* software flow control on chip mask value */
1da177e4	128	#define MOXA_MUST_EFR_SF_MASK 0x0F
1c45607a	129	/* send Xon1/Xoff1 */
1da177e4	130	#define MOXA_MUST_EFR_SF_TX1 0x08
1c45607a	131	/* send Xon2/Xoff2 */
1da177e4	132	#define MOXA_MUST_EFR_SF_TX2 0x04
1c45607a	133	/* send Xon1,Xon2/Xoff1,Xoff2 */
1da177e4	134	#define MOXA_MUST_EFR_SF_TX12 0x0C
1c45607a	135	/* don't send Xon/Xoff */
1da177e4	136	#define MOXA_MUST_EFR_SF_TX_NO 0x00
1c45607a	137	/* Tx software flow control mask */
1da177e4	138	#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
1c45607a	139	/* don't receive Xon/Xoff */
1da177e4	140	#define MOXA_MUST_EFR_SF_RX_NO 0x00
1c45607a	141	/* receive Xon1/Xoff1 */
1da177e4	142	#define MOXA_MUST_EFR_SF_RX1 0x02
1c45607a	143	/* receive Xon2/Xoff2 */
1da177e4	144	#define MOXA_MUST_EFR_SF_RX2 0x01
1c45607a	145	/* receive Xon1,Xon2/Xoff1,Xoff2 */
1da177e4	146	#define MOXA_MUST_EFR_SF_RX12 0x03
1c45607a	147	/* Rx software flow control mask */
1da177e4 LT	148	#define MOXA_MUST_EFR_SF_RX_MASK 0x03
1da177e4 LT	149
1c45607a JS	150	#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
	151	u8 __oldlcr, __efr; \
	152	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	153	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	154	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	155	__efr \|= MOXA_MUST_EFR_EFRB_ENABLE; \
	156	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	157	outb(__oldlcr, (baseio)+UART_LCR); \
	158	} while (0)
	159
	160	#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
	161	u8 __oldlcr, __efr; \
	162	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	163	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	164	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	165	__efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
	166	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	167	outb(__oldlcr, (baseio)+UART_LCR); \
	168	} while (0)
	169
	170	#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
	171	u8 __oldlcr, __efr; \
	172	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	173	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	174	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	175	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
	176	__efr \|= MOXA_MUST_EFR_BANK0; \
	177	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
1da177e4	178	outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
1c45607a JS	179	outb(__oldlcr, (baseio)+UART_LCR); \
1c45607a JS	180	} while (0)
1da177e4	181
1c45607a JS	182	#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
	183	u8 __oldlcr, __efr; \
	184	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	185	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	186	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	187	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
	188	__efr \|= MOXA_MUST_EFR_BANK0; \
	189	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
1da177e4	190	outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
1c45607a JS	191	outb(__oldlcr, (baseio)+UART_LCR); \
	192	} while (0)
	193
	194	#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
	195	u8 __oldlcr, __efr; \
	196	__oldlcr = inb((info)->ioaddr+UART_LCR); \
	197	outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
	198	__efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
	199	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
	200	__efr \|= MOXA_MUST_EFR_BANK1; \
	201	outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
	202	outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
	203	MOXA_MUST_RBRTH_REGISTER); \
	204	outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
	205	MOXA_MUST_RBRTI_REGISTER); \
	206	outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
	207	MOXA_MUST_RBRTL_REGISTER); \
	208	outb(__oldlcr, (info)->ioaddr+UART_LCR); \
	209	} while (0)
	210
	211	#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
	212	u8 __oldlcr, __efr; \
	213	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	214	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	215	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	216	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
	217	__efr \|= MOXA_MUST_EFR_BANK2; \
	218	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
1da177e4	219	outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
1c45607a JS	220	outb(__oldlcr, (baseio)+UART_LCR); \
1c45607a JS	221	} while (0)
1da177e4	222
1c45607a JS	223	#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
	224	u8 __oldlcr, __efr; \
	225	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	226	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	227	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	228	__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
	229	__efr \|= MOXA_MUST_EFR_BANK2; \
	230	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	231	*pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
	232	outb(__oldlcr, (baseio)+UART_LCR); \
	233	} while (0)
	234
	235	#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
	236	u8 __oldlcr, __efr; \
	237	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	238	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	239	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	240	__efr &= ~MOXA_MUST_EFR_SF_MASK; \
	241	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	242	outb(__oldlcr, (baseio)+UART_LCR); \
	243	} while (0)
	244
	245	#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
	246	u8 __oldlcr, __efr; \
	247	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	248	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	249	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	250	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
	251	__efr \|= MOXA_MUST_EFR_SF_TX1; \
	252	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	253	outb(__oldlcr, (baseio)+UART_LCR); \
	254	} while (0)
	255
	256	#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
	257	u8 __oldlcr, __efr; \
	258	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	259	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	260	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	261	__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
	262	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	263	outb(__oldlcr, (baseio)+UART_LCR); \
	264	} while (0)
	265
	266	#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
	267	u8 __oldlcr, __efr; \
	268	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	269	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	270	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	271	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
	272	__efr \|= MOXA_MUST_EFR_SF_RX1; \
	273	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	274	outb(__oldlcr, (baseio)+UART_LCR); \
	275	} while (0)
	276
	277	#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
	278	u8 __oldlcr, __efr; \
	279	__oldlcr = inb((baseio)+UART_LCR); \
1da177e4	280	outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
1c45607a JS	281	__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
	282	__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
	283	outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
	284	outb(__oldlcr, (baseio)+UART_LCR); \
	285	} while (0)
1da177e4	286
1da177e4	287	#endif