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Merge ssh://master.kernel.org/pub/scm/linux/kernel/git/sam/kbuild
[deliverable/linux.git] / drivers / char / mxser_new.c
CommitLineData
037ad48b
JS		 1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
3306ce3d 4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com.tw).
c88cb8f9 5 * Copyright (C) 2006 Jiri Slaby <jirislaby@gmail.com>
037ad48b 6 *
c88cb8f9
JS		 7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
037ad48b
JS		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
037ad48b
JS		 16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
17 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
18 * - Fixed x86_64 cleanness
19 * - Fixed sleep with spinlock held in mxser_send_break
20 */
21
037ad48b
JS		 22#include <linux/module.h>
23#include <linux/autoconf.h>
24#include <linux/errno.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/timer.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial.h>
32#include <linux/serial_reg.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/fcntl.h>
36#include <linux/ptrace.h>
37#include <linux/gfp.h>
38#include <linux/ioport.h>
39#include <linux/mm.h>
037ad48b
JS		 40#include <linux/delay.h>
41#include <linux/pci.h>
42
43#include <asm/system.h>
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/bitops.h>
47#include <asm/uaccess.h>
48
771f2d1a 49#include "mxser_new.h"
037ad48b 50
f64c84a1 51#define MXSER_VERSION "2.0.1" /* 1.9.15 */
037ad48b
JS		 52#define MXSERMAJOR 174
53#define MXSERCUMAJOR 175
54
037ad48b 55#define MXSER_BOARDS 4 /* Max. boards */
037ad48b 56#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
a8b74de9 57#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
18b95576 58#define MXSER_ISR_PASS_LIMIT 100
037ad48b
JS		 59
60#define MXSER_ERR_IOADDR -1
61#define MXSER_ERR_IRQ -2
62#define MXSER_ERR_IRQ_CONFLIT -3
63#define MXSER_ERR_VECTOR -4
64
ed79ba12
JS		 65/*CheckIsMoxaMust return value*/
66#define MOXA_OTHER_UART 0x00
67#define MOXA_MUST_MU150_HWID 0x01
68#define MOXA_MUST_MU860_HWID 0x02
69
037ad48b
JS		 70#define WAKEUP_CHARS 256
71
72#define UART_MCR_AFE 0x20
73#define UART_LSR_SPECIAL 0x1E
74
037ad48b 75
037ad48b
JS		 76#define C168_ASIC_ID 1
77#define C104_ASIC_ID 2
78#define C102_ASIC_ID 0xB
79#define CI132_ASIC_ID 4
80#define CI134_ASIC_ID 3
81#define CI104J_ASIC_ID 5
82
cd7ed64e
JS		 83#define MXSER_HIGHBAUD 1
84#define MXSER_HAS2 2
037ad48b
JS		 85
86/* This is only for PCI */
cd7ed64e 87static const struct {
037ad48b
JS		 88 int type;
89 int tx_fifo;
90 int rx_fifo;
91 int xmit_fifo_size;
92 int rx_high_water;
93 int rx_trigger;
94 int rx_low_water;
95 long max_baud;
cd7ed64e 96} Gpci_uart_info[] = {
037ad48b
JS		 97 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
98 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
99 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
100};
cd7ed64e
JS		 101#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
102
103struct mxser_cardinfo {
104 unsigned int nports;
105 char *name;
106 unsigned int flags;
107};
108
109static const struct mxser_cardinfo mxser_cards[] = {
110 { 8, "C168 series", }, /* C168-ISA */
111 { 4, "C104 series", }, /* C104-ISA */
112 { 4, "CI-104J series", }, /* CI104J */
113 { 8, "C168H/PCI series", }, /* C168-PCI */
114 { 4, "C104H/PCI series", }, /* C104-PCI */
115 { 4, "C102 series", MXSER_HAS2 }, /* C102-ISA */
116 { 4, "CI-132 series", MXSER_HAS2 }, /* CI132 */
117 { 4, "CI-134 series", }, /* CI134 */
118 { 2, "CP-132 series", }, /* CP132 */
119 { 4, "CP-114 series", }, /* CP114 */
120 { 4, "CT-114 series", }, /* CT114 */
121 { 2, "CP-102 series", MXSER_HIGHBAUD }, /* CP102 */
122 { 4, "CP-104U series", }, /* CP104U */
123 { 8, "CP-168U series", }, /* CP168U */
124 { 2, "CP-132U series", }, /* CP132U */
125 { 4, "CP-134U series", }, /* CP134U */
126 { 4, "CP-104JU series", }, /* CP104JU */
127 { 8, "Moxa UC7000 Serial", }, /* RC7000 */
128 { 8, "CP-118U series", }, /* CP118U */
129 { 2, "CP-102UL series", }, /* CP102UL */
130 { 2, "CP-102U series", }, /* CP102U */
131 { 8, "CP-118EL series", }, /* CP118EL */
132 { 8, "CP-168EL series", }, /* CP168EL */
133 { 4, "CP-104EL series", } /* CP104EL */
134};
037ad48b 135
cd7ed64e
JS		 136/* driver_data correspond to the lines in the structure above
137 see also ISA probe function before you change something */
037ad48b 138static struct pci_device_id mxser_pcibrds[] = {
3306ce3d 139 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C168),
cd7ed64e 140 .driver_data = 3 },
3306ce3d 141 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C104),
cd7ed64e 142 .driver_data = 4 },
3306ce3d 143 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132),
cd7ed64e 144 .driver_data = 8 },
3306ce3d 145 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114),
cd7ed64e 146 .driver_data = 9 },
3306ce3d 147 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CT114),
cd7ed64e 148 .driver_data = 10 },
3306ce3d 149 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102),
cd7ed64e 150 .driver_data = 11 },
3306ce3d 151 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104U),
cd7ed64e 152 .driver_data = 12 },
3306ce3d 153 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168U),
cd7ed64e 154 .driver_data = 13 },
3306ce3d 155 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132U),
cd7ed64e 156 .driver_data = 14 },
3306ce3d 157 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134U),
cd7ed64e 158 .driver_data = 15 },
3306ce3d 159 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104JU),
cd7ed64e 160 .driver_data = 16 },
3306ce3d 161 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_RC7000),
cd7ed64e 162 .driver_data = 17 },
3306ce3d 163 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118U),
cd7ed64e 164 .driver_data = 18 },
3306ce3d 165 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102UL),
cd7ed64e 166 .driver_data = 19 },
3306ce3d 167 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102U),
cd7ed64e 168 .driver_data = 20 },
3306ce3d 169 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL),
cd7ed64e 170 .driver_data = 21 },
3306ce3d 171 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL),
cd7ed64e 172 .driver_data = 22 },
3306ce3d 173 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL),
cd7ed64e 174 .driver_data = 23 },
3306ce3d 175 { }
037ad48b 176};
037ad48b
JS		 177MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
178
f64c84a1
JS		 179static int mxvar_baud_table[] = {
180 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
181 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600
182};
183static unsigned int mxvar_baud_table1[] = {
184 0, B50, B75, B110, B134, B150, B200, B300, B600, B1200, B1800, B2400,
185 B4800, B9600, B19200, B38400, B57600, B115200, B230400, B460800, B921600
186};
187#define BAUD_TABLE_NO ARRAY_SIZE(mxvar_baud_table)
188
189#define B_SPEC B2000000
190
037ad48b
JS		 191static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 };
192static int ttymajor = MXSERMAJOR;
193static int calloutmajor = MXSERCUMAJOR;
037ad48b
JS		 194
195/* Variables for insmod */
196
197MODULE_AUTHOR("Casper Yang");
198MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
199module_param_array(ioaddr, int, NULL, 0);
200module_param(ttymajor, int, 0);
037ad48b
JS		 201MODULE_LICENSE("GPL");
202
203struct mxser_log {
204 int tick;
205 unsigned long rxcnt[MXSER_PORTS];
206 unsigned long txcnt[MXSER_PORTS];
207};
208
209
210struct mxser_mon {
211 unsigned long rxcnt;
212 unsigned long txcnt;
213 unsigned long up_rxcnt;
214 unsigned long up_txcnt;
215 int modem_status;
216 unsigned char hold_reason;
217};
218
219struct mxser_mon_ext {
220 unsigned long rx_cnt[32];
221 unsigned long tx_cnt[32];
222 unsigned long up_rxcnt[32];
223 unsigned long up_txcnt[32];
224 int modem_status[32];
225
226 long baudrate[32];
227 int databits[32];
228 int stopbits[32];
229 int parity[32];
230 int flowctrl[32];
231 int fifo[32];
232 int iftype[32];
233};
234
55b307da
JS		 235struct mxser_board;
236
237struct mxser_port {
238 struct mxser_board *board;
239 struct tty_struct *tty;
240
241 unsigned long ioaddr;
242 unsigned long opmode_ioaddr;
243 int max_baud;
037ad48b 244
037ad48b
JS		 245 int rx_high_water;
246 int rx_trigger; /* Rx fifo trigger level */
247 int rx_low_water;
248 int baud_base; /* max. speed */
55b307da 249 long realbaud;
037ad48b 250 int type; /* UART type */
55b307da 251 int flags; /* defined in tty.h */
f64c84a1 252 int speed;
55b307da 253
037ad48b 254 int x_char; /* xon/xoff character */
037ad48b
JS		 255 int IER; /* Interrupt Enable Register */
256 int MCR; /* Modem control register */
55b307da
JS		 257
258 unsigned char stop_rx;
259 unsigned char ldisc_stop_rx;
260
261 int custom_divisor;
262 int close_delay;
263 unsigned short closing_wait;
264 unsigned char err_shadow;
037ad48b 265 unsigned long event;
55b307da 266
037ad48b
JS		 267 int count; /* # of fd on device */
268 int blocked_open; /* # of blocked opens */
55b307da
JS		 269 struct async_icount icount; /* kernel counters for 4 input interrupts */
270 int timeout;
271
272 int read_status_mask;
273 int ignore_status_mask;
274 int xmit_fifo_size;
037ad48b
JS		 275 unsigned char *xmit_buf;
276 int xmit_head;
277 int xmit_tail;
278 int xmit_cnt;
55b307da 279
606d099c 280 struct ktermios normal_termios;
55b307da
JS		 281
282 struct mxser_mon mon_data;
283
284 spinlock_t slock;
037ad48b 285 wait_queue_head_t open_wait;
037ad48b 286 wait_queue_head_t delta_msr_wait;
55b307da
JS		 287};
288
289struct mxser_board {
2094e757 290 unsigned int idx;
55b307da 291 int irq;
cd7ed64e 292 const struct mxser_cardinfo *info;
55b307da
JS		 293 unsigned long vector;
294 unsigned long vector_mask;
295
296 int chip_flag;
297 int uart_type;
298
299 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
037ad48b
JS		 300};
301
302struct mxser_mstatus {
303 tcflag_t cflag;
304 int cts;
305 int dsr;
306 int ri;
307 int dcd;
308};
309
310static struct mxser_mstatus GMStatus[MXSER_PORTS];
311
312static int mxserBoardCAP[MXSER_BOARDS] = {
313 0, 0, 0, 0
314 /* 0x180, 0x280, 0x200, 0x320 */
315};
316
55b307da 317static struct mxser_board mxser_boards[MXSER_BOARDS];
037ad48b 318static struct tty_driver *mxvar_sdriver;
037ad48b
JS		 319static struct mxser_log mxvar_log;
320static int mxvar_diagflag;
321static unsigned char mxser_msr[MXSER_PORTS + 1];
322static struct mxser_mon_ext mon_data_ext;
323static int mxser_set_baud_method[MXSER_PORTS + 1];
037ad48b 324
fb0c9295 325#ifdef CONFIG_PCI
c76b0930 326static int __devinit CheckIsMoxaMust(int io)
037ad48b
JS		 327{
328 u8 oldmcr, hwid;
329 int i;
330
331 outb(0, io + UART_LCR);
332 DISABLE_MOXA_MUST_ENCHANCE_MODE(io);
333 oldmcr = inb(io + UART_MCR);
334 outb(0, io + UART_MCR);
335 SET_MOXA_MUST_XON1_VALUE(io, 0x11);
336 if ((hwid = inb(io + UART_MCR)) != 0) {
337 outb(oldmcr, io + UART_MCR);
338 return MOXA_OTHER_UART;
339 }
340
341 GET_MOXA_MUST_HARDWARE_ID(io, &hwid);
cd7ed64e
JS		 342 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
343 if (hwid == Gpci_uart_info[i].type)
037ad48b
JS		 344 return (int)hwid;
345 }
346 return MOXA_OTHER_UART;
347}
fb0c9295 348#endif
037ad48b 349
55b307da 350static void process_txrx_fifo(struct mxser_port *info)
037ad48b
JS		 351{
352 int i;
353
354 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
355 info->rx_trigger = 1;
356 info->rx_high_water = 1;
357 info->rx_low_water = 1;
358 info->xmit_fifo_size = 1;
55b307da
JS		 359 } else
360 for (i = 0; i < UART_INFO_NUM; i++)
361 if (info->board->chip_flag == Gpci_uart_info[i].type) {
037ad48b
JS		 362 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
363 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
364 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
365 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
366 break;
367 }
037ad48b
JS		 368}
369
a8dea4ec
JS		 370static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
371{
372 unsigned char status = 0;
037ad48b 373
a8dea4ec 374 status = inb(baseaddr + UART_MSR);
037ad48b 375
a8dea4ec
JS		 376 mxser_msr[port] &= 0x0F;
377 mxser_msr[port] |= status;
378 status = mxser_msr[port];
379 if (mode)
380 mxser_msr[port] = 0;
037ad48b 381
a8dea4ec
JS		 382 return status;
383}
55b307da 384
a8dea4ec
JS		 385static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp,
386 struct mxser_port *port)
387{
388 DECLARE_WAITQUEUE(wait, current);
389 int retval;
390 int do_clocal = 0;
391 unsigned long flags;
392
393 /*
394 * If non-blocking mode is set, or the port is not enabled,
395 * then make the check up front and then exit.
396 */
214efebb
JS		 397 if ((filp->f_flags & O_NONBLOCK) ||
398 test_bit(TTY_IO_ERROR, &tty->flags)) {
a8dea4ec
JS		 399 port->flags |= ASYNC_NORMAL_ACTIVE;
400 return 0;
037ad48b 401 }
a8dea4ec
JS		 402
403 if (tty->termios->c_cflag & CLOCAL)
404 do_clocal = 1;
405
037ad48b 406 /*
a8dea4ec
JS		 407 * Block waiting for the carrier detect and the line to become
408 * free (i.e., not in use by the callout). While we are in
409 * this loop, port->count is dropped by one, so that
410 * mxser_close() knows when to free things. We restore it upon
411 * exit, either normal or abnormal.
037ad48b 412 */
a8dea4ec
JS		 413 retval = 0;
414 add_wait_queue(&port->open_wait, &wait);
037ad48b 415
a8dea4ec
JS		 416 spin_lock_irqsave(&port->slock, flags);
417 if (!tty_hung_up_p(filp))
418 port->count--;
419 spin_unlock_irqrestore(&port->slock, flags);
420 port->blocked_open++;
421 while (1) {
422 spin_lock_irqsave(&port->slock, flags);
423 outb(inb(port->ioaddr + UART_MCR) |
424 UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR);
425 spin_unlock_irqrestore(&port->slock, flags);
426 set_current_state(TASK_INTERRUPTIBLE);
427 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) {
428 if (port->flags & ASYNC_HUP_NOTIFY)
429 retval = -EAGAIN;
430 else
431 retval = -ERESTARTSYS;
432 break;
433 }
434 if (!(port->flags & ASYNC_CLOSING) &&
435 (do_clocal ||
436 (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD)))
437 break;
438 if (signal_pending(current)) {
439 retval = -ERESTARTSYS;
440 break;
441 }
442 schedule();
037ad48b 443 }
a8dea4ec
JS		 444 set_current_state(TASK_RUNNING);
445 remove_wait_queue(&port->open_wait, &wait);
446 if (!tty_hung_up_p(filp))
447 port->count++;
448 port->blocked_open--;
449 if (retval)
450 return retval;
451 port->flags |= ASYNC_NORMAL_ACTIVE;
037ad48b
JS		 452 return 0;
453}
454
a8dea4ec 455static int mxser_set_baud(struct mxser_port *info, long newspd)
037ad48b 456{
f64c84a1 457 unsigned int i;
a8dea4ec
JS		 458 int quot = 0;
459 unsigned char cval;
460 int ret = 0;
037ad48b 461
a8dea4ec
JS		 462 if (!info->tty || !info->tty->termios)
463 return ret;
037ad48b 464
a8dea4ec
JS		 465 if (!(info->ioaddr))
466 return ret;
037ad48b 467
a8dea4ec
JS		 468 if (newspd > info->max_baud)
469 return 0;
037ad48b 470
a8dea4ec 471 info->realbaud = newspd;
f64c84a1
JS		 472 for (i = 0; i < BAUD_TABLE_NO; i++)
473 if (newspd == mxvar_baud_table[i])
474 break;
475 if (i == BAUD_TABLE_NO) {
476 quot = info->baud_base / info->speed;
477 if (info->speed <= 0 || info->speed > info->max_baud)
478 quot = 0;
a8dea4ec 479 } else {
f64c84a1
JS		 480 if (newspd == 134) {
481 quot = (2 * info->baud_base / 269);
482 } else if (newspd) {
483 quot = info->baud_base / newspd;
484 if (quot == 0)
485 quot = 1;
486 } else {
487 quot = 0;
488 }
037ad48b
JS		 489 }
490
a8dea4ec
JS		 491 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
492 info->timeout += HZ / 50; /* Add .02 seconds of slop */
037ad48b 493
a8dea4ec 494 if (quot) {
a8dea4ec
JS		 495 info->MCR |= UART_MCR_DTR;
496 outb(info->MCR, info->ioaddr + UART_MCR);
a8dea4ec 497 } else {
a8dea4ec
JS		 498 info->MCR &= ~UART_MCR_DTR;
499 outb(info->MCR, info->ioaddr + UART_MCR);
a8dea4ec 500 return ret;
037ad48b 501 }
037ad48b 502
a8dea4ec 503 cval = inb(info->ioaddr + UART_LCR);
037ad48b 504
a8dea4ec 505 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
037ad48b 506
a8dea4ec
JS		 507 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
508 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
509 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
037ad48b 510
f64c84a1
JS		 511 if (i == BAUD_TABLE_NO) {
512 quot = info->baud_base % info->speed;
513 quot *= 8;
514 if ((quot % info->speed) > (info->speed / 2)) {
515 quot /= info->speed;
516 quot++;
517 } else {
518 quot /= info->speed;
519 }
520 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, quot);
521 } else
522 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, 0);
037ad48b 523
a8dea4ec
JS		 524 return ret;
525}
037ad48b 526
a8dea4ec
JS		 527/*
528 * This routine is called to set the UART divisor registers to match
529 * the specified baud rate for a serial port.
530 */
531static int mxser_change_speed(struct mxser_port *info,
606d099c 532 struct ktermios *old_termios)
a8dea4ec
JS		 533{
534 unsigned cflag, cval, fcr;
535 int ret = 0;
536 unsigned char status;
537 long baud;
037ad48b 538
a8dea4ec
JS		 539 if (!info->tty || !info->tty->termios)
540 return ret;
541 cflag = info->tty->termios->c_cflag;
542 if (!(info->ioaddr))
543 return ret;
037ad48b 544
a8dea4ec 545 if (mxser_set_baud_method[info->tty->index] == 0) {
f64c84a1
JS		 546 if ((cflag & CBAUD) == B_SPEC)
547 baud = info->speed;
548 else
549 baud = tty_get_baud_rate(info->tty);
a8dea4ec
JS		 550 mxser_set_baud(info, baud);
551 }
037ad48b 552
a8dea4ec
JS		 553 /* byte size and parity */
554 switch (cflag & CSIZE) {
555 case CS5:
556 cval = 0x00;
557 break;
558 case CS6:
559 cval = 0x01;
560 break;
561 case CS7:
562 cval = 0x02;
563 break;
564 case CS8:
565 cval = 0x03;
566 break;
567 default:
568 cval = 0x00;
569 break; /* too keep GCC shut... */
570 }
571 if (cflag & CSTOPB)
572 cval |= 0x04;
573 if (cflag & PARENB)
574 cval |= UART_LCR_PARITY;
575 if (!(cflag & PARODD))
576 cval |= UART_LCR_EPAR;
577 if (cflag & CMSPAR)
578 cval |= UART_LCR_SPAR;
037ad48b 579
a8dea4ec
JS		 580 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
581 if (info->board->chip_flag) {
582 fcr = UART_FCR_ENABLE_FIFO;
583 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
584 SET_MOXA_MUST_FIFO_VALUE(info);
585 } else
586 fcr = 0;
587 } else {
588 fcr = UART_FCR_ENABLE_FIFO;
a8dea4ec
JS		 589 if (info->board->chip_flag) {
590 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
591 SET_MOXA_MUST_FIFO_VALUE(info);
592 } else {
a8dea4ec
JS		 593 switch (info->rx_trigger) {
594 case 1:
595 fcr |= UART_FCR_TRIGGER_1;
596 break;
597 case 4:
598 fcr |= UART_FCR_TRIGGER_4;
599 break;
600 case 8:
601 fcr |= UART_FCR_TRIGGER_8;
602 break;
603 default:
604 fcr |= UART_FCR_TRIGGER_14;
605 break;
606 }
037ad48b 607 }
037ad48b
JS		 608 }
609
a8dea4ec
JS		 610 /* CTS flow control flag and modem status interrupts */
611 info->IER &= ~UART_IER_MSI;
612 info->MCR &= ~UART_MCR_AFE;
613 if (cflag & CRTSCTS) {
614 info->flags |= ASYNC_CTS_FLOW;
615 info->IER |= UART_IER_MSI;
616 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
617 info->MCR |= UART_MCR_AFE;
a8dea4ec 618 } else {
a8dea4ec 619 status = inb(info->ioaddr + UART_MSR);
a8dea4ec
JS		 620 if (info->tty->hw_stopped) {
621 if (status & UART_MSR_CTS) {
622 info->tty->hw_stopped = 0;
623 if (info->type != PORT_16550A &&
624 !info->board->chip_flag) {
625 outb(info->IER & ~UART_IER_THRI,
626 info->ioaddr +
627 UART_IER);
628 info->IER |= UART_IER_THRI;
629 outb(info->IER, info->ioaddr +
630 UART_IER);
631 }
47c85c0d
JS		 632 tty_wakeup(info->tty);
633 }
a8dea4ec
JS		 634 } else {
635 if (!(status & UART_MSR_CTS)) {
636 info->tty->hw_stopped = 1;
637 if ((info->type != PORT_16550A) &&
638 (!info->board->chip_flag)) {
639 info->IER &= ~UART_IER_THRI;
640 outb(info->IER, info->ioaddr +
641 UART_IER);
642 }
643 }
644 }
645 }
646 } else {
647 info->flags &= ~ASYNC_CTS_FLOW;
648 }
649 outb(info->MCR, info->ioaddr + UART_MCR);
650 if (cflag & CLOCAL) {
651 info->flags &= ~ASYNC_CHECK_CD;
652 } else {
653 info->flags |= ASYNC_CHECK_CD;
654 info->IER |= UART_IER_MSI;
655 }
656 outb(info->IER, info->ioaddr + UART_IER);
037ad48b 657
a8dea4ec
JS		 658 /*
659 * Set up parity check flag
660 */
661 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
662 if (I_INPCK(info->tty))
663 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
664 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
665 info->read_status_mask |= UART_LSR_BI;
037ad48b 666
a8dea4ec 667 info->ignore_status_mask = 0;
037ad48b 668
a8dea4ec
JS		 669 if (I_IGNBRK(info->tty)) {
670 info->ignore_status_mask |= UART_LSR_BI;
671 info->read_status_mask |= UART_LSR_BI;
672 /*
673 * If we're ignore parity and break indicators, ignore
674 * overruns too. (For real raw support).
675 */
676 if (I_IGNPAR(info->tty)) {
677 info->ignore_status_mask |=
678 UART_LSR_OE |
679 UART_LSR_PE |
680 UART_LSR_FE;
681 info->read_status_mask |=
682 UART_LSR_OE |
683 UART_LSR_PE |
684 UART_LSR_FE;
037ad48b 685 }
037ad48b 686 }
a8dea4ec 687 if (info->board->chip_flag) {
a8dea4ec
JS		 688 SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty));
689 SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty));
690 if (I_IXON(info->tty)) {
691 ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
692 } else {
693 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
037ad48b 694 }
a8dea4ec
JS		 695 if (I_IXOFF(info->tty)) {
696 ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
697 } else {
698 DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
037ad48b
JS		 699 }
700 }
037ad48b 701
037ad48b 702
a8dea4ec
JS		 703 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
704 outb(cval, info->ioaddr + UART_LCR);
037ad48b 705
a8dea4ec 706 return ret;
037ad48b
JS		 707}
708
a8dea4ec 709static void mxser_check_modem_status(struct mxser_port *port, int status)
037ad48b 710{
a8dea4ec
JS		 711 /* update input line counters */
712 if (status & UART_MSR_TERI)
713 port->icount.rng++;
714 if (status & UART_MSR_DDSR)
715 port->icount.dsr++;
716 if (status & UART_MSR_DDCD)
717 port->icount.dcd++;
718 if (status & UART_MSR_DCTS)
719 port->icount.cts++;
720 port->mon_data.modem_status = status;
721 wake_up_interruptible(&port->delta_msr_wait);
037ad48b 722
a8dea4ec
JS		 723 if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
724 if (status & UART_MSR_DCD)
725 wake_up_interruptible(&port->open_wait);
a8dea4ec 726 }
037ad48b 727
a8dea4ec
JS		 728 if (port->flags & ASYNC_CTS_FLOW) {
729 if (port->tty->hw_stopped) {
730 if (status & UART_MSR_CTS) {
731 port->tty->hw_stopped = 0;
732
733 if ((port->type != PORT_16550A) &&
734 (!port->board->chip_flag)) {
735 outb(port->IER & ~UART_IER_THRI,
736 port->ioaddr + UART_IER);
737 port->IER |= UART_IER_THRI;
738 outb(port->IER, port->ioaddr +
739 UART_IER);
740 }
47c85c0d 741 tty_wakeup(port->tty);
a8dea4ec
JS		 742 }
743 } else {
744 if (!(status & UART_MSR_CTS)) {
745 port->tty->hw_stopped = 1;
746 if (port->type != PORT_16550A &&
747 !port->board->chip_flag) {
748 port->IER &= ~UART_IER_THRI;
749 outb(port->IER, port->ioaddr +
750 UART_IER);
751 }
752 }
753 }
754 }
037ad48b
JS		 755}
756
a8dea4ec 757static int mxser_startup(struct mxser_port *info)
037ad48b 758{
a8dea4ec
JS		 759 unsigned long page;
760 unsigned long flags;
037ad48b 761
a8dea4ec
JS		 762 page = __get_free_page(GFP_KERNEL);
763 if (!page)
764 return -ENOMEM;
037ad48b 765
a8dea4ec 766 spin_lock_irqsave(&info->slock, flags);
037ad48b 767
a8dea4ec
JS		 768 if (info->flags & ASYNC_INITIALIZED) {
769 free_page(page);
770 spin_unlock_irqrestore(&info->slock, flags);
771 return 0;
772 }
037ad48b 773
a8dea4ec
JS		 774 if (!info->ioaddr || !info->type) {
775 if (info->tty)
776 set_bit(TTY_IO_ERROR, &info->tty->flags);
777 free_page(page);
778 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 779 return 0;
a8dea4ec
JS		 780 }
781 if (info->xmit_buf)
782 free_page(page);
783 else
784 info->xmit_buf = (unsigned char *) page;
037ad48b 785
037ad48b 786 /*
a8dea4ec
JS		 787 * Clear the FIFO buffers and disable them
788 * (they will be reenabled in mxser_change_speed())
037ad48b 789 */
a8dea4ec
JS		 790 if (info->board->chip_flag)
791 outb((UART_FCR_CLEAR_RCVR |
792 UART_FCR_CLEAR_XMIT |
793 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
794 else
795 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
796 info->ioaddr + UART_FCR);
797
798 /*
799 * At this point there's no way the LSR could still be 0xFF;
800 * if it is, then bail out, because there's likely no UART
801 * here.
802 */
803 if (inb(info->ioaddr + UART_LSR) == 0xff) {
804 spin_unlock_irqrestore(&info->slock, flags);
805 if (capable(CAP_SYS_ADMIN)) {
806 if (info->tty)
807 set_bit(TTY_IO_ERROR, &info->tty->flags);
808 return 0;
809 } else
810 return -ENODEV;
811 }
812
813 /*
814 * Clear the interrupt registers.
815 */
816 (void) inb(info->ioaddr + UART_LSR);
817 (void) inb(info->ioaddr + UART_RX);
818 (void) inb(info->ioaddr + UART_IIR);
819 (void) inb(info->ioaddr + UART_MSR);
820
821 /*
822 * Now, initialize the UART
823 */
824 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
825 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
826 outb(info->MCR, info->ioaddr + UART_MCR);
827
828 /*
829 * Finally, enable interrupts
830 */
831 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
a8dea4ec 832
a8dea4ec
JS		 833 if (info->board->chip_flag)
834 info->IER |= MOXA_MUST_IER_EGDAI;
a8dea4ec
JS		 835 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
836
837 /*
838 * And clear the interrupt registers again for luck.
839 */
840 (void) inb(info->ioaddr + UART_LSR);
841 (void) inb(info->ioaddr + UART_RX);
842 (void) inb(info->ioaddr + UART_IIR);
843 (void) inb(info->ioaddr + UART_MSR);
844
845 if (info->tty)
846 clear_bit(TTY_IO_ERROR, &info->tty->flags);
847 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
848
849 /*
850 * and set the speed of the serial port
851 */
a8dea4ec 852 mxser_change_speed(info, NULL);
5ff7205d 853 info->flags |= ASYNC_INITIALIZED;
f64c84a1 854 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec 855
a8dea4ec
JS		 856 return 0;
857}
858
859/*
860 * This routine will shutdown a serial port; interrupts maybe disabled, and
861 * DTR is dropped if the hangup on close termio flag is on.
862 */
863static void mxser_shutdown(struct mxser_port *info)
864{
865 unsigned long flags;
866
867 if (!(info->flags & ASYNC_INITIALIZED))
868 return;
869
870 spin_lock_irqsave(&info->slock, flags);
871
872 /*
873 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
874 * here so the queue might never be waken up
875 */
876 wake_up_interruptible(&info->delta_msr_wait);
877
878 /*
879 * Free the IRQ, if necessary
880 */
881 if (info->xmit_buf) {
882 free_page((unsigned long) info->xmit_buf);
883 info->xmit_buf = NULL;
884 }
885
886 info->IER = 0;
887 outb(0x00, info->ioaddr + UART_IER);
888
889 if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
890 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
891 outb(info->MCR, info->ioaddr + UART_MCR);
892
893 /* clear Rx/Tx FIFO's */
a8dea4ec
JS		 894 if (info->board->chip_flag)
895 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
896 MOXA_MUST_FCR_GDA_MODE_ENABLE,
897 info->ioaddr + UART_FCR);
898 else
a8dea4ec
JS		 899 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
900 info->ioaddr + UART_FCR);
901
902 /* read data port to reset things */
903 (void) inb(info->ioaddr + UART_RX);
904
905 if (info->tty)
906 set_bit(TTY_IO_ERROR, &info->tty->flags);
907
908 info->flags &= ~ASYNC_INITIALIZED;
909
a8dea4ec
JS		 910 if (info->board->chip_flag)
911 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
a8dea4ec
JS		 912
913 spin_unlock_irqrestore(&info->slock, flags);
914}
915
916/*
917 * This routine is called whenever a serial port is opened. It
918 * enables interrupts for a serial port, linking in its async structure into
919 * the IRQ chain. It also performs the serial-specific
920 * initialization for the tty structure.
921 */
922static int mxser_open(struct tty_struct *tty, struct file *filp)
923{
924 struct mxser_port *info;
5ff7205d 925 unsigned long flags;
a8dea4ec
JS		 926 int retval, line;
927
a8dea4ec
JS		 928 line = tty->index;
929 if (line == MXSER_PORTS)
930 return 0;
931 if (line < 0 || line > MXSER_PORTS)
932 return -ENODEV;
933 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
934 if (!info->ioaddr)
935 return -ENODEV;
936
937 tty->driver_data = info;
938 info->tty = tty;
939 /*
940 * Start up serial port
941 */
5ff7205d 942 spin_lock_irqsave(&info->slock, flags);
a8dea4ec 943 info->count++;
5ff7205d 944 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec
JS		 945 retval = mxser_startup(info);
946 if (retval)
947 return retval;
948
949 retval = mxser_block_til_ready(tty, filp, info);
950 if (retval)
951 return retval;
952
e079f495 953 /* unmark here for very high baud rate (ex. 921600 bps) used */
037ad48b
JS		 954 tty->low_latency = 1;
955 return 0;
956}
957
958/*
959 * This routine is called when the serial port gets closed. First, we
960 * wait for the last remaining data to be sent. Then, we unlink its
961 * async structure from the interrupt chain if necessary, and we free
962 * that IRQ if nothing is left in the chain.
963 */
964static void mxser_close(struct tty_struct *tty, struct file *filp)
965{
55b307da 966 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 967
968 unsigned long timeout;
969 unsigned long flags;
037ad48b
JS		 970
971 if (tty->index == MXSER_PORTS)
972 return;
973 if (!info)
974 return;
975
976 spin_lock_irqsave(&info->slock, flags);
977
978 if (tty_hung_up_p(filp)) {
979 spin_unlock_irqrestore(&info->slock, flags);
980 return;
981 }
982 if ((tty->count == 1) && (info->count != 1)) {
983 /*
984 * Uh, oh. tty->count is 1, which means that the tty
985 * structure will be freed. Info->count should always
986 * be one in these conditions. If it's greater than
987 * one, we've got real problems, since it means the
988 * serial port won't be shutdown.
989 */
990 printk(KERN_ERR "mxser_close: bad serial port count; "
991 "tty->count is 1, info->count is %d\n", info->count);
992 info->count = 1;
993 }
994 if (--info->count < 0) {
995 printk(KERN_ERR "mxser_close: bad serial port count for "
55b307da 996 "ttys%d: %d\n", tty->index, info->count);
037ad48b
JS		 997 info->count = 0;
998 }
999 if (info->count) {
1000 spin_unlock_irqrestore(&info->slock, flags);
1001 return;
1002 }
1003 info->flags |= ASYNC_CLOSING;
1004 spin_unlock_irqrestore(&info->slock, flags);
1005 /*
1006 * Save the termios structure, since this port may have
1007 * separate termios for callout and dialin.
1008 */
1009 if (info->flags & ASYNC_NORMAL_ACTIVE)
1010 info->normal_termios = *tty->termios;
1011 /*
1012 * Now we wait for the transmit buffer to clear; and we notify
1013 * the line discipline to only process XON/XOFF characters.
1014 */
1015 tty->closing = 1;
1016 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
1017 tty_wait_until_sent(tty, info->closing_wait);
1018 /*
1019 * At this point we stop accepting input. To do this, we
1020 * disable the receive line status interrupts, and tell the
1021 * interrupt driver to stop checking the data ready bit in the
1022 * line status register.
1023 */
1024 info->IER &= ~UART_IER_RLSI;
55b307da 1025 if (info->board->chip_flag)
037ad48b 1026 info->IER &= ~MOXA_MUST_RECV_ISR;
e079f495 1027
037ad48b 1028 if (info->flags & ASYNC_INITIALIZED) {
55b307da 1029 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1030 /*
1031 * Before we drop DTR, make sure the UART transmitter
1032 * has completely drained; this is especially
1033 * important if there is a transmit FIFO!
1034 */
1035 timeout = jiffies + HZ;
55b307da 1036 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
037ad48b
JS		 1037 schedule_timeout_interruptible(5);
1038 if (time_after(jiffies, timeout))
1039 break;
1040 }
1041 }
1042 mxser_shutdown(info);
1043
1044 if (tty->driver->flush_buffer)
1045 tty->driver->flush_buffer(tty);
1046
7e8bcf9a 1047 tty_ldisc_flush(tty);
037ad48b
JS		 1048
1049 tty->closing = 0;
1050 info->event = 0;
1051 info->tty = NULL;
1052 if (info->blocked_open) {
1053 if (info->close_delay)
1054 schedule_timeout_interruptible(info->close_delay);
1055 wake_up_interruptible(&info->open_wait);
1056 }
1057
1058 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
037ad48b
JS		 1059}
1060
1061static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1062{
1063 int c, total = 0;
55b307da 1064 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1065 unsigned long flags;
1066
1067 if (!info->xmit_buf)
1068 return 0;
1069
1070 while (1) {
1071 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1072 SERIAL_XMIT_SIZE - info->xmit_head));
1073 if (c <= 0)
1074 break;
1075
1076 memcpy(info->xmit_buf + info->xmit_head, buf, c);
1077 spin_lock_irqsave(&info->slock, flags);
1078 info->xmit_head = (info->xmit_head + c) &
1079 (SERIAL_XMIT_SIZE - 1);
1080 info->xmit_cnt += c;
1081 spin_unlock_irqrestore(&info->slock, flags);
1082
1083 buf += c;
1084 count -= c;
1085 total += c;
1086 }
1087
e079f495 1088 if (info->xmit_cnt && !tty->stopped) {
037ad48b
JS		 1089 if (!tty->hw_stopped ||
1090 (info->type == PORT_16550A) ||
55b307da 1091 (info->board->chip_flag)) {
037ad48b 1092 spin_lock_irqsave(&info->slock, flags);
55b307da
JS		 1093 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1094 UART_IER);
037ad48b 1095 info->IER |= UART_IER_THRI;
55b307da 1096 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1097 spin_unlock_irqrestore(&info->slock, flags);
1098 }
1099 }
1100 return total;
1101}
1102
1103static void mxser_put_char(struct tty_struct *tty, unsigned char ch)
1104{
55b307da 1105 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1106 unsigned long flags;
1107
1108 if (!info->xmit_buf)
1109 return;
1110
1111 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
1112 return;
1113
1114 spin_lock_irqsave(&info->slock, flags);
1115 info->xmit_buf[info->xmit_head++] = ch;
1116 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1117 info->xmit_cnt++;
1118 spin_unlock_irqrestore(&info->slock, flags);
e079f495 1119 if (!tty->stopped) {
037ad48b
JS		 1120 if (!tty->hw_stopped ||
1121 (info->type == PORT_16550A) ||
55b307da 1122 info->board->chip_flag) {
037ad48b 1123 spin_lock_irqsave(&info->slock, flags);
55b307da 1124 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
037ad48b 1125 info->IER |= UART_IER_THRI;
55b307da 1126 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1127 spin_unlock_irqrestore(&info->slock, flags);
1128 }
1129 }
1130}
1131
1132
1133static void mxser_flush_chars(struct tty_struct *tty)
1134{
55b307da 1135 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1136 unsigned long flags;
1137
1138 if (info->xmit_cnt <= 0 ||
1139 tty->stopped ||
1140 !info->xmit_buf ||
1141 (tty->hw_stopped &&
1142 (info->type != PORT_16550A) &&
55b307da 1143 (!info->board->chip_flag)
037ad48b
JS		 1144 ))
1145 return;
1146
1147 spin_lock_irqsave(&info->slock, flags);
1148
55b307da 1149 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
037ad48b 1150 info->IER |= UART_IER_THRI;
55b307da 1151 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1152
1153 spin_unlock_irqrestore(&info->slock, flags);
1154}
1155
1156static int mxser_write_room(struct tty_struct *tty)
1157{
55b307da 1158 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1159 int ret;
1160
1161 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1162 if (ret < 0)
1163 ret = 0;
1164 return ret;
1165}
1166
1167static int mxser_chars_in_buffer(struct tty_struct *tty)
1168{
55b307da 1169 struct mxser_port *info = tty->driver_data;
925e9c1c 1170 return info->xmit_cnt;
037ad48b
JS		 1171}
1172
1173static void mxser_flush_buffer(struct tty_struct *tty)
1174{
55b307da 1175 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1176 char fcr;
1177 unsigned long flags;
1178
1179
1180 spin_lock_irqsave(&info->slock, flags);
1181 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1182
55b307da 1183 fcr = inb(info->ioaddr + UART_FCR);
037ad48b 1184 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
55b307da
JS		 1185 info->ioaddr + UART_FCR);
1186 outb(fcr, info->ioaddr + UART_FCR);
037ad48b
JS		 1187
1188 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 1189
7e8bcf9a 1190 tty_wakeup(tty);
037ad48b
JS		 1191}
1192
a8dea4ec
JS		 1193/*
1194 * ------------------------------------------------------------
1195 * friends of mxser_ioctl()
1196 * ------------------------------------------------------------
1197 */
1198static int mxser_get_serial_info(struct mxser_port *info,
1199 struct serial_struct __user *retinfo)
037ad48b 1200{
a8dea4ec 1201 struct serial_struct tmp;
037ad48b 1202
a8dea4ec
JS		 1203 if (!retinfo)
1204 return -EFAULT;
1205 memset(&tmp, 0, sizeof(tmp));
1206 tmp.type = info->type;
1207 tmp.line = info->tty->index;
1208 tmp.port = info->ioaddr;
1209 tmp.irq = info->board->irq;
1210 tmp.flags = info->flags;
1211 tmp.baud_base = info->baud_base;
1212 tmp.close_delay = info->close_delay;
1213 tmp.closing_wait = info->closing_wait;
1214 tmp.custom_divisor = info->custom_divisor;
1215 tmp.hub6 = 0;
1216 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1217 return -EFAULT;
1218 return 0;
1219}
037ad48b 1220
a8dea4ec
JS		 1221static int mxser_set_serial_info(struct mxser_port *info,
1222 struct serial_struct __user *new_info)
1223{
1224 struct serial_struct new_serial;
f64c84a1 1225 unsigned long sl_flags;
a8dea4ec
JS		 1226 unsigned int flags;
1227 int retval = 0;
037ad48b 1228
a8dea4ec
JS		 1229 if (!new_info || !info->ioaddr)
1230 return -EFAULT;
1231 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1232 return -EFAULT;
037ad48b 1233
a8dea4ec
JS		 1234 if ((new_serial.irq != info->board->irq) ||
1235 (new_serial.port != info->ioaddr) ||
1236 (new_serial.custom_divisor != info->custom_divisor) ||
1237 (new_serial.baud_base != info->baud_base))
1238 return -EPERM;
037ad48b 1239
a8dea4ec
JS		 1240 flags = info->flags & ASYNC_SPD_MASK;
1241
1242 if (!capable(CAP_SYS_ADMIN)) {
1243 if ((new_serial.baud_base != info->baud_base) ||
1244 (new_serial.close_delay != info->close_delay) ||
1245 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK)))
1246 return -EPERM;
1247 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
1248 (new_serial.flags & ASYNC_USR_MASK));
1249 } else {
037ad48b 1250 /*
a8dea4ec
JS		 1251 * OK, past this point, all the error checking has been done.
1252 * At this point, we start making changes.....
037ad48b 1253 */
a8dea4ec
JS		 1254 info->flags = ((info->flags & ~ASYNC_FLAGS) |
1255 (new_serial.flags & ASYNC_FLAGS));
1256 info->close_delay = new_serial.close_delay * HZ / 100;
1257 info->closing_wait = new_serial.closing_wait * HZ / 100;
1258 info->tty->low_latency =
1259 (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
e079f495 1260 info->tty->low_latency = 0;
a8dea4ec 1261 }
037ad48b 1262
a8dea4ec 1263 info->type = new_serial.type;
037ad48b 1264
a8dea4ec
JS		 1265 process_txrx_fifo(info);
1266
1267 if (info->flags & ASYNC_INITIALIZED) {
f64c84a1
JS		 1268 if (flags != (info->flags & ASYNC_SPD_MASK)) {
1269 spin_lock_irqsave(&info->slock, sl_flags);
a8dea4ec 1270 mxser_change_speed(info, NULL);
f64c84a1
JS		 1271 spin_unlock_irqrestore(&info->slock, sl_flags);
1272 }
a8dea4ec
JS		 1273 } else
1274 retval = mxser_startup(info);
1275
1276 return retval;
1277}
037ad48b 1278
a8dea4ec
JS		 1279/*
1280 * mxser_get_lsr_info - get line status register info
1281 *
1282 * Purpose: Let user call ioctl() to get info when the UART physically
1283 * is emptied. On bus types like RS485, the transmitter must
1284 * release the bus after transmitting. This must be done when
1285 * the transmit shift register is empty, not be done when the
1286 * transmit holding register is empty. This functionality
1287 * allows an RS485 driver to be written in user space.
1288 */
1289static int mxser_get_lsr_info(struct mxser_port *info,
1290 unsigned int __user *value)
1291{
1292 unsigned char status;
1293 unsigned int result;
1294 unsigned long flags;
037ad48b 1295
a8dea4ec
JS		 1296 spin_lock_irqsave(&info->slock, flags);
1297 status = inb(info->ioaddr + UART_LSR);
1298 spin_unlock_irqrestore(&info->slock, flags);
1299 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1300 return put_user(result, value);
1301}
037ad48b 1302
a8dea4ec
JS		 1303/*
1304 * This routine sends a break character out the serial port.
1305 */
1306static void mxser_send_break(struct mxser_port *info, int duration)
1307{
1308 unsigned long flags;
037ad48b 1309
a8dea4ec
JS		 1310 if (!info->ioaddr)
1311 return;
1312 set_current_state(TASK_INTERRUPTIBLE);
1313 spin_lock_irqsave(&info->slock, flags);
1314 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
1315 info->ioaddr + UART_LCR);
1316 spin_unlock_irqrestore(&info->slock, flags);
1317 schedule_timeout(duration);
1318 spin_lock_irqsave(&info->slock, flags);
1319 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
1320 info->ioaddr + UART_LCR);
1321 spin_unlock_irqrestore(&info->slock, flags);
1322}
037ad48b 1323
a8dea4ec
JS		 1324static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
1325{
1326 struct mxser_port *info = tty->driver_data;
1327 unsigned char control, status;
1328 unsigned long flags;
037ad48b 1329
037ad48b 1330
a8dea4ec
JS		 1331 if (tty->index == MXSER_PORTS)
1332 return -ENOIOCTLCMD;
214efebb 1333 if (test_bit(TTY_IO_ERROR, &tty->flags))
a8dea4ec 1334 return -EIO;
037ad48b 1335
a8dea4ec 1336 control = info->MCR;
037ad48b 1337
a8dea4ec
JS		 1338 spin_lock_irqsave(&info->slock, flags);
1339 status = inb(info->ioaddr + UART_MSR);
1340 if (status & UART_MSR_ANY_DELTA)
1341 mxser_check_modem_status(info, status);
1342 spin_unlock_irqrestore(&info->slock, flags);
1343 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1344 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1345 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1346 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1347 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1348 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1349}
037ad48b 1350
a8dea4ec
JS		 1351static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1352 unsigned int set, unsigned int clear)
1353{
1354 struct mxser_port *info = tty->driver_data;
1355 unsigned long flags;
037ad48b 1356
037ad48b 1357
a8dea4ec
JS		 1358 if (tty->index == MXSER_PORTS)
1359 return -ENOIOCTLCMD;
214efebb 1360 if (test_bit(TTY_IO_ERROR, &tty->flags))
a8dea4ec 1361 return -EIO;
037ad48b 1362
a8dea4ec 1363 spin_lock_irqsave(&info->slock, flags);
037ad48b 1364
a8dea4ec
JS		 1365 if (set & TIOCM_RTS)
1366 info->MCR |= UART_MCR_RTS;
1367 if (set & TIOCM_DTR)
1368 info->MCR |= UART_MCR_DTR;
037ad48b 1369
a8dea4ec
JS		 1370 if (clear & TIOCM_RTS)
1371 info->MCR &= ~UART_MCR_RTS;
1372 if (clear & TIOCM_DTR)
1373 info->MCR &= ~UART_MCR_DTR;
037ad48b 1374
a8dea4ec
JS		 1375 outb(info->MCR, info->ioaddr + UART_MCR);
1376 spin_unlock_irqrestore(&info->slock, flags);
037ad48b
JS		 1377 return 0;
1378}
1379
c76b0930 1380static int __init mxser_program_mode(int port)
037ad48b 1381{
a8dea4ec 1382 int id, i, j, n;
037ad48b 1383
a8dea4ec
JS		 1384 outb(0, port);
1385 outb(0, port);
1386 outb(0, port);
1387 (void)inb(port);
1388 (void)inb(port);
1389 outb(0, port);
1390 (void)inb(port);
037ad48b 1391
a8dea4ec
JS		 1392 id = inb(port + 1) & 0x1F;
1393 if ((id != C168_ASIC_ID) &&
1394 (id != C104_ASIC_ID) &&
1395 (id != C102_ASIC_ID) &&
1396 (id != CI132_ASIC_ID) &&
1397 (id != CI134_ASIC_ID) &&
1398 (id != CI104J_ASIC_ID))
1399 return -1;
1400 for (i = 0, j = 0; i < 4; i++) {
1401 n = inb(port + 2);
1402 if (n == 'M') {
1403 j = 1;
1404 } else if ((j == 1) && (n == 1)) {
1405 j = 2;
1406 break;
1407 } else
1408 j = 0;
1409 }
1410 if (j != 2)
1411 id = -2;
1412 return id;
1413}
1414
c76b0930 1415static void __init mxser_normal_mode(int port)
a8dea4ec
JS		 1416{
1417 int i, n;
1418
1419 outb(0xA5, port + 1);
1420 outb(0x80, port + 3);
1421 outb(12, port + 0); /* 9600 bps */
1422 outb(0, port + 1);
1423 outb(0x03, port + 3); /* 8 data bits */
1424 outb(0x13, port + 4); /* loop back mode */
1425 for (i = 0; i < 16; i++) {
1426 n = inb(port + 5);
1427 if ((n & 0x61) == 0x60)
1428 break;
1429 if ((n & 1) == 1)
1430 (void)inb(port);
1431 }
1432 outb(0x00, port + 4);
1433}
1434
1435#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1436#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1437#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1438#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1439#define EN_CCMD 0x000 /* Chip's command register */
1440#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1441#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1442#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1443#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1444#define EN0_DCFG 0x00E /* Data configuration reg WR */
1445#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1446#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1447#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
c76b0930 1448static int __init mxser_read_register(int port, unsigned short *regs)
a8dea4ec
JS		 1449{
1450 int i, k, value, id;
1451 unsigned int j;
1452
1453 id = mxser_program_mode(port);
1454 if (id < 0)
1455 return id;
1456 for (i = 0; i < 14; i++) {
1457 k = (i & 0x3F) | 0x180;
1458 for (j = 0x100; j > 0; j >>= 1) {
1459 outb(CHIP_CS, port);
1460 if (k & j) {
1461 outb(CHIP_CS | CHIP_DO, port);
1462 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1463 } else {
1464 outb(CHIP_CS, port);
1465 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1466 }
1467 }
1468 (void)inb(port);
1469 value = 0;
1470 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1471 outb(CHIP_CS, port);
1472 outb(CHIP_CS | CHIP_SK, port);
1473 if (inb(port) & CHIP_DI)
1474 value |= j;
1475 }
1476 regs[i] = value;
1477 outb(0, port);
1478 }
1479 mxser_normal_mode(port);
1480 return id;
1481}
1482
a8dea4ec
JS		 1483static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1484{
1485 struct mxser_port *port;
1486 int result, status;
1487 unsigned int i, j;
1488
1489 switch (cmd) {
1490 case MOXA_GET_CONF:
1491/* if (copy_to_user(argp, mxsercfg,
1492 sizeof(struct mxser_hwconf) * 4))
1493 return -EFAULT;
1494 return 0;*/
1495 return -ENXIO;
1496 case MOXA_GET_MAJOR:
1497 if (copy_to_user(argp, &ttymajor, sizeof(int)))
1498 return -EFAULT;
1499 return 0;
1500
1501 case MOXA_GET_CUMAJOR:
1502 if (copy_to_user(argp, &calloutmajor, sizeof(int)))
037ad48b
JS		 1503 return -EFAULT;
1504 return 0;
1505
1506 case MOXA_CHKPORTENABLE:
1507 result = 0;
55b307da
JS		 1508
1509 for (i = 0; i < MXSER_BOARDS; i++)
1510 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1511 if (mxser_boards[i].ports[j].ioaddr)
1512 result |= (1 << i);
1513
037ad48b
JS		 1514 return put_user(result, (unsigned long __user *)argp);
1515 case MOXA_GETDATACOUNT:
1516 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1517 return -EFAULT;
1518 return 0;
1519 case MOXA_GETMSTATUS:
55b307da
JS		 1520 for (i = 0; i < MXSER_BOARDS; i++)
1521 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1522 port = &mxser_boards[i].ports[j];
1523
1524 GMStatus[i].ri = 0;
1525 if (!port->ioaddr) {
1526 GMStatus[i].dcd = 0;
1527 GMStatus[i].dsr = 0;
1528 GMStatus[i].cts = 0;
1529 continue;
1530 }
037ad48b 1531
55b307da
JS		 1532 if (!port->tty || !port->tty->termios)
1533 GMStatus[i].cflag =
1534 port->normal_termios.c_cflag;
1535 else
1536 GMStatus[i].cflag =
1537 port->tty->termios->c_cflag;
037ad48b 1538
55b307da
JS		 1539 status = inb(port->ioaddr + UART_MSR);
1540 if (status & 0x80 /*UART_MSR_DCD */ )
1541 GMStatus[i].dcd = 1;
1542 else
1543 GMStatus[i].dcd = 0;
037ad48b 1544
55b307da
JS		 1545 if (status & 0x20 /*UART_MSR_DSR */ )
1546 GMStatus[i].dsr = 1;
1547 else
1548 GMStatus[i].dsr = 0;
037ad48b
JS		 1549
1550
55b307da
JS		 1551 if (status & 0x10 /*UART_MSR_CTS */ )
1552 GMStatus[i].cts = 1;
1553 else
1554 GMStatus[i].cts = 0;
1555 }
037ad48b
JS		 1556 if (copy_to_user(argp, GMStatus,
1557 sizeof(struct mxser_mstatus) * MXSER_PORTS))
1558 return -EFAULT;
1559 return 0;
1560 case MOXA_ASPP_MON_EXT: {
2b770b4b 1561 int p, shiftbit;
55b307da
JS		 1562 unsigned long opmode;
1563 unsigned cflag, iflag;
037ad48b 1564
55b307da
JS		 1565 for (i = 0; i < MXSER_BOARDS; i++)
1566 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1567 port = &mxser_boards[i].ports[j];
1568 if (!port->ioaddr)
037ad48b
JS		 1569 continue;
1570
55b307da 1571 status = mxser_get_msr(port->ioaddr, 0, i);
55b307da 1572
037ad48b 1573 if (status & UART_MSR_TERI)
55b307da 1574 port->icount.rng++;
037ad48b 1575 if (status & UART_MSR_DDSR)
55b307da 1576 port->icount.dsr++;
037ad48b 1577 if (status & UART_MSR_DDCD)
55b307da 1578 port->icount.dcd++;
037ad48b 1579 if (status & UART_MSR_DCTS)
55b307da
JS		 1580 port->icount.cts++;
1581
1582 port->mon_data.modem_status = status;
1583 mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt;
1584 mon_data_ext.tx_cnt[i] = port->mon_data.txcnt;
1585 mon_data_ext.up_rxcnt[i] =
1586 port->mon_data.up_rxcnt;
1587 mon_data_ext.up_txcnt[i] =
1588 port->mon_data.up_txcnt;
1589 mon_data_ext.modem_status[i] =
1590 port->mon_data.modem_status;
1591 mon_data_ext.baudrate[i] = port->realbaud;
1592
1593 if (!port->tty || !port->tty->termios) {
1594 cflag = port->normal_termios.c_cflag;
1595 iflag = port->normal_termios.c_iflag;
037ad48b 1596 } else {
55b307da
JS		 1597 cflag = port->tty->termios->c_cflag;
1598 iflag = port->tty->termios->c_iflag;
037ad48b
JS		 1599 }
1600
1601 mon_data_ext.databits[i] = cflag & CSIZE;
1602
1603 mon_data_ext.stopbits[i] = cflag & CSTOPB;
1604
55b307da
JS		 1605 mon_data_ext.parity[i] =
1606 cflag & (PARENB | PARODD | CMSPAR);
037ad48b
JS		 1607
1608 mon_data_ext.flowctrl[i] = 0x00;
1609
1610 if (cflag & CRTSCTS)
1611 mon_data_ext.flowctrl[i] |= 0x03;
1612
1613 if (iflag & (IXON | IXOFF))
1614 mon_data_ext.flowctrl[i] |= 0x0C;
1615
55b307da 1616 if (port->type == PORT_16550A)
037ad48b
JS		 1617 mon_data_ext.fifo[i] = 1;
1618 else
1619 mon_data_ext.fifo[i] = 0;
1620
1621 p = i % 4;
1622 shiftbit = p * 2;
55b307da 1623 opmode = inb(port->opmode_ioaddr) >> shiftbit;
037ad48b
JS		 1624 opmode &= OP_MODE_MASK;
1625
1626 mon_data_ext.iftype[i] = opmode;
1627
1628 }
55b307da
JS		 1629 if (copy_to_user(argp, &mon_data_ext,
1630 sizeof(mon_data_ext)))
037ad48b
JS		 1631 return -EFAULT;
1632
1633 return 0;
1634
55b307da 1635 } default:
037ad48b
JS		 1636 return -ENOIOCTLCMD;
1637 }
1638 return 0;
1639}
1640
a8dea4ec
JS		 1641static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1642 unsigned int cmd, unsigned long arg)
037ad48b 1643{
55b307da 1644 struct mxser_port *info = tty->driver_data;
a8dea4ec
JS		 1645 struct async_icount cprev, cnow; /* kernel counter temps */
1646 struct serial_icounter_struct __user *p_cuser;
1647 unsigned long templ;
1648 unsigned long flags;
f64c84a1 1649 unsigned int i;
a8dea4ec
JS		 1650 void __user *argp = (void __user *)arg;
1651 int retval;
037ad48b 1652
a8dea4ec
JS		 1653 if (tty->index == MXSER_PORTS)
1654 return mxser_ioctl_special(cmd, argp);
1655
a8dea4ec
JS		 1656 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1657 int p;
1658 unsigned long opmode;
1659 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1660 int shiftbit;
1661 unsigned char val, mask;
1662
1663 p = tty->index % 4;
1664 if (cmd == MOXA_SET_OP_MODE) {
1665 if (get_user(opmode, (int __user *) argp))
1666 return -EFAULT;
1667 if (opmode != RS232_MODE &&
1668 opmode != RS485_2WIRE_MODE &&
1669 opmode != RS422_MODE &&
1670 opmode != RS485_4WIRE_MODE)
1671 return -EFAULT;
1672 mask = ModeMask[p];
1673 shiftbit = p * 2;
1674 val = inb(info->opmode_ioaddr);
1675 val &= mask;
1676 val |= (opmode << shiftbit);
1677 outb(val, info->opmode_ioaddr);
1678 } else {
1679 shiftbit = p * 2;
1680 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1681 opmode &= OP_MODE_MASK;
1682 if (copy_to_user(argp, &opmode, sizeof(int)))
1683 return -EFAULT;
3306ce3d 1684 }
a8dea4ec 1685 return 0;
037ad48b
JS		 1686 }
1687
f64c84a1
JS		 1688 if (cmd == MOXA_SET_SPECIAL_BAUD_RATE) {
1689 int speed;
1690
1691 if (get_user(speed, (int __user *)argp))
1692 return -EFAULT;
1693 if (speed <= 0 || speed > info->max_baud)
1694 return -EFAULT;
1695 if (!info->tty || !info->tty->termios || !info->ioaddr)
1696 return 0;
1697 info->tty->termios->c_cflag &= ~(CBAUD | CBAUDEX);
1698 for (i = 0; i < BAUD_TABLE_NO; i++)
1699 if (speed == mxvar_baud_table[i])
1700 break;
1701 if (i == BAUD_TABLE_NO) {
1702 info->tty->termios->c_cflag |= B_SPEC;
1703 } else if (speed != 0)
1704 info->tty->termios->c_cflag |= mxvar_baud_table1[i];
1705
1706 info->speed = speed;
1707 spin_lock_irqsave(&info->slock, flags);
a136e99f 1708 mxser_change_speed(info, NULL);
f64c84a1
JS		 1709 spin_unlock_irqrestore(&info->slock, flags);
1710
1711 return 0;
1712 } else if (cmd == MOXA_GET_SPECIAL_BAUD_RATE) {
1713 if (copy_to_user(argp, &info->speed, sizeof(int)))
1714 return -EFAULT;
1715 return 0;
1716 }
1717
214efebb
JS		 1718 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT &&
1719 test_bit(TTY_IO_ERROR, &tty->flags))
1720 return -EIO;
1721
a8dea4ec
JS		 1722 switch (cmd) {
1723 case TCSBRK: /* SVID version: non-zero arg --> no break */
1724 retval = tty_check_change(tty);
1725 if (retval)
1726 return retval;
1727 tty_wait_until_sent(tty, 0);
1728 if (!arg)
1729 mxser_send_break(info, HZ / 4); /* 1/4 second */
1730 return 0;
1731 case TCSBRKP: /* support for POSIX tcsendbreak() */
1732 retval = tty_check_change(tty);
1733 if (retval)
1734 return retval;
1735 tty_wait_until_sent(tty, 0);
1736 mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4);
1737 return 0;
1738 case TIOCGSOFTCAR:
1739 return put_user(C_CLOCAL(tty) ? 1 : 0, (unsigned long __user *)argp);
1740 case TIOCSSOFTCAR:
1741 if (get_user(templ, (unsigned long __user *) argp))
1742 return -EFAULT;
1743 arg = templ;
1744 tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0));
1745 return 0;
1746 case TIOCGSERIAL:
1747 return mxser_get_serial_info(info, argp);
1748 case TIOCSSERIAL:
1749 return mxser_set_serial_info(info, argp);
1750 case TIOCSERGETLSR: /* Get line status register */
1751 return mxser_get_lsr_info(info, argp);
1752 /*
1753 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1754 * - mask passed in arg for lines of interest
1755 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1756 * Caller should use TIOCGICOUNT to see which one it was
1757 */
b446a4a5 1758 case TIOCMIWAIT:
a8dea4ec 1759 spin_lock_irqsave(&info->slock, flags);
b446a4a5 1760 cnow = info->icount; /* note the counters on entry */
a8dea4ec 1761 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 1762
b446a4a5
JS		 1763 wait_event_interruptible(info->delta_msr_wait, ({
1764 cprev = cnow;
a8dea4ec
JS		 1765 spin_lock_irqsave(&info->slock, flags);
1766 cnow = info->icount; /* atomic copy */
1767 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 1768
b446a4a5
JS		 1769 ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
1770 ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
1771 ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
1772 ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts));
1773 }));
a8dea4ec 1774 break;
a8dea4ec
JS		 1775 /*
1776 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1777 * Return: write counters to the user passed counter struct
1778 * NB: both 1->0 and 0->1 transitions are counted except for
1779 * RI where only 0->1 is counted.
1780 */
1781 case TIOCGICOUNT:
1782 spin_lock_irqsave(&info->slock, flags);
1783 cnow = info->icount;
1784 spin_unlock_irqrestore(&info->slock, flags);
1785 p_cuser = argp;
a8dea4ec
JS		 1786 if (put_user(cnow.frame, &p_cuser->frame))
1787 return -EFAULT;
1788 if (put_user(cnow.brk, &p_cuser->brk))
1789 return -EFAULT;
1790 if (put_user(cnow.overrun, &p_cuser->overrun))
1791 return -EFAULT;
1792 if (put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1793 return -EFAULT;
1794 if (put_user(cnow.parity, &p_cuser->parity))
1795 return -EFAULT;
1796 if (put_user(cnow.rx, &p_cuser->rx))
1797 return -EFAULT;
1798 if (put_user(cnow.tx, &p_cuser->tx))
1799 return -EFAULT;
1800 put_user(cnow.cts, &p_cuser->cts);
1801 put_user(cnow.dsr, &p_cuser->dsr);
1802 put_user(cnow.rng, &p_cuser->rng);
1803 put_user(cnow.dcd, &p_cuser->dcd);
1804 return 0;
1805 case MOXA_HighSpeedOn:
1806 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1807 case MOXA_SDS_RSTICOUNTER:
1808 info->mon_data.rxcnt = 0;
1809 info->mon_data.txcnt = 0;
1810 return 0;
a8dea4ec
JS		 1811 case MOXA_ASPP_SETBAUD:{
1812 long baud;
1813 if (get_user(baud, (long __user *)argp))
1814 return -EFAULT;
f64c84a1 1815 spin_lock_irqsave(&info->slock, flags);
a8dea4ec 1816 mxser_set_baud(info, baud);
f64c84a1 1817 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec
JS		 1818 return 0;
1819 }
1820 case MOXA_ASPP_GETBAUD:
1821 if (copy_to_user(argp, &info->realbaud, sizeof(long)))
1822 return -EFAULT;
037ad48b 1823
a8dea4ec 1824 return 0;
037ad48b 1825
a8dea4ec
JS		 1826 case MOXA_ASPP_OQUEUE:{
1827 int len, lsr;
037ad48b 1828
a8dea4ec
JS		 1829 len = mxser_chars_in_buffer(tty);
1830
1831 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT;
1832
1833 len += (lsr ? 0 : 1);
1834
1835 if (copy_to_user(argp, &len, sizeof(int)))
1836 return -EFAULT;
1837
1838 return 0;
037ad48b 1839 }
a8dea4ec
JS		 1840 case MOXA_ASPP_MON: {
1841 int mcr, status;
037ad48b 1842
a8dea4ec
JS		 1843 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1844 mxser_check_modem_status(info, status);
1845
1846 mcr = inb(info->ioaddr + UART_MCR);
1847 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1848 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1849 else
1850 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1851
1852 if (mcr & MOXA_MUST_MCR_TX_XON)
1853 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1854 else
1855 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1856
1857 if (info->tty->hw_stopped)
1858 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1859 else
1860 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1861
1862 if (copy_to_user(argp, &info->mon_data,
1863 sizeof(struct mxser_mon)))
1864 return -EFAULT;
1865
1866 return 0;
1867 }
1868 case MOXA_ASPP_LSTATUS: {
1869 if (copy_to_user(argp, &info->err_shadow,
1870 sizeof(unsigned char)))
1871 return -EFAULT;
1872
1873 info->err_shadow = 0;
1874 return 0;
1875 }
1876 case MOXA_SET_BAUD_METHOD: {
1877 int method;
1878
1879 if (get_user(method, (int __user *)argp))
1880 return -EFAULT;
1881 mxser_set_baud_method[tty->index] = method;
1882 if (copy_to_user(argp, &method, sizeof(int)))
1883 return -EFAULT;
1884
1885 return 0;
1886 }
1887 default:
1888 return -ENOIOCTLCMD;
1889 }
1890 return 0;
1891}
1892
1893static void mxser_stoprx(struct tty_struct *tty)
1894{
1895 struct mxser_port *info = tty->driver_data;
037ad48b 1896
a8dea4ec
JS		 1897 info->ldisc_stop_rx = 1;
1898 if (I_IXOFF(tty)) {
55b307da 1899 if (info->board->chip_flag) {
a8dea4ec
JS		 1900 info->IER &= ~MOXA_MUST_RECV_ISR;
1901 outb(info->IER, info->ioaddr + UART_IER);
925e9c1c 1902 } else {
a8dea4ec
JS		 1903 info->x_char = STOP_CHAR(tty);
1904 outb(0, info->ioaddr + UART_IER);
1905 info->IER |= UART_IER_THRI;
1906 outb(info->IER, info->ioaddr + UART_IER);
037ad48b 1907 }
a8dea4ec 1908 }
037ad48b 1909
a8dea4ec
JS		 1910 if (info->tty->termios->c_cflag & CRTSCTS) {
1911 info->MCR &= ~UART_MCR_RTS;
1912 outb(info->MCR, info->ioaddr + UART_MCR);
1913 }
1914}
1915
1916/*
1917 * This routine is called by the upper-layer tty layer to signal that
1918 * incoming characters should be throttled.
1919 */
1920static void mxser_throttle(struct tty_struct *tty)
1921{
1922 mxser_stoprx(tty);
1923}
1924
1925static void mxser_unthrottle(struct tty_struct *tty)
1926{
1927 struct mxser_port *info = tty->driver_data;
1928
1929 /* startrx */
1930 info->ldisc_stop_rx = 0;
1931 if (I_IXOFF(tty)) {
1932 if (info->x_char)
1933 info->x_char = 0;
1934 else {
a8dea4ec
JS		 1935 if (info->board->chip_flag) {
1936 info->IER |= MOXA_MUST_RECV_ISR;
1937 outb(info->IER, info->ioaddr + UART_IER);
925e9c1c 1938 } else {
a8dea4ec
JS		 1939 info->x_char = START_CHAR(tty);
1940 outb(0, info->ioaddr + UART_IER);
1941 info->IER |= UART_IER_THRI;
1942 outb(info->IER, info->ioaddr + UART_IER);
1943 }
1944 }
1945 }
1946
1947 if (info->tty->termios->c_cflag & CRTSCTS) {
1948 info->MCR |= UART_MCR_RTS;
1949 outb(info->MCR, info->ioaddr + UART_MCR);
037ad48b
JS		 1950 }
1951}
1952
1953/*
1954 * mxser_stop() and mxser_start()
1955 *
1956 * This routines are called before setting or resetting tty->stopped.
1957 * They enable or disable transmitter interrupts, as necessary.
1958 */
1959static void mxser_stop(struct tty_struct *tty)
1960{
55b307da 1961 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1962 unsigned long flags;
1963
1964 spin_lock_irqsave(&info->slock, flags);
1965 if (info->IER & UART_IER_THRI) {
1966 info->IER &= ~UART_IER_THRI;
55b307da 1967 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1968 }
1969 spin_unlock_irqrestore(&info->slock, flags);
1970}
1971
1972static void mxser_start(struct tty_struct *tty)
1973{
55b307da 1974 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1975 unsigned long flags;
1976
1977 spin_lock_irqsave(&info->slock, flags);
e079f495 1978 if (info->xmit_cnt && info->xmit_buf) {
55b307da 1979 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
037ad48b 1980 info->IER |= UART_IER_THRI;
55b307da 1981 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1982 }
1983 spin_unlock_irqrestore(&info->slock, flags);
1984}
1985
606d099c 1986static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
a8dea4ec
JS		 1987{
1988 struct mxser_port *info = tty->driver_data;
1989 unsigned long flags;
1990
7e7d136e
AC		 1991 spin_lock_irqsave(&info->slock, flags);
1992 mxser_change_speed(info, old_termios);
1993 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec 1994
7e7d136e
AC		 1995 if ((old_termios->c_cflag & CRTSCTS) &&
1996 !(tty->termios->c_cflag & CRTSCTS)) {
1997 tty->hw_stopped = 0;
1998 mxser_start(tty);
a8dea4ec
JS		 1999 }
2000
e079f495 2001 /* Handle sw stopped */
a8dea4ec
JS		 2002 if ((old_termios->c_iflag & IXON) &&
2003 !(tty->termios->c_iflag & IXON)) {
2004 tty->stopped = 0;
2005
a8dea4ec
JS		 2006 if (info->board->chip_flag) {
2007 spin_lock_irqsave(&info->slock, flags);
2008 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
2009 spin_unlock_irqrestore(&info->slock, flags);
2010 }
a8dea4ec
JS		 2011
2012 mxser_start(tty);
2013 }
2014}
2015
037ad48b
JS		 2016/*
2017 * mxser_wait_until_sent() --- wait until the transmitter is empty
2018 */
2019static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
2020{
55b307da 2021 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 2022 unsigned long orig_jiffies, char_time;
2023 int lsr;
2024
2025 if (info->type == PORT_UNKNOWN)
2026 return;
2027
2028 if (info->xmit_fifo_size == 0)
2029 return; /* Just in case.... */
2030
2031 orig_jiffies = jiffies;
2032 /*
2033 * Set the check interval to be 1/5 of the estimated time to
2034 * send a single character, and make it at least 1. The check
2035 * interval should also be less than the timeout.
2036 *
2037 * Note: we have to use pretty tight timings here to satisfy
2038 * the NIST-PCTS.
2039 */
2040 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
2041 char_time = char_time / 5;
2042 if (char_time == 0)
2043 char_time = 1;
2044 if (timeout && timeout < char_time)
2045 char_time = timeout;
2046 /*
2047 * If the transmitter hasn't cleared in twice the approximate
2048 * amount of time to send the entire FIFO, it probably won't
2049 * ever clear. This assumes the UART isn't doing flow
2050 * control, which is currently the case. Hence, if it ever
2051 * takes longer than info->timeout, this is probably due to a
2052 * UART bug of some kind. So, we clamp the timeout parameter at
2053 * 2*info->timeout.
2054 */
2055 if (!timeout || timeout > 2 * info->timeout)
2056 timeout = 2 * info->timeout;
2057#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2058 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
2059 timeout, char_time);
2060 printk("jiff=%lu...", jiffies);
2061#endif
55b307da 2062 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
037ad48b
JS		 2063#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2064 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
2065#endif
2066 schedule_timeout_interruptible(char_time);
2067 if (signal_pending(current))
2068 break;
2069 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2070 break;
2071 }
2072 set_current_state(TASK_RUNNING);
2073
2074#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2075 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
a8dea4ec
JS		 2076#endif
2077}
037ad48b 2078
a8dea4ec
JS		 2079/*
2080 * This routine is called by tty_hangup() when a hangup is signaled.
2081 */
02d3fca0 2082static void mxser_hangup(struct tty_struct *tty)
a8dea4ec
JS		 2083{
2084 struct mxser_port *info = tty->driver_data;
037ad48b 2085
a8dea4ec
JS		 2086 mxser_flush_buffer(tty);
2087 mxser_shutdown(info);
2088 info->event = 0;
2089 info->count = 0;
2090 info->flags &= ~ASYNC_NORMAL_ACTIVE;
2091 info->tty = NULL;
2092 wake_up_interruptible(&info->open_wait);
037ad48b
JS		 2093}
2094
a8dea4ec
JS		 2095/*
2096 * mxser_rs_break() --- routine which turns the break handling on or off
2097 */
2098static void mxser_rs_break(struct tty_struct *tty, int break_state)
037ad48b 2099{
a8dea4ec 2100 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 2101 unsigned long flags;
2102
a8dea4ec
JS		 2103 spin_lock_irqsave(&info->slock, flags);
2104 if (break_state == -1)
2105 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2106 info->ioaddr + UART_LCR);
2107 else
2108 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2109 info->ioaddr + UART_LCR);
2110 spin_unlock_irqrestore(&info->slock, flags);
2111}
037ad48b 2112
a8dea4ec
JS		 2113static void mxser_receive_chars(struct mxser_port *port, int *status)
2114{
2115 struct tty_struct *tty = port->tty;
2116 unsigned char ch, gdl;
2117 int ignored = 0;
2118 int cnt = 0;
2119 int recv_room;
2120 int max = 256;
a8dea4ec
JS		 2121
2122 recv_room = tty->receive_room;
e079f495 2123 if ((recv_room == 0) && (!port->ldisc_stop_rx))
a8dea4ec 2124 mxser_stoprx(tty);
037ad48b 2125
a8dea4ec 2126 if (port->board->chip_flag != MOXA_OTHER_UART) {
037ad48b 2127
a8dea4ec
JS		 2128 if (*status & UART_LSR_SPECIAL)
2129 goto intr_old;
a8dea4ec
JS		 2130 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2131 (*status & MOXA_MUST_LSR_RERR))
2132 goto intr_old;
a8dea4ec
JS		 2133 if (*status & MOXA_MUST_LSR_RERR)
2134 goto intr_old;
2135
2136 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2137
a8dea4ec
JS		 2138 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2139 gdl &= MOXA_MUST_GDL_MASK;
2140 if (gdl >= recv_room) {
e079f495 2141 if (!port->ldisc_stop_rx)
a8dea4ec 2142 mxser_stoprx(tty);
a8dea4ec
JS		 2143 }
2144 while (gdl--) {
2145 ch = inb(port->ioaddr + UART_RX);
2146 tty_insert_flip_char(tty, ch, 0);
2147 cnt++;
2148 }
2149 goto end_intr;
037ad48b 2150 }
e079f495 2151intr_old:
037ad48b 2152
a8dea4ec
JS		 2153 do {
2154 if (max-- < 0)
2155 break;
037ad48b 2156
a8dea4ec 2157 ch = inb(port->ioaddr + UART_RX);
e079f495 2158 if (port->board->chip_flag && (*status & UART_LSR_OE))
a8dea4ec
JS		 2159 outb(0x23, port->ioaddr + UART_FCR);
2160 *status &= port->read_status_mask;
a8dea4ec
JS		 2161 if (*status & port->ignore_status_mask) {
2162 if (++ignored > 100)
2163 break;
2164 } else {
2165 char flag = 0;
2166 if (*status & UART_LSR_SPECIAL) {
2167 if (*status & UART_LSR_BI) {
2168 flag = TTY_BREAK;
a8dea4ec 2169 port->icount.brk++;
037ad48b 2170
a8dea4ec
JS		 2171 if (port->flags & ASYNC_SAK)
2172 do_SAK(tty);
2173 } else if (*status & UART_LSR_PE) {
2174 flag = TTY_PARITY;
a8dea4ec
JS		 2175 port->icount.parity++;
2176 } else if (*status & UART_LSR_FE) {
2177 flag = TTY_FRAME;
a8dea4ec
JS		 2178 port->icount.frame++;
2179 } else if (*status & UART_LSR_OE) {
2180 flag = TTY_OVERRUN;
a8dea4ec 2181 port->icount.overrun++;
f64c84a1
JS		 2182 } else
2183 flag = TTY_BREAK;
925e9c1c 2184 }
a8dea4ec
JS		 2185 tty_insert_flip_char(tty, ch, flag);
2186 cnt++;
2187 if (cnt >= recv_room) {
e079f495 2188 if (!port->ldisc_stop_rx)
a8dea4ec 2189 mxser_stoprx(tty);
a8dea4ec
JS		 2190 break;
2191 }
037ad48b 2192
a8dea4ec 2193 }
037ad48b 2194
a8dea4ec
JS		 2195 if (port->board->chip_flag)
2196 break;
037ad48b 2197
a8dea4ec 2198 *status = inb(port->ioaddr + UART_LSR);
a8dea4ec 2199 } while (*status & UART_LSR_DR);
037ad48b 2200
e079f495 2201end_intr:
a8dea4ec
JS		 2202 mxvar_log.rxcnt[port->tty->index] += cnt;
2203 port->mon_data.rxcnt += cnt;
2204 port->mon_data.up_rxcnt += cnt;
a8dea4ec 2205
67d2bc58
JYK		 2206 /*
2207 * We are called from an interrupt context with &port->slock
2208 * being held. Drop it temporarily in order to prevent
2209 * recursive locking.
2210 */
2211 spin_unlock(&port->slock);
a8dea4ec 2212 tty_flip_buffer_push(tty);
67d2bc58 2213 spin_lock(&port->slock);
037ad48b
JS		 2214}
2215
a8dea4ec 2216static void mxser_transmit_chars(struct mxser_port *port)
037ad48b 2217{
a8dea4ec 2218 int count, cnt;
037ad48b 2219
a8dea4ec
JS		 2220 if (port->x_char) {
2221 outb(port->x_char, port->ioaddr + UART_TX);
2222 port->x_char = 0;
2223 mxvar_log.txcnt[port->tty->index]++;
2224 port->mon_data.txcnt++;
2225 port->mon_data.up_txcnt++;
a8dea4ec 2226 port->icount.tx++;
f574874b 2227 return;
037ad48b
JS		 2228 }
2229
a8dea4ec 2230 if (port->xmit_buf == 0)
f574874b 2231 return;
037ad48b 2232
925e9c1c
JS		 2233 if ((port->xmit_cnt <= 0) || port->tty->stopped ||
2234 (port->tty->hw_stopped &&
a8dea4ec
JS		 2235 (port->type != PORT_16550A) &&
2236 (!port->board->chip_flag))) {
2237 port->IER &= ~UART_IER_THRI;
2238 outb(port->IER, port->ioaddr + UART_IER);
f574874b 2239 return;
a8dea4ec 2240 }
037ad48b 2241
a8dea4ec
JS		 2242 cnt = port->xmit_cnt;
2243 count = port->xmit_fifo_size;
2244 do {
2245 outb(port->xmit_buf[port->xmit_tail++],
2246 port->ioaddr + UART_TX);
2247 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2248 if (--port->xmit_cnt <= 0)
2249 break;
2250 } while (--count > 0);
2251 mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt);
55b307da 2252
a8dea4ec
JS		 2253 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2254 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
a8dea4ec 2255 port->icount.tx += (cnt - port->xmit_cnt);
037ad48b 2256
47c85c0d
JS		 2257 if (port->xmit_cnt < WAKEUP_CHARS)
2258 tty_wakeup(port->tty);
2259
a8dea4ec
JS		 2260 if (port->xmit_cnt <= 0) {
2261 port->IER &= ~UART_IER_THRI;
2262 outb(port->IER, port->ioaddr + UART_IER);
2263 }
037ad48b
JS		 2264}
2265
2266/*
a8dea4ec 2267 * This is the serial driver's generic interrupt routine
037ad48b 2268 */
b1d1c8dd 2269static irqreturn_t mxser_interrupt(int irq, void *dev_id)
037ad48b 2270{
a8dea4ec
JS		 2271 int status, iir, i;
2272 struct mxser_board *brd = NULL;
2273 struct mxser_port *port;
2274 int max, irqbits, bits, msr;
18b95576 2275 unsigned int int_cnt, pass_counter = 0;
a8dea4ec 2276 int handled = IRQ_NONE;
037ad48b 2277
a8dea4ec
JS		 2278 for (i = 0; i < MXSER_BOARDS; i++)
2279 if (dev_id == &mxser_boards[i]) {
2280 brd = dev_id;
2281 break;
2282 }
037ad48b 2283
a8dea4ec
JS		 2284 if (i == MXSER_BOARDS)
2285 goto irq_stop;
2286 if (brd == NULL)
2287 goto irq_stop;
cd7ed64e 2288 max = brd->info->nports;
18b95576 2289 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
a8dea4ec
JS		 2290 irqbits = inb(brd->vector) & brd->vector_mask;
2291 if (irqbits == brd->vector_mask)
2292 break;
037ad48b 2293
a8dea4ec
JS		 2294 handled = IRQ_HANDLED;
2295 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2296 if (irqbits == brd->vector_mask)
2297 break;
2298 if (bits & irqbits)
2299 continue;
2300 port = &brd->ports[i];
037ad48b 2301
a8dea4ec 2302 int_cnt = 0;
f574874b 2303 spin_lock(&port->slock);
a8dea4ec 2304 do {
a8dea4ec
JS		 2305 iir = inb(port->ioaddr + UART_IIR);
2306 if (iir & UART_IIR_NO_INT)
2307 break;
2308 iir &= MOXA_MUST_IIR_MASK;
f574874b
JS		 2309 if (!port->tty ||
2310 (port->flags & ASYNC_CLOSING) ||
2311 !(port->flags &
2312 ASYNC_INITIALIZED)) {
a8dea4ec
JS		 2313 status = inb(port->ioaddr + UART_LSR);
2314 outb(0x27, port->ioaddr + UART_FCR);
2315 inb(port->ioaddr + UART_MSR);
2316 break;
2317 }
037ad48b 2318
a8dea4ec
JS		 2319 status = inb(port->ioaddr + UART_LSR);
2320
2321 if (status & UART_LSR_PE)
2322 port->err_shadow |= NPPI_NOTIFY_PARITY;
2323 if (status & UART_LSR_FE)
2324 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2325 if (status & UART_LSR_OE)
2326 port->err_shadow |=
2327 NPPI_NOTIFY_HW_OVERRUN;
2328 if (status & UART_LSR_BI)
2329 port->err_shadow |= NPPI_NOTIFY_BREAK;
2330
2331 if (port->board->chip_flag) {
a8dea4ec
JS		 2332 if (iir == MOXA_MUST_IIR_GDA ||
2333 iir == MOXA_MUST_IIR_RDA ||
2334 iir == MOXA_MUST_IIR_RTO ||
2335 iir == MOXA_MUST_IIR_LSR)
2336 mxser_receive_chars(port,
2337 &status);
2338
2339 } else {
a8dea4ec
JS		 2340 status &= port->read_status_mask;
2341 if (status & UART_LSR_DR)
2342 mxser_receive_chars(port,
2343 &status);
2344 }
2345 msr = inb(port->ioaddr + UART_MSR);
2346 if (msr & UART_MSR_ANY_DELTA)
2347 mxser_check_modem_status(port, msr);
2348
a8dea4ec
JS		 2349 if (port->board->chip_flag) {
2350 if (iir == 0x02 && (status &
2351 UART_LSR_THRE))
2352 mxser_transmit_chars(port);
2353 } else {
a8dea4ec
JS		 2354 if (status & UART_LSR_THRE)
2355 mxser_transmit_chars(port);
2356 }
2357 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
f574874b 2358 spin_unlock(&port->slock);
a8dea4ec 2359 }
a8dea4ec
JS		 2360 }
2361
e079f495 2362irq_stop:
a8dea4ec 2363 return handled;
037ad48b
JS		 2364}
2365
a8dea4ec
JS		 2366static const struct tty_operations mxser_ops = {
2367 .open = mxser_open,
2368 .close = mxser_close,
2369 .write = mxser_write,
2370 .put_char = mxser_put_char,
2371 .flush_chars = mxser_flush_chars,
2372 .write_room = mxser_write_room,
2373 .chars_in_buffer = mxser_chars_in_buffer,
2374 .flush_buffer = mxser_flush_buffer,
2375 .ioctl = mxser_ioctl,
2376 .throttle = mxser_throttle,
2377 .unthrottle = mxser_unthrottle,
2378 .set_termios = mxser_set_termios,
2379 .stop = mxser_stop,
2380 .start = mxser_start,
2381 .hangup = mxser_hangup,
2382 .break_ctl = mxser_rs_break,
2383 .wait_until_sent = mxser_wait_until_sent,
2384 .tiocmget = mxser_tiocmget,
2385 .tiocmset = mxser_tiocmset,
2386};
2387
2388/*
2389 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2390 */
2391
2094e757
JS		 2392static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev,
2393 unsigned int irq)
171d3a86 2394{
171d3a86
JS		 2395 if (irq)
2396 free_irq(brd->irq, brd);
2397 if (pdev != NULL) { /* PCI */
fb0c9295 2398#ifdef CONFIG_PCI
171d3a86
JS		 2399 pci_release_region(pdev, 2);
2400 pci_release_region(pdev, 3);
fb0c9295 2401#endif
171d3a86 2402 } else {
cd7ed64e 2403 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
171d3a86
JS		 2404 release_region(brd->vector, 1);
2405 }
2406}
2407
2094e757
JS		 2408static int __devinit mxser_initbrd(struct mxser_board *brd,
2409 struct pci_dev *pdev)
037ad48b 2410{
a8dea4ec
JS		 2411 struct mxser_port *info;
2412 unsigned int i;
2413 int retval;
2414
2415 printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud);
2416
cd7ed64e 2417 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2418 info = &brd->ports[i];
2419 info->board = brd;
2420 info->stop_rx = 0;
2421 info->ldisc_stop_rx = 0;
037ad48b 2422
a8dea4ec
JS		 2423 /* Enhance mode enabled here */
2424 if (brd->chip_flag != MOXA_OTHER_UART)
2425 ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr);
037ad48b 2426
a8dea4ec
JS		 2427 info->flags = ASYNC_SHARE_IRQ;
2428 info->type = brd->uart_type;
037ad48b 2429
a8dea4ec 2430 process_txrx_fifo(info);
037ad48b 2431
a8dea4ec
JS		 2432 info->custom_divisor = info->baud_base * 16;
2433 info->close_delay = 5 * HZ / 10;
2434 info->closing_wait = 30 * HZ;
a8dea4ec
JS		 2435 info->normal_termios = mxvar_sdriver->init_termios;
2436 init_waitqueue_head(&info->open_wait);
a8dea4ec 2437 init_waitqueue_head(&info->delta_msr_wait);
f64c84a1 2438 info->speed = 9600;
a8dea4ec
JS		 2439 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2440 info->err_shadow = 0;
2441 spin_lock_init(&info->slock);
037ad48b 2442
a8dea4ec
JS		 2443 /* before set INT ISR, disable all int */
2444 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2445 info->ioaddr + UART_IER);
2446 }
037ad48b 2447
c493edd1
JS		 2448 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2449 brd);
a8dea4ec
JS		 2450 if (retval) {
2451 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2452 "conflict with another device.\n",
cd7ed64e 2453 brd->info->name, brd->irq);
171d3a86 2454 /* We hold resources, we need to release them. */
2094e757 2455 mxser_release_res(brd, pdev, 0);
a8dea4ec 2456 }
45257fa9 2457 return retval;
037ad48b
JS		 2458}
2459
943f2959 2460static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
037ad48b
JS		 2461{
2462 int id, i, bits;
2463 unsigned short regs[16], irq;
2464 unsigned char scratch, scratch2;
2465
55b307da 2466 brd->chip_flag = MOXA_OTHER_UART;
037ad48b
JS		 2467
2468 id = mxser_read_register(cap, regs);
cd7ed64e
JS		 2469 switch (id) {
2470 case C168_ASIC_ID:
2471 brd->info = &mxser_cards[0];
2472 break;
2473 case C104_ASIC_ID:
2474 brd->info = &mxser_cards[1];
2475 break;
2476 case CI104J_ASIC_ID:
2477 brd->info = &mxser_cards[2];
2478 break;
2479 case C102_ASIC_ID:
2480 brd->info = &mxser_cards[5];
2481 break;
2482 case CI132_ASIC_ID:
2483 brd->info = &mxser_cards[6];
2484 break;
2485 case CI134_ASIC_ID:
2486 brd->info = &mxser_cards[7];
2487 break;
2488 default:
037ad48b 2489 return 0;
cd7ed64e 2490 }
037ad48b
JS		 2491
2492 irq = 0;
cd7ed64e
JS		 2493 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2494 Flag-hack checks if configuration should be read as 2-port here. */
2495 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
037ad48b
JS		 2496 irq = regs[9] & 0xF000;
2497 irq = irq | (irq >> 4);
2498 if (irq != (regs[9] & 0xFF00))
2499 return MXSER_ERR_IRQ_CONFLIT;
cd7ed64e 2500 } else if (brd->info->nports == 4) {
037ad48b
JS		 2501 irq = regs[9] & 0xF000;
2502 irq = irq | (irq >> 4);
2503 irq = irq | (irq >> 8);
2504 if (irq != regs[9])
2505 return MXSER_ERR_IRQ_CONFLIT;
cd7ed64e 2506 } else if (brd->info->nports == 8) {
037ad48b
JS		 2507 irq = regs[9] & 0xF000;
2508 irq = irq | (irq >> 4);
2509 irq = irq | (irq >> 8);
2510 if ((irq != regs[9]) || (irq != regs[10]))
2511 return MXSER_ERR_IRQ_CONFLIT;
2512 }
2513
a8dea4ec
JS		 2514 if (!irq)
2515 return MXSER_ERR_IRQ;
2516 brd->irq = ((int)(irq & 0xF000) >> 12);
2517 for (i = 0; i < 8; i++)
2518 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
2519 if ((regs[12] & 0x80) == 0)
2520 return MXSER_ERR_VECTOR;
2521 brd->vector = (int)regs[11]; /* interrupt vector */
2522 if (id == 1)
2523 brd->vector_mask = 0x00FF;
2524 else
2525 brd->vector_mask = 0x000F;
2526 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2527 if (regs[12] & bits) {
2528 brd->ports[i].baud_base = 921600;
e079f495 2529 brd->ports[i].max_baud = 921600;
a8dea4ec
JS		 2530 } else {
2531 brd->ports[i].baud_base = 115200;
e079f495 2532 brd->ports[i].max_baud = 115200;
a8dea4ec
JS		 2533 }
2534 }
2535 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2536 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2537 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2538 outb(scratch2, cap + UART_LCR);
2539 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2540 scratch = inb(cap + UART_IIR);
2541
2542 if (scratch & 0xC0)
2543 brd->uart_type = PORT_16550A;
2544 else
2545 brd->uart_type = PORT_16450;
cd7ed64e
JS		 2546 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2547 "mxser(IO)"))
a8dea4ec
JS		 2548 return MXSER_ERR_IOADDR;
2549 if (!request_region(brd->vector, 1, "mxser(vector)")) {
cd7ed64e 2550 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
a8dea4ec
JS		 2551 return MXSER_ERR_VECTOR;
2552 }
cd7ed64e 2553 return brd->info->nports;
a8dea4ec
JS		 2554}
2555
2094e757
JS		 2556static int __devinit mxser_probe(struct pci_dev *pdev,
2557 const struct pci_device_id *ent)
a8dea4ec 2558{
fb0c9295 2559#ifdef CONFIG_PCI
2094e757 2560 struct mxser_board *brd;
a8dea4ec
JS		 2561 unsigned int i, j;
2562 unsigned long ioaddress;
2094e757
JS		 2563 int retval = -EINVAL;
2564
2565 for (i = 0; i < MXSER_BOARDS; i++)
2566 if (mxser_boards[i].info == NULL)
2567 break;
2568
2569 if (i >= MXSER_BOARDS) {
2570 printk(KERN_ERR "Too many Smartio/Industio family boards found "
2571 "(maximum %d), board not configured\n", MXSER_BOARDS);
2572 goto err;
2573 }
2574
2575 brd = &mxser_boards[i];
2576 brd->idx = i * MXSER_PORTS_PER_BOARD;
2577 printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2578 mxser_cards[ent->driver_data].name,
2579 pdev->bus->number, PCI_SLOT(pdev->devfn));
2580
2581 retval = pci_enable_device(pdev);
2582 if (retval) {
2583 printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n");
2584 goto err;
2585 }
a8dea4ec
JS		 2586
2587 /* io address */
a8dea4ec
JS		 2588 ioaddress = pci_resource_start(pdev, 2);
2589 retval = pci_request_region(pdev, 2, "mxser(IO)");
2590 if (retval)
2591 goto err;
2592
2094e757 2593 brd->info = &mxser_cards[ent->driver_data];
cd7ed64e 2594 for (i = 0; i < brd->info->nports; i++)
a8dea4ec
JS		 2595 brd->ports[i].ioaddr = ioaddress + 8 * i;
2596
2597 /* vector */
2598 ioaddress = pci_resource_start(pdev, 3);
2599 retval = pci_request_region(pdev, 3, "mxser(vector)");
2600 if (retval)
2601 goto err_relio;
2602 brd->vector = ioaddress;
2603
2604 /* irq */
2605 brd->irq = pdev->irq;
2606
2607 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2608 brd->uart_type = PORT_16550A;
2609 brd->vector_mask = 0;
2610
cd7ed64e 2611 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2612 for (j = 0; j < UART_INFO_NUM; j++) {
2613 if (Gpci_uart_info[j].type == brd->chip_flag) {
2614 brd->ports[i].max_baud =
2615 Gpci_uart_info[j].max_baud;
2616
2617 /* exception....CP-102 */
cd7ed64e 2618 if (brd->info->flags & MXSER_HIGHBAUD)
a8dea4ec
JS		 2619 brd->ports[i].max_baud = 921600;
2620 break;
2621 }
2622 }
2623 }
2624
2625 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
cd7ed64e 2626 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2627 if (i < 4)
2628 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2629 else
2630 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
2631 }
2632 outb(0, ioaddress + 4); /* default set to RS232 mode */
2633 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
2634 }
2635
cd7ed64e 2636 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2637 brd->vector_mask |= (1 << i);
2638 brd->ports[i].baud_base = 921600;
2639 }
2094e757
JS		 2640
2641 /* mxser_initbrd will hook ISR. */
45257fa9
JS		 2642 retval = mxser_initbrd(brd, pdev);
2643 if (retval)
2644 goto err_null;
2094e757
JS		 2645
2646 for (i = 0; i < brd->info->nports; i++)
2647 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2648
2649 pci_set_drvdata(pdev, brd);
2650
a8dea4ec
JS		 2651 return 0;
2652err_relio:
2653 pci_release_region(pdev, 2);
45257fa9 2654err_null:
2094e757 2655 brd->info = NULL;
a8dea4ec
JS		 2656err:
2657 return retval;
fb0c9295
JS		 2658#else
2659 return -ENODEV;
2660#endif
a8dea4ec
JS		 2661}
2662
2094e757
JS		 2663static void __devexit mxser_remove(struct pci_dev *pdev)
2664{
2665 struct mxser_board *brd = pci_get_drvdata(pdev);
2666 unsigned int i;
2667
2668 for (i = 0; i < brd->info->nports; i++)
2669 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2670
2671 mxser_release_res(brd, pdev, 1);
45257fa9 2672 brd->info = NULL;
2094e757
JS		 2673}
2674
2675static struct pci_driver mxser_driver = {
2676 .name = "mxser",
2677 .id_table = mxser_pcibrds,
2678 .probe = mxser_probe,
2679 .remove = __devexit_p(mxser_remove)
2680};
2681
a8dea4ec
JS		 2682static int __init mxser_module_init(void)
2683{
a8dea4ec 2684 struct mxser_board *brd;
eae4436a
JS		 2685 unsigned long cap;
2686 unsigned int i, m, isaloop;
2094e757 2687 int retval, b;
a8dea4ec
JS		 2688
2689 pr_debug("Loading module mxser ...\n");
2690
2691 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2692 if (!mxvar_sdriver)
2693 return -ENOMEM;
a8dea4ec 2694
a8dea4ec
JS		 2695 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2696 MXSER_VERSION);
2697
2698 /* Initialize the tty_driver structure */
31f87cf4 2699 mxvar_sdriver->owner = THIS_MODULE;
a8dea4ec 2700 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
e930790d 2701 mxvar_sdriver->name = "ttyMI";
a8dea4ec
JS		 2702 mxvar_sdriver->major = ttymajor;
2703 mxvar_sdriver->minor_start = 0;
2704 mxvar_sdriver->num = MXSER_PORTS + 1;
2705 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2706 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2707 mxvar_sdriver->init_termios = tty_std_termios;
2708 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
938ef180 2709 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
a8dea4ec 2710 tty_set_operations(mxvar_sdriver, &mxser_ops);
a8dea4ec 2711
938ef180
JS		 2712 retval = tty_register_driver(mxvar_sdriver);
2713 if (retval) {
2714 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2715 "tty driver !\n");
2716 goto err_put;
2717 }
2718
a8dea4ec
JS		 2719 mxvar_diagflag = 0;
2720
2721 m = 0;
2722 /* Start finding ISA boards here */
eae4436a
JS		 2723 for (isaloop = 0; isaloop < 2; isaloop++)
2724 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
2725 if (!isaloop)
2726 cap = mxserBoardCAP[b]; /* predefined */
2727 else
2728 cap = ioaddr[b]; /* module param */
a8dea4ec 2729
eae4436a
JS		 2730 if (!cap)
2731 continue;
a8dea4ec 2732
eae4436a
JS		 2733 brd = &mxser_boards[m];
2734 retval = mxser_get_ISA_conf(cap, brd);
2735
2736 if (retval != 0)
2737 printk(KERN_INFO "Found MOXA %s board "
2738 "(CAP=0x%x)\n",
cd7ed64e 2739 brd->info->name, ioaddr[b]);
eae4436a
JS		 2740
2741 if (retval <= 0) {
2742 if (retval == MXSER_ERR_IRQ)
2743 printk(KERN_ERR "Invalid interrupt "
2744 "number, board not "
2745 "configured\n");
2746 else if (retval == MXSER_ERR_IRQ_CONFLIT)
2747 printk(KERN_ERR "Invalid interrupt "
2748 "number, board not "
2749 "configured\n");
2750 else if (retval == MXSER_ERR_VECTOR)
2751 printk(KERN_ERR "Invalid interrupt "
2752 "vector, board not "
2753 "configured\n");
2754 else if (retval == MXSER_ERR_IOADDR)
2755 printk(KERN_ERR "Invalid I/O address, "
2756 "board not configured\n");
a8dea4ec 2757
2094e757 2758 brd->info = NULL;
eae4436a
JS		 2759 continue;
2760 }
a8dea4ec 2761
eae4436a 2762 /* mxser_initbrd will hook ISR. */
2094e757
JS		 2763 if (mxser_initbrd(brd, NULL) < 0) {
2764 brd->info = NULL;
a8dea4ec
JS		 2765 continue;
2766 }
2094e757
JS		 2767
2768 brd->idx = m * MXSER_PORTS_PER_BOARD;
cd7ed64e 2769 for (i = 0; i < brd->info->nports; i++)
2094e757
JS		 2770 tty_register_device(mxvar_sdriver, brd->idx + i,
2771 NULL);
938ef180 2772
a8dea4ec 2773 m++;
a8dea4ec 2774 }
037ad48b 2775
2094e757
JS		 2776 retval = pci_register_driver(&mxser_driver);
2777 if (retval) {
2778 printk(KERN_ERR "Can't register pci driver\n");
2779 if (!m) {
2780 retval = -ENODEV;
2781 goto err_unr;
2782 } /* else: we have some ISA cards under control */
037ad48b 2783 }
a8dea4ec
JS		 2784
2785 pr_debug("Done.\n");
2786
938ef180
JS		 2787 return 0;
2788err_unr:
2789 tty_unregister_driver(mxvar_sdriver);
2790err_put:
2791 put_tty_driver(mxvar_sdriver);
a8dea4ec 2792 return retval;
037ad48b
JS		 2793}
2794
a8dea4ec 2795static void __exit mxser_module_exit(void)
037ad48b 2796{
2094e757 2797 unsigned int i, j;
037ad48b 2798
a8dea4ec 2799 pr_debug("Unloading module mxser ...\n");
037ad48b 2800
2094e757
JS		 2801 pci_unregister_driver(&mxser_driver);
2802
2803 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2804 if (mxser_boards[i].info != NULL)
2805 for (j = 0; j < mxser_boards[i].info->nports; j++)
2806 tty_unregister_device(mxvar_sdriver,
2807 mxser_boards[i].idx + j);
ead568c9
JS		 2808 tty_unregister_driver(mxvar_sdriver);
2809 put_tty_driver(mxvar_sdriver);
037ad48b 2810
171d3a86 2811 for (i = 0; i < MXSER_BOARDS; i++)
cd7ed64e 2812 if (mxser_boards[i].info != NULL)
2094e757 2813 mxser_release_res(&mxser_boards[i], NULL, 1);
037ad48b 2814
a8dea4ec 2815 pr_debug("Done.\n");
037ad48b
JS		 2816}
2817
2818module_init(mxser_module_init);
2819module_exit(mxser_module_exit);
Linux kernel - Deliverables
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