[deliverable/linux.git] / drivers / char / pc8736x_gpio.c

/* linux/drivers/char/pc8736x_gpio.c

   National Semiconductor PC8736x GPIO driver.  Allows a user space
   process to play with the GPIO pins.

   Copyright (c) 2005,2006 Jim Cromie <jim.cromie@gmail.com>

   adapted from linux/drivers/char/scx200_gpio.c
   Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
*/

#include <linux/fs.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cdev.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/nsc_gpio.h>
#include <linux/platform_device.h>
#include <asm/uaccess.h>

#define DEVNAME "pc8736x_gpio"

MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
MODULE_LICENSE("GPL");

static int major;		/* default to dynamic major */
module_param(major, int, 0);
MODULE_PARM_DESC(major, "Major device number");

static DEFINE_MUTEX(pc8736x_gpio_config_lock);
static unsigned pc8736x_gpio_base;
static u8 pc8736x_gpio_shadow[4];

#define SIO_BASE1       0x2E	/* 1st command-reg to check */
#define SIO_BASE2       0x4E	/* alt command-reg to check */

#define SIO_SID		0x20	/* SuperI/O ID Register */
#define SIO_SID_VALUE	0xe9	/* Expected value in SuperI/O ID Register */

#define SIO_CF1		0x21	/* chip config, bit0 is chip enable */

#define PC8736X_GPIO_RANGE	16 /* ioaddr range */
#define PC8736X_GPIO_CT		32 /* minors matching 4 8 bit ports */

#define SIO_UNIT_SEL	0x7	/* unit select reg */
#define SIO_UNIT_ACT	0x30	/* unit enable */
#define SIO_GPIO_UNIT	0x7	/* unit number of GPIO */
#define SIO_VLM_UNIT	0x0D
#define SIO_TMS_UNIT	0x0E

/* config-space addrs to read/write each unit's runtime addr */
#define SIO_BASE_HADDR		0x60
#define SIO_BASE_LADDR		0x61

/* GPIO config-space pin-control addresses */
#define SIO_GPIO_PIN_SELECT	0xF0
#define SIO_GPIO_PIN_CONFIG     0xF1
#define SIO_GPIO_PIN_EVENT      0xF2

static unsigned char superio_cmd = 0;
static unsigned char selected_device = 0xFF;	/* bogus start val */

/* GPIO port runtime access, functionality */
static int port_offset[] = { 0, 4, 8, 10 };	/* non-uniform offsets ! */
/* static int event_capable[] = { 1, 1, 0, 0 };   ports 2,3 are hobbled */

#define PORT_OUT	0
#define PORT_IN		1
#define PORT_EVT_EN	2
#define PORT_EVT_STST	3

static struct platform_device *pdev;  /* use in dev_*() */

static inline void superio_outb(int addr, int val)
{
	outb_p(addr, superio_cmd);
	outb_p(val, superio_cmd + 1);
}

static inline int superio_inb(int addr)
{
	outb_p(addr, superio_cmd);
	return inb_p(superio_cmd + 1);
}

static int pc8736x_superio_present(void)
{
	/* try the 2 possible values, read a hardware reg to verify */
	superio_cmd = SIO_BASE1;
	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
		return superio_cmd;

	superio_cmd = SIO_BASE2;
	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
		return superio_cmd;

	return 0;
}

static void device_select(unsigned devldn)
{
	superio_outb(SIO_UNIT_SEL, devldn);
	selected_device = devldn;
}

static void select_pin(unsigned iminor)
{
	/* select GPIO port/pin from device minor number */
	device_select(SIO_GPIO_UNIT);
	superio_outb(SIO_GPIO_PIN_SELECT,
		     ((iminor << 1) & 0xF0) | (iminor & 0x7));
}

static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
					    u32 func_slct)
{
	u32 config, new_config;

	mutex_lock(&pc8736x_gpio_config_lock);

	device_select(SIO_GPIO_UNIT);
	select_pin(index);

	/* read current config value */
	config = superio_inb(func_slct);

	/* set new config */
	new_config = (config & mask) | bits;
	superio_outb(func_slct, new_config);

	mutex_unlock(&pc8736x_gpio_config_lock);

	return config;
}

static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
{
	return pc8736x_gpio_configure_fn(index, mask, bits,
					 SIO_GPIO_PIN_CONFIG);
}

static int pc8736x_gpio_get(unsigned minor)
{
	int port, bit, val;

	port = minor >> 3;
	bit = minor & 7;
	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	val >>= bit;
	val &= 1;

	dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
		minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
		val);

	return val;
}

static void pc8736x_gpio_set(unsigned minor, int val)
{
	int port, bit, curval;

	minor &= 0x1f;
	port = minor >> 3;
	bit = minor & 7;
	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);

	dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
		pc8736x_gpio_base + port_offset[port] + PORT_OUT,
		curval, bit, (curval & ~(1 << bit)), val, (val << bit));

	val = (curval & ~(1 << bit)) | (val << bit);

	dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
		" %2x -> %2x\n", minor, port, bit, curval, val);

	outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);

	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);

	dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
	pc8736x_gpio_shadow[port] = val;
}

static int pc8736x_gpio_current(unsigned minor)
{
	int port, bit;
	minor &= 0x1f;
	port = minor >> 3;
	bit = minor & 7;
	return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
}

static void pc8736x_gpio_change(unsigned index)
{
	pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
}

static struct nsc_gpio_ops pc8736x_gpio_ops = {
	.owner		= THIS_MODULE,
	.gpio_config	= pc8736x_gpio_configure,
	.gpio_dump	= nsc_gpio_dump,
	.gpio_get	= pc8736x_gpio_get,
	.gpio_set	= pc8736x_gpio_set,
	.gpio_change	= pc8736x_gpio_change,
	.gpio_current	= pc8736x_gpio_current
};

/* No BKL needed here; no global resources accessed */
static int pc8736x_gpio_open(struct inode *inode, struct file *file)
{
	unsigned m = iminor(inode);
	file->private_data = &pc8736x_gpio_ops;

	dev_dbg(&pdev->dev, "open %d\n", m);

	if (m >= PC8736X_GPIO_CT)
		return -EINVAL;
	return nonseekable_open(inode, file);
}

static const struct file_operations pc8736x_gpio_fileops = {
	.owner	= THIS_MODULE,
	.open	= pc8736x_gpio_open,
	.write	= nsc_gpio_write,
	.read	= nsc_gpio_read,
};

static void __init pc8736x_init_shadow(void)
{
	int port;

	/* read the current values driven on the GPIO signals */
	for (port = 0; port < 4; ++port)
		pc8736x_gpio_shadow[port]
		    = inb_p(pc8736x_gpio_base + port_offset[port]
			    + PORT_OUT);

}

static struct cdev pc8736x_gpio_cdev;

static int __init pc8736x_gpio_init(void)
{
	int rc;
	dev_t devid;

	pdev = platform_device_alloc(DEVNAME, 0);
	if (!pdev)
		return -ENOMEM;

	rc = platform_device_add(pdev);
	if (rc) {
		rc = -ENODEV;
		goto undo_platform_dev_alloc;
	}
	dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");

	if (!pc8736x_superio_present()) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "no device found\n");
		goto undo_platform_dev_add;
	}
	pc8736x_gpio_ops.dev = &pdev->dev;

	/* Verify that chip and it's GPIO unit are both enabled.
	   My BIOS does this, so I take minimum action here
	 */
	rc = superio_inb(SIO_CF1);
	if (!(rc & 0x01)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "device not enabled\n");
		goto undo_platform_dev_add;
	}
	device_select(SIO_GPIO_UNIT);
	if (!superio_inb(SIO_UNIT_ACT)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "GPIO unit not enabled\n");
		goto undo_platform_dev_add;
	}

	/* read the GPIO unit base addr that chip responds to */
	pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
			     | superio_inb(SIO_BASE_LADDR));

	if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "GPIO ioport %x busy\n",
			pc8736x_gpio_base);
		goto undo_platform_dev_add;
	}
	dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);

	if (major) {
		devid = MKDEV(major, 0);
		rc = register_chrdev_region(devid, PC8736X_GPIO_CT, DEVNAME);
	} else {
		rc = alloc_chrdev_region(&devid, 0, PC8736X_GPIO_CT, DEVNAME);
		major = MAJOR(devid);
	}

	if (rc < 0) {
		dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
		goto undo_request_region;
	}
	if (!major) {
		major = rc;
		dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
	}

	pc8736x_init_shadow();

	/* ignore minor errs, and succeed */
	cdev_init(&pc8736x_gpio_cdev, &pc8736x_gpio_fileops);
	cdev_add(&pc8736x_gpio_cdev, devid, PC8736X_GPIO_CT);

	return 0;

undo_request_region:
	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
undo_platform_dev_add:
	platform_device_del(pdev);
undo_platform_dev_alloc:
	platform_device_put(pdev);

	return rc;
}

static void __exit pc8736x_gpio_cleanup(void)
{
	dev_dbg(&pdev->dev, "cleanup\n");

	cdev_del(&pc8736x_gpio_cdev);
	unregister_chrdev_region(MKDEV(major,0), PC8736X_GPIO_CT);
	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);

	platform_device_del(pdev);
	platform_device_put(pdev);
}

module_init(pc8736x_gpio_init);
module_exit(pc8736x_gpio_cleanup);
Commit	Line	Data
681a3e7d JC	1	/* linux/drivers/char/pc8736x_gpio.c
	2
	3	National Semiconductor PC8736x GPIO driver. Allows a user space
	4	process to play with the GPIO pins.
	5
27385085	6	Copyright (c) 2005,2006 Jim Cromie <jim.cromie@gmail.com>
681a3e7d JC	7
	8	adapted from linux/drivers/char/scx200_gpio.c
	9	Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
	10	*/
	11
681a3e7d JC	12	#include <linux/fs.h>
	13	#include <linux/module.h>
	14	#include <linux/errno.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
27385085	17	#include <linux/cdev.h>
ec312310	18	#include <linux/io.h>
681a3e7d	19	#include <linux/ioport.h>
8bcf6135	20	#include <linux/mutex.h>
681a3e7d	21	#include <linux/nsc_gpio.h>
58b087cd	22	#include <linux/platform_device.h>
681a3e7d	23	#include <asm/uaccess.h>
681a3e7d	24
58b087cd	25	#define DEVNAME "pc8736x_gpio"
681a3e7d JC	26
681a3e7d JC	27	MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
4f197842	28	MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
681a3e7d JC	29	MODULE_LICENSE("GPL");
	30
	31	static int major; /* default to dynamic major */
	32	module_param(major, int, 0);
	33	MODULE_PARM_DESC(major, "Major device number");
	34
8bcf6135	35	static DEFINE_MUTEX(pc8736x_gpio_config_lock);
681a3e7d	36	static unsigned pc8736x_gpio_base;
6cad56fd	37	static u8 pc8736x_gpio_shadow[4];
681a3e7d JC	38
	39	#define SIO_BASE1 0x2E /* 1st command-reg to check */
	40	#define SIO_BASE2 0x4E /* alt command-reg to check */
681a3e7d JC	41
	42	#define SIO_SID 0x20 /* SuperI/O ID Register */
	43	#define SIO_SID_VALUE 0xe9 /* Expected value in SuperI/O ID Register */
	44
	45	#define SIO_CF1 0x21 /* chip config, bit0 is chip enable */
	46
4f197842 JC	47	#define PC8736X_GPIO_RANGE 16 /* ioaddr range */
4f197842 JC	48	#define PC8736X_GPIO_CT 32 /* minors matching 4 8 bit ports */
58b087cd	49
681a3e7d JC	50	#define SIO_UNIT_SEL 0x7 /* unit select reg */
	51	#define SIO_UNIT_ACT 0x30 /* unit enable */
	52	#define SIO_GPIO_UNIT 0x7 /* unit number of GPIO */
	53	#define SIO_VLM_UNIT 0x0D
	54	#define SIO_TMS_UNIT 0x0E
	55
	56	/* config-space addrs to read/write each unit's runtime addr */
	57	#define SIO_BASE_HADDR 0x60
	58	#define SIO_BASE_LADDR 0x61
	59
	60	/* GPIO config-space pin-control addresses */
	61	#define SIO_GPIO_PIN_SELECT 0xF0
	62	#define SIO_GPIO_PIN_CONFIG 0xF1
	63	#define SIO_GPIO_PIN_EVENT 0xF2
	64
	65	static unsigned char superio_cmd = 0;
	66	static unsigned char selected_device = 0xFF; /* bogus start val */
	67
	68	/* GPIO port runtime access, functionality */
	69	static int port_offset[] = { 0, 4, 8, 10 }; /* non-uniform offsets ! */
	70	/* static int event_capable[] = { 1, 1, 0, 0 }; ports 2,3 are hobbled */
	71
	72	#define PORT_OUT 0
	73	#define PORT_IN 1
	74	#define PORT_EVT_EN 2
	75	#define PORT_EVT_STST 3
	76
58b087cd JC	77	static struct platform_device pdev; / use in dev_() /
58b087cd JC	78
681a3e7d JC	79	static inline void superio_outb(int addr, int val)
	80	{
	81	outb_p(addr, superio_cmd);
	82	outb_p(val, superio_cmd + 1);
	83	}
	84
	85	static inline int superio_inb(int addr)
	86	{
	87	outb_p(addr, superio_cmd);
	88	return inb_p(superio_cmd + 1);
	89	}
	90
	91	static int pc8736x_superio_present(void)
	92	{
	93	/* try the 2 possible values, read a hardware reg to verify */
	94	superio_cmd = SIO_BASE1;
	95	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
	96	return superio_cmd;
	97
	98	superio_cmd = SIO_BASE2;
	99	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
	100	return superio_cmd;
	101
	102	return 0;
	103	}
	104
	105	static void device_select(unsigned devldn)
	106	{
	107	superio_outb(SIO_UNIT_SEL, devldn);
	108	selected_device = devldn;
	109	}
	110
	111	static void select_pin(unsigned iminor)
	112	{
	113	/* select GPIO port/pin from device minor number */
	114	device_select(SIO_GPIO_UNIT);
	115	superio_outb(SIO_GPIO_PIN_SELECT,
	116	((iminor << 1) & 0xF0) \| (iminor & 0x7));
	117	}
	118
	119	static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
	120	u32 func_slct)
	121	{
	122	u32 config, new_config;
681a3e7d	123
8bcf6135	124	mutex_lock(&pc8736x_gpio_config_lock);
681a3e7d JC	125
	126	device_select(SIO_GPIO_UNIT);
	127	select_pin(index);
	128
	129	/* read current config value */
	130	config = superio_inb(func_slct);
	131
	132	/* set new config */
	133	new_config = (config & mask) \| bits;
	134	superio_outb(func_slct, new_config);
	135
8bcf6135	136	mutex_unlock(&pc8736x_gpio_config_lock);
681a3e7d JC	137
	138	return config;
	139	}
	140
	141	static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
	142	{
	143	return pc8736x_gpio_configure_fn(index, mask, bits,
	144	SIO_GPIO_PIN_CONFIG);
	145	}
	146
	147	static int pc8736x_gpio_get(unsigned minor)
	148	{
	149	int port, bit, val;
	150
	151	port = minor >> 3;
	152	bit = minor & 7;
	153	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	154	val >>= bit;
	155	val &= 1;
	156
58b087cd JC	157	dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
	158	minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
	159	val);
681a3e7d JC	160
	161	return val;
	162	}
	163
	164	static void pc8736x_gpio_set(unsigned minor, int val)
	165	{
	166	int port, bit, curval;
	167
	168	minor &= 0x1f;
	169	port = minor >> 3;
	170	bit = minor & 7;
	171	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	172
58b087cd JC	173	dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
	174	pc8736x_gpio_base + port_offset[port] + PORT_OUT,
	175	curval, bit, (curval & ~(1 << bit)), val, (val << bit));
681a3e7d JC	176
	177	val = (curval & ~(1 << bit)) \| (val << bit);
	178
58b087cd JC	179	dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
58b087cd JC	180	" %2x -> %2x\n", minor, port, bit, curval, val);
681a3e7d JC	181
	182	outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	183
	184	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	185	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	186
58b087cd	187	dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
6cad56fd	188	pc8736x_gpio_shadow[port] = val;
681a3e7d JC	189	}
681a3e7d JC	190
6cad56fd	191	static int pc8736x_gpio_current(unsigned minor)
681a3e7d	192	{
6cad56fd JC	193	int port, bit;
	194	minor &= 0x1f;
	195	port = minor >> 3;
	196	bit = minor & 7;
	197	return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
681a3e7d JC	198	}
	199
	200	static void pc8736x_gpio_change(unsigned index)
	201	{
6cad56fd	202	pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
681a3e7d JC	203	}
681a3e7d JC	204
2e8f7a31	205	static struct nsc_gpio_ops pc8736x_gpio_ops = {
681a3e7d JC	206	.owner = THIS_MODULE,
	207	.gpio_config = pc8736x_gpio_configure,
	208	.gpio_dump = nsc_gpio_dump,
	209	.gpio_get = pc8736x_gpio_get,
	210	.gpio_set = pc8736x_gpio_set,
681a3e7d JC	211	.gpio_change = pc8736x_gpio_change,
	212	.gpio_current = pc8736x_gpio_current
	213	};
	214
d21c95c5	215	/* No BKL needed here; no global resources accessed */
681a3e7d JC	216	static int pc8736x_gpio_open(struct inode inode, struct file file)
	217	{
	218	unsigned m = iminor(inode);
2e8f7a31	219	file->private_data = &pc8736x_gpio_ops;
681a3e7d	220
58b087cd	221	dev_dbg(&pdev->dev, "open %d\n", m);
681a3e7d	222
4f197842	223	if (m >= PC8736X_GPIO_CT)
681a3e7d JC	224	return -EINVAL;
	225	return nonseekable_open(inode, file);
	226	}
	227
2e8f7a31	228	static const struct file_operations pc8736x_gpio_fileops = {
58b087cd JC	229	.owner = THIS_MODULE,
	230	.open = pc8736x_gpio_open,
	231	.write = nsc_gpio_write,
	232	.read = nsc_gpio_read,
681a3e7d JC	233	};
681a3e7d JC	234
6cad56fd JC	235	static void __init pc8736x_init_shadow(void)
	236	{
	237	int port;
	238
	239	/* read the current values driven on the GPIO signals */
	240	for (port = 0; port < 4; ++port)
	241	pc8736x_gpio_shadow[port]
	242	= inb_p(pc8736x_gpio_base + port_offset[port]
	243	+ PORT_OUT);
	244
	245	}
	246
27385085 JC	247	static struct cdev pc8736x_gpio_cdev;
27385085 JC	248
681a3e7d JC	249	static int __init pc8736x_gpio_init(void)
681a3e7d JC	250	{
babcfade JC	251	int rc;
babcfade JC	252	dev_t devid;
58b087cd JC	253
	254	pdev = platform_device_alloc(DEVNAME, 0);
	255	if (!pdev)
	256	return -ENOMEM;
681a3e7d	257
58b087cd JC	258	rc = platform_device_add(pdev);
	259	if (rc) {
	260	rc = -ENODEV;
	261	goto undo_platform_dev_alloc;
	262	}
	263	dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");
681a3e7d JC	264
681a3e7d JC	265	if (!pc8736x_superio_present()) {
58b087cd JC	266	rc = -ENODEV;
	267	dev_err(&pdev->dev, "no device found\n");
	268	goto undo_platform_dev_add;
681a3e7d	269	}
2e8f7a31	270	pc8736x_gpio_ops.dev = &pdev->dev;
681a3e7d JC	271
	272	/* Verify that chip and it's GPIO unit are both enabled.
	273	My BIOS does this, so I take minimum action here
	274	*/
	275	rc = superio_inb(SIO_CF1);
	276	if (!(rc & 0x01)) {
58b087cd JC	277	rc = -ENODEV;
	278	dev_err(&pdev->dev, "device not enabled\n");
	279	goto undo_platform_dev_add;
681a3e7d JC	280	}
	281	device_select(SIO_GPIO_UNIT);
	282	if (!superio_inb(SIO_UNIT_ACT)) {
58b087cd JC	283	rc = -ENODEV;
	284	dev_err(&pdev->dev, "GPIO unit not enabled\n");
	285	goto undo_platform_dev_add;
681a3e7d JC	286	}
681a3e7d JC	287
58b087cd	288	/* read the GPIO unit base addr that chip responds to */
681a3e7d JC	289	pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
	290	\| superio_inb(SIO_BASE_LADDR));
	291
4f197842	292	if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
58b087cd JC	293	rc = -ENODEV;
	294	dev_err(&pdev->dev, "GPIO ioport %x busy\n",
	295	pc8736x_gpio_base);
	296	goto undo_platform_dev_add;
	297	}
	298	dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);
681a3e7d	299
babcfade JC	300	if (major) {
	301	devid = MKDEV(major, 0);
	302	rc = register_chrdev_region(devid, PC8736X_GPIO_CT, DEVNAME);
	303	} else {
	304	rc = alloc_chrdev_region(&devid, 0, PC8736X_GPIO_CT, DEVNAME);
	305	major = MAJOR(devid);
	306	}
	307
58b087cd JC	308	if (rc < 0) {
58b087cd JC	309	dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
27385085	310	goto undo_request_region;
681a3e7d JC	311	}
681a3e7d JC	312	if (!major) {
58b087cd JC	313	major = rc;
58b087cd JC	314	dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
681a3e7d JC	315	}
	316
	317	pc8736x_init_shadow();
babcfade JC	318
babcfade JC	319	/* ignore minor errs, and succeed */
2e8f7a31	320	cdev_init(&pc8736x_gpio_cdev, &pc8736x_gpio_fileops);
babcfade JC	321	cdev_add(&pc8736x_gpio_cdev, devid, PC8736X_GPIO_CT);
babcfade JC	322
681a3e7d	323	return 0;
58b087cd	324
27385085 JC	325	undo_request_region:
27385085 JC	326	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
58b087cd	327	undo_platform_dev_add:
1017f6af	328	platform_device_del(pdev);
58b087cd	329	undo_platform_dev_alloc:
1017f6af IM	330	platform_device_put(pdev);
1017f6af IM	331
58b087cd	332	return rc;
681a3e7d JC	333	}
	334
	335	static void __exit pc8736x_gpio_cleanup(void)
	336	{
27385085	337	dev_dbg(&pdev->dev, "cleanup\n");
681a3e7d	338
27385085 JC	339	cdev_del(&pc8736x_gpio_cdev);
	340	unregister_chrdev_region(MKDEV(major,0), PC8736X_GPIO_CT);
	341	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
681a3e7d	342
27385085 JC	343	platform_device_del(pdev);
27385085 JC	344	platform_device_put(pdev);
681a3e7d JC	345	}
	346
	347	module_init(pc8736x_gpio_init);
	348	module_exit(pc8736x_gpio_cleanup);