[deliverable/linux.git] / drivers / char / pc8736x_gpio.c

/* linux/drivers/char/pc8736x_gpio.c

   National Semiconductor PC8736x GPIO driver.  Allows a user space
   process to play with the GPIO pins.

   Copyright (c) 2005,2006 Jim Cromie <jim.cromie@gmail.com>

   adapted from linux/drivers/char/scx200_gpio.c
   Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
*/

#include <linux/fs.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cdev.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/nsc_gpio.h>
#include <linux/platform_device.h>
#include <linux/smp_lock.h>
#include <asm/uaccess.h>

#define DEVNAME "pc8736x_gpio"

MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
MODULE_LICENSE("GPL");

static int major;		/* default to dynamic major */
module_param(major, int, 0);
MODULE_PARM_DESC(major, "Major device number");

static DEFINE_MUTEX(pc8736x_gpio_config_lock);
static unsigned pc8736x_gpio_base;
static u8 pc8736x_gpio_shadow[4];

#define SIO_BASE1       0x2E	/* 1st command-reg to check */
#define SIO_BASE2       0x4E	/* alt command-reg to check */

#define SIO_SID		0x20	/* SuperI/O ID Register */
#define SIO_SID_VALUE	0xe9	/* Expected value in SuperI/O ID Register */

#define SIO_CF1		0x21	/* chip config, bit0 is chip enable */

#define PC8736X_GPIO_RANGE	16 /* ioaddr range */
#define PC8736X_GPIO_CT		32 /* minors matching 4 8 bit ports */

#define SIO_UNIT_SEL	0x7	/* unit select reg */
#define SIO_UNIT_ACT	0x30	/* unit enable */
#define SIO_GPIO_UNIT	0x7	/* unit number of GPIO */
#define SIO_VLM_UNIT	0x0D
#define SIO_TMS_UNIT	0x0E

/* config-space addrs to read/write each unit's runtime addr */
#define SIO_BASE_HADDR		0x60
#define SIO_BASE_LADDR		0x61

/* GPIO config-space pin-control addresses */
#define SIO_GPIO_PIN_SELECT	0xF0
#define SIO_GPIO_PIN_CONFIG     0xF1
#define SIO_GPIO_PIN_EVENT      0xF2

static unsigned char superio_cmd = 0;
static unsigned char selected_device = 0xFF;	/* bogus start val */

/* GPIO port runtime access, functionality */
static int port_offset[] = { 0, 4, 8, 10 };	/* non-uniform offsets ! */
/* static int event_capable[] = { 1, 1, 0, 0 };   ports 2,3 are hobbled */

#define PORT_OUT	0
#define PORT_IN		1
#define PORT_EVT_EN	2
#define PORT_EVT_STST	3

static struct platform_device *pdev;  /* use in dev_*() */

static inline void superio_outb(int addr, int val)
{
	outb_p(addr, superio_cmd);
	outb_p(val, superio_cmd + 1);
}

static inline int superio_inb(int addr)
{
	outb_p(addr, superio_cmd);
	return inb_p(superio_cmd + 1);
}

static int pc8736x_superio_present(void)
{
	/* try the 2 possible values, read a hardware reg to verify */
	superio_cmd = SIO_BASE1;
	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
		return superio_cmd;

	superio_cmd = SIO_BASE2;
	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
		return superio_cmd;

	return 0;
}

static void device_select(unsigned devldn)
{
	superio_outb(SIO_UNIT_SEL, devldn);
	selected_device = devldn;
}

static void select_pin(unsigned iminor)
{
	/* select GPIO port/pin from device minor number */
	device_select(SIO_GPIO_UNIT);
	superio_outb(SIO_GPIO_PIN_SELECT,
		     ((iminor << 1) & 0xF0) | (iminor & 0x7));
}

static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
					    u32 func_slct)
{
	u32 config, new_config;

	mutex_lock(&pc8736x_gpio_config_lock);

	device_select(SIO_GPIO_UNIT);
	select_pin(index);

	/* read current config value */
	config = superio_inb(func_slct);

	/* set new config */
	new_config = (config & mask) | bits;
	superio_outb(func_slct, new_config);

	mutex_unlock(&pc8736x_gpio_config_lock);

	return config;
}

static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
{
	return pc8736x_gpio_configure_fn(index, mask, bits,
					 SIO_GPIO_PIN_CONFIG);
}

static int pc8736x_gpio_get(unsigned minor)
{
	int port, bit, val;

	port = minor >> 3;
	bit = minor & 7;
	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	val >>= bit;
	val &= 1;

	dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
		minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
		val);

	return val;
}

static void pc8736x_gpio_set(unsigned minor, int val)
{
	int port, bit, curval;

	minor &= 0x1f;
	port = minor >> 3;
	bit = minor & 7;
	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);

	dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
		pc8736x_gpio_base + port_offset[port] + PORT_OUT,
		curval, bit, (curval & ~(1 << bit)), val, (val << bit));

	val = (curval & ~(1 << bit)) | (val << bit);

	dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
		" %2x -> %2x\n", minor, port, bit, curval, val);

	outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);

	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);

	dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
	pc8736x_gpio_shadow[port] = val;
}

static int pc8736x_gpio_current(unsigned minor)
{
	int port, bit;
	minor &= 0x1f;
	port = minor >> 3;
	bit = minor & 7;
	return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
}

static void pc8736x_gpio_change(unsigned index)
{
	pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
}

static struct nsc_gpio_ops pc8736x_gpio_ops = {
	.owner		= THIS_MODULE,
	.gpio_config	= pc8736x_gpio_configure,
	.gpio_dump	= nsc_gpio_dump,
	.gpio_get	= pc8736x_gpio_get,
	.gpio_set	= pc8736x_gpio_set,
	.gpio_change	= pc8736x_gpio_change,
	.gpio_current	= pc8736x_gpio_current
};

static int pc8736x_gpio_open(struct inode *inode, struct file *file)
{
	unsigned m = iminor(inode);
	file->private_data = &pc8736x_gpio_ops;

	cycle_kernel_lock();
	dev_dbg(&pdev->dev, "open %d\n", m);

	if (m >= PC8736X_GPIO_CT)
		return -EINVAL;
	return nonseekable_open(inode, file);
}

static const struct file_operations pc8736x_gpio_fileops = {
	.owner	= THIS_MODULE,
	.open	= pc8736x_gpio_open,
	.write	= nsc_gpio_write,
	.read	= nsc_gpio_read,
};

static void __init pc8736x_init_shadow(void)
{
	int port;

	/* read the current values driven on the GPIO signals */
	for (port = 0; port < 4; ++port)
		pc8736x_gpio_shadow[port]
		    = inb_p(pc8736x_gpio_base + port_offset[port]
			    + PORT_OUT);

}

static struct cdev pc8736x_gpio_cdev;

static int __init pc8736x_gpio_init(void)
{
	int rc;
	dev_t devid;

	pdev = platform_device_alloc(DEVNAME, 0);
	if (!pdev)
		return -ENOMEM;

	rc = platform_device_add(pdev);
	if (rc) {
		rc = -ENODEV;
		goto undo_platform_dev_alloc;
	}
	dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");

	if (!pc8736x_superio_present()) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "no device found\n");
		goto undo_platform_dev_add;
	}
	pc8736x_gpio_ops.dev = &pdev->dev;

	/* Verify that chip and it's GPIO unit are both enabled.
	   My BIOS does this, so I take minimum action here
	 */
	rc = superio_inb(SIO_CF1);
	if (!(rc & 0x01)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "device not enabled\n");
		goto undo_platform_dev_add;
	}
	device_select(SIO_GPIO_UNIT);
	if (!superio_inb(SIO_UNIT_ACT)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "GPIO unit not enabled\n");
		goto undo_platform_dev_add;
	}

	/* read the GPIO unit base addr that chip responds to */
	pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
			     | superio_inb(SIO_BASE_LADDR));

	if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
		rc = -ENODEV;
		dev_err(&pdev->dev, "GPIO ioport %x busy\n",
			pc8736x_gpio_base);
		goto undo_platform_dev_add;
	}
	dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);

	if (major) {
		devid = MKDEV(major, 0);
		rc = register_chrdev_region(devid, PC8736X_GPIO_CT, DEVNAME);
	} else {
		rc = alloc_chrdev_region(&devid, 0, PC8736X_GPIO_CT, DEVNAME);
		major = MAJOR(devid);
	}

	if (rc < 0) {
		dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
		goto undo_request_region;
	}
	if (!major) {
		major = rc;
		dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
	}

	pc8736x_init_shadow();

	/* ignore minor errs, and succeed */
	cdev_init(&pc8736x_gpio_cdev, &pc8736x_gpio_fileops);
	cdev_add(&pc8736x_gpio_cdev, devid, PC8736X_GPIO_CT);

	return 0;

undo_request_region:
	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
undo_platform_dev_add:
	platform_device_del(pdev);
undo_platform_dev_alloc:
	platform_device_put(pdev);

	return rc;
}

static void __exit pc8736x_gpio_cleanup(void)
{
	dev_dbg(&pdev->dev, "cleanup\n");

	cdev_del(&pc8736x_gpio_cdev);
	unregister_chrdev_region(MKDEV(major,0), PC8736X_GPIO_CT);
	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);

	platform_device_del(pdev);
	platform_device_put(pdev);
}

module_init(pc8736x_gpio_init);
module_exit(pc8736x_gpio_cleanup);
Commit	Line	Data
681a3e7d JC	1	/* linux/drivers/char/pc8736x_gpio.c
	2
	3	National Semiconductor PC8736x GPIO driver. Allows a user space
	4	process to play with the GPIO pins.
	5
27385085	6	Copyright (c) 2005,2006 Jim Cromie <jim.cromie@gmail.com>
681a3e7d JC	7
	8	adapted from linux/drivers/char/scx200_gpio.c
	9	Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
	10	*/
	11
681a3e7d JC	12	#include <linux/fs.h>
	13	#include <linux/module.h>
	14	#include <linux/errno.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
27385085	17	#include <linux/cdev.h>
ec312310	18	#include <linux/io.h>
681a3e7d	19	#include <linux/ioport.h>
8bcf6135	20	#include <linux/mutex.h>
681a3e7d	21	#include <linux/nsc_gpio.h>
58b087cd	22	#include <linux/platform_device.h>
f2b9857e	23	#include <linux/smp_lock.h>
681a3e7d	24	#include <asm/uaccess.h>
681a3e7d	25
58b087cd	26	#define DEVNAME "pc8736x_gpio"
681a3e7d JC	27
681a3e7d JC	28	MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
4f197842	29	MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
681a3e7d JC	30	MODULE_LICENSE("GPL");
	31
	32	static int major; /* default to dynamic major */
	33	module_param(major, int, 0);
	34	MODULE_PARM_DESC(major, "Major device number");
	35
8bcf6135	36	static DEFINE_MUTEX(pc8736x_gpio_config_lock);
681a3e7d	37	static unsigned pc8736x_gpio_base;
6cad56fd	38	static u8 pc8736x_gpio_shadow[4];
681a3e7d JC	39
	40	#define SIO_BASE1 0x2E /* 1st command-reg to check */
	41	#define SIO_BASE2 0x4E /* alt command-reg to check */
681a3e7d JC	42
	43	#define SIO_SID 0x20 /* SuperI/O ID Register */
	44	#define SIO_SID_VALUE 0xe9 /* Expected value in SuperI/O ID Register */
	45
	46	#define SIO_CF1 0x21 /* chip config, bit0 is chip enable */
	47
4f197842 JC	48	#define PC8736X_GPIO_RANGE 16 /* ioaddr range */
4f197842 JC	49	#define PC8736X_GPIO_CT 32 /* minors matching 4 8 bit ports */
58b087cd	50
681a3e7d JC	51	#define SIO_UNIT_SEL 0x7 /* unit select reg */
	52	#define SIO_UNIT_ACT 0x30 /* unit enable */
	53	#define SIO_GPIO_UNIT 0x7 /* unit number of GPIO */
	54	#define SIO_VLM_UNIT 0x0D
	55	#define SIO_TMS_UNIT 0x0E
	56
	57	/* config-space addrs to read/write each unit's runtime addr */
	58	#define SIO_BASE_HADDR 0x60
	59	#define SIO_BASE_LADDR 0x61
	60
	61	/* GPIO config-space pin-control addresses */
	62	#define SIO_GPIO_PIN_SELECT 0xF0
	63	#define SIO_GPIO_PIN_CONFIG 0xF1
	64	#define SIO_GPIO_PIN_EVENT 0xF2
	65
	66	static unsigned char superio_cmd = 0;
	67	static unsigned char selected_device = 0xFF; /* bogus start val */
	68
	69	/* GPIO port runtime access, functionality */
	70	static int port_offset[] = { 0, 4, 8, 10 }; /* non-uniform offsets ! */
	71	/* static int event_capable[] = { 1, 1, 0, 0 }; ports 2,3 are hobbled */
	72
	73	#define PORT_OUT 0
	74	#define PORT_IN 1
	75	#define PORT_EVT_EN 2
	76	#define PORT_EVT_STST 3
	77
58b087cd JC	78	static struct platform_device pdev; / use in dev_() /
58b087cd JC	79
681a3e7d JC	80	static inline void superio_outb(int addr, int val)
	81	{
	82	outb_p(addr, superio_cmd);
	83	outb_p(val, superio_cmd + 1);
	84	}
	85
	86	static inline int superio_inb(int addr)
	87	{
	88	outb_p(addr, superio_cmd);
	89	return inb_p(superio_cmd + 1);
	90	}
	91
	92	static int pc8736x_superio_present(void)
	93	{
	94	/* try the 2 possible values, read a hardware reg to verify */
	95	superio_cmd = SIO_BASE1;
	96	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
	97	return superio_cmd;
	98
	99	superio_cmd = SIO_BASE2;
	100	if (superio_inb(SIO_SID) == SIO_SID_VALUE)
	101	return superio_cmd;
	102
	103	return 0;
	104	}
	105
	106	static void device_select(unsigned devldn)
	107	{
	108	superio_outb(SIO_UNIT_SEL, devldn);
	109	selected_device = devldn;
	110	}
	111
	112	static void select_pin(unsigned iminor)
	113	{
	114	/* select GPIO port/pin from device minor number */
	115	device_select(SIO_GPIO_UNIT);
	116	superio_outb(SIO_GPIO_PIN_SELECT,
	117	((iminor << 1) & 0xF0) \| (iminor & 0x7));
	118	}
	119
	120	static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
	121	u32 func_slct)
	122	{
	123	u32 config, new_config;
681a3e7d	124
8bcf6135	125	mutex_lock(&pc8736x_gpio_config_lock);
681a3e7d JC	126
	127	device_select(SIO_GPIO_UNIT);
	128	select_pin(index);
	129
	130	/* read current config value */
	131	config = superio_inb(func_slct);
	132
	133	/* set new config */
	134	new_config = (config & mask) \| bits;
	135	superio_outb(func_slct, new_config);
	136
8bcf6135	137	mutex_unlock(&pc8736x_gpio_config_lock);
681a3e7d JC	138
	139	return config;
	140	}
	141
	142	static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
	143	{
	144	return pc8736x_gpio_configure_fn(index, mask, bits,
	145	SIO_GPIO_PIN_CONFIG);
	146	}
	147
	148	static int pc8736x_gpio_get(unsigned minor)
	149	{
	150	int port, bit, val;
	151
	152	port = minor >> 3;
	153	bit = minor & 7;
	154	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	155	val >>= bit;
	156	val &= 1;
	157
58b087cd JC	158	dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
	159	minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
	160	val);
681a3e7d JC	161
	162	return val;
	163	}
	164
	165	static void pc8736x_gpio_set(unsigned minor, int val)
	166	{
	167	int port, bit, curval;
	168
	169	minor &= 0x1f;
	170	port = minor >> 3;
	171	bit = minor & 7;
	172	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	173
58b087cd JC	174	dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
	175	pc8736x_gpio_base + port_offset[port] + PORT_OUT,
	176	curval, bit, (curval & ~(1 << bit)), val, (val << bit));
681a3e7d JC	177
	178	val = (curval & ~(1 << bit)) \| (val << bit);
	179
58b087cd JC	180	dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
58b087cd JC	181	" %2x -> %2x\n", minor, port, bit, curval, val);
681a3e7d JC	182
	183	outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	184
	185	curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
	186	val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
	187
58b087cd	188	dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
6cad56fd	189	pc8736x_gpio_shadow[port] = val;
681a3e7d JC	190	}
681a3e7d JC	191
6cad56fd	192	static int pc8736x_gpio_current(unsigned minor)
681a3e7d	193	{
6cad56fd JC	194	int port, bit;
	195	minor &= 0x1f;
	196	port = minor >> 3;
	197	bit = minor & 7;
	198	return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
681a3e7d JC	199	}
	200
	201	static void pc8736x_gpio_change(unsigned index)
	202	{
6cad56fd	203	pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
681a3e7d JC	204	}
681a3e7d JC	205
2e8f7a31	206	static struct nsc_gpio_ops pc8736x_gpio_ops = {
681a3e7d JC	207	.owner = THIS_MODULE,
	208	.gpio_config = pc8736x_gpio_configure,
	209	.gpio_dump = nsc_gpio_dump,
	210	.gpio_get = pc8736x_gpio_get,
	211	.gpio_set = pc8736x_gpio_set,
681a3e7d JC	212	.gpio_change = pc8736x_gpio_change,
	213	.gpio_current = pc8736x_gpio_current
	214	};
	215
	216	static int pc8736x_gpio_open(struct inode inode, struct file file)
	217	{
	218	unsigned m = iminor(inode);
2e8f7a31	219	file->private_data = &pc8736x_gpio_ops;
681a3e7d	220
f2b9857e	221	cycle_kernel_lock();
58b087cd	222	dev_dbg(&pdev->dev, "open %d\n", m);
681a3e7d	223
4f197842	224	if (m >= PC8736X_GPIO_CT)
681a3e7d JC	225	return -EINVAL;
	226	return nonseekable_open(inode, file);
	227	}
	228
2e8f7a31	229	static const struct file_operations pc8736x_gpio_fileops = {
58b087cd JC	230	.owner = THIS_MODULE,
	231	.open = pc8736x_gpio_open,
	232	.write = nsc_gpio_write,
	233	.read = nsc_gpio_read,
681a3e7d JC	234	};
681a3e7d JC	235
6cad56fd JC	236	static void __init pc8736x_init_shadow(void)
	237	{
	238	int port;
	239
	240	/* read the current values driven on the GPIO signals */
	241	for (port = 0; port < 4; ++port)
	242	pc8736x_gpio_shadow[port]
	243	= inb_p(pc8736x_gpio_base + port_offset[port]
	244	+ PORT_OUT);
	245
	246	}
	247
27385085 JC	248	static struct cdev pc8736x_gpio_cdev;
27385085 JC	249
681a3e7d JC	250	static int __init pc8736x_gpio_init(void)
681a3e7d JC	251	{
babcfade JC	252	int rc;
babcfade JC	253	dev_t devid;
58b087cd JC	254
	255	pdev = platform_device_alloc(DEVNAME, 0);
	256	if (!pdev)
	257	return -ENOMEM;
681a3e7d	258
58b087cd JC	259	rc = platform_device_add(pdev);
	260	if (rc) {
	261	rc = -ENODEV;
	262	goto undo_platform_dev_alloc;
	263	}
	264	dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");
681a3e7d JC	265
681a3e7d JC	266	if (!pc8736x_superio_present()) {
58b087cd JC	267	rc = -ENODEV;
	268	dev_err(&pdev->dev, "no device found\n");
	269	goto undo_platform_dev_add;
681a3e7d	270	}
2e8f7a31	271	pc8736x_gpio_ops.dev = &pdev->dev;
681a3e7d JC	272
	273	/* Verify that chip and it's GPIO unit are both enabled.
	274	My BIOS does this, so I take minimum action here
	275	*/
	276	rc = superio_inb(SIO_CF1);
	277	if (!(rc & 0x01)) {
58b087cd JC	278	rc = -ENODEV;
	279	dev_err(&pdev->dev, "device not enabled\n");
	280	goto undo_platform_dev_add;
681a3e7d JC	281	}
	282	device_select(SIO_GPIO_UNIT);
	283	if (!superio_inb(SIO_UNIT_ACT)) {
58b087cd JC	284	rc = -ENODEV;
	285	dev_err(&pdev->dev, "GPIO unit not enabled\n");
	286	goto undo_platform_dev_add;
681a3e7d JC	287	}
681a3e7d JC	288
58b087cd	289	/* read the GPIO unit base addr that chip responds to */
681a3e7d JC	290	pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
	291	\| superio_inb(SIO_BASE_LADDR));
	292
4f197842	293	if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
58b087cd JC	294	rc = -ENODEV;
	295	dev_err(&pdev->dev, "GPIO ioport %x busy\n",
	296	pc8736x_gpio_base);
	297	goto undo_platform_dev_add;
	298	}
	299	dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);
681a3e7d	300
babcfade JC	301	if (major) {
	302	devid = MKDEV(major, 0);
	303	rc = register_chrdev_region(devid, PC8736X_GPIO_CT, DEVNAME);
	304	} else {
	305	rc = alloc_chrdev_region(&devid, 0, PC8736X_GPIO_CT, DEVNAME);
	306	major = MAJOR(devid);
	307	}
	308
58b087cd JC	309	if (rc < 0) {
58b087cd JC	310	dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
27385085	311	goto undo_request_region;
681a3e7d JC	312	}
681a3e7d JC	313	if (!major) {
58b087cd JC	314	major = rc;
58b087cd JC	315	dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
681a3e7d JC	316	}
	317
	318	pc8736x_init_shadow();
babcfade JC	319
babcfade JC	320	/* ignore minor errs, and succeed */
2e8f7a31	321	cdev_init(&pc8736x_gpio_cdev, &pc8736x_gpio_fileops);
babcfade JC	322	cdev_add(&pc8736x_gpio_cdev, devid, PC8736X_GPIO_CT);
babcfade JC	323
681a3e7d	324	return 0;
58b087cd	325
27385085 JC	326	undo_request_region:
27385085 JC	327	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
58b087cd	328	undo_platform_dev_add:
1017f6af	329	platform_device_del(pdev);
58b087cd	330	undo_platform_dev_alloc:
1017f6af IM	331	platform_device_put(pdev);
1017f6af IM	332
58b087cd	333	return rc;
681a3e7d JC	334	}
	335
	336	static void __exit pc8736x_gpio_cleanup(void)
	337	{
27385085	338	dev_dbg(&pdev->dev, "cleanup\n");
681a3e7d	339
27385085 JC	340	cdev_del(&pc8736x_gpio_cdev);
	341	unregister_chrdev_region(MKDEV(major,0), PC8736X_GPIO_CT);
	342	release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
681a3e7d	343
27385085 JC	344	platform_device_del(pdev);
27385085 JC	345	platform_device_put(pdev);
681a3e7d JC	346	}
	347
	348	module_init(pc8736x_gpio_init);
	349	module_exit(pc8736x_gpio_cleanup);