Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/pcmcia/synclink_cs.c | |
3 | * | |
a7482a2e | 4 | * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $ |
1da177e4 LT |
5 | * |
6 | * Device driver for Microgate SyncLink PC Card | |
7 | * multiprotocol serial adapter. | |
8 | * | |
9 | * written by Paul Fulghum for Microgate Corporation | |
10 | * paulkf@microgate.com | |
11 | * | |
12 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
13 | * | |
14 | * This code is released under the GNU General Public License (GPL) | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
18 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
19 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
20 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
22 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
24 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
26 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
27 | */ | |
28 | ||
29 | #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) | |
30 | #if defined(__i386__) | |
31 | # define BREAKPOINT() asm(" int $3"); | |
32 | #else | |
33 | # define BREAKPOINT() { } | |
34 | #endif | |
35 | ||
36 | #define MAX_DEVICE_COUNT 4 | |
37 | ||
1da177e4 LT |
38 | #include <linux/module.h> |
39 | #include <linux/errno.h> | |
40 | #include <linux/signal.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/timer.h> | |
43 | #include <linux/time.h> | |
44 | #include <linux/interrupt.h> | |
1da177e4 LT |
45 | #include <linux/tty.h> |
46 | #include <linux/tty_flip.h> | |
47 | #include <linux/serial.h> | |
48 | #include <linux/major.h> | |
49 | #include <linux/string.h> | |
50 | #include <linux/fcntl.h> | |
51 | #include <linux/ptrace.h> | |
52 | #include <linux/ioport.h> | |
53 | #include <linux/mm.h> | |
87687144 | 54 | #include <linux/seq_file.h> |
1da177e4 LT |
55 | #include <linux/slab.h> |
56 | #include <linux/netdevice.h> | |
57 | #include <linux/vmalloc.h> | |
58 | #include <linux/init.h> | |
1da177e4 LT |
59 | #include <linux/delay.h> |
60 | #include <linux/ioctl.h> | |
3dd1247f | 61 | #include <linux/synclink.h> |
1da177e4 | 62 | |
1da177e4 LT |
63 | #include <asm/io.h> |
64 | #include <asm/irq.h> | |
65 | #include <asm/dma.h> | |
66 | #include <linux/bitops.h> | |
67 | #include <asm/types.h> | |
68 | #include <linux/termios.h> | |
69 | #include <linux/workqueue.h> | |
70 | #include <linux/hdlc.h> | |
71 | ||
1da177e4 LT |
72 | #include <pcmcia/cistpl.h> |
73 | #include <pcmcia/cisreg.h> | |
74 | #include <pcmcia/ds.h> | |
75 | ||
af69c7f9 PF |
76 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE)) |
77 | #define SYNCLINK_GENERIC_HDLC 1 | |
78 | #else | |
79 | #define SYNCLINK_GENERIC_HDLC 0 | |
1da177e4 LT |
80 | #endif |
81 | ||
82 | #define GET_USER(error,value,addr) error = get_user(value,addr) | |
83 | #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 | |
84 | #define PUT_USER(error,value,addr) error = put_user(value,addr) | |
85 | #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 | |
86 | ||
87 | #include <asm/uaccess.h> | |
88 | ||
1da177e4 LT |
89 | static MGSL_PARAMS default_params = { |
90 | MGSL_MODE_HDLC, /* unsigned long mode */ | |
91 | 0, /* unsigned char loopback; */ | |
92 | HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ | |
93 | HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ | |
94 | 0, /* unsigned long clock_speed; */ | |
95 | 0xff, /* unsigned char addr_filter; */ | |
96 | HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ | |
97 | HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ | |
98 | HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ | |
99 | 9600, /* unsigned long data_rate; */ | |
100 | 8, /* unsigned char data_bits; */ | |
101 | 1, /* unsigned char stop_bits; */ | |
102 | ASYNC_PARITY_NONE /* unsigned char parity; */ | |
103 | }; | |
104 | ||
105 | typedef struct | |
106 | { | |
107 | int count; | |
108 | unsigned char status; | |
109 | char data[1]; | |
110 | } RXBUF; | |
111 | ||
112 | /* The queue of BH actions to be performed */ | |
113 | ||
114 | #define BH_RECEIVE 1 | |
115 | #define BH_TRANSMIT 2 | |
116 | #define BH_STATUS 4 | |
117 | ||
118 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
119 | ||
120 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
121 | ||
122 | struct _input_signal_events { | |
d12341f9 | 123 | int ri_up; |
1da177e4 LT |
124 | int ri_down; |
125 | int dsr_up; | |
126 | int dsr_down; | |
127 | int dcd_up; | |
128 | int dcd_down; | |
129 | int cts_up; | |
130 | int cts_down; | |
131 | }; | |
132 | ||
133 | ||
134 | /* | |
135 | * Device instance data structure | |
136 | */ | |
d12341f9 | 137 | |
1da177e4 | 138 | typedef struct _mgslpc_info { |
eeb46134 | 139 | struct tty_port port; |
1da177e4 LT |
140 | void *if_ptr; /* General purpose pointer (used by SPPP) */ |
141 | int magic; | |
1da177e4 | 142 | int line; |
d12341f9 | 143 | |
1da177e4 | 144 | struct mgsl_icount icount; |
d12341f9 | 145 | |
1da177e4 LT |
146 | int timeout; |
147 | int x_char; /* xon/xoff character */ | |
1da177e4 | 148 | unsigned char read_status_mask; |
d12341f9 | 149 | unsigned char ignore_status_mask; |
1da177e4 LT |
150 | |
151 | unsigned char *tx_buf; | |
152 | int tx_put; | |
153 | int tx_get; | |
154 | int tx_count; | |
155 | ||
156 | /* circular list of fixed length rx buffers */ | |
157 | ||
158 | unsigned char *rx_buf; /* memory allocated for all rx buffers */ | |
159 | int rx_buf_total_size; /* size of memory allocated for rx buffers */ | |
160 | int rx_put; /* index of next empty rx buffer */ | |
161 | int rx_get; /* index of next full rx buffer */ | |
162 | int rx_buf_size; /* size in bytes of single rx buffer */ | |
163 | int rx_buf_count; /* total number of rx buffers */ | |
164 | int rx_frame_count; /* number of full rx buffers */ | |
d12341f9 | 165 | |
1da177e4 LT |
166 | wait_queue_head_t status_event_wait_q; |
167 | wait_queue_head_t event_wait_q; | |
168 | struct timer_list tx_timer; /* HDLC transmit timeout timer */ | |
169 | struct _mgslpc_info *next_device; /* device list link */ | |
170 | ||
171 | unsigned short imra_value; | |
172 | unsigned short imrb_value; | |
173 | unsigned char pim_value; | |
174 | ||
175 | spinlock_t lock; | |
176 | struct work_struct task; /* task structure for scheduling bh */ | |
177 | ||
178 | u32 max_frame_size; | |
179 | ||
180 | u32 pending_bh; | |
181 | ||
0fab6de0 JP |
182 | bool bh_running; |
183 | bool bh_requested; | |
d12341f9 | 184 | |
1da177e4 LT |
185 | int dcd_chkcount; /* check counts to prevent */ |
186 | int cts_chkcount; /* too many IRQs if a signal */ | |
187 | int dsr_chkcount; /* is floating */ | |
188 | int ri_chkcount; | |
189 | ||
0fab6de0 JP |
190 | bool rx_enabled; |
191 | bool rx_overflow; | |
1da177e4 | 192 | |
0fab6de0 JP |
193 | bool tx_enabled; |
194 | bool tx_active; | |
195 | bool tx_aborting; | |
1da177e4 LT |
196 | u32 idle_mode; |
197 | ||
198 | int if_mode; /* serial interface selection (RS-232, v.35 etc) */ | |
199 | ||
200 | char device_name[25]; /* device instance name */ | |
201 | ||
202 | unsigned int io_base; /* base I/O address of adapter */ | |
203 | unsigned int irq_level; | |
d12341f9 | 204 | |
1da177e4 LT |
205 | MGSL_PARAMS params; /* communications parameters */ |
206 | ||
207 | unsigned char serial_signals; /* current serial signal states */ | |
208 | ||
0fab6de0 | 209 | bool irq_occurred; /* for diagnostics use */ |
1da177e4 LT |
210 | char testing_irq; |
211 | unsigned int init_error; /* startup error (DIAGS) */ | |
212 | ||
213 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | |
0fab6de0 | 214 | bool drop_rts_on_tx_done; |
1da177e4 LT |
215 | |
216 | struct _input_signal_events input_signal_events; | |
217 | ||
218 | /* PCMCIA support */ | |
fd238232 | 219 | struct pcmcia_device *p_dev; |
1da177e4 LT |
220 | int stop; |
221 | ||
222 | /* SPPP/Cisco HDLC device parts */ | |
223 | int netcount; | |
1da177e4 LT |
224 | spinlock_t netlock; |
225 | ||
af69c7f9 | 226 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
227 | struct net_device *netdev; |
228 | #endif | |
229 | ||
230 | } MGSLPC_INFO; | |
231 | ||
232 | #define MGSLPC_MAGIC 0x5402 | |
233 | ||
234 | /* | |
235 | * The size of the serial xmit buffer is 1 page, or 4096 bytes | |
236 | */ | |
237 | #define TXBUFSIZE 4096 | |
238 | ||
d12341f9 | 239 | |
1da177e4 LT |
240 | #define CHA 0x00 /* channel A offset */ |
241 | #define CHB 0x40 /* channel B offset */ | |
242 | ||
243 | /* | |
244 | * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it. | |
245 | */ | |
246 | #undef PVR | |
247 | ||
248 | #define RXFIFO 0 | |
249 | #define TXFIFO 0 | |
250 | #define STAR 0x20 | |
251 | #define CMDR 0x20 | |
252 | #define RSTA 0x21 | |
253 | #define PRE 0x21 | |
254 | #define MODE 0x22 | |
255 | #define TIMR 0x23 | |
256 | #define XAD1 0x24 | |
257 | #define XAD2 0x25 | |
258 | #define RAH1 0x26 | |
259 | #define RAH2 0x27 | |
260 | #define DAFO 0x27 | |
261 | #define RAL1 0x28 | |
262 | #define RFC 0x28 | |
263 | #define RHCR 0x29 | |
264 | #define RAL2 0x29 | |
265 | #define RBCL 0x2a | |
266 | #define XBCL 0x2a | |
267 | #define RBCH 0x2b | |
268 | #define XBCH 0x2b | |
269 | #define CCR0 0x2c | |
270 | #define CCR1 0x2d | |
271 | #define CCR2 0x2e | |
272 | #define CCR3 0x2f | |
273 | #define VSTR 0x34 | |
274 | #define BGR 0x34 | |
275 | #define RLCR 0x35 | |
276 | #define AML 0x36 | |
277 | #define AMH 0x37 | |
278 | #define GIS 0x38 | |
279 | #define IVA 0x38 | |
280 | #define IPC 0x39 | |
281 | #define ISR 0x3a | |
282 | #define IMR 0x3a | |
283 | #define PVR 0x3c | |
284 | #define PIS 0x3d | |
285 | #define PIM 0x3d | |
286 | #define PCR 0x3e | |
287 | #define CCR4 0x3f | |
d12341f9 | 288 | |
1da177e4 | 289 | // IMR/ISR |
d12341f9 | 290 | |
1da177e4 LT |
291 | #define IRQ_BREAK_ON BIT15 // rx break detected |
292 | #define IRQ_DATAOVERRUN BIT14 // receive data overflow | |
293 | #define IRQ_ALLSENT BIT13 // all sent | |
294 | #define IRQ_UNDERRUN BIT12 // transmit data underrun | |
295 | #define IRQ_TIMER BIT11 // timer interrupt | |
296 | #define IRQ_CTS BIT10 // CTS status change | |
297 | #define IRQ_TXREPEAT BIT9 // tx message repeat | |
298 | #define IRQ_TXFIFO BIT8 // transmit pool ready | |
299 | #define IRQ_RXEOM BIT7 // receive message end | |
300 | #define IRQ_EXITHUNT BIT6 // receive frame start | |
301 | #define IRQ_RXTIME BIT6 // rx char timeout | |
302 | #define IRQ_DCD BIT2 // carrier detect status change | |
303 | #define IRQ_OVERRUN BIT1 // receive frame overflow | |
304 | #define IRQ_RXFIFO BIT0 // receive pool full | |
d12341f9 | 305 | |
1da177e4 | 306 | // STAR |
d12341f9 | 307 | |
1da177e4 LT |
308 | #define XFW BIT6 // transmit FIFO write enable |
309 | #define CEC BIT2 // command executing | |
310 | #define CTS BIT1 // CTS state | |
d12341f9 | 311 | |
1da177e4 LT |
312 | #define PVR_DTR BIT0 |
313 | #define PVR_DSR BIT1 | |
314 | #define PVR_RI BIT2 | |
315 | #define PVR_AUTOCTS BIT3 | |
316 | #define PVR_RS232 0x20 /* 0010b */ | |
317 | #define PVR_V35 0xe0 /* 1110b */ | |
318 | #define PVR_RS422 0x40 /* 0100b */ | |
d12341f9 JG |
319 | |
320 | /* Register access functions */ | |
321 | ||
1da177e4 LT |
322 | #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg)) |
323 | #define read_reg(info, reg) inb((info)->io_base + (reg)) | |
324 | ||
d12341f9 | 325 | #define read_reg16(info, reg) inw((info)->io_base + (reg)) |
1da177e4 | 326 | #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg)) |
d12341f9 | 327 | |
1da177e4 LT |
328 | #define set_reg_bits(info, reg, mask) \ |
329 | write_reg(info, (reg), \ | |
d12341f9 | 330 | (unsigned char) (read_reg(info, (reg)) | (mask))) |
1da177e4 LT |
331 | #define clear_reg_bits(info, reg, mask) \ |
332 | write_reg(info, (reg), \ | |
d12341f9 | 333 | (unsigned char) (read_reg(info, (reg)) & ~(mask))) |
1da177e4 LT |
334 | /* |
335 | * interrupt enable/disable routines | |
d12341f9 JG |
336 | */ |
337 | static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) | |
1da177e4 LT |
338 | { |
339 | if (channel == CHA) { | |
340 | info->imra_value |= mask; | |
341 | write_reg16(info, CHA + IMR, info->imra_value); | |
342 | } else { | |
343 | info->imrb_value |= mask; | |
344 | write_reg16(info, CHB + IMR, info->imrb_value); | |
345 | } | |
346 | } | |
d12341f9 | 347 | static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) |
1da177e4 LT |
348 | { |
349 | if (channel == CHA) { | |
350 | info->imra_value &= ~mask; | |
351 | write_reg16(info, CHA + IMR, info->imra_value); | |
352 | } else { | |
353 | info->imrb_value &= ~mask; | |
354 | write_reg16(info, CHB + IMR, info->imrb_value); | |
355 | } | |
356 | } | |
357 | ||
358 | #define port_irq_disable(info, mask) \ | |
359 | { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); } | |
360 | ||
361 | #define port_irq_enable(info, mask) \ | |
362 | { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); } | |
363 | ||
364 | static void rx_start(MGSLPC_INFO *info); | |
365 | static void rx_stop(MGSLPC_INFO *info); | |
366 | ||
eeb46134 | 367 | static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty); |
1da177e4 LT |
368 | static void tx_stop(MGSLPC_INFO *info); |
369 | static void tx_set_idle(MGSLPC_INFO *info); | |
370 | ||
371 | static void get_signals(MGSLPC_INFO *info); | |
372 | static void set_signals(MGSLPC_INFO *info); | |
373 | ||
374 | static void reset_device(MGSLPC_INFO *info); | |
375 | ||
376 | static void hdlc_mode(MGSLPC_INFO *info); | |
377 | static void async_mode(MGSLPC_INFO *info); | |
378 | ||
379 | static void tx_timeout(unsigned long context); | |
380 | ||
eeb46134 | 381 | static int carrier_raised(struct tty_port *port); |
fcc8ac18 | 382 | static void dtr_rts(struct tty_port *port, int onoff); |
1da177e4 | 383 | |
af69c7f9 | 384 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
385 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
386 | static void hdlcdev_tx_done(MGSLPC_INFO *info); | |
387 | static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size); | |
388 | static int hdlcdev_init(MGSLPC_INFO *info); | |
389 | static void hdlcdev_exit(MGSLPC_INFO *info); | |
390 | #endif | |
391 | ||
392 | static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit); | |
393 | ||
0fab6de0 JP |
394 | static bool register_test(MGSLPC_INFO *info); |
395 | static bool irq_test(MGSLPC_INFO *info); | |
1da177e4 LT |
396 | static int adapter_test(MGSLPC_INFO *info); |
397 | ||
398 | static int claim_resources(MGSLPC_INFO *info); | |
399 | static void release_resources(MGSLPC_INFO *info); | |
400 | static void mgslpc_add_device(MGSLPC_INFO *info); | |
401 | static void mgslpc_remove_device(MGSLPC_INFO *info); | |
402 | ||
eeb46134 | 403 | static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty); |
1da177e4 LT |
404 | static void rx_reset_buffers(MGSLPC_INFO *info); |
405 | static int rx_alloc_buffers(MGSLPC_INFO *info); | |
406 | static void rx_free_buffers(MGSLPC_INFO *info); | |
407 | ||
7d12e780 | 408 | static irqreturn_t mgslpc_isr(int irq, void *dev_id); |
1da177e4 LT |
409 | |
410 | /* | |
411 | * Bottom half interrupt handlers | |
412 | */ | |
c4028958 | 413 | static void bh_handler(struct work_struct *work); |
eeb46134 | 414 | static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty); |
1da177e4 LT |
415 | static void bh_status(MGSLPC_INFO *info); |
416 | ||
417 | /* | |
418 | * ioctl handlers | |
419 | */ | |
60b33c13 | 420 | static int tiocmget(struct tty_struct *tty); |
20b9d177 AC |
421 | static int tiocmset(struct tty_struct *tty, |
422 | unsigned int set, unsigned int clear); | |
1da177e4 LT |
423 | static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount); |
424 | static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params); | |
eeb46134 | 425 | static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty); |
1da177e4 LT |
426 | static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode); |
427 | static int set_txidle(MGSLPC_INFO *info, int idle_mode); | |
eeb46134 | 428 | static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty); |
1da177e4 LT |
429 | static int tx_abort(MGSLPC_INFO *info); |
430 | static int set_rxenable(MGSLPC_INFO *info, int enable); | |
431 | static int wait_events(MGSLPC_INFO *info, int __user *mask); | |
432 | ||
433 | static MGSLPC_INFO *mgslpc_device_list = NULL; | |
434 | static int mgslpc_device_count = 0; | |
435 | ||
436 | /* | |
437 | * Set this param to non-zero to load eax with the | |
438 | * .text section address and breakpoint on module load. | |
439 | * This is useful for use with gdb and add-symbol-file command. | |
440 | */ | |
90ab5ee9 | 441 | static bool break_on_load=0; |
1da177e4 LT |
442 | |
443 | /* | |
444 | * Driver major number, defaults to zero to get auto | |
445 | * assigned major number. May be forced as module parameter. | |
446 | */ | |
447 | static int ttymajor=0; | |
448 | ||
449 | static int debug_level = 0; | |
450 | static int maxframe[MAX_DEVICE_COUNT] = {0,}; | |
1da177e4 LT |
451 | |
452 | module_param(break_on_load, bool, 0); | |
453 | module_param(ttymajor, int, 0); | |
454 | module_param(debug_level, int, 0); | |
455 | module_param_array(maxframe, int, NULL, 0); | |
1da177e4 LT |
456 | |
457 | MODULE_LICENSE("GPL"); | |
458 | ||
459 | static char *driver_name = "SyncLink PC Card driver"; | |
a7482a2e | 460 | static char *driver_version = "$Revision: 4.34 $"; |
1da177e4 LT |
461 | |
462 | static struct tty_driver *serial_driver; | |
463 | ||
464 | /* number of characters left in xmit buffer before we ask for more */ | |
465 | #define WAKEUP_CHARS 256 | |
466 | ||
eeb46134 | 467 | static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty); |
1da177e4 LT |
468 | static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout); |
469 | ||
470 | /* PCMCIA prototypes */ | |
471 | ||
15b99ac1 | 472 | static int mgslpc_config(struct pcmcia_device *link); |
1da177e4 | 473 | static void mgslpc_release(u_long arg); |
cc3b4866 | 474 | static void mgslpc_detach(struct pcmcia_device *p_dev); |
1da177e4 | 475 | |
1da177e4 LT |
476 | /* |
477 | * 1st function defined in .text section. Calling this function in | |
478 | * init_module() followed by a breakpoint allows a remote debugger | |
479 | * (gdb) to get the .text address for the add-symbol-file command. | |
480 | * This allows remote debugging of dynamically loadable modules. | |
481 | */ | |
482 | static void* mgslpc_get_text_ptr(void) | |
483 | { | |
484 | return mgslpc_get_text_ptr; | |
485 | } | |
486 | ||
487 | /** | |
488 | * line discipline callback wrappers | |
489 | * | |
490 | * The wrappers maintain line discipline references | |
491 | * while calling into the line discipline. | |
492 | * | |
1da177e4 LT |
493 | * ldisc_receive_buf - pass receive data to line discipline |
494 | */ | |
495 | ||
1da177e4 LT |
496 | static void ldisc_receive_buf(struct tty_struct *tty, |
497 | const __u8 *data, char *flags, int count) | |
498 | { | |
499 | struct tty_ldisc *ld; | |
500 | if (!tty) | |
501 | return; | |
502 | ld = tty_ldisc_ref(tty); | |
503 | if (ld) { | |
a352def2 AC |
504 | if (ld->ops->receive_buf) |
505 | ld->ops->receive_buf(tty, data, flags, count); | |
1da177e4 LT |
506 | tty_ldisc_deref(ld); |
507 | } | |
508 | } | |
509 | ||
eeb46134 AC |
510 | static const struct tty_port_operations mgslpc_port_ops = { |
511 | .carrier_raised = carrier_raised, | |
fcc8ac18 | 512 | .dtr_rts = dtr_rts |
eeb46134 AC |
513 | }; |
514 | ||
15b99ac1 | 515 | static int mgslpc_probe(struct pcmcia_device *link) |
1da177e4 LT |
516 | { |
517 | MGSLPC_INFO *info; | |
15b99ac1 | 518 | int ret; |
fd238232 | 519 | |
1da177e4 LT |
520 | if (debug_level >= DEBUG_LEVEL_INFO) |
521 | printk("mgslpc_attach\n"); | |
fd238232 | 522 | |
dd00cc48 | 523 | info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL); |
1da177e4 LT |
524 | if (!info) { |
525 | printk("Error can't allocate device instance data\n"); | |
f8cfa618 | 526 | return -ENOMEM; |
1da177e4 LT |
527 | } |
528 | ||
1da177e4 | 529 | info->magic = MGSLPC_MAGIC; |
eeb46134 AC |
530 | tty_port_init(&info->port); |
531 | info->port.ops = &mgslpc_port_ops; | |
c4028958 | 532 | INIT_WORK(&info->task, bh_handler); |
1da177e4 | 533 | info->max_frame_size = 4096; |
eeb46134 AC |
534 | info->port.close_delay = 5*HZ/10; |
535 | info->port.closing_wait = 30*HZ; | |
1da177e4 LT |
536 | init_waitqueue_head(&info->status_event_wait_q); |
537 | init_waitqueue_head(&info->event_wait_q); | |
538 | spin_lock_init(&info->lock); | |
539 | spin_lock_init(&info->netlock); | |
540 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
d12341f9 | 541 | info->idle_mode = HDLC_TXIDLE_FLAGS; |
1da177e4 LT |
542 | info->imra_value = 0xffff; |
543 | info->imrb_value = 0xffff; | |
544 | info->pim_value = 0xff; | |
545 | ||
fba395ee | 546 | info->p_dev = link; |
1da177e4 | 547 | link->priv = info; |
fd238232 | 548 | |
fba395ee | 549 | /* Initialize the struct pcmcia_device structure */ |
1da177e4 | 550 | |
15b99ac1 DB |
551 | ret = mgslpc_config(link); |
552 | if (ret) | |
553 | return ret; | |
1da177e4 LT |
554 | |
555 | mgslpc_add_device(info); | |
556 | ||
f8cfa618 | 557 | return 0; |
1da177e4 LT |
558 | } |
559 | ||
560 | /* Card has been inserted. | |
561 | */ | |
562 | ||
00990e7c | 563 | static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data) |
aaa8cfda | 564 | { |
90abdc3b | 565 | return pcmcia_request_io(p_dev); |
aaa8cfda DB |
566 | } |
567 | ||
15b99ac1 | 568 | static int mgslpc_config(struct pcmcia_device *link) |
1da177e4 | 569 | { |
1da177e4 | 570 | MGSLPC_INFO *info = link->priv; |
cbf624f0 | 571 | int ret; |
d12341f9 | 572 | |
1da177e4 LT |
573 | if (debug_level >= DEBUG_LEVEL_INFO) |
574 | printk("mgslpc_config(0x%p)\n", link); | |
575 | ||
00990e7c DB |
576 | link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO; |
577 | ||
cbf624f0 DB |
578 | ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL); |
579 | if (ret != 0) | |
580 | goto failed; | |
1da177e4 | 581 | |
7feabb64 DB |
582 | link->config_index = 8; |
583 | link->config_regs = PRESENT_OPTION; | |
d12341f9 | 584 | |
eb14120f | 585 | ret = pcmcia_request_irq(link, mgslpc_isr); |
cbf624f0 DB |
586 | if (ret) |
587 | goto failed; | |
1ac71e5a | 588 | ret = pcmcia_enable_device(link); |
cbf624f0 DB |
589 | if (ret) |
590 | goto failed; | |
1da177e4 | 591 | |
9a017a91 | 592 | info->io_base = link->resource[0]->start; |
eb14120f | 593 | info->irq_level = link->irq; |
15b99ac1 | 594 | return 0; |
1da177e4 | 595 | |
cbf624f0 | 596 | failed: |
1da177e4 | 597 | mgslpc_release((u_long)link); |
15b99ac1 | 598 | return -ENODEV; |
1da177e4 LT |
599 | } |
600 | ||
601 | /* Card has been removed. | |
602 | * Unregister device and release PCMCIA configuration. | |
603 | * If device is open, postpone until it is closed. | |
604 | */ | |
605 | static void mgslpc_release(u_long arg) | |
606 | { | |
e2d40963 | 607 | struct pcmcia_device *link = (struct pcmcia_device *)arg; |
1da177e4 | 608 | |
e2d40963 DB |
609 | if (debug_level >= DEBUG_LEVEL_INFO) |
610 | printk("mgslpc_release(0x%p)\n", link); | |
1da177e4 | 611 | |
e2d40963 | 612 | pcmcia_disable_device(link); |
1da177e4 LT |
613 | } |
614 | ||
fba395ee | 615 | static void mgslpc_detach(struct pcmcia_device *link) |
1da177e4 | 616 | { |
e2d40963 DB |
617 | if (debug_level >= DEBUG_LEVEL_INFO) |
618 | printk("mgslpc_detach(0x%p)\n", link); | |
cc3b4866 | 619 | |
e2d40963 DB |
620 | ((MGSLPC_INFO *)link->priv)->stop = 1; |
621 | mgslpc_release((u_long)link); | |
1da177e4 | 622 | |
e2d40963 | 623 | mgslpc_remove_device((MGSLPC_INFO *)link->priv); |
1da177e4 LT |
624 | } |
625 | ||
fba395ee | 626 | static int mgslpc_suspend(struct pcmcia_device *link) |
98e4c28b | 627 | { |
98e4c28b DB |
628 | MGSLPC_INFO *info = link->priv; |
629 | ||
98e4c28b | 630 | info->stop = 1; |
98e4c28b DB |
631 | |
632 | return 0; | |
633 | } | |
634 | ||
fba395ee | 635 | static int mgslpc_resume(struct pcmcia_device *link) |
98e4c28b | 636 | { |
98e4c28b DB |
637 | MGSLPC_INFO *info = link->priv; |
638 | ||
98e4c28b DB |
639 | info->stop = 0; |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | ||
0fab6de0 | 645 | static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info, |
1da177e4 LT |
646 | char *name, const char *routine) |
647 | { | |
648 | #ifdef MGSLPC_PARANOIA_CHECK | |
649 | static const char *badmagic = | |
650 | "Warning: bad magic number for mgsl struct (%s) in %s\n"; | |
651 | static const char *badinfo = | |
652 | "Warning: null mgslpc_info for (%s) in %s\n"; | |
653 | ||
654 | if (!info) { | |
655 | printk(badinfo, name, routine); | |
0fab6de0 | 656 | return true; |
1da177e4 LT |
657 | } |
658 | if (info->magic != MGSLPC_MAGIC) { | |
659 | printk(badmagic, name, routine); | |
0fab6de0 | 660 | return true; |
1da177e4 LT |
661 | } |
662 | #else | |
663 | if (!info) | |
0fab6de0 | 664 | return true; |
1da177e4 | 665 | #endif |
0fab6de0 | 666 | return false; |
1da177e4 LT |
667 | } |
668 | ||
669 | ||
670 | #define CMD_RXFIFO BIT7 // release current rx FIFO | |
671 | #define CMD_RXRESET BIT6 // receiver reset | |
672 | #define CMD_RXFIFO_READ BIT5 | |
673 | #define CMD_START_TIMER BIT4 | |
674 | #define CMD_TXFIFO BIT3 // release current tx FIFO | |
675 | #define CMD_TXEOM BIT1 // transmit end message | |
676 | #define CMD_TXRESET BIT0 // transmit reset | |
677 | ||
0fab6de0 | 678 | static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel) |
1da177e4 LT |
679 | { |
680 | int i = 0; | |
d12341f9 | 681 | /* wait for command completion */ |
1da177e4 LT |
682 | while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) { |
683 | udelay(1); | |
684 | if (i++ == 1000) | |
0fab6de0 | 685 | return false; |
1da177e4 | 686 | } |
0fab6de0 | 687 | return true; |
1da177e4 LT |
688 | } |
689 | ||
d12341f9 | 690 | static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd) |
1da177e4 LT |
691 | { |
692 | wait_command_complete(info, channel); | |
693 | write_reg(info, (unsigned char) (channel + CMDR), cmd); | |
694 | } | |
695 | ||
696 | static void tx_pause(struct tty_struct *tty) | |
697 | { | |
698 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
699 | unsigned long flags; | |
d12341f9 | 700 | |
1da177e4 LT |
701 | if (mgslpc_paranoia_check(info, tty->name, "tx_pause")) |
702 | return; | |
703 | if (debug_level >= DEBUG_LEVEL_INFO) | |
d12341f9 JG |
704 | printk("tx_pause(%s)\n",info->device_name); |
705 | ||
1da177e4 LT |
706 | spin_lock_irqsave(&info->lock,flags); |
707 | if (info->tx_enabled) | |
708 | tx_stop(info); | |
709 | spin_unlock_irqrestore(&info->lock,flags); | |
710 | } | |
711 | ||
712 | static void tx_release(struct tty_struct *tty) | |
713 | { | |
714 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
715 | unsigned long flags; | |
d12341f9 | 716 | |
1da177e4 LT |
717 | if (mgslpc_paranoia_check(info, tty->name, "tx_release")) |
718 | return; | |
719 | if (debug_level >= DEBUG_LEVEL_INFO) | |
d12341f9 JG |
720 | printk("tx_release(%s)\n",info->device_name); |
721 | ||
1da177e4 LT |
722 | spin_lock_irqsave(&info->lock,flags); |
723 | if (!info->tx_enabled) | |
eeb46134 | 724 | tx_start(info, tty); |
1da177e4 LT |
725 | spin_unlock_irqrestore(&info->lock,flags); |
726 | } | |
727 | ||
728 | /* Return next bottom half action to perform. | |
729 | * or 0 if nothing to do. | |
730 | */ | |
731 | static int bh_action(MGSLPC_INFO *info) | |
732 | { | |
733 | unsigned long flags; | |
734 | int rc = 0; | |
d12341f9 | 735 | |
1da177e4 LT |
736 | spin_lock_irqsave(&info->lock,flags); |
737 | ||
738 | if (info->pending_bh & BH_RECEIVE) { | |
739 | info->pending_bh &= ~BH_RECEIVE; | |
740 | rc = BH_RECEIVE; | |
741 | } else if (info->pending_bh & BH_TRANSMIT) { | |
742 | info->pending_bh &= ~BH_TRANSMIT; | |
743 | rc = BH_TRANSMIT; | |
744 | } else if (info->pending_bh & BH_STATUS) { | |
745 | info->pending_bh &= ~BH_STATUS; | |
746 | rc = BH_STATUS; | |
747 | } | |
748 | ||
749 | if (!rc) { | |
750 | /* Mark BH routine as complete */ | |
0fab6de0 JP |
751 | info->bh_running = false; |
752 | info->bh_requested = false; | |
1da177e4 | 753 | } |
d12341f9 | 754 | |
1da177e4 | 755 | spin_unlock_irqrestore(&info->lock,flags); |
d12341f9 | 756 | |
1da177e4 LT |
757 | return rc; |
758 | } | |
759 | ||
c4028958 | 760 | static void bh_handler(struct work_struct *work) |
1da177e4 | 761 | { |
c4028958 | 762 | MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task); |
eeb46134 | 763 | struct tty_struct *tty; |
1da177e4 LT |
764 | int action; |
765 | ||
766 | if (!info) | |
767 | return; | |
d12341f9 | 768 | |
1da177e4 LT |
769 | if (debug_level >= DEBUG_LEVEL_BH) |
770 | printk( "%s(%d):bh_handler(%s) entry\n", | |
771 | __FILE__,__LINE__,info->device_name); | |
d12341f9 | 772 | |
0fab6de0 | 773 | info->bh_running = true; |
eeb46134 | 774 | tty = tty_port_tty_get(&info->port); |
1da177e4 LT |
775 | |
776 | while((action = bh_action(info)) != 0) { | |
d12341f9 | 777 | |
1da177e4 LT |
778 | /* Process work item */ |
779 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
780 | printk( "%s(%d):bh_handler() work item action=%d\n", | |
781 | __FILE__,__LINE__,action); | |
782 | ||
783 | switch (action) { | |
d12341f9 | 784 | |
1da177e4 | 785 | case BH_RECEIVE: |
eeb46134 | 786 | while(rx_get_frame(info, tty)); |
1da177e4 LT |
787 | break; |
788 | case BH_TRANSMIT: | |
eeb46134 | 789 | bh_transmit(info, tty); |
1da177e4 LT |
790 | break; |
791 | case BH_STATUS: | |
792 | bh_status(info); | |
793 | break; | |
794 | default: | |
795 | /* unknown work item ID */ | |
796 | printk("Unknown work item ID=%08X!\n", action); | |
797 | break; | |
798 | } | |
799 | } | |
800 | ||
eeb46134 | 801 | tty_kref_put(tty); |
1da177e4 LT |
802 | if (debug_level >= DEBUG_LEVEL_BH) |
803 | printk( "%s(%d):bh_handler(%s) exit\n", | |
804 | __FILE__,__LINE__,info->device_name); | |
805 | } | |
806 | ||
eeb46134 | 807 | static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 | 808 | { |
1da177e4 LT |
809 | if (debug_level >= DEBUG_LEVEL_BH) |
810 | printk("bh_transmit() entry on %s\n", info->device_name); | |
811 | ||
b963a844 | 812 | if (tty) |
1da177e4 | 813 | tty_wakeup(tty); |
1da177e4 LT |
814 | } |
815 | ||
cdaad343 | 816 | static void bh_status(MGSLPC_INFO *info) |
1da177e4 LT |
817 | { |
818 | info->ri_chkcount = 0; | |
819 | info->dsr_chkcount = 0; | |
820 | info->dcd_chkcount = 0; | |
821 | info->cts_chkcount = 0; | |
822 | } | |
823 | ||
d12341f9 | 824 | /* eom: non-zero = end of frame */ |
1da177e4 LT |
825 | static void rx_ready_hdlc(MGSLPC_INFO *info, int eom) |
826 | { | |
827 | unsigned char data[2]; | |
828 | unsigned char fifo_count, read_count, i; | |
829 | RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size)); | |
830 | ||
831 | if (debug_level >= DEBUG_LEVEL_ISR) | |
832 | printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom); | |
d12341f9 | 833 | |
1da177e4 LT |
834 | if (!info->rx_enabled) |
835 | return; | |
836 | ||
837 | if (info->rx_frame_count >= info->rx_buf_count) { | |
838 | /* no more free buffers */ | |
839 | issue_command(info, CHA, CMD_RXRESET); | |
840 | info->pending_bh |= BH_RECEIVE; | |
0fab6de0 | 841 | info->rx_overflow = true; |
1da177e4 LT |
842 | info->icount.buf_overrun++; |
843 | return; | |
844 | } | |
845 | ||
846 | if (eom) { | |
d12341f9 | 847 | /* end of frame, get FIFO count from RBCL register */ |
1da177e4 LT |
848 | if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f))) |
849 | fifo_count = 32; | |
850 | } else | |
851 | fifo_count = 32; | |
d12341f9 | 852 | |
1da177e4 LT |
853 | do { |
854 | if (fifo_count == 1) { | |
855 | read_count = 1; | |
856 | data[0] = read_reg(info, CHA + RXFIFO); | |
857 | } else { | |
858 | read_count = 2; | |
859 | *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO); | |
860 | } | |
861 | fifo_count -= read_count; | |
862 | if (!fifo_count && eom) | |
863 | buf->status = data[--read_count]; | |
864 | ||
865 | for (i = 0; i < read_count; i++) { | |
866 | if (buf->count >= info->max_frame_size) { | |
867 | /* frame too large, reset receiver and reset current buffer */ | |
868 | issue_command(info, CHA, CMD_RXRESET); | |
869 | buf->count = 0; | |
870 | return; | |
871 | } | |
872 | *(buf->data + buf->count) = data[i]; | |
873 | buf->count++; | |
874 | } | |
875 | } while (fifo_count); | |
876 | ||
877 | if (eom) { | |
878 | info->pending_bh |= BH_RECEIVE; | |
879 | info->rx_frame_count++; | |
880 | info->rx_put++; | |
881 | if (info->rx_put >= info->rx_buf_count) | |
882 | info->rx_put = 0; | |
883 | } | |
884 | issue_command(info, CHA, CMD_RXFIFO); | |
885 | } | |
886 | ||
eeb46134 | 887 | static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty) |
1da177e4 | 888 | { |
33f0f88f | 889 | unsigned char data, status, flag; |
1da177e4 | 890 | int fifo_count; |
33f0f88f | 891 | int work = 0; |
1da177e4 LT |
892 | struct mgsl_icount *icount = &info->icount; |
893 | ||
894 | if (tcd) { | |
d12341f9 | 895 | /* early termination, get FIFO count from RBCL register */ |
1da177e4 LT |
896 | fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f); |
897 | ||
898 | /* Zero fifo count could mean 0 or 32 bytes available. | |
899 | * If BIT5 of STAR is set then at least 1 byte is available. | |
900 | */ | |
901 | if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) | |
902 | fifo_count = 32; | |
903 | } else | |
904 | fifo_count = 32; | |
33f0f88f AC |
905 | |
906 | tty_buffer_request_room(tty, fifo_count); | |
d12341f9 | 907 | /* Flush received async data to receive data buffer. */ |
1da177e4 LT |
908 | while (fifo_count) { |
909 | data = read_reg(info, CHA + RXFIFO); | |
910 | status = read_reg(info, CHA + RXFIFO); | |
911 | fifo_count -= 2; | |
912 | ||
1da177e4 | 913 | icount->rx++; |
33f0f88f | 914 | flag = TTY_NORMAL; |
1da177e4 LT |
915 | |
916 | // if no frameing/crc error then save data | |
917 | // BIT7:parity error | |
918 | // BIT6:framing error | |
919 | ||
920 | if (status & (BIT7 + BIT6)) { | |
d12341f9 | 921 | if (status & BIT7) |
1da177e4 LT |
922 | icount->parity++; |
923 | else | |
924 | icount->frame++; | |
925 | ||
926 | /* discard char if tty control flags say so */ | |
927 | if (status & info->ignore_status_mask) | |
928 | continue; | |
d12341f9 | 929 | |
1da177e4 LT |
930 | status &= info->read_status_mask; |
931 | ||
932 | if (status & BIT7) | |
33f0f88f | 933 | flag = TTY_PARITY; |
1da177e4 | 934 | else if (status & BIT6) |
33f0f88f | 935 | flag = TTY_FRAME; |
1da177e4 | 936 | } |
33f0f88f | 937 | work += tty_insert_flip_char(tty, data, flag); |
1da177e4 LT |
938 | } |
939 | issue_command(info, CHA, CMD_RXFIFO); | |
940 | ||
941 | if (debug_level >= DEBUG_LEVEL_ISR) { | |
33f0f88f AC |
942 | printk("%s(%d):rx_ready_async", |
943 | __FILE__,__LINE__); | |
1da177e4 LT |
944 | printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n", |
945 | __FILE__,__LINE__,icount->rx,icount->brk, | |
946 | icount->parity,icount->frame,icount->overrun); | |
947 | } | |
d12341f9 | 948 | |
33f0f88f | 949 | if (work) |
1da177e4 LT |
950 | tty_flip_buffer_push(tty); |
951 | } | |
952 | ||
953 | ||
eeb46134 | 954 | static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
955 | { |
956 | if (!info->tx_active) | |
957 | return; | |
d12341f9 | 958 | |
0fab6de0 JP |
959 | info->tx_active = false; |
960 | info->tx_aborting = false; | |
1da177e4 LT |
961 | |
962 | if (info->params.mode == MGSL_MODE_ASYNC) | |
963 | return; | |
964 | ||
965 | info->tx_count = info->tx_put = info->tx_get = 0; | |
d12341f9 JG |
966 | del_timer(&info->tx_timer); |
967 | ||
1da177e4 LT |
968 | if (info->drop_rts_on_tx_done) { |
969 | get_signals(info); | |
970 | if (info->serial_signals & SerialSignal_RTS) { | |
971 | info->serial_signals &= ~SerialSignal_RTS; | |
972 | set_signals(info); | |
973 | } | |
0fab6de0 | 974 | info->drop_rts_on_tx_done = false; |
1da177e4 LT |
975 | } |
976 | ||
af69c7f9 | 977 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
978 | if (info->netcount) |
979 | hdlcdev_tx_done(info); | |
d12341f9 | 980 | else |
1da177e4 LT |
981 | #endif |
982 | { | |
eeb46134 | 983 | if (tty->stopped || tty->hw_stopped) { |
1da177e4 LT |
984 | tx_stop(info); |
985 | return; | |
986 | } | |
987 | info->pending_bh |= BH_TRANSMIT; | |
988 | } | |
989 | } | |
990 | ||
eeb46134 | 991 | static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
992 | { |
993 | unsigned char fifo_count = 32; | |
994 | int c; | |
995 | ||
996 | if (debug_level >= DEBUG_LEVEL_ISR) | |
997 | printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name); | |
998 | ||
999 | if (info->params.mode == MGSL_MODE_HDLC) { | |
1000 | if (!info->tx_active) | |
1001 | return; | |
1002 | } else { | |
eeb46134 | 1003 | if (tty->stopped || tty->hw_stopped) { |
1da177e4 LT |
1004 | tx_stop(info); |
1005 | return; | |
1006 | } | |
1007 | if (!info->tx_count) | |
0fab6de0 | 1008 | info->tx_active = false; |
1da177e4 LT |
1009 | } |
1010 | ||
1011 | if (!info->tx_count) | |
1012 | return; | |
1013 | ||
1014 | while (info->tx_count && fifo_count) { | |
1015 | c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get))); | |
d12341f9 | 1016 | |
1da177e4 LT |
1017 | if (c == 1) { |
1018 | write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get)); | |
1019 | } else { | |
1020 | write_reg16(info, CHA + TXFIFO, | |
1021 | *((unsigned short*)(info->tx_buf + info->tx_get))); | |
1022 | } | |
1023 | info->tx_count -= c; | |
1024 | info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1); | |
1025 | fifo_count -= c; | |
1026 | } | |
1027 | ||
1028 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
1029 | if (info->tx_count < WAKEUP_CHARS) | |
1030 | info->pending_bh |= BH_TRANSMIT; | |
1031 | issue_command(info, CHA, CMD_TXFIFO); | |
1032 | } else { | |
1033 | if (info->tx_count) | |
1034 | issue_command(info, CHA, CMD_TXFIFO); | |
1035 | else | |
1036 | issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM); | |
1037 | } | |
1038 | } | |
1039 | ||
eeb46134 | 1040 | static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
1041 | { |
1042 | get_signals(info); | |
1043 | if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1044 | irq_disable(info, CHB, IRQ_CTS); | |
1045 | info->icount.cts++; | |
1046 | if (info->serial_signals & SerialSignal_CTS) | |
1047 | info->input_signal_events.cts_up++; | |
1048 | else | |
1049 | info->input_signal_events.cts_down++; | |
1050 | wake_up_interruptible(&info->status_event_wait_q); | |
1051 | wake_up_interruptible(&info->event_wait_q); | |
1052 | ||
eeb46134 AC |
1053 | if (info->port.flags & ASYNC_CTS_FLOW) { |
1054 | if (tty->hw_stopped) { | |
1da177e4 LT |
1055 | if (info->serial_signals & SerialSignal_CTS) { |
1056 | if (debug_level >= DEBUG_LEVEL_ISR) | |
1057 | printk("CTS tx start..."); | |
eeb46134 AC |
1058 | if (tty) |
1059 | tty->hw_stopped = 0; | |
1060 | tx_start(info, tty); | |
1da177e4 LT |
1061 | info->pending_bh |= BH_TRANSMIT; |
1062 | return; | |
1063 | } | |
1064 | } else { | |
1065 | if (!(info->serial_signals & SerialSignal_CTS)) { | |
1066 | if (debug_level >= DEBUG_LEVEL_ISR) | |
1067 | printk("CTS tx stop..."); | |
eeb46134 AC |
1068 | if (tty) |
1069 | tty->hw_stopped = 1; | |
1da177e4 LT |
1070 | tx_stop(info); |
1071 | } | |
1072 | } | |
1073 | } | |
1074 | info->pending_bh |= BH_STATUS; | |
1075 | } | |
1076 | ||
eeb46134 | 1077 | static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
1078 | { |
1079 | get_signals(info); | |
1080 | if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1081 | irq_disable(info, CHB, IRQ_DCD); | |
1082 | info->icount.dcd++; | |
1083 | if (info->serial_signals & SerialSignal_DCD) { | |
1084 | info->input_signal_events.dcd_up++; | |
1085 | } | |
1086 | else | |
1087 | info->input_signal_events.dcd_down++; | |
af69c7f9 | 1088 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
1089 | if (info->netcount) { |
1090 | if (info->serial_signals & SerialSignal_DCD) | |
1091 | netif_carrier_on(info->netdev); | |
1092 | else | |
1093 | netif_carrier_off(info->netdev); | |
1094 | } | |
1da177e4 LT |
1095 | #endif |
1096 | wake_up_interruptible(&info->status_event_wait_q); | |
1097 | wake_up_interruptible(&info->event_wait_q); | |
1098 | ||
eeb46134 | 1099 | if (info->port.flags & ASYNC_CHECK_CD) { |
1da177e4 LT |
1100 | if (debug_level >= DEBUG_LEVEL_ISR) |
1101 | printk("%s CD now %s...", info->device_name, | |
1102 | (info->serial_signals & SerialSignal_DCD) ? "on" : "off"); | |
1103 | if (info->serial_signals & SerialSignal_DCD) | |
eeb46134 | 1104 | wake_up_interruptible(&info->port.open_wait); |
1da177e4 LT |
1105 | else { |
1106 | if (debug_level >= DEBUG_LEVEL_ISR) | |
1107 | printk("doing serial hangup..."); | |
eeb46134 AC |
1108 | if (tty) |
1109 | tty_hangup(tty); | |
1da177e4 LT |
1110 | } |
1111 | } | |
1112 | info->pending_bh |= BH_STATUS; | |
1113 | } | |
1114 | ||
1115 | static void dsr_change(MGSLPC_INFO *info) | |
1116 | { | |
1117 | get_signals(info); | |
1118 | if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1119 | port_irq_disable(info, PVR_DSR); | |
1120 | info->icount.dsr++; | |
1121 | if (info->serial_signals & SerialSignal_DSR) | |
1122 | info->input_signal_events.dsr_up++; | |
1123 | else | |
1124 | info->input_signal_events.dsr_down++; | |
1125 | wake_up_interruptible(&info->status_event_wait_q); | |
1126 | wake_up_interruptible(&info->event_wait_q); | |
1127 | info->pending_bh |= BH_STATUS; | |
1128 | } | |
1129 | ||
1130 | static void ri_change(MGSLPC_INFO *info) | |
1131 | { | |
1132 | get_signals(info); | |
1133 | if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1134 | port_irq_disable(info, PVR_RI); | |
1135 | info->icount.rng++; | |
1136 | if (info->serial_signals & SerialSignal_RI) | |
1137 | info->input_signal_events.ri_up++; | |
1138 | else | |
1139 | info->input_signal_events.ri_down++; | |
1140 | wake_up_interruptible(&info->status_event_wait_q); | |
1141 | wake_up_interruptible(&info->event_wait_q); | |
1142 | info->pending_bh |= BH_STATUS; | |
1143 | } | |
1144 | ||
1145 | /* Interrupt service routine entry point. | |
d12341f9 | 1146 | * |
1da177e4 | 1147 | * Arguments: |
d12341f9 | 1148 | * |
1da177e4 LT |
1149 | * irq interrupt number that caused interrupt |
1150 | * dev_id device ID supplied during interrupt registration | |
1da177e4 | 1151 | */ |
a6f97b29 | 1152 | static irqreturn_t mgslpc_isr(int dummy, void *dev_id) |
1da177e4 | 1153 | { |
a6f97b29 | 1154 | MGSLPC_INFO *info = dev_id; |
eeb46134 | 1155 | struct tty_struct *tty; |
1da177e4 LT |
1156 | unsigned short isr; |
1157 | unsigned char gis, pis; | |
1158 | int count=0; | |
1159 | ||
d12341f9 | 1160 | if (debug_level >= DEBUG_LEVEL_ISR) |
a6f97b29 | 1161 | printk("mgslpc_isr(%d) entry.\n", info->irq_level); |
d12341f9 | 1162 | |
e2d40963 | 1163 | if (!(info->p_dev->_locked)) |
1da177e4 LT |
1164 | return IRQ_HANDLED; |
1165 | ||
eeb46134 AC |
1166 | tty = tty_port_tty_get(&info->port); |
1167 | ||
1da177e4 LT |
1168 | spin_lock(&info->lock); |
1169 | ||
1170 | while ((gis = read_reg(info, CHA + GIS))) { | |
d12341f9 | 1171 | if (debug_level >= DEBUG_LEVEL_ISR) |
1da177e4 LT |
1172 | printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis); |
1173 | ||
1174 | if ((gis & 0x70) || count > 1000) { | |
1175 | printk("synclink_cs:hardware failed or ejected\n"); | |
1176 | break; | |
1177 | } | |
1178 | count++; | |
1179 | ||
1180 | if (gis & (BIT1 + BIT0)) { | |
1181 | isr = read_reg16(info, CHB + ISR); | |
1182 | if (isr & IRQ_DCD) | |
eeb46134 | 1183 | dcd_change(info, tty); |
1da177e4 | 1184 | if (isr & IRQ_CTS) |
eeb46134 | 1185 | cts_change(info, tty); |
1da177e4 LT |
1186 | } |
1187 | if (gis & (BIT3 + BIT2)) | |
1188 | { | |
1189 | isr = read_reg16(info, CHA + ISR); | |
1190 | if (isr & IRQ_TIMER) { | |
0fab6de0 | 1191 | info->irq_occurred = true; |
1da177e4 LT |
1192 | irq_disable(info, CHA, IRQ_TIMER); |
1193 | } | |
1194 | ||
d12341f9 | 1195 | /* receive IRQs */ |
1da177e4 LT |
1196 | if (isr & IRQ_EXITHUNT) { |
1197 | info->icount.exithunt++; | |
1198 | wake_up_interruptible(&info->event_wait_q); | |
1199 | } | |
1200 | if (isr & IRQ_BREAK_ON) { | |
1201 | info->icount.brk++; | |
eeb46134 AC |
1202 | if (info->port.flags & ASYNC_SAK) |
1203 | do_SAK(tty); | |
1da177e4 LT |
1204 | } |
1205 | if (isr & IRQ_RXTIME) { | |
1206 | issue_command(info, CHA, CMD_RXFIFO_READ); | |
1207 | } | |
1208 | if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) { | |
1209 | if (info->params.mode == MGSL_MODE_HDLC) | |
d12341f9 | 1210 | rx_ready_hdlc(info, isr & IRQ_RXEOM); |
1da177e4 | 1211 | else |
eeb46134 | 1212 | rx_ready_async(info, isr & IRQ_RXEOM, tty); |
1da177e4 LT |
1213 | } |
1214 | ||
d12341f9 | 1215 | /* transmit IRQs */ |
1da177e4 LT |
1216 | if (isr & IRQ_UNDERRUN) { |
1217 | if (info->tx_aborting) | |
1218 | info->icount.txabort++; | |
1219 | else | |
1220 | info->icount.txunder++; | |
eeb46134 | 1221 | tx_done(info, tty); |
1da177e4 LT |
1222 | } |
1223 | else if (isr & IRQ_ALLSENT) { | |
1224 | info->icount.txok++; | |
eeb46134 | 1225 | tx_done(info, tty); |
1da177e4 LT |
1226 | } |
1227 | else if (isr & IRQ_TXFIFO) | |
eeb46134 | 1228 | tx_ready(info, tty); |
1da177e4 LT |
1229 | } |
1230 | if (gis & BIT7) { | |
1231 | pis = read_reg(info, CHA + PIS); | |
1232 | if (pis & BIT1) | |
1233 | dsr_change(info); | |
1234 | if (pis & BIT2) | |
1235 | ri_change(info); | |
1236 | } | |
1237 | } | |
d12341f9 JG |
1238 | |
1239 | /* Request bottom half processing if there's something | |
1da177e4 LT |
1240 | * for it to do and the bh is not already running |
1241 | */ | |
1242 | ||
1243 | if (info->pending_bh && !info->bh_running && !info->bh_requested) { | |
d12341f9 | 1244 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
1da177e4 LT |
1245 | printk("%s(%d):%s queueing bh task.\n", |
1246 | __FILE__,__LINE__,info->device_name); | |
1247 | schedule_work(&info->task); | |
0fab6de0 | 1248 | info->bh_requested = true; |
1da177e4 LT |
1249 | } |
1250 | ||
1251 | spin_unlock(&info->lock); | |
eeb46134 | 1252 | tty_kref_put(tty); |
d12341f9 JG |
1253 | |
1254 | if (debug_level >= DEBUG_LEVEL_ISR) | |
1da177e4 | 1255 | printk("%s(%d):mgslpc_isr(%d)exit.\n", |
a6f97b29 | 1256 | __FILE__, __LINE__, info->irq_level); |
1da177e4 LT |
1257 | |
1258 | return IRQ_HANDLED; | |
1259 | } | |
1260 | ||
1261 | /* Initialize and start device. | |
1262 | */ | |
eeb46134 | 1263 | static int startup(MGSLPC_INFO * info, struct tty_struct *tty) |
1da177e4 LT |
1264 | { |
1265 | int retval = 0; | |
d12341f9 | 1266 | |
1da177e4 LT |
1267 | if (debug_level >= DEBUG_LEVEL_INFO) |
1268 | printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name); | |
d12341f9 | 1269 | |
eeb46134 | 1270 | if (info->port.flags & ASYNC_INITIALIZED) |
1da177e4 | 1271 | return 0; |
d12341f9 | 1272 | |
1da177e4 LT |
1273 | if (!info->tx_buf) { |
1274 | /* allocate a page of memory for a transmit buffer */ | |
1275 | info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL); | |
1276 | if (!info->tx_buf) { | |
1277 | printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", | |
1278 | __FILE__,__LINE__,info->device_name); | |
1279 | return -ENOMEM; | |
1280 | } | |
1281 | } | |
1282 | ||
1283 | info->pending_bh = 0; | |
d12341f9 | 1284 | |
a7482a2e PF |
1285 | memset(&info->icount, 0, sizeof(info->icount)); |
1286 | ||
40565f19 | 1287 | setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); |
1da177e4 LT |
1288 | |
1289 | /* Allocate and claim adapter resources */ | |
1290 | retval = claim_resources(info); | |
d12341f9 | 1291 | |
25985edc | 1292 | /* perform existence check and diagnostics */ |
1da177e4 LT |
1293 | if ( !retval ) |
1294 | retval = adapter_test(info); | |
d12341f9 | 1295 | |
1da177e4 | 1296 | if ( retval ) { |
eeb46134 AC |
1297 | if (capable(CAP_SYS_ADMIN) && tty) |
1298 | set_bit(TTY_IO_ERROR, &tty->flags); | |
1da177e4 LT |
1299 | release_resources(info); |
1300 | return retval; | |
1301 | } | |
1302 | ||
1303 | /* program hardware for current parameters */ | |
eeb46134 | 1304 | mgslpc_change_params(info, tty); |
d12341f9 | 1305 | |
eeb46134 AC |
1306 | if (tty) |
1307 | clear_bit(TTY_IO_ERROR, &tty->flags); | |
1da177e4 | 1308 | |
eeb46134 | 1309 | info->port.flags |= ASYNC_INITIALIZED; |
d12341f9 | 1310 | |
1da177e4 LT |
1311 | return 0; |
1312 | } | |
1313 | ||
1314 | /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware | |
1315 | */ | |
eeb46134 | 1316 | static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty) |
1da177e4 LT |
1317 | { |
1318 | unsigned long flags; | |
d12341f9 | 1319 | |
eeb46134 | 1320 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
1da177e4 LT |
1321 | return; |
1322 | ||
1323 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1324 | printk("%s(%d):mgslpc_shutdown(%s)\n", | |
1325 | __FILE__,__LINE__, info->device_name ); | |
1326 | ||
1327 | /* clear status wait queue because status changes */ | |
1328 | /* can't happen after shutting down the hardware */ | |
1329 | wake_up_interruptible(&info->status_event_wait_q); | |
1330 | wake_up_interruptible(&info->event_wait_q); | |
1331 | ||
40565f19 | 1332 | del_timer_sync(&info->tx_timer); |
1da177e4 LT |
1333 | |
1334 | if (info->tx_buf) { | |
1335 | free_page((unsigned long) info->tx_buf); | |
1336 | info->tx_buf = NULL; | |
1337 | } | |
1338 | ||
1339 | spin_lock_irqsave(&info->lock,flags); | |
1340 | ||
1341 | rx_stop(info); | |
1342 | tx_stop(info); | |
1343 | ||
1344 | /* TODO:disable interrupts instead of reset to preserve signal states */ | |
1345 | reset_device(info); | |
d12341f9 | 1346 | |
373f5aed | 1347 | if (!tty || tty->termios.c_cflag & HUPCL) { |
1da177e4 LT |
1348 | info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS); |
1349 | set_signals(info); | |
1350 | } | |
d12341f9 | 1351 | |
1da177e4 LT |
1352 | spin_unlock_irqrestore(&info->lock,flags); |
1353 | ||
d12341f9 JG |
1354 | release_resources(info); |
1355 | ||
eeb46134 AC |
1356 | if (tty) |
1357 | set_bit(TTY_IO_ERROR, &tty->flags); | |
1da177e4 | 1358 | |
eeb46134 | 1359 | info->port.flags &= ~ASYNC_INITIALIZED; |
1da177e4 LT |
1360 | } |
1361 | ||
eeb46134 | 1362 | static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
1363 | { |
1364 | unsigned long flags; | |
1365 | ||
1366 | spin_lock_irqsave(&info->lock,flags); | |
d12341f9 | 1367 | |
1da177e4 LT |
1368 | rx_stop(info); |
1369 | tx_stop(info); | |
1370 | info->tx_count = info->tx_put = info->tx_get = 0; | |
d12341f9 | 1371 | |
1da177e4 LT |
1372 | if (info->params.mode == MGSL_MODE_HDLC || info->netcount) |
1373 | hdlc_mode(info); | |
1374 | else | |
1375 | async_mode(info); | |
d12341f9 | 1376 | |
1da177e4 | 1377 | set_signals(info); |
d12341f9 | 1378 | |
1da177e4 LT |
1379 | info->dcd_chkcount = 0; |
1380 | info->cts_chkcount = 0; | |
1381 | info->ri_chkcount = 0; | |
1382 | info->dsr_chkcount = 0; | |
1383 | ||
1384 | irq_enable(info, CHB, IRQ_DCD | IRQ_CTS); | |
1385 | port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI); | |
1386 | get_signals(info); | |
d12341f9 | 1387 | |
373f5aed | 1388 | if (info->netcount || (tty && (tty->termios.c_cflag & CREAD))) |
1da177e4 | 1389 | rx_start(info); |
d12341f9 | 1390 | |
1da177e4 LT |
1391 | spin_unlock_irqrestore(&info->lock,flags); |
1392 | } | |
1393 | ||
1394 | /* Reconfigure adapter based on new parameters | |
1395 | */ | |
eeb46134 | 1396 | static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
1397 | { |
1398 | unsigned cflag; | |
1399 | int bits_per_char; | |
1400 | ||
373f5aed | 1401 | if (!tty) |
1da177e4 | 1402 | return; |
d12341f9 | 1403 | |
1da177e4 LT |
1404 | if (debug_level >= DEBUG_LEVEL_INFO) |
1405 | printk("%s(%d):mgslpc_change_params(%s)\n", | |
1406 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 | 1407 | |
373f5aed | 1408 | cflag = tty->termios.c_cflag; |
1da177e4 LT |
1409 | |
1410 | /* if B0 rate (hangup) specified then negate DTR and RTS */ | |
1411 | /* otherwise assert DTR and RTS */ | |
1412 | if (cflag & CBAUD) | |
1413 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; | |
1414 | else | |
1415 | info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
d12341f9 | 1416 | |
1da177e4 | 1417 | /* byte size and parity */ |
d12341f9 | 1418 | |
1da177e4 LT |
1419 | switch (cflag & CSIZE) { |
1420 | case CS5: info->params.data_bits = 5; break; | |
1421 | case CS6: info->params.data_bits = 6; break; | |
1422 | case CS7: info->params.data_bits = 7; break; | |
1423 | case CS8: info->params.data_bits = 8; break; | |
1424 | default: info->params.data_bits = 7; break; | |
1425 | } | |
d12341f9 | 1426 | |
1da177e4 LT |
1427 | if (cflag & CSTOPB) |
1428 | info->params.stop_bits = 2; | |
1429 | else | |
1430 | info->params.stop_bits = 1; | |
1431 | ||
1432 | info->params.parity = ASYNC_PARITY_NONE; | |
1433 | if (cflag & PARENB) { | |
1434 | if (cflag & PARODD) | |
1435 | info->params.parity = ASYNC_PARITY_ODD; | |
1436 | else | |
1437 | info->params.parity = ASYNC_PARITY_EVEN; | |
1438 | #ifdef CMSPAR | |
1439 | if (cflag & CMSPAR) | |
1440 | info->params.parity = ASYNC_PARITY_SPACE; | |
1441 | #endif | |
1442 | } | |
1443 | ||
1444 | /* calculate number of jiffies to transmit a full | |
1445 | * FIFO (32 bytes) at specified data rate | |
1446 | */ | |
d12341f9 | 1447 | bits_per_char = info->params.data_bits + |
1da177e4 LT |
1448 | info->params.stop_bits + 1; |
1449 | ||
1450 | /* if port data rate is set to 460800 or less then | |
1451 | * allow tty settings to override, otherwise keep the | |
1452 | * current data rate. | |
1453 | */ | |
1454 | if (info->params.data_rate <= 460800) { | |
eeb46134 | 1455 | info->params.data_rate = tty_get_baud_rate(tty); |
1da177e4 | 1456 | } |
d12341f9 | 1457 | |
1da177e4 | 1458 | if ( info->params.data_rate ) { |
d12341f9 | 1459 | info->timeout = (32*HZ*bits_per_char) / |
1da177e4 LT |
1460 | info->params.data_rate; |
1461 | } | |
1462 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
1463 | ||
1464 | if (cflag & CRTSCTS) | |
eeb46134 | 1465 | info->port.flags |= ASYNC_CTS_FLOW; |
1da177e4 | 1466 | else |
eeb46134 | 1467 | info->port.flags &= ~ASYNC_CTS_FLOW; |
d12341f9 | 1468 | |
1da177e4 | 1469 | if (cflag & CLOCAL) |
eeb46134 | 1470 | info->port.flags &= ~ASYNC_CHECK_CD; |
1da177e4 | 1471 | else |
eeb46134 | 1472 | info->port.flags |= ASYNC_CHECK_CD; |
1da177e4 LT |
1473 | |
1474 | /* process tty input control flags */ | |
d12341f9 | 1475 | |
1da177e4 | 1476 | info->read_status_mask = 0; |
eeb46134 | 1477 | if (I_INPCK(tty)) |
1da177e4 | 1478 | info->read_status_mask |= BIT7 | BIT6; |
eeb46134 | 1479 | if (I_IGNPAR(tty)) |
1da177e4 LT |
1480 | info->ignore_status_mask |= BIT7 | BIT6; |
1481 | ||
eeb46134 | 1482 | mgslpc_program_hw(info, tty); |
1da177e4 LT |
1483 | } |
1484 | ||
1485 | /* Add a character to the transmit buffer | |
1486 | */ | |
d7e752e2 | 1487 | static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch) |
1da177e4 LT |
1488 | { |
1489 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1490 | unsigned long flags; | |
1491 | ||
1492 | if (debug_level >= DEBUG_LEVEL_INFO) { | |
1493 | printk( "%s(%d):mgslpc_put_char(%d) on %s\n", | |
1494 | __FILE__,__LINE__,ch,info->device_name); | |
1495 | } | |
1496 | ||
1497 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char")) | |
d7e752e2 | 1498 | return 0; |
1da177e4 | 1499 | |
326f28e9 | 1500 | if (!info->tx_buf) |
d7e752e2 | 1501 | return 0; |
1da177e4 LT |
1502 | |
1503 | spin_lock_irqsave(&info->lock,flags); | |
d12341f9 | 1504 | |
1da177e4 LT |
1505 | if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) { |
1506 | if (info->tx_count < TXBUFSIZE - 1) { | |
1507 | info->tx_buf[info->tx_put++] = ch; | |
1508 | info->tx_put &= TXBUFSIZE-1; | |
1509 | info->tx_count++; | |
1510 | } | |
1511 | } | |
d12341f9 | 1512 | |
1da177e4 | 1513 | spin_unlock_irqrestore(&info->lock,flags); |
d7e752e2 | 1514 | return 1; |
1da177e4 LT |
1515 | } |
1516 | ||
1517 | /* Enable transmitter so remaining characters in the | |
1518 | * transmit buffer are sent. | |
1519 | */ | |
1520 | static void mgslpc_flush_chars(struct tty_struct *tty) | |
1521 | { | |
1522 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1523 | unsigned long flags; | |
d12341f9 | 1524 | |
1da177e4 LT |
1525 | if (debug_level >= DEBUG_LEVEL_INFO) |
1526 | printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n", | |
1527 | __FILE__,__LINE__,info->device_name,info->tx_count); | |
d12341f9 | 1528 | |
1da177e4 LT |
1529 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars")) |
1530 | return; | |
1531 | ||
1532 | if (info->tx_count <= 0 || tty->stopped || | |
1533 | tty->hw_stopped || !info->tx_buf) | |
1534 | return; | |
1535 | ||
1536 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1537 | printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n", | |
1538 | __FILE__,__LINE__,info->device_name); | |
1539 | ||
1540 | spin_lock_irqsave(&info->lock,flags); | |
1541 | if (!info->tx_active) | |
eeb46134 | 1542 | tx_start(info, tty); |
1da177e4 LT |
1543 | spin_unlock_irqrestore(&info->lock,flags); |
1544 | } | |
1545 | ||
1546 | /* Send a block of data | |
d12341f9 | 1547 | * |
1da177e4 | 1548 | * Arguments: |
d12341f9 | 1549 | * |
1da177e4 LT |
1550 | * tty pointer to tty information structure |
1551 | * buf pointer to buffer containing send data | |
1552 | * count size of send data in bytes | |
d12341f9 | 1553 | * |
1da177e4 LT |
1554 | * Returns: number of characters written |
1555 | */ | |
1556 | static int mgslpc_write(struct tty_struct * tty, | |
1557 | const unsigned char *buf, int count) | |
1558 | { | |
1559 | int c, ret = 0; | |
1560 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1561 | unsigned long flags; | |
d12341f9 | 1562 | |
1da177e4 LT |
1563 | if (debug_level >= DEBUG_LEVEL_INFO) |
1564 | printk( "%s(%d):mgslpc_write(%s) count=%d\n", | |
1565 | __FILE__,__LINE__,info->device_name,count); | |
d12341f9 | 1566 | |
1da177e4 | 1567 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") || |
326f28e9 | 1568 | !info->tx_buf) |
1da177e4 LT |
1569 | goto cleanup; |
1570 | ||
1571 | if (info->params.mode == MGSL_MODE_HDLC) { | |
1572 | if (count > TXBUFSIZE) { | |
1573 | ret = -EIO; | |
1574 | goto cleanup; | |
1575 | } | |
1576 | if (info->tx_active) | |
1577 | goto cleanup; | |
1578 | else if (info->tx_count) | |
1579 | goto start; | |
1580 | } | |
1581 | ||
1582 | for (;;) { | |
1583 | c = min(count, | |
1584 | min(TXBUFSIZE - info->tx_count - 1, | |
1585 | TXBUFSIZE - info->tx_put)); | |
1586 | if (c <= 0) | |
1587 | break; | |
d12341f9 | 1588 | |
1da177e4 LT |
1589 | memcpy(info->tx_buf + info->tx_put, buf, c); |
1590 | ||
1591 | spin_lock_irqsave(&info->lock,flags); | |
1592 | info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1); | |
1593 | info->tx_count += c; | |
1594 | spin_unlock_irqrestore(&info->lock,flags); | |
1595 | ||
1596 | buf += c; | |
1597 | count -= c; | |
1598 | ret += c; | |
1599 | } | |
1600 | start: | |
1601 | if (info->tx_count && !tty->stopped && !tty->hw_stopped) { | |
1602 | spin_lock_irqsave(&info->lock,flags); | |
1603 | if (!info->tx_active) | |
eeb46134 | 1604 | tx_start(info, tty); |
1da177e4 LT |
1605 | spin_unlock_irqrestore(&info->lock,flags); |
1606 | } | |
d12341f9 | 1607 | cleanup: |
1da177e4 LT |
1608 | if (debug_level >= DEBUG_LEVEL_INFO) |
1609 | printk( "%s(%d):mgslpc_write(%s) returning=%d\n", | |
1610 | __FILE__,__LINE__,info->device_name,ret); | |
1611 | return ret; | |
1612 | } | |
1613 | ||
1614 | /* Return the count of free bytes in transmit buffer | |
1615 | */ | |
1616 | static int mgslpc_write_room(struct tty_struct *tty) | |
1617 | { | |
1618 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1619 | int ret; | |
d12341f9 | 1620 | |
1da177e4 LT |
1621 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room")) |
1622 | return 0; | |
1623 | ||
1624 | if (info->params.mode == MGSL_MODE_HDLC) { | |
1625 | /* HDLC (frame oriented) mode */ | |
1626 | if (info->tx_active) | |
1627 | return 0; | |
1628 | else | |
1629 | return HDLC_MAX_FRAME_SIZE; | |
1630 | } else { | |
1631 | ret = TXBUFSIZE - info->tx_count - 1; | |
1632 | if (ret < 0) | |
1633 | ret = 0; | |
1634 | } | |
d12341f9 | 1635 | |
1da177e4 LT |
1636 | if (debug_level >= DEBUG_LEVEL_INFO) |
1637 | printk("%s(%d):mgslpc_write_room(%s)=%d\n", | |
1638 | __FILE__,__LINE__, info->device_name, ret); | |
1639 | return ret; | |
1640 | } | |
1641 | ||
1642 | /* Return the count of bytes in transmit buffer | |
1643 | */ | |
1644 | static int mgslpc_chars_in_buffer(struct tty_struct *tty) | |
1645 | { | |
1646 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1647 | int rc; | |
d12341f9 | 1648 | |
1da177e4 LT |
1649 | if (debug_level >= DEBUG_LEVEL_INFO) |
1650 | printk("%s(%d):mgslpc_chars_in_buffer(%s)\n", | |
1651 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 | 1652 | |
1da177e4 LT |
1653 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer")) |
1654 | return 0; | |
d12341f9 | 1655 | |
1da177e4 LT |
1656 | if (info->params.mode == MGSL_MODE_HDLC) |
1657 | rc = info->tx_active ? info->max_frame_size : 0; | |
1658 | else | |
1659 | rc = info->tx_count; | |
1660 | ||
1661 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1662 | printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n", | |
1663 | __FILE__,__LINE__, info->device_name, rc); | |
d12341f9 | 1664 | |
1da177e4 LT |
1665 | return rc; |
1666 | } | |
1667 | ||
1668 | /* Discard all data in the send buffer | |
1669 | */ | |
1670 | static void mgslpc_flush_buffer(struct tty_struct *tty) | |
1671 | { | |
1672 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1673 | unsigned long flags; | |
d12341f9 | 1674 | |
1da177e4 LT |
1675 | if (debug_level >= DEBUG_LEVEL_INFO) |
1676 | printk("%s(%d):mgslpc_flush_buffer(%s) entry\n", | |
1677 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 | 1678 | |
1da177e4 LT |
1679 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer")) |
1680 | return; | |
d12341f9 JG |
1681 | |
1682 | spin_lock_irqsave(&info->lock,flags); | |
1da177e4 | 1683 | info->tx_count = info->tx_put = info->tx_get = 0; |
d12341f9 | 1684 | del_timer(&info->tx_timer); |
1da177e4 LT |
1685 | spin_unlock_irqrestore(&info->lock,flags); |
1686 | ||
1687 | wake_up_interruptible(&tty->write_wait); | |
1688 | tty_wakeup(tty); | |
1689 | } | |
1690 | ||
1691 | /* Send a high-priority XON/XOFF character | |
1692 | */ | |
1693 | static void mgslpc_send_xchar(struct tty_struct *tty, char ch) | |
1694 | { | |
1695 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1696 | unsigned long flags; | |
1697 | ||
1698 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1699 | printk("%s(%d):mgslpc_send_xchar(%s,%d)\n", | |
1700 | __FILE__,__LINE__, info->device_name, ch ); | |
d12341f9 | 1701 | |
1da177e4 LT |
1702 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar")) |
1703 | return; | |
1704 | ||
1705 | info->x_char = ch; | |
1706 | if (ch) { | |
1707 | spin_lock_irqsave(&info->lock,flags); | |
1708 | if (!info->tx_enabled) | |
eeb46134 | 1709 | tx_start(info, tty); |
1da177e4 LT |
1710 | spin_unlock_irqrestore(&info->lock,flags); |
1711 | } | |
1712 | } | |
1713 | ||
1714 | /* Signal remote device to throttle send data (our receive data) | |
1715 | */ | |
1716 | static void mgslpc_throttle(struct tty_struct * tty) | |
1717 | { | |
1718 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1719 | unsigned long flags; | |
d12341f9 | 1720 | |
1da177e4 LT |
1721 | if (debug_level >= DEBUG_LEVEL_INFO) |
1722 | printk("%s(%d):mgslpc_throttle(%s) entry\n", | |
1723 | __FILE__,__LINE__, info->device_name ); | |
1724 | ||
1725 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle")) | |
1726 | return; | |
d12341f9 | 1727 | |
1da177e4 LT |
1728 | if (I_IXOFF(tty)) |
1729 | mgslpc_send_xchar(tty, STOP_CHAR(tty)); | |
d12341f9 | 1730 | |
373f5aed | 1731 | if (tty->termios.c_cflag & CRTSCTS) { |
1da177e4 LT |
1732 | spin_lock_irqsave(&info->lock,flags); |
1733 | info->serial_signals &= ~SerialSignal_RTS; | |
1734 | set_signals(info); | |
1735 | spin_unlock_irqrestore(&info->lock,flags); | |
1736 | } | |
1737 | } | |
1738 | ||
1739 | /* Signal remote device to stop throttling send data (our receive data) | |
1740 | */ | |
1741 | static void mgslpc_unthrottle(struct tty_struct * tty) | |
1742 | { | |
1743 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
1744 | unsigned long flags; | |
d12341f9 | 1745 | |
1da177e4 LT |
1746 | if (debug_level >= DEBUG_LEVEL_INFO) |
1747 | printk("%s(%d):mgslpc_unthrottle(%s) entry\n", | |
1748 | __FILE__,__LINE__, info->device_name ); | |
1749 | ||
1750 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle")) | |
1751 | return; | |
d12341f9 | 1752 | |
1da177e4 LT |
1753 | if (I_IXOFF(tty)) { |
1754 | if (info->x_char) | |
1755 | info->x_char = 0; | |
1756 | else | |
1757 | mgslpc_send_xchar(tty, START_CHAR(tty)); | |
1758 | } | |
d12341f9 | 1759 | |
373f5aed | 1760 | if (tty->termios.c_cflag & CRTSCTS) { |
1da177e4 LT |
1761 | spin_lock_irqsave(&info->lock,flags); |
1762 | info->serial_signals |= SerialSignal_RTS; | |
1763 | set_signals(info); | |
1764 | spin_unlock_irqrestore(&info->lock,flags); | |
1765 | } | |
1766 | } | |
1767 | ||
1768 | /* get the current serial statistics | |
1769 | */ | |
1770 | static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount) | |
1771 | { | |
1772 | int err; | |
1773 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1774 | printk("get_params(%s)\n", info->device_name); | |
a7482a2e PF |
1775 | if (!user_icount) { |
1776 | memset(&info->icount, 0, sizeof(info->icount)); | |
1777 | } else { | |
1778 | COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); | |
1779 | if (err) | |
1780 | return -EFAULT; | |
1781 | } | |
1da177e4 LT |
1782 | return 0; |
1783 | } | |
1784 | ||
1785 | /* get the current serial parameters | |
1786 | */ | |
1787 | static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params) | |
1788 | { | |
1789 | int err; | |
1790 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1791 | printk("get_params(%s)\n", info->device_name); | |
1792 | COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); | |
1793 | if (err) | |
1794 | return -EFAULT; | |
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | /* set the serial parameters | |
d12341f9 | 1799 | * |
1da177e4 | 1800 | * Arguments: |
d12341f9 | 1801 | * |
1da177e4 LT |
1802 | * info pointer to device instance data |
1803 | * new_params user buffer containing new serial params | |
1804 | * | |
1805 | * Returns: 0 if success, otherwise error code | |
1806 | */ | |
eeb46134 | 1807 | static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty) |
1da177e4 LT |
1808 | { |
1809 | unsigned long flags; | |
1810 | MGSL_PARAMS tmp_params; | |
1811 | int err; | |
d12341f9 | 1812 | |
1da177e4 LT |
1813 | if (debug_level >= DEBUG_LEVEL_INFO) |
1814 | printk("%s(%d):set_params %s\n", __FILE__,__LINE__, | |
1815 | info->device_name ); | |
1816 | COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); | |
1817 | if (err) { | |
1818 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1819 | printk( "%s(%d):set_params(%s) user buffer copy failed\n", | |
1820 | __FILE__,__LINE__,info->device_name); | |
1821 | return -EFAULT; | |
1822 | } | |
d12341f9 | 1823 | |
1da177e4 LT |
1824 | spin_lock_irqsave(&info->lock,flags); |
1825 | memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); | |
1826 | spin_unlock_irqrestore(&info->lock,flags); | |
d12341f9 | 1827 | |
eeb46134 | 1828 | mgslpc_change_params(info, tty); |
d12341f9 | 1829 | |
1da177e4 LT |
1830 | return 0; |
1831 | } | |
1832 | ||
1833 | static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode) | |
1834 | { | |
1835 | int err; | |
1836 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1837 | printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode); | |
1838 | COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); | |
1839 | if (err) | |
1840 | return -EFAULT; | |
1841 | return 0; | |
1842 | } | |
1843 | ||
1844 | static int set_txidle(MGSLPC_INFO * info, int idle_mode) | |
1845 | { | |
1846 | unsigned long flags; | |
1847 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1848 | printk("set_txidle(%s,%d)\n", info->device_name, idle_mode); | |
1849 | spin_lock_irqsave(&info->lock,flags); | |
1850 | info->idle_mode = idle_mode; | |
1851 | tx_set_idle(info); | |
1852 | spin_unlock_irqrestore(&info->lock,flags); | |
1853 | return 0; | |
1854 | } | |
1855 | ||
1856 | static int get_interface(MGSLPC_INFO * info, int __user *if_mode) | |
1857 | { | |
1858 | int err; | |
1859 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1860 | printk("get_interface(%s)=%d\n", info->device_name, info->if_mode); | |
1861 | COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int)); | |
1862 | if (err) | |
1863 | return -EFAULT; | |
1864 | return 0; | |
1865 | } | |
1866 | ||
1867 | static int set_interface(MGSLPC_INFO * info, int if_mode) | |
1868 | { | |
1869 | unsigned long flags; | |
1870 | unsigned char val; | |
1871 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1872 | printk("set_interface(%s,%d)\n", info->device_name, if_mode); | |
1873 | spin_lock_irqsave(&info->lock,flags); | |
1874 | info->if_mode = if_mode; | |
1875 | ||
1876 | val = read_reg(info, PVR) & 0x0f; | |
1877 | switch (info->if_mode) | |
1878 | { | |
1879 | case MGSL_INTERFACE_RS232: val |= PVR_RS232; break; | |
1880 | case MGSL_INTERFACE_V35: val |= PVR_V35; break; | |
1881 | case MGSL_INTERFACE_RS422: val |= PVR_RS422; break; | |
1882 | } | |
1883 | write_reg(info, PVR, val); | |
1884 | ||
1885 | spin_unlock_irqrestore(&info->lock,flags); | |
1886 | return 0; | |
1887 | } | |
1888 | ||
eeb46134 | 1889 | static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty) |
1da177e4 LT |
1890 | { |
1891 | unsigned long flags; | |
d12341f9 | 1892 | |
1da177e4 LT |
1893 | if (debug_level >= DEBUG_LEVEL_INFO) |
1894 | printk("set_txenable(%s,%d)\n", info->device_name, enable); | |
d12341f9 | 1895 | |
1da177e4 LT |
1896 | spin_lock_irqsave(&info->lock,flags); |
1897 | if (enable) { | |
1898 | if (!info->tx_enabled) | |
eeb46134 | 1899 | tx_start(info, tty); |
1da177e4 LT |
1900 | } else { |
1901 | if (info->tx_enabled) | |
1902 | tx_stop(info); | |
1903 | } | |
1904 | spin_unlock_irqrestore(&info->lock,flags); | |
1905 | return 0; | |
1906 | } | |
1907 | ||
1908 | static int tx_abort(MGSLPC_INFO * info) | |
1909 | { | |
1910 | unsigned long flags; | |
d12341f9 | 1911 | |
1da177e4 LT |
1912 | if (debug_level >= DEBUG_LEVEL_INFO) |
1913 | printk("tx_abort(%s)\n", info->device_name); | |
d12341f9 | 1914 | |
1da177e4 LT |
1915 | spin_lock_irqsave(&info->lock,flags); |
1916 | if (info->tx_active && info->tx_count && | |
1917 | info->params.mode == MGSL_MODE_HDLC) { | |
1918 | /* clear data count so FIFO is not filled on next IRQ. | |
1919 | * This results in underrun and abort transmission. | |
1920 | */ | |
1921 | info->tx_count = info->tx_put = info->tx_get = 0; | |
0fab6de0 | 1922 | info->tx_aborting = true; |
1da177e4 LT |
1923 | } |
1924 | spin_unlock_irqrestore(&info->lock,flags); | |
1925 | return 0; | |
1926 | } | |
1927 | ||
1928 | static int set_rxenable(MGSLPC_INFO * info, int enable) | |
1929 | { | |
1930 | unsigned long flags; | |
d12341f9 | 1931 | |
1da177e4 LT |
1932 | if (debug_level >= DEBUG_LEVEL_INFO) |
1933 | printk("set_rxenable(%s,%d)\n", info->device_name, enable); | |
d12341f9 | 1934 | |
1da177e4 LT |
1935 | spin_lock_irqsave(&info->lock,flags); |
1936 | if (enable) { | |
1937 | if (!info->rx_enabled) | |
1938 | rx_start(info); | |
1939 | } else { | |
1940 | if (info->rx_enabled) | |
1941 | rx_stop(info); | |
1942 | } | |
1943 | spin_unlock_irqrestore(&info->lock,flags); | |
1944 | return 0; | |
1945 | } | |
1946 | ||
1947 | /* wait for specified event to occur | |
d12341f9 | 1948 | * |
1da177e4 LT |
1949 | * Arguments: info pointer to device instance data |
1950 | * mask pointer to bitmask of events to wait for | |
1951 | * Return Value: 0 if successful and bit mask updated with | |
1952 | * of events triggerred, | |
1953 | * otherwise error code | |
1954 | */ | |
1955 | static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr) | |
1956 | { | |
1957 | unsigned long flags; | |
1958 | int s; | |
1959 | int rc=0; | |
1960 | struct mgsl_icount cprev, cnow; | |
1961 | int events; | |
1962 | int mask; | |
1963 | struct _input_signal_events oldsigs, newsigs; | |
1964 | DECLARE_WAITQUEUE(wait, current); | |
1965 | ||
1966 | COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); | |
1967 | if (rc) | |
1968 | return -EFAULT; | |
d12341f9 | 1969 | |
1da177e4 LT |
1970 | if (debug_level >= DEBUG_LEVEL_INFO) |
1971 | printk("wait_events(%s,%d)\n", info->device_name, mask); | |
1972 | ||
1973 | spin_lock_irqsave(&info->lock,flags); | |
1974 | ||
1975 | /* return immediately if state matches requested events */ | |
1976 | get_signals(info); | |
1977 | s = info->serial_signals; | |
1978 | events = mask & | |
1979 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
1980 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
1981 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
1982 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
1983 | if (events) { | |
1984 | spin_unlock_irqrestore(&info->lock,flags); | |
1985 | goto exit; | |
1986 | } | |
1987 | ||
1988 | /* save current irq counts */ | |
1989 | cprev = info->icount; | |
1990 | oldsigs = info->input_signal_events; | |
d12341f9 | 1991 | |
1da177e4 LT |
1992 | if ((info->params.mode == MGSL_MODE_HDLC) && |
1993 | (mask & MgslEvent_ExitHuntMode)) | |
1994 | irq_enable(info, CHA, IRQ_EXITHUNT); | |
d12341f9 | 1995 | |
1da177e4 LT |
1996 | set_current_state(TASK_INTERRUPTIBLE); |
1997 | add_wait_queue(&info->event_wait_q, &wait); | |
d12341f9 | 1998 | |
1da177e4 | 1999 | spin_unlock_irqrestore(&info->lock,flags); |
d12341f9 JG |
2000 | |
2001 | ||
1da177e4 LT |
2002 | for(;;) { |
2003 | schedule(); | |
2004 | if (signal_pending(current)) { | |
2005 | rc = -ERESTARTSYS; | |
2006 | break; | |
2007 | } | |
d12341f9 | 2008 | |
1da177e4 LT |
2009 | /* get current irq counts */ |
2010 | spin_lock_irqsave(&info->lock,flags); | |
2011 | cnow = info->icount; | |
2012 | newsigs = info->input_signal_events; | |
2013 | set_current_state(TASK_INTERRUPTIBLE); | |
2014 | spin_unlock_irqrestore(&info->lock,flags); | |
2015 | ||
2016 | /* if no change, wait aborted for some reason */ | |
2017 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
2018 | newsigs.dsr_down == oldsigs.dsr_down && | |
2019 | newsigs.dcd_up == oldsigs.dcd_up && | |
2020 | newsigs.dcd_down == oldsigs.dcd_down && | |
2021 | newsigs.cts_up == oldsigs.cts_up && | |
2022 | newsigs.cts_down == oldsigs.cts_down && | |
2023 | newsigs.ri_up == oldsigs.ri_up && | |
2024 | newsigs.ri_down == oldsigs.ri_down && | |
2025 | cnow.exithunt == cprev.exithunt && | |
2026 | cnow.rxidle == cprev.rxidle) { | |
2027 | rc = -EIO; | |
2028 | break; | |
2029 | } | |
2030 | ||
2031 | events = mask & | |
2032 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
2033 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
2034 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
2035 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
2036 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
2037 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
2038 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
2039 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
2040 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
2041 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
2042 | if (events) | |
2043 | break; | |
d12341f9 | 2044 | |
1da177e4 LT |
2045 | cprev = cnow; |
2046 | oldsigs = newsigs; | |
2047 | } | |
d12341f9 | 2048 | |
1da177e4 LT |
2049 | remove_wait_queue(&info->event_wait_q, &wait); |
2050 | set_current_state(TASK_RUNNING); | |
2051 | ||
2052 | if (mask & MgslEvent_ExitHuntMode) { | |
2053 | spin_lock_irqsave(&info->lock,flags); | |
2054 | if (!waitqueue_active(&info->event_wait_q)) | |
2055 | irq_disable(info, CHA, IRQ_EXITHUNT); | |
2056 | spin_unlock_irqrestore(&info->lock,flags); | |
2057 | } | |
2058 | exit: | |
2059 | if (rc == 0) | |
2060 | PUT_USER(rc, events, mask_ptr); | |
2061 | return rc; | |
2062 | } | |
2063 | ||
2064 | static int modem_input_wait(MGSLPC_INFO *info,int arg) | |
2065 | { | |
2066 | unsigned long flags; | |
2067 | int rc; | |
2068 | struct mgsl_icount cprev, cnow; | |
2069 | DECLARE_WAITQUEUE(wait, current); | |
2070 | ||
2071 | /* save current irq counts */ | |
2072 | spin_lock_irqsave(&info->lock,flags); | |
2073 | cprev = info->icount; | |
2074 | add_wait_queue(&info->status_event_wait_q, &wait); | |
2075 | set_current_state(TASK_INTERRUPTIBLE); | |
2076 | spin_unlock_irqrestore(&info->lock,flags); | |
2077 | ||
2078 | for(;;) { | |
2079 | schedule(); | |
2080 | if (signal_pending(current)) { | |
2081 | rc = -ERESTARTSYS; | |
2082 | break; | |
2083 | } | |
2084 | ||
2085 | /* get new irq counts */ | |
2086 | spin_lock_irqsave(&info->lock,flags); | |
2087 | cnow = info->icount; | |
2088 | set_current_state(TASK_INTERRUPTIBLE); | |
2089 | spin_unlock_irqrestore(&info->lock,flags); | |
2090 | ||
2091 | /* if no change, wait aborted for some reason */ | |
2092 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
2093 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
2094 | rc = -EIO; | |
2095 | break; | |
2096 | } | |
2097 | ||
2098 | /* check for change in caller specified modem input */ | |
2099 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
2100 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
2101 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
2102 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
2103 | rc = 0; | |
2104 | break; | |
2105 | } | |
2106 | ||
2107 | cprev = cnow; | |
2108 | } | |
2109 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
2110 | set_current_state(TASK_RUNNING); | |
2111 | return rc; | |
2112 | } | |
2113 | ||
2114 | /* return the state of the serial control and status signals | |
2115 | */ | |
60b33c13 | 2116 | static int tiocmget(struct tty_struct *tty) |
1da177e4 LT |
2117 | { |
2118 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
2119 | unsigned int result; | |
2120 | unsigned long flags; | |
2121 | ||
2122 | spin_lock_irqsave(&info->lock,flags); | |
2123 | get_signals(info); | |
2124 | spin_unlock_irqrestore(&info->lock,flags); | |
2125 | ||
2126 | result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
2127 | ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
2128 | ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
2129 | ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
2130 | ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
2131 | ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
2132 | ||
2133 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2134 | printk("%s(%d):%s tiocmget() value=%08X\n", | |
2135 | __FILE__,__LINE__, info->device_name, result ); | |
2136 | return result; | |
2137 | } | |
2138 | ||
2139 | /* set modem control signals (DTR/RTS) | |
2140 | */ | |
20b9d177 | 2141 | static int tiocmset(struct tty_struct *tty, |
1da177e4 LT |
2142 | unsigned int set, unsigned int clear) |
2143 | { | |
2144 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
2145 | unsigned long flags; | |
2146 | ||
2147 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2148 | printk("%s(%d):%s tiocmset(%x,%x)\n", | |
2149 | __FILE__,__LINE__,info->device_name, set, clear); | |
2150 | ||
2151 | if (set & TIOCM_RTS) | |
2152 | info->serial_signals |= SerialSignal_RTS; | |
2153 | if (set & TIOCM_DTR) | |
2154 | info->serial_signals |= SerialSignal_DTR; | |
2155 | if (clear & TIOCM_RTS) | |
2156 | info->serial_signals &= ~SerialSignal_RTS; | |
2157 | if (clear & TIOCM_DTR) | |
2158 | info->serial_signals &= ~SerialSignal_DTR; | |
2159 | ||
2160 | spin_lock_irqsave(&info->lock,flags); | |
2161 | set_signals(info); | |
2162 | spin_unlock_irqrestore(&info->lock,flags); | |
2163 | ||
2164 | return 0; | |
2165 | } | |
2166 | ||
2167 | /* Set or clear transmit break condition | |
2168 | * | |
2169 | * Arguments: tty pointer to tty instance data | |
2170 | * break_state -1=set break condition, 0=clear | |
2171 | */ | |
9e98966c | 2172 | static int mgslpc_break(struct tty_struct *tty, int break_state) |
1da177e4 LT |
2173 | { |
2174 | MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; | |
2175 | unsigned long flags; | |
d12341f9 | 2176 | |
1da177e4 LT |
2177 | if (debug_level >= DEBUG_LEVEL_INFO) |
2178 | printk("%s(%d):mgslpc_break(%s,%d)\n", | |
2179 | __FILE__,__LINE__, info->device_name, break_state); | |
d12341f9 | 2180 | |
1da177e4 | 2181 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break")) |
9e98966c | 2182 | return -EINVAL; |
1da177e4 LT |
2183 | |
2184 | spin_lock_irqsave(&info->lock,flags); | |
2185 | if (break_state == -1) | |
2186 | set_reg_bits(info, CHA+DAFO, BIT6); | |
d12341f9 | 2187 | else |
1da177e4 LT |
2188 | clear_reg_bits(info, CHA+DAFO, BIT6); |
2189 | spin_unlock_irqrestore(&info->lock,flags); | |
9e98966c | 2190 | return 0; |
1da177e4 LT |
2191 | } |
2192 | ||
0587102c AC |
2193 | static int mgslpc_get_icount(struct tty_struct *tty, |
2194 | struct serial_icounter_struct *icount) | |
2195 | { | |
2196 | MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; | |
2197 | struct mgsl_icount cnow; /* kernel counter temps */ | |
2198 | unsigned long flags; | |
2199 | ||
2200 | spin_lock_irqsave(&info->lock,flags); | |
2201 | cnow = info->icount; | |
2202 | spin_unlock_irqrestore(&info->lock,flags); | |
2203 | ||
2204 | icount->cts = cnow.cts; | |
2205 | icount->dsr = cnow.dsr; | |
2206 | icount->rng = cnow.rng; | |
2207 | icount->dcd = cnow.dcd; | |
2208 | icount->rx = cnow.rx; | |
2209 | icount->tx = cnow.tx; | |
2210 | icount->frame = cnow.frame; | |
2211 | icount->overrun = cnow.overrun; | |
2212 | icount->parity = cnow.parity; | |
2213 | icount->brk = cnow.brk; | |
2214 | icount->buf_overrun = cnow.buf_overrun; | |
2215 | ||
2216 | return 0; | |
2217 | } | |
2218 | ||
1da177e4 | 2219 | /* Service an IOCTL request |
d12341f9 | 2220 | * |
1da177e4 | 2221 | * Arguments: |
d12341f9 | 2222 | * |
1da177e4 | 2223 | * tty pointer to tty instance data |
1da177e4 LT |
2224 | * cmd IOCTL command code |
2225 | * arg command argument/context | |
d12341f9 | 2226 | * |
1da177e4 LT |
2227 | * Return Value: 0 if success, otherwise error code |
2228 | */ | |
751b3840 | 2229 | static int mgslpc_ioctl(struct tty_struct *tty, |
1da177e4 LT |
2230 | unsigned int cmd, unsigned long arg) |
2231 | { | |
2232 | MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; | |
eeb46134 | 2233 | void __user *argp = (void __user *)arg; |
d12341f9 | 2234 | |
1da177e4 LT |
2235 | if (debug_level >= DEBUG_LEVEL_INFO) |
2236 | printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__, | |
2237 | info->device_name, cmd ); | |
d12341f9 | 2238 | |
1da177e4 LT |
2239 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl")) |
2240 | return -ENODEV; | |
2241 | ||
2242 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
0587102c | 2243 | (cmd != TIOCMIWAIT)) { |
1da177e4 LT |
2244 | if (tty->flags & (1 << TTY_IO_ERROR)) |
2245 | return -EIO; | |
2246 | } | |
2247 | ||
1da177e4 LT |
2248 | switch (cmd) { |
2249 | case MGSL_IOCGPARAMS: | |
2250 | return get_params(info, argp); | |
2251 | case MGSL_IOCSPARAMS: | |
eeb46134 | 2252 | return set_params(info, argp, tty); |
1da177e4 LT |
2253 | case MGSL_IOCGTXIDLE: |
2254 | return get_txidle(info, argp); | |
2255 | case MGSL_IOCSTXIDLE: | |
2256 | return set_txidle(info, (int)arg); | |
2257 | case MGSL_IOCGIF: | |
2258 | return get_interface(info, argp); | |
2259 | case MGSL_IOCSIF: | |
2260 | return set_interface(info,(int)arg); | |
2261 | case MGSL_IOCTXENABLE: | |
eeb46134 | 2262 | return set_txenable(info,(int)arg, tty); |
1da177e4 LT |
2263 | case MGSL_IOCRXENABLE: |
2264 | return set_rxenable(info,(int)arg); | |
2265 | case MGSL_IOCTXABORT: | |
2266 | return tx_abort(info); | |
2267 | case MGSL_IOCGSTATS: | |
2268 | return get_stats(info, argp); | |
2269 | case MGSL_IOCWAITEVENT: | |
2270 | return wait_events(info, argp); | |
2271 | case TIOCMIWAIT: | |
2272 | return modem_input_wait(info,(int)arg); | |
1da177e4 LT |
2273 | default: |
2274 | return -ENOIOCTLCMD; | |
2275 | } | |
2276 | return 0; | |
2277 | } | |
2278 | ||
2279 | /* Set new termios settings | |
d12341f9 | 2280 | * |
1da177e4 | 2281 | * Arguments: |
d12341f9 | 2282 | * |
1da177e4 LT |
2283 | * tty pointer to tty structure |
2284 | * termios pointer to buffer to hold returned old termios | |
2285 | */ | |
606d099c | 2286 | static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1da177e4 LT |
2287 | { |
2288 | MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; | |
2289 | unsigned long flags; | |
d12341f9 | 2290 | |
1da177e4 LT |
2291 | if (debug_level >= DEBUG_LEVEL_INFO) |
2292 | printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__, | |
2293 | tty->driver->name ); | |
d12341f9 | 2294 | |
1da177e4 | 2295 | /* just return if nothing has changed */ |
373f5aed AC |
2296 | if ((tty->termios.c_cflag == old_termios->c_cflag) |
2297 | && (RELEVANT_IFLAG(tty->termios.c_iflag) | |
1da177e4 LT |
2298 | == RELEVANT_IFLAG(old_termios->c_iflag))) |
2299 | return; | |
2300 | ||
eeb46134 | 2301 | mgslpc_change_params(info, tty); |
1da177e4 LT |
2302 | |
2303 | /* Handle transition to B0 status */ | |
2304 | if (old_termios->c_cflag & CBAUD && | |
373f5aed | 2305 | !(tty->termios.c_cflag & CBAUD)) { |
1da177e4 LT |
2306 | info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); |
2307 | spin_lock_irqsave(&info->lock,flags); | |
2308 | set_signals(info); | |
2309 | spin_unlock_irqrestore(&info->lock,flags); | |
2310 | } | |
d12341f9 | 2311 | |
1da177e4 LT |
2312 | /* Handle transition away from B0 status */ |
2313 | if (!(old_termios->c_cflag & CBAUD) && | |
373f5aed | 2314 | tty->termios.c_cflag & CBAUD) { |
1da177e4 | 2315 | info->serial_signals |= SerialSignal_DTR; |
373f5aed | 2316 | if (!(tty->termios.c_cflag & CRTSCTS) || |
1da177e4 LT |
2317 | !test_bit(TTY_THROTTLED, &tty->flags)) { |
2318 | info->serial_signals |= SerialSignal_RTS; | |
2319 | } | |
2320 | spin_lock_irqsave(&info->lock,flags); | |
2321 | set_signals(info); | |
2322 | spin_unlock_irqrestore(&info->lock,flags); | |
2323 | } | |
d12341f9 | 2324 | |
1da177e4 LT |
2325 | /* Handle turning off CRTSCTS */ |
2326 | if (old_termios->c_cflag & CRTSCTS && | |
373f5aed | 2327 | !(tty->termios.c_cflag & CRTSCTS)) { |
1da177e4 LT |
2328 | tty->hw_stopped = 0; |
2329 | tx_release(tty); | |
2330 | } | |
2331 | } | |
2332 | ||
2333 | static void mgslpc_close(struct tty_struct *tty, struct file * filp) | |
2334 | { | |
2335 | MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; | |
eeb46134 | 2336 | struct tty_port *port = &info->port; |
1da177e4 LT |
2337 | |
2338 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close")) | |
2339 | return; | |
d12341f9 | 2340 | |
1da177e4 LT |
2341 | if (debug_level >= DEBUG_LEVEL_INFO) |
2342 | printk("%s(%d):mgslpc_close(%s) entry, count=%d\n", | |
eeb46134 | 2343 | __FILE__,__LINE__, info->device_name, port->count); |
1da177e4 | 2344 | |
eeb46134 | 2345 | WARN_ON(!port->count); |
d12341f9 | 2346 | |
eeb46134 | 2347 | if (tty_port_close_start(port, tty, filp) == 0) |
1da177e4 | 2348 | goto cleanup; |
d12341f9 | 2349 | |
eeb46134 | 2350 | if (port->flags & ASYNC_INITIALIZED) |
1da177e4 LT |
2351 | mgslpc_wait_until_sent(tty, info->timeout); |
2352 | ||
978e595f | 2353 | mgslpc_flush_buffer(tty); |
1da177e4 | 2354 | |
978e595f | 2355 | tty_ldisc_flush(tty); |
eeb46134 AC |
2356 | shutdown(info, tty); |
2357 | ||
2358 | tty_port_close_end(port, tty); | |
2359 | tty_port_tty_set(port, NULL); | |
d12341f9 | 2360 | cleanup: |
1da177e4 LT |
2361 | if (debug_level >= DEBUG_LEVEL_INFO) |
2362 | printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__, | |
eeb46134 | 2363 | tty->driver->name, port->count); |
1da177e4 LT |
2364 | } |
2365 | ||
2366 | /* Wait until the transmitter is empty. | |
2367 | */ | |
2368 | static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout) | |
2369 | { | |
2370 | MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; | |
2371 | unsigned long orig_jiffies, char_time; | |
2372 | ||
2373 | if (!info ) | |
2374 | return; | |
2375 | ||
2376 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2377 | printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n", | |
2378 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 | 2379 | |
1da177e4 LT |
2380 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent")) |
2381 | return; | |
2382 | ||
eeb46134 | 2383 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
1da177e4 | 2384 | goto exit; |
d12341f9 | 2385 | |
1da177e4 | 2386 | orig_jiffies = jiffies; |
d12341f9 | 2387 | |
1da177e4 LT |
2388 | /* Set check interval to 1/5 of estimated time to |
2389 | * send a character, and make it at least 1. The check | |
2390 | * interval should also be less than the timeout. | |
2391 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
d12341f9 JG |
2392 | */ |
2393 | ||
1da177e4 LT |
2394 | if ( info->params.data_rate ) { |
2395 | char_time = info->timeout/(32 * 5); | |
2396 | if (!char_time) | |
2397 | char_time++; | |
2398 | } else | |
2399 | char_time = 1; | |
d12341f9 | 2400 | |
1da177e4 LT |
2401 | if (timeout) |
2402 | char_time = min_t(unsigned long, char_time, timeout); | |
d12341f9 | 2403 | |
1da177e4 LT |
2404 | if (info->params.mode == MGSL_MODE_HDLC) { |
2405 | while (info->tx_active) { | |
2406 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
2407 | if (signal_pending(current)) | |
2408 | break; | |
2409 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
2410 | break; | |
2411 | } | |
2412 | } else { | |
2413 | while ((info->tx_count || info->tx_active) && | |
2414 | info->tx_enabled) { | |
2415 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
2416 | if (signal_pending(current)) | |
2417 | break; | |
2418 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
2419 | break; | |
2420 | } | |
2421 | } | |
d12341f9 | 2422 | |
1da177e4 LT |
2423 | exit: |
2424 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2425 | printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n", | |
2426 | __FILE__,__LINE__, info->device_name ); | |
2427 | } | |
2428 | ||
2429 | /* Called by tty_hangup() when a hangup is signaled. | |
2430 | * This is the same as closing all open files for the port. | |
2431 | */ | |
2432 | static void mgslpc_hangup(struct tty_struct *tty) | |
2433 | { | |
2434 | MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; | |
d12341f9 | 2435 | |
1da177e4 LT |
2436 | if (debug_level >= DEBUG_LEVEL_INFO) |
2437 | printk("%s(%d):mgslpc_hangup(%s)\n", | |
2438 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 | 2439 | |
1da177e4 LT |
2440 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup")) |
2441 | return; | |
2442 | ||
2443 | mgslpc_flush_buffer(tty); | |
eeb46134 AC |
2444 | shutdown(info, tty); |
2445 | tty_port_hangup(&info->port); | |
1da177e4 LT |
2446 | } |
2447 | ||
eeb46134 | 2448 | static int carrier_raised(struct tty_port *port) |
1da177e4 | 2449 | { |
eeb46134 AC |
2450 | MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port); |
2451 | unsigned long flags; | |
d12341f9 | 2452 | |
eeb46134 AC |
2453 | spin_lock_irqsave(&info->lock,flags); |
2454 | get_signals(info); | |
2455 | spin_unlock_irqrestore(&info->lock,flags); | |
d12341f9 | 2456 | |
eeb46134 AC |
2457 | if (info->serial_signals & SerialSignal_DCD) |
2458 | return 1; | |
2459 | return 0; | |
2460 | } | |
d12341f9 | 2461 | |
fcc8ac18 | 2462 | static void dtr_rts(struct tty_port *port, int onoff) |
eeb46134 AC |
2463 | { |
2464 | MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port); | |
2465 | unsigned long flags; | |
d12341f9 | 2466 | |
eeb46134 | 2467 | spin_lock_irqsave(&info->lock,flags); |
fcc8ac18 AC |
2468 | if (onoff) |
2469 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2470 | else | |
2471 | info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR; | |
eeb46134 AC |
2472 | set_signals(info); |
2473 | spin_unlock_irqrestore(&info->lock,flags); | |
1da177e4 LT |
2474 | } |
2475 | ||
eeb46134 | 2476 | |
1da177e4 LT |
2477 | static int mgslpc_open(struct tty_struct *tty, struct file * filp) |
2478 | { | |
2479 | MGSLPC_INFO *info; | |
eeb46134 | 2480 | struct tty_port *port; |
1da177e4 LT |
2481 | int retval, line; |
2482 | unsigned long flags; | |
2483 | ||
d12341f9 | 2484 | /* verify range of specified line number */ |
1da177e4 | 2485 | line = tty->index; |
410235fd | 2486 | if (line >= mgslpc_device_count) { |
1da177e4 LT |
2487 | printk("%s(%d):mgslpc_open with invalid line #%d.\n", |
2488 | __FILE__,__LINE__,line); | |
2489 | return -ENODEV; | |
2490 | } | |
2491 | ||
2492 | /* find the info structure for the specified line */ | |
2493 | info = mgslpc_device_list; | |
2494 | while(info && info->line != line) | |
2495 | info = info->next_device; | |
2496 | if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open")) | |
2497 | return -ENODEV; | |
d12341f9 | 2498 | |
eeb46134 | 2499 | port = &info->port; |
1da177e4 | 2500 | tty->driver_data = info; |
eeb46134 | 2501 | tty_port_tty_set(port, tty); |
d12341f9 | 2502 | |
1da177e4 LT |
2503 | if (debug_level >= DEBUG_LEVEL_INFO) |
2504 | printk("%s(%d):mgslpc_open(%s), old ref count = %d\n", | |
eeb46134 | 2505 | __FILE__,__LINE__,tty->driver->name, port->count); |
1da177e4 LT |
2506 | |
2507 | /* If port is closing, signal caller to try again */ | |
eeb46134 AC |
2508 | if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){ |
2509 | if (port->flags & ASYNC_CLOSING) | |
2510 | interruptible_sleep_on(&port->close_wait); | |
2511 | retval = ((port->flags & ASYNC_HUP_NOTIFY) ? | |
1da177e4 LT |
2512 | -EAGAIN : -ERESTARTSYS); |
2513 | goto cleanup; | |
2514 | } | |
d12341f9 | 2515 | |
eeb46134 | 2516 | tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
1da177e4 LT |
2517 | |
2518 | spin_lock_irqsave(&info->netlock, flags); | |
2519 | if (info->netcount) { | |
2520 | retval = -EBUSY; | |
2521 | spin_unlock_irqrestore(&info->netlock, flags); | |
2522 | goto cleanup; | |
2523 | } | |
eeb46134 AC |
2524 | spin_lock(&port->lock); |
2525 | port->count++; | |
2526 | spin_unlock(&port->lock); | |
1da177e4 LT |
2527 | spin_unlock_irqrestore(&info->netlock, flags); |
2528 | ||
eeb46134 | 2529 | if (port->count == 1) { |
1da177e4 | 2530 | /* 1st open on this device, init hardware */ |
eeb46134 | 2531 | retval = startup(info, tty); |
1da177e4 LT |
2532 | if (retval < 0) |
2533 | goto cleanup; | |
2534 | } | |
2535 | ||
eeb46134 | 2536 | retval = tty_port_block_til_ready(&info->port, tty, filp); |
1da177e4 LT |
2537 | if (retval) { |
2538 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2539 | printk("%s(%d):block_til_ready(%s) returned %d\n", | |
2540 | __FILE__,__LINE__, info->device_name, retval); | |
2541 | goto cleanup; | |
2542 | } | |
2543 | ||
2544 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2545 | printk("%s(%d):mgslpc_open(%s) success\n", | |
2546 | __FILE__,__LINE__, info->device_name); | |
2547 | retval = 0; | |
d12341f9 JG |
2548 | |
2549 | cleanup: | |
1da177e4 LT |
2550 | return retval; |
2551 | } | |
2552 | ||
2553 | /* | |
2554 | * /proc fs routines.... | |
2555 | */ | |
2556 | ||
87687144 | 2557 | static inline void line_info(struct seq_file *m, MGSLPC_INFO *info) |
1da177e4 LT |
2558 | { |
2559 | char stat_buf[30]; | |
1da177e4 LT |
2560 | unsigned long flags; |
2561 | ||
87687144 | 2562 | seq_printf(m, "%s:io:%04X irq:%d", |
1da177e4 LT |
2563 | info->device_name, info->io_base, info->irq_level); |
2564 | ||
2565 | /* output current serial signal states */ | |
2566 | spin_lock_irqsave(&info->lock,flags); | |
2567 | get_signals(info); | |
2568 | spin_unlock_irqrestore(&info->lock,flags); | |
d12341f9 | 2569 | |
1da177e4 LT |
2570 | stat_buf[0] = 0; |
2571 | stat_buf[1] = 0; | |
2572 | if (info->serial_signals & SerialSignal_RTS) | |
2573 | strcat(stat_buf, "|RTS"); | |
2574 | if (info->serial_signals & SerialSignal_CTS) | |
2575 | strcat(stat_buf, "|CTS"); | |
2576 | if (info->serial_signals & SerialSignal_DTR) | |
2577 | strcat(stat_buf, "|DTR"); | |
2578 | if (info->serial_signals & SerialSignal_DSR) | |
2579 | strcat(stat_buf, "|DSR"); | |
2580 | if (info->serial_signals & SerialSignal_DCD) | |
2581 | strcat(stat_buf, "|CD"); | |
2582 | if (info->serial_signals & SerialSignal_RI) | |
2583 | strcat(stat_buf, "|RI"); | |
2584 | ||
2585 | if (info->params.mode == MGSL_MODE_HDLC) { | |
87687144 | 2586 | seq_printf(m, " HDLC txok:%d rxok:%d", |
1da177e4 LT |
2587 | info->icount.txok, info->icount.rxok); |
2588 | if (info->icount.txunder) | |
87687144 | 2589 | seq_printf(m, " txunder:%d", info->icount.txunder); |
1da177e4 | 2590 | if (info->icount.txabort) |
87687144 | 2591 | seq_printf(m, " txabort:%d", info->icount.txabort); |
1da177e4 | 2592 | if (info->icount.rxshort) |
87687144 | 2593 | seq_printf(m, " rxshort:%d", info->icount.rxshort); |
1da177e4 | 2594 | if (info->icount.rxlong) |
87687144 | 2595 | seq_printf(m, " rxlong:%d", info->icount.rxlong); |
1da177e4 | 2596 | if (info->icount.rxover) |
87687144 | 2597 | seq_printf(m, " rxover:%d", info->icount.rxover); |
1da177e4 | 2598 | if (info->icount.rxcrc) |
87687144 | 2599 | seq_printf(m, " rxcrc:%d", info->icount.rxcrc); |
1da177e4 | 2600 | } else { |
87687144 | 2601 | seq_printf(m, " ASYNC tx:%d rx:%d", |
1da177e4 LT |
2602 | info->icount.tx, info->icount.rx); |
2603 | if (info->icount.frame) | |
87687144 | 2604 | seq_printf(m, " fe:%d", info->icount.frame); |
1da177e4 | 2605 | if (info->icount.parity) |
87687144 | 2606 | seq_printf(m, " pe:%d", info->icount.parity); |
1da177e4 | 2607 | if (info->icount.brk) |
87687144 | 2608 | seq_printf(m, " brk:%d", info->icount.brk); |
1da177e4 | 2609 | if (info->icount.overrun) |
87687144 | 2610 | seq_printf(m, " oe:%d", info->icount.overrun); |
1da177e4 | 2611 | } |
d12341f9 | 2612 | |
1da177e4 | 2613 | /* Append serial signal status to end */ |
87687144 | 2614 | seq_printf(m, " %s\n", stat_buf+1); |
d12341f9 | 2615 | |
87687144 | 2616 | seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", |
1da177e4 LT |
2617 | info->tx_active,info->bh_requested,info->bh_running, |
2618 | info->pending_bh); | |
1da177e4 LT |
2619 | } |
2620 | ||
2621 | /* Called to print information about devices | |
2622 | */ | |
87687144 | 2623 | static int mgslpc_proc_show(struct seq_file *m, void *v) |
1da177e4 | 2624 | { |
1da177e4 | 2625 | MGSLPC_INFO *info; |
d12341f9 | 2626 | |
87687144 | 2627 | seq_printf(m, "synclink driver:%s\n", driver_version); |
d12341f9 | 2628 | |
1da177e4 LT |
2629 | info = mgslpc_device_list; |
2630 | while( info ) { | |
87687144 | 2631 | line_info(m, info); |
1da177e4 LT |
2632 | info = info->next_device; |
2633 | } | |
87687144 AD |
2634 | return 0; |
2635 | } | |
1da177e4 | 2636 | |
87687144 AD |
2637 | static int mgslpc_proc_open(struct inode *inode, struct file *file) |
2638 | { | |
2639 | return single_open(file, mgslpc_proc_show, NULL); | |
1da177e4 LT |
2640 | } |
2641 | ||
87687144 AD |
2642 | static const struct file_operations mgslpc_proc_fops = { |
2643 | .owner = THIS_MODULE, | |
2644 | .open = mgslpc_proc_open, | |
2645 | .read = seq_read, | |
2646 | .llseek = seq_lseek, | |
2647 | .release = single_release, | |
2648 | }; | |
2649 | ||
cdaad343 | 2650 | static int rx_alloc_buffers(MGSLPC_INFO *info) |
1da177e4 LT |
2651 | { |
2652 | /* each buffer has header and data */ | |
2653 | info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size; | |
2654 | ||
2655 | /* calculate total allocation size for 8 buffers */ | |
2656 | info->rx_buf_total_size = info->rx_buf_size * 8; | |
2657 | ||
2658 | /* limit total allocated memory */ | |
2659 | if (info->rx_buf_total_size > 0x10000) | |
2660 | info->rx_buf_total_size = 0x10000; | |
2661 | ||
2662 | /* calculate number of buffers */ | |
2663 | info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size; | |
2664 | ||
2665 | info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL); | |
2666 | if (info->rx_buf == NULL) | |
2667 | return -ENOMEM; | |
2668 | ||
2669 | rx_reset_buffers(info); | |
2670 | return 0; | |
2671 | } | |
2672 | ||
cdaad343 | 2673 | static void rx_free_buffers(MGSLPC_INFO *info) |
1da177e4 | 2674 | { |
735d5661 | 2675 | kfree(info->rx_buf); |
1da177e4 LT |
2676 | info->rx_buf = NULL; |
2677 | } | |
2678 | ||
cdaad343 | 2679 | static int claim_resources(MGSLPC_INFO *info) |
1da177e4 LT |
2680 | { |
2681 | if (rx_alloc_buffers(info) < 0 ) { | |
25985edc | 2682 | printk( "Can't allocate rx buffer %s\n", info->device_name); |
1da177e4 LT |
2683 | release_resources(info); |
2684 | return -ENODEV; | |
d12341f9 | 2685 | } |
1da177e4 LT |
2686 | return 0; |
2687 | } | |
2688 | ||
cdaad343 | 2689 | static void release_resources(MGSLPC_INFO *info) |
1da177e4 LT |
2690 | { |
2691 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2692 | printk("release_resources(%s)\n", info->device_name); | |
2693 | rx_free_buffers(info); | |
2694 | } | |
2695 | ||
2696 | /* Add the specified device instance data structure to the | |
2697 | * global linked list of devices and increment the device count. | |
d12341f9 | 2698 | * |
1da177e4 LT |
2699 | * Arguments: info pointer to device instance data |
2700 | */ | |
cdaad343 | 2701 | static void mgslpc_add_device(MGSLPC_INFO *info) |
1da177e4 LT |
2702 | { |
2703 | info->next_device = NULL; | |
2704 | info->line = mgslpc_device_count; | |
2705 | sprintf(info->device_name,"ttySLP%d",info->line); | |
d12341f9 | 2706 | |
1da177e4 LT |
2707 | if (info->line < MAX_DEVICE_COUNT) { |
2708 | if (maxframe[info->line]) | |
2709 | info->max_frame_size = maxframe[info->line]; | |
1da177e4 LT |
2710 | } |
2711 | ||
2712 | mgslpc_device_count++; | |
d12341f9 | 2713 | |
1da177e4 LT |
2714 | if (!mgslpc_device_list) |
2715 | mgslpc_device_list = info; | |
d12341f9 | 2716 | else { |
1da177e4 LT |
2717 | MGSLPC_INFO *current_dev = mgslpc_device_list; |
2718 | while( current_dev->next_device ) | |
2719 | current_dev = current_dev->next_device; | |
2720 | current_dev->next_device = info; | |
2721 | } | |
d12341f9 | 2722 | |
1da177e4 LT |
2723 | if (info->max_frame_size < 4096) |
2724 | info->max_frame_size = 4096; | |
2725 | else if (info->max_frame_size > 65535) | |
2726 | info->max_frame_size = 65535; | |
d12341f9 | 2727 | |
1da177e4 LT |
2728 | printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n", |
2729 | info->device_name, info->io_base, info->irq_level); | |
2730 | ||
af69c7f9 | 2731 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
2732 | hdlcdev_init(info); |
2733 | #endif | |
16a1065f JS |
2734 | tty_port_register_device(&info->port, serial_driver, info->line, |
2735 | &info->p_dev.dev); | |
1da177e4 LT |
2736 | } |
2737 | ||
cdaad343 | 2738 | static void mgslpc_remove_device(MGSLPC_INFO *remove_info) |
1da177e4 LT |
2739 | { |
2740 | MGSLPC_INFO *info = mgslpc_device_list; | |
2741 | MGSLPC_INFO *last = NULL; | |
2742 | ||
2743 | while(info) { | |
2744 | if (info == remove_info) { | |
2745 | if (last) | |
2746 | last->next_device = info->next_device; | |
2747 | else | |
2748 | mgslpc_device_list = info->next_device; | |
16a1065f | 2749 | tty_unregister_device(serial_driver, info->line); |
af69c7f9 | 2750 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
2751 | hdlcdev_exit(info); |
2752 | #endif | |
2753 | release_resources(info); | |
2754 | kfree(info); | |
2755 | mgslpc_device_count--; | |
2756 | return; | |
2757 | } | |
2758 | last = info; | |
2759 | info = info->next_device; | |
2760 | } | |
2761 | } | |
2762 | ||
25f8f54f | 2763 | static const struct pcmcia_device_id mgslpc_ids[] = { |
4af48c8c DB |
2764 | PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050), |
2765 | PCMCIA_DEVICE_NULL | |
2766 | }; | |
2767 | MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids); | |
2768 | ||
1da177e4 LT |
2769 | static struct pcmcia_driver mgslpc_driver = { |
2770 | .owner = THIS_MODULE, | |
2e9b981a | 2771 | .name = "synclink_cs", |
15b99ac1 | 2772 | .probe = mgslpc_probe, |
cc3b4866 | 2773 | .remove = mgslpc_detach, |
4af48c8c | 2774 | .id_table = mgslpc_ids, |
98e4c28b DB |
2775 | .suspend = mgslpc_suspend, |
2776 | .resume = mgslpc_resume, | |
1da177e4 LT |
2777 | }; |
2778 | ||
b68e31d0 | 2779 | static const struct tty_operations mgslpc_ops = { |
1da177e4 LT |
2780 | .open = mgslpc_open, |
2781 | .close = mgslpc_close, | |
2782 | .write = mgslpc_write, | |
2783 | .put_char = mgslpc_put_char, | |
2784 | .flush_chars = mgslpc_flush_chars, | |
2785 | .write_room = mgslpc_write_room, | |
2786 | .chars_in_buffer = mgslpc_chars_in_buffer, | |
2787 | .flush_buffer = mgslpc_flush_buffer, | |
2788 | .ioctl = mgslpc_ioctl, | |
2789 | .throttle = mgslpc_throttle, | |
2790 | .unthrottle = mgslpc_unthrottle, | |
2791 | .send_xchar = mgslpc_send_xchar, | |
2792 | .break_ctl = mgslpc_break, | |
2793 | .wait_until_sent = mgslpc_wait_until_sent, | |
1da177e4 LT |
2794 | .set_termios = mgslpc_set_termios, |
2795 | .stop = tx_pause, | |
2796 | .start = tx_release, | |
2797 | .hangup = mgslpc_hangup, | |
2798 | .tiocmget = tiocmget, | |
2799 | .tiocmset = tiocmset, | |
dc98d965 | 2800 | .get_icount = mgslpc_get_icount, |
87687144 | 2801 | .proc_fops = &mgslpc_proc_fops, |
1da177e4 LT |
2802 | }; |
2803 | ||
1da177e4 LT |
2804 | static int __init synclink_cs_init(void) |
2805 | { | |
2806 | int rc; | |
2807 | ||
2808 | if (break_on_load) { | |
2809 | mgslpc_get_text_ptr(); | |
2810 | BREAKPOINT(); | |
2811 | } | |
2812 | ||
16a1065f JS |
2813 | serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT, |
2814 | TTY_DRIVER_REAL_RAW | | |
2815 | TTY_DRIVER_DYNAMIC_DEV); | |
1da177e4 LT |
2816 | if (!serial_driver) { |
2817 | rc = -ENOMEM; | |
16a1065f | 2818 | goto err; |
1da177e4 LT |
2819 | } |
2820 | ||
2821 | /* Initialize the tty_driver structure */ | |
d12341f9 | 2822 | |
1da177e4 LT |
2823 | serial_driver->driver_name = "synclink_cs"; |
2824 | serial_driver->name = "ttySLP"; | |
2825 | serial_driver->major = ttymajor; | |
2826 | serial_driver->minor_start = 64; | |
2827 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
2828 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
2829 | serial_driver->init_termios = tty_std_termios; | |
2830 | serial_driver->init_termios.c_cflag = | |
2831 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
1da177e4 LT |
2832 | tty_set_operations(serial_driver, &mgslpc_ops); |
2833 | ||
2834 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
2835 | printk("%s(%d):Couldn't register serial driver\n", | |
2836 | __FILE__,__LINE__); | |
737586fe | 2837 | goto err_put_tty; |
1da177e4 | 2838 | } |
d12341f9 | 2839 | |
16a1065f JS |
2840 | rc = pcmcia_register_driver(&mgslpc_driver); |
2841 | if (rc < 0) | |
2842 | goto err_unreg_tty; | |
2843 | ||
1da177e4 LT |
2844 | printk("%s %s, tty major#%d\n", |
2845 | driver_name, driver_version, | |
2846 | serial_driver->major); | |
d12341f9 | 2847 | |
737586fe | 2848 | return 0; |
16a1065f JS |
2849 | err_unreg_tty: |
2850 | tty_unregister_driver(serial_driver); | |
737586fe JS |
2851 | err_put_tty: |
2852 | put_tty_driver(serial_driver); | |
16a1065f | 2853 | err: |
737586fe | 2854 | return rc; |
1da177e4 LT |
2855 | } |
2856 | ||
d12341f9 | 2857 | static void __exit synclink_cs_exit(void) |
1da177e4 | 2858 | { |
16a1065f | 2859 | pcmcia_unregister_driver(&mgslpc_driver); |
737586fe JS |
2860 | tty_unregister_driver(serial_driver); |
2861 | put_tty_driver(serial_driver); | |
1da177e4 LT |
2862 | } |
2863 | ||
2864 | module_init(synclink_cs_init); | |
2865 | module_exit(synclink_cs_exit); | |
2866 | ||
2867 | static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate) | |
2868 | { | |
2869 | unsigned int M, N; | |
2870 | unsigned char val; | |
2871 | ||
d12341f9 JG |
2872 | /* note:standard BRG mode is broken in V3.2 chip |
2873 | * so enhanced mode is always used | |
1da177e4 LT |
2874 | */ |
2875 | ||
2876 | if (rate) { | |
2877 | N = 3686400 / rate; | |
2878 | if (!N) | |
2879 | N = 1; | |
2880 | N >>= 1; | |
2881 | for (M = 1; N > 64 && M < 16; M++) | |
2882 | N >>= 1; | |
2883 | N--; | |
2884 | ||
2885 | /* BGR[5..0] = N | |
2886 | * BGR[9..6] = M | |
2887 | * BGR[7..0] contained in BGR register | |
2888 | * BGR[9..8] contained in CCR2[7..6] | |
2889 | * divisor = (N+1)*2^M | |
2890 | * | |
2891 | * Note: M *must* not be zero (causes asymetric duty cycle) | |
d12341f9 | 2892 | */ |
1da177e4 LT |
2893 | write_reg(info, (unsigned char) (channel + BGR), |
2894 | (unsigned char) ((M << 6) + N)); | |
2895 | val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; | |
2896 | val |= ((M << 4) & 0xc0); | |
2897 | write_reg(info, (unsigned char) (channel + CCR2), val); | |
2898 | } | |
2899 | } | |
2900 | ||
2901 | /* Enabled the AUX clock output at the specified frequency. | |
2902 | */ | |
2903 | static void enable_auxclk(MGSLPC_INFO *info) | |
2904 | { | |
2905 | unsigned char val; | |
d12341f9 | 2906 | |
1da177e4 LT |
2907 | /* MODE |
2908 | * | |
2909 | * 07..06 MDS[1..0] 10 = transparent HDLC mode | |
2910 | * 05 ADM Address Mode, 0 = no addr recognition | |
2911 | * 04 TMD Timer Mode, 0 = external | |
2912 | * 03 RAC Receiver Active, 0 = inactive | |
2913 | * 02 RTS 0=RTS active during xmit, 1=RTS always active | |
2914 | * 01 TRS Timer Resolution, 1=512 | |
2915 | * 00 TLP Test Loop, 0 = no loop | |
2916 | * | |
2917 | * 1000 0010 | |
d12341f9 | 2918 | */ |
1da177e4 | 2919 | val = 0x82; |
d12341f9 JG |
2920 | |
2921 | /* channel B RTS is used to enable AUXCLK driver on SP505 */ | |
1da177e4 LT |
2922 | if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) |
2923 | val |= BIT2; | |
2924 | write_reg(info, CHB + MODE, val); | |
d12341f9 | 2925 | |
1da177e4 LT |
2926 | /* CCR0 |
2927 | * | |
2928 | * 07 PU Power Up, 1=active, 0=power down | |
2929 | * 06 MCE Master Clock Enable, 1=enabled | |
2930 | * 05 Reserved, 0 | |
2931 | * 04..02 SC[2..0] Encoding | |
2932 | * 01..00 SM[1..0] Serial Mode, 00=HDLC | |
2933 | * | |
2934 | * 11000000 | |
d12341f9 | 2935 | */ |
1da177e4 | 2936 | write_reg(info, CHB + CCR0, 0xc0); |
d12341f9 | 2937 | |
1da177e4 LT |
2938 | /* CCR1 |
2939 | * | |
2940 | * 07 SFLG Shared Flag, 0 = disable shared flags | |
2941 | * 06 GALP Go Active On Loop, 0 = not used | |
2942 | * 05 GLP Go On Loop, 0 = not used | |
2943 | * 04 ODS Output Driver Select, 1=TxD is push-pull output | |
2944 | * 03 ITF Interframe Time Fill, 0=mark, 1=flag | |
2945 | * 02..00 CM[2..0] Clock Mode | |
2946 | * | |
2947 | * 0001 0111 | |
d12341f9 | 2948 | */ |
1da177e4 | 2949 | write_reg(info, CHB + CCR1, 0x17); |
d12341f9 | 2950 | |
1da177e4 LT |
2951 | /* CCR2 (Channel B) |
2952 | * | |
2953 | * 07..06 BGR[9..8] Baud rate bits 9..8 | |
2954 | * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value | |
2955 | * 04 SSEL Clock source select, 1=submode b | |
2956 | * 03 TOE 0=TxCLK is input, 1=TxCLK is output | |
2957 | * 02 RWX Read/Write Exchange 0=disabled | |
2958 | * 01 C32, CRC select, 0=CRC-16, 1=CRC-32 | |
2959 | * 00 DIV, data inversion 0=disabled, 1=enabled | |
2960 | * | |
2961 | * 0011 1000 | |
d12341f9 | 2962 | */ |
1da177e4 LT |
2963 | if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) |
2964 | write_reg(info, CHB + CCR2, 0x38); | |
2965 | else | |
2966 | write_reg(info, CHB + CCR2, 0x30); | |
d12341f9 | 2967 | |
1da177e4 LT |
2968 | /* CCR4 |
2969 | * | |
2970 | * 07 MCK4 Master Clock Divide by 4, 1=enabled | |
2971 | * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled | |
2972 | * 05 TST1 Test Pin, 0=normal operation | |
2973 | * 04 ICD Ivert Carrier Detect, 1=enabled (active low) | |
2974 | * 03..02 Reserved, must be 0 | |
2975 | * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes | |
2976 | * | |
2977 | * 0101 0000 | |
d12341f9 | 2978 | */ |
1da177e4 | 2979 | write_reg(info, CHB + CCR4, 0x50); |
d12341f9 | 2980 | |
1da177e4 LT |
2981 | /* if auxclk not enabled, set internal BRG so |
2982 | * CTS transitions can be detected (requires TxC) | |
d12341f9 | 2983 | */ |
1da177e4 LT |
2984 | if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) |
2985 | mgslpc_set_rate(info, CHB, info->params.clock_speed); | |
2986 | else | |
2987 | mgslpc_set_rate(info, CHB, 921600); | |
2988 | } | |
2989 | ||
d12341f9 | 2990 | static void loopback_enable(MGSLPC_INFO *info) |
1da177e4 LT |
2991 | { |
2992 | unsigned char val; | |
d12341f9 JG |
2993 | |
2994 | /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */ | |
1da177e4 LT |
2995 | val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0); |
2996 | write_reg(info, CHA + CCR1, val); | |
d12341f9 JG |
2997 | |
2998 | /* CCR2:04 SSEL Clock source select, 1=submode b */ | |
1da177e4 LT |
2999 | val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5); |
3000 | write_reg(info, CHA + CCR2, val); | |
d12341f9 JG |
3001 | |
3002 | /* set LinkSpeed if available, otherwise default to 2Mbps */ | |
1da177e4 LT |
3003 | if (info->params.clock_speed) |
3004 | mgslpc_set_rate(info, CHA, info->params.clock_speed); | |
3005 | else | |
3006 | mgslpc_set_rate(info, CHA, 1843200); | |
d12341f9 JG |
3007 | |
3008 | /* MODE:00 TLP Test Loop, 1=loopback enabled */ | |
1da177e4 LT |
3009 | val = read_reg(info, CHA + MODE) | BIT0; |
3010 | write_reg(info, CHA + MODE, val); | |
3011 | } | |
3012 | ||
cdaad343 | 3013 | static void hdlc_mode(MGSLPC_INFO *info) |
1da177e4 LT |
3014 | { |
3015 | unsigned char val; | |
3016 | unsigned char clkmode, clksubmode; | |
3017 | ||
d12341f9 | 3018 | /* disable all interrupts */ |
1da177e4 LT |
3019 | irq_disable(info, CHA, 0xffff); |
3020 | irq_disable(info, CHB, 0xffff); | |
3021 | port_irq_disable(info, 0xff); | |
d12341f9 JG |
3022 | |
3023 | /* assume clock mode 0a, rcv=RxC xmt=TxC */ | |
1da177e4 LT |
3024 | clkmode = clksubmode = 0; |
3025 | if (info->params.flags & HDLC_FLAG_RXC_DPLL | |
3026 | && info->params.flags & HDLC_FLAG_TXC_DPLL) { | |
d12341f9 | 3027 | /* clock mode 7a, rcv = DPLL, xmt = DPLL */ |
1da177e4 LT |
3028 | clkmode = 7; |
3029 | } else if (info->params.flags & HDLC_FLAG_RXC_BRG | |
3030 | && info->params.flags & HDLC_FLAG_TXC_BRG) { | |
d12341f9 | 3031 | /* clock mode 7b, rcv = BRG, xmt = BRG */ |
1da177e4 LT |
3032 | clkmode = 7; |
3033 | clksubmode = 1; | |
3034 | } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) { | |
3035 | if (info->params.flags & HDLC_FLAG_TXC_BRG) { | |
d12341f9 | 3036 | /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */ |
1da177e4 LT |
3037 | clkmode = 6; |
3038 | clksubmode = 1; | |
3039 | } else { | |
d12341f9 | 3040 | /* clock mode 6a, rcv = DPLL, xmt = TxC */ |
1da177e4 LT |
3041 | clkmode = 6; |
3042 | } | |
3043 | } else if (info->params.flags & HDLC_FLAG_TXC_BRG) { | |
d12341f9 | 3044 | /* clock mode 0b, rcv = RxC, xmt = BRG */ |
1da177e4 LT |
3045 | clksubmode = 1; |
3046 | } | |
d12341f9 | 3047 | |
1da177e4 LT |
3048 | /* MODE |
3049 | * | |
3050 | * 07..06 MDS[1..0] 10 = transparent HDLC mode | |
3051 | * 05 ADM Address Mode, 0 = no addr recognition | |
3052 | * 04 TMD Timer Mode, 0 = external | |
3053 | * 03 RAC Receiver Active, 0 = inactive | |
3054 | * 02 RTS 0=RTS active during xmit, 1=RTS always active | |
3055 | * 01 TRS Timer Resolution, 1=512 | |
3056 | * 00 TLP Test Loop, 0 = no loop | |
3057 | * | |
3058 | * 1000 0010 | |
d12341f9 | 3059 | */ |
1da177e4 LT |
3060 | val = 0x82; |
3061 | if (info->params.loopback) | |
3062 | val |= BIT0; | |
d12341f9 JG |
3063 | |
3064 | /* preserve RTS state */ | |
1da177e4 LT |
3065 | if (info->serial_signals & SerialSignal_RTS) |
3066 | val |= BIT2; | |
3067 | write_reg(info, CHA + MODE, val); | |
d12341f9 | 3068 | |
1da177e4 LT |
3069 | /* CCR0 |
3070 | * | |
3071 | * 07 PU Power Up, 1=active, 0=power down | |
3072 | * 06 MCE Master Clock Enable, 1=enabled | |
3073 | * 05 Reserved, 0 | |
3074 | * 04..02 SC[2..0] Encoding | |
3075 | * 01..00 SM[1..0] Serial Mode, 00=HDLC | |
3076 | * | |
3077 | * 11000000 | |
d12341f9 | 3078 | */ |
1da177e4 LT |
3079 | val = 0xc0; |
3080 | switch (info->params.encoding) | |
3081 | { | |
3082 | case HDLC_ENCODING_NRZI: | |
3083 | val |= BIT3; | |
3084 | break; | |
3085 | case HDLC_ENCODING_BIPHASE_SPACE: | |
3086 | val |= BIT4; | |
3087 | break; // FM0 | |
3088 | case HDLC_ENCODING_BIPHASE_MARK: | |
3089 | val |= BIT4 + BIT2; | |
3090 | break; // FM1 | |
3091 | case HDLC_ENCODING_BIPHASE_LEVEL: | |
3092 | val |= BIT4 + BIT3; | |
3093 | break; // Manchester | |
3094 | } | |
3095 | write_reg(info, CHA + CCR0, val); | |
d12341f9 | 3096 | |
1da177e4 LT |
3097 | /* CCR1 |
3098 | * | |
3099 | * 07 SFLG Shared Flag, 0 = disable shared flags | |
3100 | * 06 GALP Go Active On Loop, 0 = not used | |
3101 | * 05 GLP Go On Loop, 0 = not used | |
3102 | * 04 ODS Output Driver Select, 1=TxD is push-pull output | |
3103 | * 03 ITF Interframe Time Fill, 0=mark, 1=flag | |
3104 | * 02..00 CM[2..0] Clock Mode | |
3105 | * | |
3106 | * 0001 0000 | |
d12341f9 | 3107 | */ |
1da177e4 LT |
3108 | val = 0x10 + clkmode; |
3109 | write_reg(info, CHA + CCR1, val); | |
d12341f9 | 3110 | |
1da177e4 LT |
3111 | /* CCR2 |
3112 | * | |
3113 | * 07..06 BGR[9..8] Baud rate bits 9..8 | |
3114 | * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value | |
3115 | * 04 SSEL Clock source select, 1=submode b | |
3116 | * 03 TOE 0=TxCLK is input, 0=TxCLK is input | |
3117 | * 02 RWX Read/Write Exchange 0=disabled | |
3118 | * 01 C32, CRC select, 0=CRC-16, 1=CRC-32 | |
3119 | * 00 DIV, data inversion 0=disabled, 1=enabled | |
3120 | * | |
3121 | * 0000 0000 | |
d12341f9 | 3122 | */ |
1da177e4 LT |
3123 | val = 0x00; |
3124 | if (clkmode == 2 || clkmode == 3 || clkmode == 6 | |
3125 | || clkmode == 7 || (clkmode == 0 && clksubmode == 1)) | |
3126 | val |= BIT5; | |
3127 | if (clksubmode) | |
3128 | val |= BIT4; | |
3129 | if (info->params.crc_type == HDLC_CRC_32_CCITT) | |
3130 | val |= BIT1; | |
3131 | if (info->params.encoding == HDLC_ENCODING_NRZB) | |
3132 | val |= BIT0; | |
3133 | write_reg(info, CHA + CCR2, val); | |
d12341f9 | 3134 | |
1da177e4 LT |
3135 | /* CCR3 |
3136 | * | |
3137 | * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8 | |
3138 | * 05 EPT Enable preamble transmission, 1=enabled | |
3139 | * 04 RADD Receive address pushed to FIFO, 0=disabled | |
3140 | * 03 CRL CRC Reset Level, 0=FFFF | |
3141 | * 02 RCRC Rx CRC 0=On 1=Off | |
3142 | * 01 TCRC Tx CRC 0=On 1=Off | |
3143 | * 00 PSD DPLL Phase Shift Disable | |
3144 | * | |
3145 | * 0000 0000 | |
d12341f9 | 3146 | */ |
1da177e4 LT |
3147 | val = 0x00; |
3148 | if (info->params.crc_type == HDLC_CRC_NONE) | |
3149 | val |= BIT2 + BIT1; | |
3150 | if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) | |
3151 | val |= BIT5; | |
3152 | switch (info->params.preamble_length) | |
3153 | { | |
3154 | case HDLC_PREAMBLE_LENGTH_16BITS: | |
3155 | val |= BIT6; | |
3156 | break; | |
3157 | case HDLC_PREAMBLE_LENGTH_32BITS: | |
3158 | val |= BIT6; | |
3159 | break; | |
3160 | case HDLC_PREAMBLE_LENGTH_64BITS: | |
3161 | val |= BIT7 + BIT6; | |
3162 | break; | |
3163 | } | |
3164 | write_reg(info, CHA + CCR3, val); | |
d12341f9 JG |
3165 | |
3166 | /* PRE - Preamble pattern */ | |
1da177e4 LT |
3167 | val = 0; |
3168 | switch (info->params.preamble) | |
3169 | { | |
3170 | case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; | |
3171 | case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break; | |
3172 | case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break; | |
3173 | case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; | |
3174 | } | |
3175 | write_reg(info, CHA + PRE, val); | |
d12341f9 | 3176 | |
1da177e4 LT |
3177 | /* CCR4 |
3178 | * | |
3179 | * 07 MCK4 Master Clock Divide by 4, 1=enabled | |
3180 | * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled | |
3181 | * 05 TST1 Test Pin, 0=normal operation | |
3182 | * 04 ICD Ivert Carrier Detect, 1=enabled (active low) | |
3183 | * 03..02 Reserved, must be 0 | |
3184 | * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes | |
3185 | * | |
3186 | * 0101 0000 | |
d12341f9 | 3187 | */ |
1da177e4 LT |
3188 | val = 0x50; |
3189 | write_reg(info, CHA + CCR4, val); | |
3190 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
3191 | mgslpc_set_rate(info, CHA, info->params.clock_speed * 16); | |
3192 | else | |
3193 | mgslpc_set_rate(info, CHA, info->params.clock_speed); | |
d12341f9 | 3194 | |
1da177e4 LT |
3195 | /* RLCR Receive length check register |
3196 | * | |
3197 | * 7 1=enable receive length check | |
3198 | * 6..0 Max frame length = (RL + 1) * 32 | |
d12341f9 | 3199 | */ |
1da177e4 | 3200 | write_reg(info, CHA + RLCR, 0); |
d12341f9 | 3201 | |
1da177e4 LT |
3202 | /* XBCH Transmit Byte Count High |
3203 | * | |
3204 | * 07 DMA mode, 0 = interrupt driven | |
3205 | * 06 NRM, 0=ABM (ignored) | |
3206 | * 05 CAS Carrier Auto Start | |
3207 | * 04 XC Transmit Continuously (ignored) | |
3208 | * 03..00 XBC[10..8] Transmit byte count bits 10..8 | |
3209 | * | |
3210 | * 0000 0000 | |
d12341f9 | 3211 | */ |
1da177e4 LT |
3212 | val = 0x00; |
3213 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
3214 | val |= BIT5; | |
3215 | write_reg(info, CHA + XBCH, val); | |
3216 | enable_auxclk(info); | |
3217 | if (info->params.loopback || info->testing_irq) | |
3218 | loopback_enable(info); | |
3219 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
3220 | { | |
3221 | irq_enable(info, CHB, IRQ_CTS); | |
d12341f9 | 3222 | /* PVR[3] 1=AUTO CTS active */ |
1da177e4 LT |
3223 | set_reg_bits(info, CHA + PVR, BIT3); |
3224 | } else | |
3225 | clear_reg_bits(info, CHA + PVR, BIT3); | |
3226 | ||
3227 | irq_enable(info, CHA, | |
3228 | IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT + | |
3229 | IRQ_UNDERRUN + IRQ_TXFIFO); | |
3230 | issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET); | |
3231 | wait_command_complete(info, CHA); | |
3232 | read_reg16(info, CHA + ISR); /* clear pending IRQs */ | |
d12341f9 | 3233 | |
1da177e4 LT |
3234 | /* Master clock mode enabled above to allow reset commands |
3235 | * to complete even if no data clocks are present. | |
3236 | * | |
3237 | * Disable master clock mode for normal communications because | |
3238 | * V3.2 of the ESCC2 has a bug that prevents the transmit all sent | |
3239 | * IRQ when in master clock mode. | |
3240 | * | |
3241 | * Leave master clock mode enabled for IRQ test because the | |
3242 | * timer IRQ used by the test can only happen in master clock mode. | |
d12341f9 | 3243 | */ |
1da177e4 LT |
3244 | if (!info->testing_irq) |
3245 | clear_reg_bits(info, CHA + CCR0, BIT6); | |
3246 | ||
3247 | tx_set_idle(info); | |
3248 | ||
3249 | tx_stop(info); | |
3250 | rx_stop(info); | |
3251 | } | |
3252 | ||
cdaad343 | 3253 | static void rx_stop(MGSLPC_INFO *info) |
1da177e4 LT |
3254 | { |
3255 | if (debug_level >= DEBUG_LEVEL_ISR) | |
3256 | printk("%s(%d):rx_stop(%s)\n", | |
3257 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 JG |
3258 | |
3259 | /* MODE:03 RAC Receiver Active, 0=inactive */ | |
1da177e4 LT |
3260 | clear_reg_bits(info, CHA + MODE, BIT3); |
3261 | ||
0fab6de0 JP |
3262 | info->rx_enabled = false; |
3263 | info->rx_overflow = false; | |
1da177e4 LT |
3264 | } |
3265 | ||
cdaad343 | 3266 | static void rx_start(MGSLPC_INFO *info) |
1da177e4 LT |
3267 | { |
3268 | if (debug_level >= DEBUG_LEVEL_ISR) | |
3269 | printk("%s(%d):rx_start(%s)\n", | |
3270 | __FILE__,__LINE__, info->device_name ); | |
3271 | ||
3272 | rx_reset_buffers(info); | |
0fab6de0 JP |
3273 | info->rx_enabled = false; |
3274 | info->rx_overflow = false; | |
1da177e4 | 3275 | |
d12341f9 | 3276 | /* MODE:03 RAC Receiver Active, 1=active */ |
1da177e4 LT |
3277 | set_reg_bits(info, CHA + MODE, BIT3); |
3278 | ||
0fab6de0 | 3279 | info->rx_enabled = true; |
1da177e4 LT |
3280 | } |
3281 | ||
eeb46134 | 3282 | static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
3283 | { |
3284 | if (debug_level >= DEBUG_LEVEL_ISR) | |
3285 | printk("%s(%d):tx_start(%s)\n", | |
3286 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 | 3287 | |
1da177e4 LT |
3288 | if (info->tx_count) { |
3289 | /* If auto RTS enabled and RTS is inactive, then assert */ | |
3290 | /* RTS and set a flag indicating that the driver should */ | |
3291 | /* negate RTS when the transmission completes. */ | |
0fab6de0 | 3292 | info->drop_rts_on_tx_done = false; |
1da177e4 LT |
3293 | |
3294 | if (info->params.flags & HDLC_FLAG_AUTO_RTS) { | |
3295 | get_signals(info); | |
3296 | if (!(info->serial_signals & SerialSignal_RTS)) { | |
3297 | info->serial_signals |= SerialSignal_RTS; | |
3298 | set_signals(info); | |
0fab6de0 | 3299 | info->drop_rts_on_tx_done = true; |
1da177e4 LT |
3300 | } |
3301 | } | |
3302 | ||
3303 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
3304 | if (!info->tx_active) { | |
0fab6de0 | 3305 | info->tx_active = true; |
eeb46134 | 3306 | tx_ready(info, tty); |
1da177e4 LT |
3307 | } |
3308 | } else { | |
0fab6de0 | 3309 | info->tx_active = true; |
eeb46134 | 3310 | tx_ready(info, tty); |
40565f19 JS |
3311 | mod_timer(&info->tx_timer, jiffies + |
3312 | msecs_to_jiffies(5000)); | |
1da177e4 LT |
3313 | } |
3314 | } | |
3315 | ||
3316 | if (!info->tx_enabled) | |
0fab6de0 | 3317 | info->tx_enabled = true; |
1da177e4 LT |
3318 | } |
3319 | ||
cdaad343 | 3320 | static void tx_stop(MGSLPC_INFO *info) |
1da177e4 LT |
3321 | { |
3322 | if (debug_level >= DEBUG_LEVEL_ISR) | |
3323 | printk("%s(%d):tx_stop(%s)\n", | |
3324 | __FILE__,__LINE__, info->device_name ); | |
d12341f9 JG |
3325 | |
3326 | del_timer(&info->tx_timer); | |
1da177e4 | 3327 | |
0fab6de0 JP |
3328 | info->tx_enabled = false; |
3329 | info->tx_active = false; | |
1da177e4 LT |
3330 | } |
3331 | ||
3332 | /* Reset the adapter to a known state and prepare it for further use. | |
3333 | */ | |
cdaad343 | 3334 | static void reset_device(MGSLPC_INFO *info) |
1da177e4 | 3335 | { |
d12341f9 | 3336 | /* power up both channels (set BIT7) */ |
1da177e4 LT |
3337 | write_reg(info, CHA + CCR0, 0x80); |
3338 | write_reg(info, CHB + CCR0, 0x80); | |
3339 | write_reg(info, CHA + MODE, 0); | |
3340 | write_reg(info, CHB + MODE, 0); | |
d12341f9 JG |
3341 | |
3342 | /* disable all interrupts */ | |
1da177e4 LT |
3343 | irq_disable(info, CHA, 0xffff); |
3344 | irq_disable(info, CHB, 0xffff); | |
3345 | port_irq_disable(info, 0xff); | |
d12341f9 | 3346 | |
1da177e4 LT |
3347 | /* PCR Port Configuration Register |
3348 | * | |
3349 | * 07..04 DEC[3..0] Serial I/F select outputs | |
3350 | * 03 output, 1=AUTO CTS control enabled | |
3351 | * 02 RI Ring Indicator input 0=active | |
3352 | * 01 DSR input 0=active | |
3353 | * 00 DTR output 0=active | |
3354 | * | |
3355 | * 0000 0110 | |
d12341f9 | 3356 | */ |
1da177e4 | 3357 | write_reg(info, PCR, 0x06); |
d12341f9 | 3358 | |
1da177e4 LT |
3359 | /* PVR Port Value Register |
3360 | * | |
3361 | * 07..04 DEC[3..0] Serial I/F select (0000=disabled) | |
3362 | * 03 AUTO CTS output 1=enabled | |
3363 | * 02 RI Ring Indicator input | |
3364 | * 01 DSR input | |
3365 | * 00 DTR output (1=inactive) | |
3366 | * | |
3367 | * 0000 0001 | |
3368 | */ | |
3369 | // write_reg(info, PVR, PVR_DTR); | |
d12341f9 | 3370 | |
1da177e4 LT |
3371 | /* IPC Interrupt Port Configuration |
3372 | * | |
3373 | * 07 VIS 1=Masked interrupts visible | |
3374 | * 06..05 Reserved, 0 | |
3375 | * 04..03 SLA Slave address, 00 ignored | |
3376 | * 02 CASM Cascading Mode, 1=daisy chain | |
3377 | * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low | |
3378 | * | |
3379 | * 0000 0101 | |
d12341f9 | 3380 | */ |
1da177e4 LT |
3381 | write_reg(info, IPC, 0x05); |
3382 | } | |
3383 | ||
cdaad343 | 3384 | static void async_mode(MGSLPC_INFO *info) |
1da177e4 LT |
3385 | { |
3386 | unsigned char val; | |
3387 | ||
d12341f9 | 3388 | /* disable all interrupts */ |
1da177e4 LT |
3389 | irq_disable(info, CHA, 0xffff); |
3390 | irq_disable(info, CHB, 0xffff); | |
3391 | port_irq_disable(info, 0xff); | |
d12341f9 | 3392 | |
1da177e4 LT |
3393 | /* MODE |
3394 | * | |
3395 | * 07 Reserved, 0 | |
3396 | * 06 FRTS RTS State, 0=active | |
3397 | * 05 FCTS Flow Control on CTS | |
3398 | * 04 FLON Flow Control Enable | |
3399 | * 03 RAC Receiver Active, 0 = inactive | |
3400 | * 02 RTS 0=Auto RTS, 1=manual RTS | |
3401 | * 01 TRS Timer Resolution, 1=512 | |
3402 | * 00 TLP Test Loop, 0 = no loop | |
3403 | * | |
3404 | * 0000 0110 | |
d12341f9 | 3405 | */ |
1da177e4 LT |
3406 | val = 0x06; |
3407 | if (info->params.loopback) | |
3408 | val |= BIT0; | |
d12341f9 JG |
3409 | |
3410 | /* preserve RTS state */ | |
1da177e4 LT |
3411 | if (!(info->serial_signals & SerialSignal_RTS)) |
3412 | val |= BIT6; | |
3413 | write_reg(info, CHA + MODE, val); | |
d12341f9 | 3414 | |
1da177e4 LT |
3415 | /* CCR0 |
3416 | * | |
3417 | * 07 PU Power Up, 1=active, 0=power down | |
3418 | * 06 MCE Master Clock Enable, 1=enabled | |
3419 | * 05 Reserved, 0 | |
3420 | * 04..02 SC[2..0] Encoding, 000=NRZ | |
3421 | * 01..00 SM[1..0] Serial Mode, 11=Async | |
3422 | * | |
3423 | * 1000 0011 | |
d12341f9 | 3424 | */ |
1da177e4 | 3425 | write_reg(info, CHA + CCR0, 0x83); |
d12341f9 | 3426 | |
1da177e4 LT |
3427 | /* CCR1 |
3428 | * | |
3429 | * 07..05 Reserved, 0 | |
3430 | * 04 ODS Output Driver Select, 1=TxD is push-pull output | |
3431 | * 03 BCR Bit Clock Rate, 1=16x | |
3432 | * 02..00 CM[2..0] Clock Mode, 111=BRG | |
3433 | * | |
3434 | * 0001 1111 | |
d12341f9 | 3435 | */ |
1da177e4 | 3436 | write_reg(info, CHA + CCR1, 0x1f); |
d12341f9 | 3437 | |
1da177e4 LT |
3438 | /* CCR2 (channel A) |
3439 | * | |
3440 | * 07..06 BGR[9..8] Baud rate bits 9..8 | |
3441 | * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value | |
3442 | * 04 SSEL Clock source select, 1=submode b | |
3443 | * 03 TOE 0=TxCLK is input, 0=TxCLK is input | |
3444 | * 02 RWX Read/Write Exchange 0=disabled | |
3445 | * 01 Reserved, 0 | |
3446 | * 00 DIV, data inversion 0=disabled, 1=enabled | |
3447 | * | |
3448 | * 0001 0000 | |
d12341f9 | 3449 | */ |
1da177e4 | 3450 | write_reg(info, CHA + CCR2, 0x10); |
d12341f9 | 3451 | |
1da177e4 LT |
3452 | /* CCR3 |
3453 | * | |
3454 | * 07..01 Reserved, 0 | |
3455 | * 00 PSD DPLL Phase Shift Disable | |
3456 | * | |
3457 | * 0000 0000 | |
d12341f9 | 3458 | */ |
1da177e4 | 3459 | write_reg(info, CHA + CCR3, 0); |
d12341f9 | 3460 | |
1da177e4 LT |
3461 | /* CCR4 |
3462 | * | |
3463 | * 07 MCK4 Master Clock Divide by 4, 1=enabled | |
3464 | * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled | |
3465 | * 05 TST1 Test Pin, 0=normal operation | |
3466 | * 04 ICD Ivert Carrier Detect, 1=enabled (active low) | |
3467 | * 03..00 Reserved, must be 0 | |
3468 | * | |
3469 | * 0101 0000 | |
d12341f9 | 3470 | */ |
1da177e4 LT |
3471 | write_reg(info, CHA + CCR4, 0x50); |
3472 | mgslpc_set_rate(info, CHA, info->params.data_rate * 16); | |
d12341f9 | 3473 | |
1da177e4 LT |
3474 | /* DAFO Data Format |
3475 | * | |
3476 | * 07 Reserved, 0 | |
3477 | * 06 XBRK transmit break, 0=normal operation | |
3478 | * 05 Stop bits (0=1, 1=2) | |
3479 | * 04..03 PAR[1..0] Parity (01=odd, 10=even) | |
3480 | * 02 PAREN Parity Enable | |
3481 | * 01..00 CHL[1..0] Character Length (00=8, 01=7) | |
3482 | * | |
d12341f9 | 3483 | */ |
1da177e4 LT |
3484 | val = 0x00; |
3485 | if (info->params.data_bits != 8) | |
3486 | val |= BIT0; /* 7 bits */ | |
3487 | if (info->params.stop_bits != 1) | |
3488 | val |= BIT5; | |
3489 | if (info->params.parity != ASYNC_PARITY_NONE) | |
3490 | { | |
3491 | val |= BIT2; /* Parity enable */ | |
3492 | if (info->params.parity == ASYNC_PARITY_ODD) | |
3493 | val |= BIT3; | |
3494 | else | |
3495 | val |= BIT4; | |
3496 | } | |
3497 | write_reg(info, CHA + DAFO, val); | |
d12341f9 | 3498 | |
1da177e4 LT |
3499 | /* RFC Rx FIFO Control |
3500 | * | |
3501 | * 07 Reserved, 0 | |
3502 | * 06 DPS, 1=parity bit not stored in data byte | |
3503 | * 05 DXS, 0=all data stored in FIFO (including XON/XOFF) | |
3504 | * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO | |
3505 | * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte | |
3506 | * 01 Reserved, 0 | |
3507 | * 00 TCDE Terminate Char Detect Enable, 0=disabled | |
3508 | * | |
3509 | * 0101 1100 | |
d12341f9 | 3510 | */ |
1da177e4 | 3511 | write_reg(info, CHA + RFC, 0x5c); |
d12341f9 | 3512 | |
1da177e4 LT |
3513 | /* RLCR Receive length check register |
3514 | * | |
3515 | * Max frame length = (RL + 1) * 32 | |
d12341f9 | 3516 | */ |
1da177e4 | 3517 | write_reg(info, CHA + RLCR, 0); |
d12341f9 | 3518 | |
1da177e4 LT |
3519 | /* XBCH Transmit Byte Count High |
3520 | * | |
3521 | * 07 DMA mode, 0 = interrupt driven | |
3522 | * 06 NRM, 0=ABM (ignored) | |
3523 | * 05 CAS Carrier Auto Start | |
3524 | * 04 XC Transmit Continuously (ignored) | |
3525 | * 03..00 XBC[10..8] Transmit byte count bits 10..8 | |
3526 | * | |
3527 | * 0000 0000 | |
d12341f9 | 3528 | */ |
1da177e4 LT |
3529 | val = 0x00; |
3530 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
3531 | val |= BIT5; | |
3532 | write_reg(info, CHA + XBCH, val); | |
3533 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
3534 | irq_enable(info, CHA, IRQ_CTS); | |
d12341f9 JG |
3535 | |
3536 | /* MODE:03 RAC Receiver Active, 1=active */ | |
1da177e4 LT |
3537 | set_reg_bits(info, CHA + MODE, BIT3); |
3538 | enable_auxclk(info); | |
3539 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) { | |
3540 | irq_enable(info, CHB, IRQ_CTS); | |
d12341f9 | 3541 | /* PVR[3] 1=AUTO CTS active */ |
1da177e4 LT |
3542 | set_reg_bits(info, CHA + PVR, BIT3); |
3543 | } else | |
3544 | clear_reg_bits(info, CHA + PVR, BIT3); | |
3545 | irq_enable(info, CHA, | |
3546 | IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME + | |
3547 | IRQ_ALLSENT + IRQ_TXFIFO); | |
3548 | issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET); | |
3549 | wait_command_complete(info, CHA); | |
3550 | read_reg16(info, CHA + ISR); /* clear pending IRQs */ | |
3551 | } | |
3552 | ||
3553 | /* Set the HDLC idle mode for the transmitter. | |
3554 | */ | |
cdaad343 | 3555 | static void tx_set_idle(MGSLPC_INFO *info) |
1da177e4 | 3556 | { |
d12341f9 | 3557 | /* Note: ESCC2 only supports flags and one idle modes */ |
1da177e4 LT |
3558 | if (info->idle_mode == HDLC_TXIDLE_FLAGS) |
3559 | set_reg_bits(info, CHA + CCR1, BIT3); | |
3560 | else | |
3561 | clear_reg_bits(info, CHA + CCR1, BIT3); | |
3562 | } | |
3563 | ||
3564 | /* get state of the V24 status (input) signals. | |
3565 | */ | |
cdaad343 | 3566 | static void get_signals(MGSLPC_INFO *info) |
1da177e4 LT |
3567 | { |
3568 | unsigned char status = 0; | |
d12341f9 JG |
3569 | |
3570 | /* preserve DTR and RTS */ | |
1da177e4 LT |
3571 | info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS; |
3572 | ||
3573 | if (read_reg(info, CHB + VSTR) & BIT7) | |
3574 | info->serial_signals |= SerialSignal_DCD; | |
3575 | if (read_reg(info, CHB + STAR) & BIT1) | |
3576 | info->serial_signals |= SerialSignal_CTS; | |
3577 | ||
3578 | status = read_reg(info, CHA + PVR); | |
3579 | if (!(status & PVR_RI)) | |
3580 | info->serial_signals |= SerialSignal_RI; | |
3581 | if (!(status & PVR_DSR)) | |
3582 | info->serial_signals |= SerialSignal_DSR; | |
3583 | } | |
3584 | ||
3585 | /* Set the state of DTR and RTS based on contents of | |
3586 | * serial_signals member of device extension. | |
3587 | */ | |
cdaad343 | 3588 | static void set_signals(MGSLPC_INFO *info) |
1da177e4 LT |
3589 | { |
3590 | unsigned char val; | |
3591 | ||
3592 | val = read_reg(info, CHA + MODE); | |
3593 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
3594 | if (info->serial_signals & SerialSignal_RTS) | |
3595 | val &= ~BIT6; | |
3596 | else | |
3597 | val |= BIT6; | |
3598 | } else { | |
3599 | if (info->serial_signals & SerialSignal_RTS) | |
3600 | val |= BIT2; | |
3601 | else | |
3602 | val &= ~BIT2; | |
3603 | } | |
3604 | write_reg(info, CHA + MODE, val); | |
3605 | ||
3606 | if (info->serial_signals & SerialSignal_DTR) | |
3607 | clear_reg_bits(info, CHA + PVR, PVR_DTR); | |
3608 | else | |
3609 | set_reg_bits(info, CHA + PVR, PVR_DTR); | |
3610 | } | |
3611 | ||
cdaad343 | 3612 | static void rx_reset_buffers(MGSLPC_INFO *info) |
1da177e4 LT |
3613 | { |
3614 | RXBUF *buf; | |
3615 | int i; | |
3616 | ||
3617 | info->rx_put = 0; | |
3618 | info->rx_get = 0; | |
3619 | info->rx_frame_count = 0; | |
3620 | for (i=0 ; i < info->rx_buf_count ; i++) { | |
3621 | buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size)); | |
3622 | buf->status = buf->count = 0; | |
3623 | } | |
3624 | } | |
3625 | ||
3626 | /* Attempt to return a received HDLC frame | |
3627 | * Only frames received without errors are returned. | |
3628 | * | |
0fab6de0 | 3629 | * Returns true if frame returned, otherwise false |
1da177e4 | 3630 | */ |
eeb46134 | 3631 | static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty) |
1da177e4 LT |
3632 | { |
3633 | unsigned short status; | |
3634 | RXBUF *buf; | |
3635 | unsigned int framesize = 0; | |
3636 | unsigned long flags; | |
0fab6de0 | 3637 | bool return_frame = false; |
d12341f9 | 3638 | |
1da177e4 | 3639 | if (info->rx_frame_count == 0) |
0fab6de0 | 3640 | return false; |
1da177e4 LT |
3641 | |
3642 | buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size)); | |
3643 | ||
3644 | status = buf->status; | |
3645 | ||
3646 | /* 07 VFR 1=valid frame | |
3647 | * 06 RDO 1=data overrun | |
3648 | * 05 CRC 1=OK, 0=error | |
3649 | * 04 RAB 1=frame aborted | |
3650 | */ | |
3651 | if ((status & 0xf0) != 0xA0) { | |
3652 | if (!(status & BIT7) || (status & BIT4)) | |
3653 | info->icount.rxabort++; | |
3654 | else if (status & BIT6) | |
3655 | info->icount.rxover++; | |
3656 | else if (!(status & BIT5)) { | |
3657 | info->icount.rxcrc++; | |
3658 | if (info->params.crc_type & HDLC_CRC_RETURN_EX) | |
0fab6de0 | 3659 | return_frame = true; |
1da177e4 LT |
3660 | } |
3661 | framesize = 0; | |
af69c7f9 | 3662 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 | 3663 | { |
198191c4 KH |
3664 | info->netdev->stats.rx_errors++; |
3665 | info->netdev->stats.rx_frame_errors++; | |
1da177e4 LT |
3666 | } |
3667 | #endif | |
3668 | } else | |
0fab6de0 | 3669 | return_frame = true; |
1da177e4 LT |
3670 | |
3671 | if (return_frame) | |
3672 | framesize = buf->count; | |
3673 | ||
3674 | if (debug_level >= DEBUG_LEVEL_BH) | |
3675 | printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n", | |
3676 | __FILE__,__LINE__,info->device_name,status,framesize); | |
d12341f9 | 3677 | |
1da177e4 | 3678 | if (debug_level >= DEBUG_LEVEL_DATA) |
d12341f9 JG |
3679 | trace_block(info, buf->data, framesize, 0); |
3680 | ||
1da177e4 LT |
3681 | if (framesize) { |
3682 | if ((info->params.crc_type & HDLC_CRC_RETURN_EX && | |
3683 | framesize+1 > info->max_frame_size) || | |
3684 | framesize > info->max_frame_size) | |
3685 | info->icount.rxlong++; | |
3686 | else { | |
3687 | if (status & BIT5) | |
3688 | info->icount.rxok++; | |
3689 | ||
3690 | if (info->params.crc_type & HDLC_CRC_RETURN_EX) { | |
3691 | *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR; | |
3692 | ++framesize; | |
3693 | } | |
3694 | ||
af69c7f9 | 3695 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
3696 | if (info->netcount) |
3697 | hdlcdev_rx(info, buf->data, framesize); | |
3698 | else | |
3699 | #endif | |
3700 | ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize); | |
3701 | } | |
3702 | } | |
3703 | ||
3704 | spin_lock_irqsave(&info->lock,flags); | |
3705 | buf->status = buf->count = 0; | |
3706 | info->rx_frame_count--; | |
3707 | info->rx_get++; | |
3708 | if (info->rx_get >= info->rx_buf_count) | |
3709 | info->rx_get = 0; | |
3710 | spin_unlock_irqrestore(&info->lock,flags); | |
3711 | ||
0fab6de0 | 3712 | return true; |
1da177e4 LT |
3713 | } |
3714 | ||
0fab6de0 | 3715 | static bool register_test(MGSLPC_INFO *info) |
1da177e4 | 3716 | { |
d12341f9 | 3717 | static unsigned char patterns[] = |
1da177e4 | 3718 | { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f }; |
fe971071 | 3719 | static unsigned int count = ARRAY_SIZE(patterns); |
1da177e4 | 3720 | unsigned int i; |
0fab6de0 | 3721 | bool rc = true; |
1da177e4 LT |
3722 | unsigned long flags; |
3723 | ||
3724 | spin_lock_irqsave(&info->lock,flags); | |
3725 | reset_device(info); | |
3726 | ||
3727 | for (i = 0; i < count; i++) { | |
3728 | write_reg(info, XAD1, patterns[i]); | |
3729 | write_reg(info, XAD2, patterns[(i + 1) % count]); | |
fe971071 | 3730 | if ((read_reg(info, XAD1) != patterns[i]) || |
1da177e4 | 3731 | (read_reg(info, XAD2) != patterns[(i + 1) % count])) { |
0fab6de0 | 3732 | rc = false; |
1da177e4 LT |
3733 | break; |
3734 | } | |
3735 | } | |
3736 | ||
3737 | spin_unlock_irqrestore(&info->lock,flags); | |
3738 | return rc; | |
3739 | } | |
3740 | ||
0fab6de0 | 3741 | static bool irq_test(MGSLPC_INFO *info) |
1da177e4 LT |
3742 | { |
3743 | unsigned long end_time; | |
3744 | unsigned long flags; | |
3745 | ||
3746 | spin_lock_irqsave(&info->lock,flags); | |
3747 | reset_device(info); | |
3748 | ||
0fab6de0 | 3749 | info->testing_irq = true; |
1da177e4 LT |
3750 | hdlc_mode(info); |
3751 | ||
0fab6de0 | 3752 | info->irq_occurred = false; |
1da177e4 LT |
3753 | |
3754 | /* init hdlc mode */ | |
3755 | ||
3756 | irq_enable(info, CHA, IRQ_TIMER); | |
3757 | write_reg(info, CHA + TIMR, 0); /* 512 cycles */ | |
3758 | issue_command(info, CHA, CMD_START_TIMER); | |
3759 | ||
3760 | spin_unlock_irqrestore(&info->lock,flags); | |
3761 | ||
3762 | end_time=100; | |
3763 | while(end_time-- && !info->irq_occurred) { | |
3764 | msleep_interruptible(10); | |
3765 | } | |
d12341f9 | 3766 | |
0fab6de0 | 3767 | info->testing_irq = false; |
1da177e4 LT |
3768 | |
3769 | spin_lock_irqsave(&info->lock,flags); | |
3770 | reset_device(info); | |
3771 | spin_unlock_irqrestore(&info->lock,flags); | |
d12341f9 | 3772 | |
0fab6de0 | 3773 | return info->irq_occurred; |
1da177e4 LT |
3774 | } |
3775 | ||
cdaad343 | 3776 | static int adapter_test(MGSLPC_INFO *info) |
1da177e4 LT |
3777 | { |
3778 | if (!register_test(info)) { | |
3779 | info->init_error = DiagStatus_AddressFailure; | |
3780 | printk( "%s(%d):Register test failure for device %s Addr=%04X\n", | |
3781 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) ); | |
3782 | return -ENODEV; | |
3783 | } | |
3784 | ||
3785 | if (!irq_test(info)) { | |
3786 | info->init_error = DiagStatus_IrqFailure; | |
3787 | printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", | |
3788 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); | |
3789 | return -ENODEV; | |
3790 | } | |
3791 | ||
3792 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3793 | printk("%s(%d):device %s passed diagnostics\n", | |
3794 | __FILE__,__LINE__,info->device_name); | |
3795 | return 0; | |
3796 | } | |
3797 | ||
cdaad343 | 3798 | static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit) |
1da177e4 LT |
3799 | { |
3800 | int i; | |
3801 | int linecount; | |
3802 | if (xmit) | |
3803 | printk("%s tx data:\n",info->device_name); | |
3804 | else | |
3805 | printk("%s rx data:\n",info->device_name); | |
d12341f9 | 3806 | |
1da177e4 LT |
3807 | while(count) { |
3808 | if (count > 16) | |
3809 | linecount = 16; | |
3810 | else | |
3811 | linecount = count; | |
d12341f9 | 3812 | |
1da177e4 LT |
3813 | for(i=0;i<linecount;i++) |
3814 | printk("%02X ",(unsigned char)data[i]); | |
3815 | for(;i<17;i++) | |
3816 | printk(" "); | |
3817 | for(i=0;i<linecount;i++) { | |
3818 | if (data[i]>=040 && data[i]<=0176) | |
3819 | printk("%c",data[i]); | |
3820 | else | |
3821 | printk("."); | |
3822 | } | |
3823 | printk("\n"); | |
d12341f9 | 3824 | |
1da177e4 LT |
3825 | data += linecount; |
3826 | count -= linecount; | |
3827 | } | |
3828 | } | |
3829 | ||
3830 | /* HDLC frame time out | |
3831 | * update stats and do tx completion processing | |
3832 | */ | |
cdaad343 | 3833 | static void tx_timeout(unsigned long context) |
1da177e4 LT |
3834 | { |
3835 | MGSLPC_INFO *info = (MGSLPC_INFO*)context; | |
3836 | unsigned long flags; | |
d12341f9 | 3837 | |
1da177e4 LT |
3838 | if ( debug_level >= DEBUG_LEVEL_INFO ) |
3839 | printk( "%s(%d):tx_timeout(%s)\n", | |
3840 | __FILE__,__LINE__,info->device_name); | |
3841 | if(info->tx_active && | |
3842 | info->params.mode == MGSL_MODE_HDLC) { | |
3843 | info->icount.txtimeout++; | |
3844 | } | |
3845 | spin_lock_irqsave(&info->lock,flags); | |
0fab6de0 | 3846 | info->tx_active = false; |
1da177e4 LT |
3847 | info->tx_count = info->tx_put = info->tx_get = 0; |
3848 | ||
3849 | spin_unlock_irqrestore(&info->lock,flags); | |
d12341f9 | 3850 | |
af69c7f9 | 3851 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
3852 | if (info->netcount) |
3853 | hdlcdev_tx_done(info); | |
3854 | else | |
3855 | #endif | |
eeb46134 AC |
3856 | { |
3857 | struct tty_struct *tty = tty_port_tty_get(&info->port); | |
3858 | bh_transmit(info, tty); | |
3859 | tty_kref_put(tty); | |
3860 | } | |
1da177e4 LT |
3861 | } |
3862 | ||
af69c7f9 | 3863 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
3864 | |
3865 | /** | |
3866 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
3867 | * set encoding and frame check sequence (FCS) options | |
3868 | * | |
3869 | * dev pointer to network device structure | |
3870 | * encoding serial encoding setting | |
3871 | * parity FCS setting | |
3872 | * | |
3873 | * returns 0 if success, otherwise error code | |
3874 | */ | |
3875 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
3876 | unsigned short parity) | |
3877 | { | |
3878 | MGSLPC_INFO *info = dev_to_port(dev); | |
eeb46134 | 3879 | struct tty_struct *tty; |
1da177e4 LT |
3880 | unsigned char new_encoding; |
3881 | unsigned short new_crctype; | |
3882 | ||
3883 | /* return error if TTY interface open */ | |
eeb46134 | 3884 | if (info->port.count) |
1da177e4 LT |
3885 | return -EBUSY; |
3886 | ||
3887 | switch (encoding) | |
3888 | { | |
3889 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
3890 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
3891 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
3892 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
3893 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
3894 | default: return -EINVAL; | |
3895 | } | |
3896 | ||
3897 | switch (parity) | |
3898 | { | |
3899 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
3900 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
3901 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
3902 | default: return -EINVAL; | |
3903 | } | |
3904 | ||
3905 | info->params.encoding = new_encoding; | |
53b3531b | 3906 | info->params.crc_type = new_crctype; |
1da177e4 LT |
3907 | |
3908 | /* if network interface up, reprogram hardware */ | |
eeb46134 AC |
3909 | if (info->netcount) { |
3910 | tty = tty_port_tty_get(&info->port); | |
3911 | mgslpc_program_hw(info, tty); | |
3912 | tty_kref_put(tty); | |
3913 | } | |
1da177e4 LT |
3914 | |
3915 | return 0; | |
3916 | } | |
3917 | ||
3918 | /** | |
3919 | * called by generic HDLC layer to send frame | |
3920 | * | |
3921 | * skb socket buffer containing HDLC frame | |
3922 | * dev pointer to network device structure | |
1da177e4 | 3923 | */ |
4c5d502d SH |
3924 | static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, |
3925 | struct net_device *dev) | |
1da177e4 LT |
3926 | { |
3927 | MGSLPC_INFO *info = dev_to_port(dev); | |
1da177e4 LT |
3928 | unsigned long flags; |
3929 | ||
3930 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3931 | printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); | |
3932 | ||
3933 | /* stop sending until this frame completes */ | |
3934 | netif_stop_queue(dev); | |
3935 | ||
3936 | /* copy data to device buffers */ | |
d626f62b | 3937 | skb_copy_from_linear_data(skb, info->tx_buf, skb->len); |
1da177e4 LT |
3938 | info->tx_get = 0; |
3939 | info->tx_put = info->tx_count = skb->len; | |
3940 | ||
3941 | /* update network statistics */ | |
198191c4 KH |
3942 | dev->stats.tx_packets++; |
3943 | dev->stats.tx_bytes += skb->len; | |
1da177e4 LT |
3944 | |
3945 | /* done with socket buffer, so free it */ | |
3946 | dev_kfree_skb(skb); | |
3947 | ||
3948 | /* save start time for transmit timeout detection */ | |
3949 | dev->trans_start = jiffies; | |
3950 | ||
3951 | /* start hardware transmitter if necessary */ | |
3952 | spin_lock_irqsave(&info->lock,flags); | |
eeb46134 AC |
3953 | if (!info->tx_active) { |
3954 | struct tty_struct *tty = tty_port_tty_get(&info->port); | |
3955 | tx_start(info, tty); | |
3956 | tty_kref_put(tty); | |
3957 | } | |
1da177e4 LT |
3958 | spin_unlock_irqrestore(&info->lock,flags); |
3959 | ||
4c5d502d | 3960 | return NETDEV_TX_OK; |
1da177e4 LT |
3961 | } |
3962 | ||
3963 | /** | |
3964 | * called by network layer when interface enabled | |
3965 | * claim resources and initialize hardware | |
3966 | * | |
3967 | * dev pointer to network device structure | |
3968 | * | |
3969 | * returns 0 if success, otherwise error code | |
3970 | */ | |
3971 | static int hdlcdev_open(struct net_device *dev) | |
3972 | { | |
3973 | MGSLPC_INFO *info = dev_to_port(dev); | |
eeb46134 | 3974 | struct tty_struct *tty; |
1da177e4 LT |
3975 | int rc; |
3976 | unsigned long flags; | |
3977 | ||
3978 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3979 | printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); | |
3980 | ||
3981 | /* generic HDLC layer open processing */ | |
3982 | if ((rc = hdlc_open(dev))) | |
3983 | return rc; | |
3984 | ||
3985 | /* arbitrate between network and tty opens */ | |
3986 | spin_lock_irqsave(&info->netlock, flags); | |
eeb46134 | 3987 | if (info->port.count != 0 || info->netcount != 0) { |
1da177e4 LT |
3988 | printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); |
3989 | spin_unlock_irqrestore(&info->netlock, flags); | |
3990 | return -EBUSY; | |
3991 | } | |
3992 | info->netcount=1; | |
3993 | spin_unlock_irqrestore(&info->netlock, flags); | |
3994 | ||
eeb46134 | 3995 | tty = tty_port_tty_get(&info->port); |
1da177e4 | 3996 | /* claim resources and init adapter */ |
eeb46134 AC |
3997 | if ((rc = startup(info, tty)) != 0) { |
3998 | tty_kref_put(tty); | |
1da177e4 LT |
3999 | spin_lock_irqsave(&info->netlock, flags); |
4000 | info->netcount=0; | |
4001 | spin_unlock_irqrestore(&info->netlock, flags); | |
4002 | return rc; | |
4003 | } | |
1da177e4 LT |
4004 | /* assert DTR and RTS, apply hardware settings */ |
4005 | info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; | |
eeb46134 AC |
4006 | mgslpc_program_hw(info, tty); |
4007 | tty_kref_put(tty); | |
1da177e4 LT |
4008 | |
4009 | /* enable network layer transmit */ | |
4010 | dev->trans_start = jiffies; | |
4011 | netif_start_queue(dev); | |
4012 | ||
4013 | /* inform generic HDLC layer of current DCD status */ | |
4014 | spin_lock_irqsave(&info->lock, flags); | |
4015 | get_signals(info); | |
4016 | spin_unlock_irqrestore(&info->lock, flags); | |
fbeff3c1 KH |
4017 | if (info->serial_signals & SerialSignal_DCD) |
4018 | netif_carrier_on(dev); | |
4019 | else | |
4020 | netif_carrier_off(dev); | |
1da177e4 LT |
4021 | return 0; |
4022 | } | |
4023 | ||
4024 | /** | |
4025 | * called by network layer when interface is disabled | |
4026 | * shutdown hardware and release resources | |
4027 | * | |
4028 | * dev pointer to network device structure | |
4029 | * | |
4030 | * returns 0 if success, otherwise error code | |
4031 | */ | |
4032 | static int hdlcdev_close(struct net_device *dev) | |
4033 | { | |
4034 | MGSLPC_INFO *info = dev_to_port(dev); | |
eeb46134 | 4035 | struct tty_struct *tty = tty_port_tty_get(&info->port); |
1da177e4 LT |
4036 | unsigned long flags; |
4037 | ||
4038 | if (debug_level >= DEBUG_LEVEL_INFO) | |
4039 | printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); | |
4040 | ||
4041 | netif_stop_queue(dev); | |
4042 | ||
4043 | /* shutdown adapter and release resources */ | |
eeb46134 AC |
4044 | shutdown(info, tty); |
4045 | tty_kref_put(tty); | |
1da177e4 LT |
4046 | hdlc_close(dev); |
4047 | ||
4048 | spin_lock_irqsave(&info->netlock, flags); | |
4049 | info->netcount=0; | |
4050 | spin_unlock_irqrestore(&info->netlock, flags); | |
4051 | ||
4052 | return 0; | |
4053 | } | |
4054 | ||
4055 | /** | |
4056 | * called by network layer to process IOCTL call to network device | |
4057 | * | |
4058 | * dev pointer to network device structure | |
4059 | * ifr pointer to network interface request structure | |
4060 | * cmd IOCTL command code | |
4061 | * | |
4062 | * returns 0 if success, otherwise error code | |
4063 | */ | |
4064 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
4065 | { | |
4066 | const size_t size = sizeof(sync_serial_settings); | |
4067 | sync_serial_settings new_line; | |
4068 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
4069 | MGSLPC_INFO *info = dev_to_port(dev); | |
4070 | unsigned int flags; | |
4071 | ||
4072 | if (debug_level >= DEBUG_LEVEL_INFO) | |
4073 | printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); | |
4074 | ||
4075 | /* return error if TTY interface open */ | |
eeb46134 | 4076 | if (info->port.count) |
1da177e4 LT |
4077 | return -EBUSY; |
4078 | ||
4079 | if (cmd != SIOCWANDEV) | |
4080 | return hdlc_ioctl(dev, ifr, cmd); | |
4081 | ||
5b917a14 VK |
4082 | memset(&new_line, 0, size); |
4083 | ||
1da177e4 LT |
4084 | switch(ifr->ifr_settings.type) { |
4085 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
4086 | ||
4087 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
4088 | if (ifr->ifr_settings.size < size) { | |
4089 | ifr->ifr_settings.size = size; /* data size wanted */ | |
4090 | return -ENOBUFS; | |
4091 | } | |
4092 | ||
4093 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
4094 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
4095 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
4096 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
4097 | ||
4098 | switch (flags){ | |
4099 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
4100 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
4101 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
4102 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
4103 | default: new_line.clock_type = CLOCK_DEFAULT; | |
4104 | } | |
4105 | ||
4106 | new_line.clock_rate = info->params.clock_speed; | |
4107 | new_line.loopback = info->params.loopback ? 1:0; | |
4108 | ||
4109 | if (copy_to_user(line, &new_line, size)) | |
4110 | return -EFAULT; | |
4111 | return 0; | |
4112 | ||
4113 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
4114 | ||
4115 | if(!capable(CAP_NET_ADMIN)) | |
4116 | return -EPERM; | |
4117 | if (copy_from_user(&new_line, line, size)) | |
4118 | return -EFAULT; | |
4119 | ||
4120 | switch (new_line.clock_type) | |
4121 | { | |
4122 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
4123 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
4124 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
4125 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
4126 | case CLOCK_DEFAULT: flags = info->params.flags & | |
4127 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
4128 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
4129 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
4130 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
4131 | default: return -EINVAL; | |
4132 | } | |
4133 | ||
4134 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
4135 | return -EINVAL; | |
4136 | ||
4137 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
4138 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
4139 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
4140 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
4141 | info->params.flags |= flags; | |
4142 | ||
4143 | info->params.loopback = new_line.loopback; | |
4144 | ||
4145 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
4146 | info->params.clock_speed = new_line.clock_rate; | |
4147 | else | |
4148 | info->params.clock_speed = 0; | |
4149 | ||
4150 | /* if network interface up, reprogram hardware */ | |
eeb46134 AC |
4151 | if (info->netcount) { |
4152 | struct tty_struct *tty = tty_port_tty_get(&info->port); | |
4153 | mgslpc_program_hw(info, tty); | |
4154 | tty_kref_put(tty); | |
4155 | } | |
1da177e4 LT |
4156 | return 0; |
4157 | ||
4158 | default: | |
4159 | return hdlc_ioctl(dev, ifr, cmd); | |
4160 | } | |
4161 | } | |
4162 | ||
4163 | /** | |
4164 | * called by network layer when transmit timeout is detected | |
4165 | * | |
4166 | * dev pointer to network device structure | |
4167 | */ | |
4168 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
4169 | { | |
4170 | MGSLPC_INFO *info = dev_to_port(dev); | |
1da177e4 LT |
4171 | unsigned long flags; |
4172 | ||
4173 | if (debug_level >= DEBUG_LEVEL_INFO) | |
4174 | printk("hdlcdev_tx_timeout(%s)\n",dev->name); | |
4175 | ||
198191c4 KH |
4176 | dev->stats.tx_errors++; |
4177 | dev->stats.tx_aborted_errors++; | |
1da177e4 LT |
4178 | |
4179 | spin_lock_irqsave(&info->lock,flags); | |
4180 | tx_stop(info); | |
4181 | spin_unlock_irqrestore(&info->lock,flags); | |
4182 | ||
4183 | netif_wake_queue(dev); | |
4184 | } | |
4185 | ||
4186 | /** | |
4187 | * called by device driver when transmit completes | |
4188 | * reenable network layer transmit if stopped | |
4189 | * | |
4190 | * info pointer to device instance information | |
4191 | */ | |
4192 | static void hdlcdev_tx_done(MGSLPC_INFO *info) | |
4193 | { | |
4194 | if (netif_queue_stopped(info->netdev)) | |
4195 | netif_wake_queue(info->netdev); | |
4196 | } | |
4197 | ||
4198 | /** | |
4199 | * called by device driver when frame received | |
4200 | * pass frame to network layer | |
4201 | * | |
4202 | * info pointer to device instance information | |
4203 | * buf pointer to buffer contianing frame data | |
4204 | * size count of data bytes in buf | |
4205 | */ | |
4206 | static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size) | |
4207 | { | |
4208 | struct sk_buff *skb = dev_alloc_skb(size); | |
4209 | struct net_device *dev = info->netdev; | |
1da177e4 LT |
4210 | |
4211 | if (debug_level >= DEBUG_LEVEL_INFO) | |
4212 | printk("hdlcdev_rx(%s)\n",dev->name); | |
4213 | ||
4214 | if (skb == NULL) { | |
4215 | printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name); | |
198191c4 | 4216 | dev->stats.rx_dropped++; |
1da177e4 LT |
4217 | return; |
4218 | } | |
4219 | ||
198191c4 | 4220 | memcpy(skb_put(skb, size), buf, size); |
1da177e4 | 4221 | |
198191c4 | 4222 | skb->protocol = hdlc_type_trans(skb, dev); |
1da177e4 | 4223 | |
198191c4 KH |
4224 | dev->stats.rx_packets++; |
4225 | dev->stats.rx_bytes += size; | |
1da177e4 LT |
4226 | |
4227 | netif_rx(skb); | |
1da177e4 LT |
4228 | } |
4229 | ||
991990a1 KH |
4230 | static const struct net_device_ops hdlcdev_ops = { |
4231 | .ndo_open = hdlcdev_open, | |
4232 | .ndo_stop = hdlcdev_close, | |
4233 | .ndo_change_mtu = hdlc_change_mtu, | |
4234 | .ndo_start_xmit = hdlc_start_xmit, | |
4235 | .ndo_do_ioctl = hdlcdev_ioctl, | |
4236 | .ndo_tx_timeout = hdlcdev_tx_timeout, | |
4237 | }; | |
4238 | ||
1da177e4 LT |
4239 | /** |
4240 | * called by device driver when adding device instance | |
4241 | * do generic HDLC initialization | |
4242 | * | |
4243 | * info pointer to device instance information | |
4244 | * | |
4245 | * returns 0 if success, otherwise error code | |
4246 | */ | |
4247 | static int hdlcdev_init(MGSLPC_INFO *info) | |
4248 | { | |
4249 | int rc; | |
4250 | struct net_device *dev; | |
4251 | hdlc_device *hdlc; | |
4252 | ||
4253 | /* allocate and initialize network and HDLC layer objects */ | |
4254 | ||
4255 | if (!(dev = alloc_hdlcdev(info))) { | |
4256 | printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); | |
4257 | return -ENOMEM; | |
4258 | } | |
4259 | ||
4260 | /* for network layer reporting purposes only */ | |
4261 | dev->base_addr = info->io_base; | |
4262 | dev->irq = info->irq_level; | |
4263 | ||
4264 | /* network layer callbacks and settings */ | |
991990a1 KH |
4265 | dev->netdev_ops = &hdlcdev_ops; |
4266 | dev->watchdog_timeo = 10 * HZ; | |
1da177e4 LT |
4267 | dev->tx_queue_len = 50; |
4268 | ||
4269 | /* generic HDLC layer callbacks and settings */ | |
4270 | hdlc = dev_to_hdlc(dev); | |
4271 | hdlc->attach = hdlcdev_attach; | |
4272 | hdlc->xmit = hdlcdev_xmit; | |
4273 | ||
4274 | /* register objects with HDLC layer */ | |
4275 | if ((rc = register_hdlc_device(dev))) { | |
4276 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); | |
4277 | free_netdev(dev); | |
4278 | return rc; | |
4279 | } | |
4280 | ||
4281 | info->netdev = dev; | |
4282 | return 0; | |
4283 | } | |
4284 | ||
4285 | /** | |
4286 | * called by device driver when removing device instance | |
4287 | * do generic HDLC cleanup | |
4288 | * | |
4289 | * info pointer to device instance information | |
4290 | */ | |
4291 | static void hdlcdev_exit(MGSLPC_INFO *info) | |
4292 | { | |
4293 | unregister_hdlc_device(info->netdev); | |
4294 | free_netdev(info->netdev); | |
4295 | info->netdev = NULL; | |
4296 | } | |
4297 | ||
4298 | #endif /* CONFIG_HDLC */ | |
4299 |