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tty: Replace TTY_IO_ERROR bit tests with tty_io_error()
[deliverable/linux.git] / drivers / char / pcmcia / synclink_cs.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
a7482a2e 4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
1da177e4
LT		 5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30#if defined(__i386__)
31# define BREAKPOINT() asm(" int $3");
32#else
33# define BREAKPOINT() { }
34#endif
35
36#define MAX_DEVICE_COUNT 4
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/errno.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/timer.h>
43#include <linux/time.h>
44#include <linux/interrupt.h>
1da177e4
LT		 45#include <linux/tty.h>
46#include <linux/tty_flip.h>
47#include <linux/serial.h>
48#include <linux/major.h>
49#include <linux/string.h>
50#include <linux/fcntl.h>
51#include <linux/ptrace.h>
52#include <linux/ioport.h>
53#include <linux/mm.h>
87687144 54#include <linux/seq_file.h>
1da177e4
LT		 55#include <linux/slab.h>
56#include <linux/netdevice.h>
57#include <linux/vmalloc.h>
58#include <linux/init.h>
1da177e4
LT		 59#include <linux/delay.h>
60#include <linux/ioctl.h>
3dd1247f 61#include <linux/synclink.h>
1da177e4 62
1da177e4
LT		 63#include <asm/io.h>
64#include <asm/irq.h>
65#include <asm/dma.h>
66#include <linux/bitops.h>
67#include <asm/types.h>
68#include <linux/termios.h>
69#include <linux/workqueue.h>
70#include <linux/hdlc.h>
71
1da177e4
LT		 72#include <pcmcia/cistpl.h>
73#include <pcmcia/cisreg.h>
74#include <pcmcia/ds.h>
75
af69c7f9
PF		 76#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
77#define SYNCLINK_GENERIC_HDLC 1
78#else
79#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 80#endif
81
82#define GET_USER(error,value,addr) error = get_user(value,addr)
83#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
84#define PUT_USER(error,value,addr) error = put_user(value,addr)
85#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
86
87#include <asm/uaccess.h>
88
1da177e4
LT		 89static MGSL_PARAMS default_params = {
90 MGSL_MODE_HDLC, /* unsigned long mode */
91 0, /* unsigned char loopback; */
92 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
93 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
94 0, /* unsigned long clock_speed; */
95 0xff, /* unsigned char addr_filter; */
96 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
97 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
98 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
99 9600, /* unsigned long data_rate; */
100 8, /* unsigned char data_bits; */
101 1, /* unsigned char stop_bits; */
102 ASYNC_PARITY_NONE /* unsigned char parity; */
103};
104
3d553993 105typedef struct {
1da177e4
LT		 106 int count;
107 unsigned char status;
108 char data[1];
109} RXBUF;
110
111/* The queue of BH actions to be performed */
112
113#define BH_RECEIVE 1
114#define BH_TRANSMIT 2
115#define BH_STATUS 4
116
117#define IO_PIN_SHUTDOWN_LIMIT 100
118
119#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
120
121struct _input_signal_events {
d12341f9 122 int ri_up;
1da177e4
LT		 123 int ri_down;
124 int dsr_up;
125 int dsr_down;
126 int dcd_up;
127 int dcd_down;
128 int cts_up;
129 int cts_down;
130};
131
132
133/*
134 * Device instance data structure
135 */
d12341f9 136
1da177e4 137typedef struct _mgslpc_info {
eeb46134 138 struct tty_port port;
1da177e4
LT		 139 void *if_ptr; /* General purpose pointer (used by SPPP) */
140 int magic;
1da177e4 141 int line;
d12341f9 142
1da177e4 143 struct mgsl_icount icount;
d12341f9 144
1da177e4
LT		 145 int timeout;
146 int x_char; /* xon/xoff character */
1da177e4 147 unsigned char read_status_mask;
d12341f9 148 unsigned char ignore_status_mask;
1da177e4
LT		 149
150 unsigned char *tx_buf;
151 int tx_put;
152 int tx_get;
153 int tx_count;
154
155 /* circular list of fixed length rx buffers */
156
157 unsigned char *rx_buf; /* memory allocated for all rx buffers */
158 int rx_buf_total_size; /* size of memory allocated for rx buffers */
159 int rx_put; /* index of next empty rx buffer */
160 int rx_get; /* index of next full rx buffer */
161 int rx_buf_size; /* size in bytes of single rx buffer */
162 int rx_buf_count; /* total number of rx buffers */
163 int rx_frame_count; /* number of full rx buffers */
d12341f9 164
1da177e4
LT		 165 wait_queue_head_t status_event_wait_q;
166 wait_queue_head_t event_wait_q;
167 struct timer_list tx_timer; /* HDLC transmit timeout timer */
168 struct _mgslpc_info *next_device; /* device list link */
169
170 unsigned short imra_value;
171 unsigned short imrb_value;
172 unsigned char pim_value;
173
174 spinlock_t lock;
175 struct work_struct task; /* task structure for scheduling bh */
176
177 u32 max_frame_size;
178
179 u32 pending_bh;
180
0fab6de0
JP		 181 bool bh_running;
182 bool bh_requested;
d12341f9 183
1da177e4
LT		 184 int dcd_chkcount; /* check counts to prevent */
185 int cts_chkcount; /* too many IRQs if a signal */
186 int dsr_chkcount; /* is floating */
187 int ri_chkcount;
188
0fab6de0
JP		 189 bool rx_enabled;
190 bool rx_overflow;
1da177e4 191
0fab6de0
JP		 192 bool tx_enabled;
193 bool tx_active;
194 bool tx_aborting;
1da177e4
LT		 195 u32 idle_mode;
196
197 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
198
199 char device_name[25]; /* device instance name */
200
201 unsigned int io_base; /* base I/O address of adapter */
202 unsigned int irq_level;
d12341f9 203
1da177e4
LT		 204 MGSL_PARAMS params; /* communications parameters */
205
206 unsigned char serial_signals; /* current serial signal states */
207
0fab6de0 208 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 209 char testing_irq;
210 unsigned int init_error; /* startup error (DIAGS) */
211
a6b68a69 212 char *flag_buf;
0fab6de0 213 bool drop_rts_on_tx_done;
1da177e4
LT		 214
215 struct _input_signal_events input_signal_events;
216
217 /* PCMCIA support */
fd238232 218 struct pcmcia_device *p_dev;
1da177e4
LT		 219 int stop;
220
221 /* SPPP/Cisco HDLC device parts */
222 int netcount;
1da177e4
LT		 223 spinlock_t netlock;
224
af69c7f9 225#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 226 struct net_device *netdev;
227#endif
228
229} MGSLPC_INFO;
230
231#define MGSLPC_MAGIC 0x5402
232
233/*
234 * The size of the serial xmit buffer is 1 page, or 4096 bytes
235 */
236#define TXBUFSIZE 4096
237
d12341f9 238
1da177e4
LT		 239#define CHA 0x00 /* channel A offset */
240#define CHB 0x40 /* channel B offset */
241
242/*
243 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
244 */
245#undef PVR
246
247#define RXFIFO 0
248#define TXFIFO 0
249#define STAR 0x20
250#define CMDR 0x20
251#define RSTA 0x21
252#define PRE 0x21
253#define MODE 0x22
254#define TIMR 0x23
255#define XAD1 0x24
256#define XAD2 0x25
257#define RAH1 0x26
258#define RAH2 0x27
259#define DAFO 0x27
260#define RAL1 0x28
261#define RFC 0x28
262#define RHCR 0x29
263#define RAL2 0x29
264#define RBCL 0x2a
265#define XBCL 0x2a
266#define RBCH 0x2b
267#define XBCH 0x2b
268#define CCR0 0x2c
269#define CCR1 0x2d
270#define CCR2 0x2e
271#define CCR3 0x2f
272#define VSTR 0x34
273#define BGR 0x34
274#define RLCR 0x35
275#define AML 0x36
276#define AMH 0x37
277#define GIS 0x38
278#define IVA 0x38
279#define IPC 0x39
280#define ISR 0x3a
281#define IMR 0x3a
282#define PVR 0x3c
283#define PIS 0x3d
284#define PIM 0x3d
285#define PCR 0x3e
286#define CCR4 0x3f
d12341f9 287
1da177e4 288// IMR/ISR
d12341f9 289
1da177e4
LT		 290#define IRQ_BREAK_ON BIT15 // rx break detected
291#define IRQ_DATAOVERRUN BIT14 // receive data overflow
292#define IRQ_ALLSENT BIT13 // all sent
293#define IRQ_UNDERRUN BIT12 // transmit data underrun
294#define IRQ_TIMER BIT11 // timer interrupt
295#define IRQ_CTS BIT10 // CTS status change
296#define IRQ_TXREPEAT BIT9 // tx message repeat
297#define IRQ_TXFIFO BIT8 // transmit pool ready
298#define IRQ_RXEOM BIT7 // receive message end
299#define IRQ_EXITHUNT BIT6 // receive frame start
300#define IRQ_RXTIME BIT6 // rx char timeout
301#define IRQ_DCD BIT2 // carrier detect status change
302#define IRQ_OVERRUN BIT1 // receive frame overflow
303#define IRQ_RXFIFO BIT0 // receive pool full
d12341f9 304
1da177e4 305// STAR
d12341f9 306
1da177e4
LT		 307#define XFW BIT6 // transmit FIFO write enable
308#define CEC BIT2 // command executing
309#define CTS BIT1 // CTS state
d12341f9 310
1da177e4
LT		 311#define PVR_DTR BIT0
312#define PVR_DSR BIT1
313#define PVR_RI BIT2
314#define PVR_AUTOCTS BIT3
315#define PVR_RS232 0x20 /* 0010b */
316#define PVR_V35 0xe0 /* 1110b */
317#define PVR_RS422 0x40 /* 0100b */
d12341f9
JG		 318
319/* Register access functions */
320
1da177e4
LT		 321#define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
322#define read_reg(info, reg) inb((info)->io_base + (reg))
323
d12341f9 324#define read_reg16(info, reg) inw((info)->io_base + (reg))
1da177e4 325#define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
d12341f9 326
1da177e4 327#define set_reg_bits(info, reg, mask) \
3d553993 328 write_reg(info, (reg), \
d12341f9 329 (unsigned char) (read_reg(info, (reg)) | (mask)))
1da177e4 330#define clear_reg_bits(info, reg, mask) \
3d553993 331 write_reg(info, (reg), \
d12341f9 332 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
1da177e4
LT		 333/*
334 * interrupt enable/disable routines
d12341f9
JG		 335 */
336static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 337{
338 if (channel == CHA) {
339 info->imra_value |= mask;
340 write_reg16(info, CHA + IMR, info->imra_value);
341 } else {
342 info->imrb_value |= mask;
343 write_reg16(info, CHB + IMR, info->imrb_value);
344 }
345}
d12341f9 346static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 347{
348 if (channel == CHA) {
349 info->imra_value &= ~mask;
350 write_reg16(info, CHA + IMR, info->imra_value);
351 } else {
352 info->imrb_value &= ~mask;
353 write_reg16(info, CHB + IMR, info->imrb_value);
354 }
355}
356
357#define port_irq_disable(info, mask) \
3d553993 358 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
1da177e4
LT		 359
360#define port_irq_enable(info, mask) \
3d553993 361 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
1da177e4
LT		 362
363static void rx_start(MGSLPC_INFO *info);
364static void rx_stop(MGSLPC_INFO *info);
365
eeb46134 366static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 367static void tx_stop(MGSLPC_INFO *info);
368static void tx_set_idle(MGSLPC_INFO *info);
369
370static void get_signals(MGSLPC_INFO *info);
371static void set_signals(MGSLPC_INFO *info);
372
373static void reset_device(MGSLPC_INFO *info);
374
375static void hdlc_mode(MGSLPC_INFO *info);
376static void async_mode(MGSLPC_INFO *info);
377
378static void tx_timeout(unsigned long context);
379
eeb46134 380static int carrier_raised(struct tty_port *port);
fcc8ac18 381static void dtr_rts(struct tty_port *port, int onoff);
1da177e4 382
af69c7f9 383#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 384#define dev_to_port(D) (dev_to_hdlc(D)->priv)
385static void hdlcdev_tx_done(MGSLPC_INFO *info);
386static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
387static int hdlcdev_init(MGSLPC_INFO *info);
388static void hdlcdev_exit(MGSLPC_INFO *info);
389#endif
390
391static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
392
0fab6de0
JP		 393static bool register_test(MGSLPC_INFO *info);
394static bool irq_test(MGSLPC_INFO *info);
1da177e4
LT		 395static int adapter_test(MGSLPC_INFO *info);
396
397static int claim_resources(MGSLPC_INFO *info);
398static void release_resources(MGSLPC_INFO *info);
d34138d0 399static int mgslpc_add_device(MGSLPC_INFO *info);
1da177e4
LT		 400static void mgslpc_remove_device(MGSLPC_INFO *info);
401
eeb46134 402static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 403static void rx_reset_buffers(MGSLPC_INFO *info);
404static int rx_alloc_buffers(MGSLPC_INFO *info);
405static void rx_free_buffers(MGSLPC_INFO *info);
406
7d12e780 407static irqreturn_t mgslpc_isr(int irq, void *dev_id);
1da177e4
LT		 408
409/*
410 * Bottom half interrupt handlers
411 */
c4028958 412static void bh_handler(struct work_struct *work);
eeb46134 413static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 414static void bh_status(MGSLPC_INFO *info);
415
416/*
417 * ioctl handlers
418 */
60b33c13 419static int tiocmget(struct tty_struct *tty);
20b9d177
AC		 420static int tiocmset(struct tty_struct *tty,
421 unsigned int set, unsigned int clear);
1da177e4
LT		 422static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
423static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
eeb46134 424static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
1da177e4
LT		 425static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
426static int set_txidle(MGSLPC_INFO *info, int idle_mode);
eeb46134 427static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
1da177e4
LT		 428static int tx_abort(MGSLPC_INFO *info);
429static int set_rxenable(MGSLPC_INFO *info, int enable);
430static int wait_events(MGSLPC_INFO *info, int __user *mask);
431
432static MGSLPC_INFO *mgslpc_device_list = NULL;
433static int mgslpc_device_count = 0;
434
435/*
436 * Set this param to non-zero to load eax with the
437 * .text section address and breakpoint on module load.
438 * This is useful for use with gdb and add-symbol-file command.
439 */
208250dd 440static bool break_on_load;
1da177e4
LT		 441
442/*
443 * Driver major number, defaults to zero to get auto
444 * assigned major number. May be forced as module parameter.
445 */
446static int ttymajor=0;
447
448static int debug_level = 0;
449static int maxframe[MAX_DEVICE_COUNT] = {0,};
1da177e4
LT		 450
451module_param(break_on_load, bool, 0);
452module_param(ttymajor, int, 0);
453module_param(debug_level, int, 0);
454module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 455
456MODULE_LICENSE("GPL");
457
458static char *driver_name = "SyncLink PC Card driver";
a7482a2e 459static char *driver_version = "$Revision: 4.34 $";
1da177e4
LT		 460
461static struct tty_driver *serial_driver;
462
463/* number of characters left in xmit buffer before we ask for more */
464#define WAKEUP_CHARS 256
465
eeb46134 466static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 467static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
468
469/* PCMCIA prototypes */
470
15b99ac1 471static int mgslpc_config(struct pcmcia_device *link);
1da177e4 472static void mgslpc_release(u_long arg);
cc3b4866 473static void mgslpc_detach(struct pcmcia_device *p_dev);
1da177e4 474
1da177e4
LT		 475/*
476 * 1st function defined in .text section. Calling this function in
477 * init_module() followed by a breakpoint allows a remote debugger
478 * (gdb) to get the .text address for the add-symbol-file command.
479 * This allows remote debugging of dynamically loadable modules.
480 */
481static void* mgslpc_get_text_ptr(void)
482{
483 return mgslpc_get_text_ptr;
484}
485
486/**
487 * line discipline callback wrappers
488 *
489 * The wrappers maintain line discipline references
490 * while calling into the line discipline.
491 *
1da177e4
LT		 492 * ldisc_receive_buf - pass receive data to line discipline
493 */
494
1da177e4
LT		 495static void ldisc_receive_buf(struct tty_struct *tty,
496 const __u8 *data, char *flags, int count)
497{
498 struct tty_ldisc *ld;
499 if (!tty)
500 return;
501 ld = tty_ldisc_ref(tty);
502 if (ld) {
a352def2
AC		 503 if (ld->ops->receive_buf)
504 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 505 tty_ldisc_deref(ld);
506 }
507}
508
eeb46134
AC		 509static const struct tty_port_operations mgslpc_port_ops = {
510 .carrier_raised = carrier_raised,
fcc8ac18 511 .dtr_rts = dtr_rts
eeb46134
AC		 512};
513
15b99ac1 514static int mgslpc_probe(struct pcmcia_device *link)
1da177e4 515{
3d553993
AK		 516 MGSLPC_INFO *info;
517 int ret;
518
519 if (debug_level >= DEBUG_LEVEL_INFO)
520 printk("mgslpc_attach\n");
521
522 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
523 if (!info) {
524 printk("Error can't allocate device instance data\n");
525 return -ENOMEM;
526 }
527
528 info->magic = MGSLPC_MAGIC;
529 tty_port_init(&info->port);
530 info->port.ops = &mgslpc_port_ops;
531 INIT_WORK(&info->task, bh_handler);
532 info->max_frame_size = 4096;
533 info->port.close_delay = 5*HZ/10;
534 info->port.closing_wait = 30*HZ;
535 init_waitqueue_head(&info->status_event_wait_q);
536 init_waitqueue_head(&info->event_wait_q);
537 spin_lock_init(&info->lock);
538 spin_lock_init(&info->netlock);
539 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
540 info->idle_mode = HDLC_TXIDLE_FLAGS;
541 info->imra_value = 0xffff;
542 info->imrb_value = 0xffff;
543 info->pim_value = 0xff;
544
545 info->p_dev = link;
546 link->priv = info;
547
548 /* Initialize the struct pcmcia_device structure */
549
550 ret = mgslpc_config(link);
551 if (ret != 0)
552 goto failed;
553
554 ret = mgslpc_add_device(info);
555 if (ret != 0)
556 goto failed_release;
557
558 return 0;
d34138d0
AK		 559
560failed_release:
3d553993 561 mgslpc_release((u_long)link);
d34138d0 562failed:
3d553993
AK		 563 tty_port_destroy(&info->port);
564 kfree(info);
565 return ret;
1da177e4
LT		 566}
567
568/* Card has been inserted.
569 */
570
00990e7c 571static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
aaa8cfda 572{
90abdc3b 573 return pcmcia_request_io(p_dev);
aaa8cfda
DB		 574}
575
15b99ac1 576static int mgslpc_config(struct pcmcia_device *link)
1da177e4 577{
3d553993
AK		 578 MGSLPC_INFO *info = link->priv;
579 int ret;
d12341f9 580
3d553993
AK		 581 if (debug_level >= DEBUG_LEVEL_INFO)
582 printk("mgslpc_config(0x%p)\n", link);
1da177e4 583
3d553993 584 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
00990e7c 585
3d553993
AK		 586 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
587 if (ret != 0)
588 goto failed;
1da177e4 589
3d553993
AK		 590 link->config_index = 8;
591 link->config_regs = PRESENT_OPTION;
d12341f9 592
3d553993
AK		 593 ret = pcmcia_request_irq(link, mgslpc_isr);
594 if (ret)
595 goto failed;
596 ret = pcmcia_enable_device(link);
597 if (ret)
598 goto failed;
1da177e4 599
3d553993
AK		 600 info->io_base = link->resource[0]->start;
601 info->irq_level = link->irq;
602 return 0;
1da177e4 603
cbf624f0 604failed:
3d553993
AK		 605 mgslpc_release((u_long)link);
606 return -ENODEV;
1da177e4
LT		 607}
608
609/* Card has been removed.
610 * Unregister device and release PCMCIA configuration.
611 * If device is open, postpone until it is closed.
612 */
613static void mgslpc_release(u_long arg)
614{
e2d40963 615 struct pcmcia_device *link = (struct pcmcia_device *)arg;
1da177e4 616
e2d40963
DB		 617 if (debug_level >= DEBUG_LEVEL_INFO)
618 printk("mgslpc_release(0x%p)\n", link);
1da177e4 619
e2d40963 620 pcmcia_disable_device(link);
1da177e4
LT		 621}
622
fba395ee 623static void mgslpc_detach(struct pcmcia_device *link)
1da177e4 624{
e2d40963
DB		 625 if (debug_level >= DEBUG_LEVEL_INFO)
626 printk("mgslpc_detach(0x%p)\n", link);
cc3b4866 627
e2d40963
DB		 628 ((MGSLPC_INFO *)link->priv)->stop = 1;
629 mgslpc_release((u_long)link);
1da177e4 630
e2d40963 631 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
1da177e4
LT		 632}
633
fba395ee 634static int mgslpc_suspend(struct pcmcia_device *link)
98e4c28b 635{
98e4c28b
DB		 636 MGSLPC_INFO *info = link->priv;
637
98e4c28b 638 info->stop = 1;
98e4c28b
DB		 639
640 return 0;
641}
642
fba395ee 643static int mgslpc_resume(struct pcmcia_device *link)
98e4c28b 644{
98e4c28b
DB		 645 MGSLPC_INFO *info = link->priv;
646
98e4c28b
DB		 647 info->stop = 0;
648
649 return 0;
650}
651
652
0fab6de0 653static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
1da177e4
LT		 654 char *name, const char *routine)
655{
656#ifdef MGSLPC_PARANOIA_CHECK
657 static const char *badmagic =
658 "Warning: bad magic number for mgsl struct (%s) in %s\n";
659 static const char *badinfo =
660 "Warning: null mgslpc_info for (%s) in %s\n";
661
662 if (!info) {
663 printk(badinfo, name, routine);
0fab6de0 664 return true;
1da177e4
LT		 665 }
666 if (info->magic != MGSLPC_MAGIC) {
667 printk(badmagic, name, routine);
0fab6de0 668 return true;
1da177e4
LT		 669 }
670#else
671 if (!info)
0fab6de0 672 return true;
1da177e4 673#endif
0fab6de0 674 return false;
1da177e4
LT		 675}
676
677
678#define CMD_RXFIFO BIT7 // release current rx FIFO
679#define CMD_RXRESET BIT6 // receiver reset
680#define CMD_RXFIFO_READ BIT5
681#define CMD_START_TIMER BIT4
682#define CMD_TXFIFO BIT3 // release current tx FIFO
683#define CMD_TXEOM BIT1 // transmit end message
684#define CMD_TXRESET BIT0 // transmit reset
685
0fab6de0 686static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
1da177e4
LT		 687{
688 int i = 0;
d12341f9 689 /* wait for command completion */
1da177e4
LT		 690 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
691 udelay(1);
692 if (i++ == 1000)
0fab6de0 693 return false;
1da177e4 694 }
0fab6de0 695 return true;
1da177e4
LT		 696}
697
d12341f9 698static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
1da177e4
LT		 699{
700 wait_command_complete(info, channel);
701 write_reg(info, (unsigned char) (channel + CMDR), cmd);
702}
703
704static void tx_pause(struct tty_struct *tty)
705{
706 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
707 unsigned long flags;
d12341f9 708
1da177e4
LT		 709 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
710 return;
711 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 712 printk("tx_pause(%s)\n", info->device_name);
d12341f9 713
3d553993 714 spin_lock_irqsave(&info->lock, flags);
1da177e4 715 if (info->tx_enabled)
3d553993
AK		 716 tx_stop(info);
717 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 718}
719
720static void tx_release(struct tty_struct *tty)
721{
722 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
723 unsigned long flags;
d12341f9 724
1da177e4
LT		 725 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
726 return;
727 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 728 printk("tx_release(%s)\n", info->device_name);
d12341f9 729
3d553993 730 spin_lock_irqsave(&info->lock, flags);
1da177e4 731 if (!info->tx_enabled)
3d553993
AK		 732 tx_start(info, tty);
733 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 734}
735
736/* Return next bottom half action to perform.
737 * or 0 if nothing to do.
738 */
739static int bh_action(MGSLPC_INFO *info)
740{
741 unsigned long flags;
742 int rc = 0;
d12341f9 743
3d553993 744 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 745
746 if (info->pending_bh & BH_RECEIVE) {
747 info->pending_bh &= ~BH_RECEIVE;
748 rc = BH_RECEIVE;
749 } else if (info->pending_bh & BH_TRANSMIT) {
750 info->pending_bh &= ~BH_TRANSMIT;
751 rc = BH_TRANSMIT;
752 } else if (info->pending_bh & BH_STATUS) {
753 info->pending_bh &= ~BH_STATUS;
754 rc = BH_STATUS;
755 }
756
757 if (!rc) {
758 /* Mark BH routine as complete */
0fab6de0
JP		 759 info->bh_running = false;
760 info->bh_requested = false;
1da177e4 761 }
d12341f9 762
3d553993 763 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 764
1da177e4
LT		 765 return rc;
766}
767
c4028958 768static void bh_handler(struct work_struct *work)
1da177e4 769{
c4028958 770 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
eeb46134 771 struct tty_struct *tty;
1da177e4
LT		 772 int action;
773
1da177e4 774 if (debug_level >= DEBUG_LEVEL_BH)
3d553993 775 printk("%s(%d):bh_handler(%s) entry\n",
1da177e4 776 __FILE__,__LINE__,info->device_name);
d12341f9 777
0fab6de0 778 info->bh_running = true;
eeb46134 779 tty = tty_port_tty_get(&info->port);
1da177e4
LT		 780
781 while((action = bh_action(info)) != 0) {
d12341f9 782
1da177e4 783 /* Process work item */
3d553993
AK		 784 if (debug_level >= DEBUG_LEVEL_BH)
785 printk("%s(%d):bh_handler() work item action=%d\n",
1da177e4
LT		 786 __FILE__,__LINE__,action);
787
788 switch (action) {
d12341f9 789
1da177e4 790 case BH_RECEIVE:
eeb46134 791 while(rx_get_frame(info, tty));
1da177e4
LT		 792 break;
793 case BH_TRANSMIT:
eeb46134 794 bh_transmit(info, tty);
1da177e4
LT		 795 break;
796 case BH_STATUS:
797 bh_status(info);
798 break;
799 default:
800 /* unknown work item ID */
801 printk("Unknown work item ID=%08X!\n", action);
802 break;
803 }
804 }
805
eeb46134 806 tty_kref_put(tty);
1da177e4 807 if (debug_level >= DEBUG_LEVEL_BH)
3d553993 808 printk("%s(%d):bh_handler(%s) exit\n",
1da177e4
LT		 809 __FILE__,__LINE__,info->device_name);
810}
811
eeb46134 812static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4 813{
1da177e4
LT		 814 if (debug_level >= DEBUG_LEVEL_BH)
815 printk("bh_transmit() entry on %s\n", info->device_name);
816
b963a844 817 if (tty)
1da177e4 818 tty_wakeup(tty);
1da177e4
LT		 819}
820
cdaad343 821static void bh_status(MGSLPC_INFO *info)
1da177e4
LT		 822{
823 info->ri_chkcount = 0;
824 info->dsr_chkcount = 0;
825 info->dcd_chkcount = 0;
826 info->cts_chkcount = 0;
827}
828
d12341f9 829/* eom: non-zero = end of frame */
1da177e4
LT		 830static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
831{
832 unsigned char data[2];
833 unsigned char fifo_count, read_count, i;
834 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
835
836 if (debug_level >= DEBUG_LEVEL_ISR)
3d553993 837 printk("%s(%d):rx_ready_hdlc(eom=%d)\n", __FILE__, __LINE__, eom);
d12341f9 838
1da177e4
LT		 839 if (!info->rx_enabled)
840 return;
841
842 if (info->rx_frame_count >= info->rx_buf_count) {
843 /* no more free buffers */
844 issue_command(info, CHA, CMD_RXRESET);
845 info->pending_bh |= BH_RECEIVE;
0fab6de0 846 info->rx_overflow = true;
1da177e4
LT		 847 info->icount.buf_overrun++;
848 return;
849 }
850
851 if (eom) {
d12341f9 852 /* end of frame, get FIFO count from RBCL register */
3d553993
AK		 853 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
854 if (fifo_count == 0)
1da177e4
LT		 855 fifo_count = 32;
856 } else
857 fifo_count = 32;
d12341f9 858
1da177e4
LT		 859 do {
860 if (fifo_count == 1) {
861 read_count = 1;
862 data[0] = read_reg(info, CHA + RXFIFO);
863 } else {
864 read_count = 2;
865 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
866 }
867 fifo_count -= read_count;
868 if (!fifo_count && eom)
869 buf->status = data[--read_count];
870
871 for (i = 0; i < read_count; i++) {
872 if (buf->count >= info->max_frame_size) {
873 /* frame too large, reset receiver and reset current buffer */
874 issue_command(info, CHA, CMD_RXRESET);
875 buf->count = 0;
876 return;
877 }
878 *(buf->data + buf->count) = data[i];
879 buf->count++;
880 }
881 } while (fifo_count);
882
883 if (eom) {
884 info->pending_bh |= BH_RECEIVE;
885 info->rx_frame_count++;
886 info->rx_put++;
887 if (info->rx_put >= info->rx_buf_count)
888 info->rx_put = 0;
889 }
890 issue_command(info, CHA, CMD_RXFIFO);
891}
892
2e124b4a 893static void rx_ready_async(MGSLPC_INFO *info, int tcd)
1da177e4 894{
227434f8 895 struct tty_port *port = &info->port;
33f0f88f 896 unsigned char data, status, flag;
1da177e4 897 int fifo_count;
33f0f88f 898 int work = 0;
3d553993 899 struct mgsl_icount *icount = &info->icount;
1da177e4
LT		 900
901 if (tcd) {
d12341f9 902 /* early termination, get FIFO count from RBCL register */
1da177e4
LT		 903 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
904
905 /* Zero fifo count could mean 0 or 32 bytes available.
906 * If BIT5 of STAR is set then at least 1 byte is available.
907 */
908 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
909 fifo_count = 32;
910 } else
911 fifo_count = 32;
33f0f88f 912
227434f8 913 tty_buffer_request_room(port, fifo_count);
d12341f9 914 /* Flush received async data to receive data buffer. */
1da177e4
LT		 915 while (fifo_count) {
916 data = read_reg(info, CHA + RXFIFO);
917 status = read_reg(info, CHA + RXFIFO);
918 fifo_count -= 2;
919
1da177e4 920 icount->rx++;
33f0f88f 921 flag = TTY_NORMAL;
1da177e4
LT		 922
923 // if no frameing/crc error then save data
924 // BIT7:parity error
925 // BIT6:framing error
926
927 if (status & (BIT7 + BIT6)) {
d12341f9 928 if (status & BIT7)
1da177e4
LT		 929 icount->parity++;
930 else
931 icount->frame++;
932
933 /* discard char if tty control flags say so */
934 if (status & info->ignore_status_mask)
935 continue;
d12341f9 936
1da177e4
LT		 937 status &= info->read_status_mask;
938
939 if (status & BIT7)
33f0f88f 940 flag = TTY_PARITY;
1da177e4 941 else if (status & BIT6)
33f0f88f 942 flag = TTY_FRAME;
1da177e4 943 }
92a19f9c 944 work += tty_insert_flip_char(port, data, flag);
1da177e4
LT		 945 }
946 issue_command(info, CHA, CMD_RXFIFO);
947
948 if (debug_level >= DEBUG_LEVEL_ISR) {
33f0f88f
AC		 949 printk("%s(%d):rx_ready_async",
950 __FILE__,__LINE__);
1da177e4
LT		 951 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
952 __FILE__,__LINE__,icount->rx,icount->brk,
953 icount->parity,icount->frame,icount->overrun);
954 }
d12341f9 955
33f0f88f 956 if (work)
2e124b4a 957 tty_flip_buffer_push(port);
1da177e4
LT		 958}
959
960
eeb46134 961static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 962{
963 if (!info->tx_active)
964 return;
d12341f9 965
0fab6de0
JP		 966 info->tx_active = false;
967 info->tx_aborting = false;
1da177e4
LT		 968
969 if (info->params.mode == MGSL_MODE_ASYNC)
970 return;
971
972 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9
JG		 973 del_timer(&info->tx_timer);
974
1da177e4
LT		 975 if (info->drop_rts_on_tx_done) {
976 get_signals(info);
977 if (info->serial_signals & SerialSignal_RTS) {
978 info->serial_signals &= ~SerialSignal_RTS;
979 set_signals(info);
980 }
0fab6de0 981 info->drop_rts_on_tx_done = false;
1da177e4
LT		 982 }
983
af69c7f9 984#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 985 if (info->netcount)
986 hdlcdev_tx_done(info);
d12341f9 987 else
1da177e4
LT		 988#endif
989 {
221b7b57 990 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 991 tx_stop(info);
992 return;
993 }
994 info->pending_bh |= BH_TRANSMIT;
995 }
996}
997
eeb46134 998static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 999{
1000 unsigned char fifo_count = 32;
1001 int c;
1002
1003 if (debug_level >= DEBUG_LEVEL_ISR)
3d553993 1004 printk("%s(%d):tx_ready(%s)\n", __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1005
1006 if (info->params.mode == MGSL_MODE_HDLC) {
1007 if (!info->tx_active)
1008 return;
1009 } else {
221b7b57 1010 if (tty && (tty->stopped || tty->hw_stopped)) {
1da177e4
LT		 1011 tx_stop(info);
1012 return;
1013 }
1014 if (!info->tx_count)
0fab6de0 1015 info->tx_active = false;
1da177e4
LT		 1016 }
1017
1018 if (!info->tx_count)
1019 return;
1020
1021 while (info->tx_count && fifo_count) {
1022 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
d12341f9 1023
1da177e4
LT		 1024 if (c == 1) {
1025 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1026 } else {
1027 write_reg16(info, CHA + TXFIFO,
1028 *((unsigned short*)(info->tx_buf + info->tx_get)));
1029 }
1030 info->tx_count -= c;
1031 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1032 fifo_count -= c;
1033 }
1034
1035 if (info->params.mode == MGSL_MODE_ASYNC) {
1036 if (info->tx_count < WAKEUP_CHARS)
1037 info->pending_bh |= BH_TRANSMIT;
1038 issue_command(info, CHA, CMD_TXFIFO);
1039 } else {
1040 if (info->tx_count)
1041 issue_command(info, CHA, CMD_TXFIFO);
1042 else
1043 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1044 }
1045}
1046
eeb46134 1047static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1048{
1049 get_signals(info);
1050 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1051 irq_disable(info, CHB, IRQ_CTS);
1052 info->icount.cts++;
1053 if (info->serial_signals & SerialSignal_CTS)
1054 info->input_signal_events.cts_up++;
1055 else
1056 info->input_signal_events.cts_down++;
1057 wake_up_interruptible(&info->status_event_wait_q);
1058 wake_up_interruptible(&info->event_wait_q);
1059
3498d13b 1060 if (tty && tty_port_cts_enabled(&info->port)) {
eeb46134 1061 if (tty->hw_stopped) {
1da177e4
LT		 1062 if (info->serial_signals & SerialSignal_CTS) {
1063 if (debug_level >= DEBUG_LEVEL_ISR)
1064 printk("CTS tx start...");
221b7b57 1065 tty->hw_stopped = 0;
eeb46134 1066 tx_start(info, tty);
1da177e4
LT		 1067 info->pending_bh |= BH_TRANSMIT;
1068 return;
1069 }
1070 } else {
1071 if (!(info->serial_signals & SerialSignal_CTS)) {
1072 if (debug_level >= DEBUG_LEVEL_ISR)
1073 printk("CTS tx stop...");
221b7b57 1074 tty->hw_stopped = 1;
1da177e4
LT		 1075 tx_stop(info);
1076 }
1077 }
1078 }
1079 info->pending_bh |= BH_STATUS;
1080}
1081
eeb46134 1082static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1083{
1084 get_signals(info);
1085 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1086 irq_disable(info, CHB, IRQ_DCD);
1087 info->icount.dcd++;
1088 if (info->serial_signals & SerialSignal_DCD) {
1089 info->input_signal_events.dcd_up++;
1090 }
1091 else
1092 info->input_signal_events.dcd_down++;
af69c7f9 1093#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1094 if (info->netcount) {
1095 if (info->serial_signals & SerialSignal_DCD)
1096 netif_carrier_on(info->netdev);
1097 else
1098 netif_carrier_off(info->netdev);
1099 }
1da177e4
LT		 1100#endif
1101 wake_up_interruptible(&info->status_event_wait_q);
1102 wake_up_interruptible(&info->event_wait_q);
1103
eeb46134 1104 if (info->port.flags & ASYNC_CHECK_CD) {
1da177e4
LT		 1105 if (debug_level >= DEBUG_LEVEL_ISR)
1106 printk("%s CD now %s...", info->device_name,
1107 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1108 if (info->serial_signals & SerialSignal_DCD)
eeb46134 1109 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1110 else {
1111 if (debug_level >= DEBUG_LEVEL_ISR)
1112 printk("doing serial hangup...");
eeb46134
AC		 1113 if (tty)
1114 tty_hangup(tty);
1da177e4
LT		 1115 }
1116 }
1117 info->pending_bh |= BH_STATUS;
1118}
1119
1120static void dsr_change(MGSLPC_INFO *info)
1121{
1122 get_signals(info);
1123 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1124 port_irq_disable(info, PVR_DSR);
1125 info->icount.dsr++;
1126 if (info->serial_signals & SerialSignal_DSR)
1127 info->input_signal_events.dsr_up++;
1128 else
1129 info->input_signal_events.dsr_down++;
1130 wake_up_interruptible(&info->status_event_wait_q);
1131 wake_up_interruptible(&info->event_wait_q);
1132 info->pending_bh |= BH_STATUS;
1133}
1134
1135static void ri_change(MGSLPC_INFO *info)
1136{
1137 get_signals(info);
1138 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1139 port_irq_disable(info, PVR_RI);
1140 info->icount.rng++;
1141 if (info->serial_signals & SerialSignal_RI)
1142 info->input_signal_events.ri_up++;
1143 else
1144 info->input_signal_events.ri_down++;
1145 wake_up_interruptible(&info->status_event_wait_q);
1146 wake_up_interruptible(&info->event_wait_q);
1147 info->pending_bh |= BH_STATUS;
1148}
1149
1150/* Interrupt service routine entry point.
d12341f9 1151 *
1da177e4 1152 * Arguments:
d12341f9 1153 *
1da177e4
LT		 1154 * irq interrupt number that caused interrupt
1155 * dev_id device ID supplied during interrupt registration
1da177e4 1156 */
a6f97b29 1157static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
1da177e4 1158{
a6f97b29 1159 MGSLPC_INFO *info = dev_id;
eeb46134 1160 struct tty_struct *tty;
1da177e4
LT		 1161 unsigned short isr;
1162 unsigned char gis, pis;
1163 int count=0;
1164
d12341f9 1165 if (debug_level >= DEBUG_LEVEL_ISR)
a6f97b29 1166 printk("mgslpc_isr(%d) entry.\n", info->irq_level);
d12341f9 1167
e2d40963 1168 if (!(info->p_dev->_locked))
1da177e4
LT		 1169 return IRQ_HANDLED;
1170
eeb46134
AC		 1171 tty = tty_port_tty_get(&info->port);
1172
1da177e4
LT		 1173 spin_lock(&info->lock);
1174
1175 while ((gis = read_reg(info, CHA + GIS))) {
d12341f9 1176 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1177 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1178
1179 if ((gis & 0x70) || count > 1000) {
1180 printk("synclink_cs:hardware failed or ejected\n");
1181 break;
1182 }
1183 count++;
1184
ecda040f 1185 if (gis & (BIT1 | BIT0)) {
1da177e4
LT		 1186 isr = read_reg16(info, CHB + ISR);
1187 if (isr & IRQ_DCD)
eeb46134 1188 dcd_change(info, tty);
1da177e4 1189 if (isr & IRQ_CTS)
eeb46134 1190 cts_change(info, tty);
1da177e4 1191 }
ecda040f 1192 if (gis & (BIT3 | BIT2))
1da177e4
LT		 1193 {
1194 isr = read_reg16(info, CHA + ISR);
1195 if (isr & IRQ_TIMER) {
0fab6de0 1196 info->irq_occurred = true;
1da177e4
LT		 1197 irq_disable(info, CHA, IRQ_TIMER);
1198 }
1199
d12341f9 1200 /* receive IRQs */
1da177e4
LT		 1201 if (isr & IRQ_EXITHUNT) {
1202 info->icount.exithunt++;
1203 wake_up_interruptible(&info->event_wait_q);
1204 }
1205 if (isr & IRQ_BREAK_ON) {
1206 info->icount.brk++;
eeb46134
AC		 1207 if (info->port.flags & ASYNC_SAK)
1208 do_SAK(tty);
1da177e4
LT		 1209 }
1210 if (isr & IRQ_RXTIME) {
1211 issue_command(info, CHA, CMD_RXFIFO_READ);
1212 }
ecda040f 1213 if (isr & (IRQ_RXEOM | IRQ_RXFIFO)) {
1da177e4 1214 if (info->params.mode == MGSL_MODE_HDLC)
d12341f9 1215 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1da177e4 1216 else
2e124b4a 1217 rx_ready_async(info, isr & IRQ_RXEOM);
1da177e4
LT		 1218 }
1219
d12341f9 1220 /* transmit IRQs */
1da177e4
LT		 1221 if (isr & IRQ_UNDERRUN) {
1222 if (info->tx_aborting)
1223 info->icount.txabort++;
1224 else
1225 info->icount.txunder++;
eeb46134 1226 tx_done(info, tty);
1da177e4
LT		 1227 }
1228 else if (isr & IRQ_ALLSENT) {
1229 info->icount.txok++;
eeb46134 1230 tx_done(info, tty);
1da177e4
LT		 1231 }
1232 else if (isr & IRQ_TXFIFO)
eeb46134 1233 tx_ready(info, tty);
1da177e4
LT		 1234 }
1235 if (gis & BIT7) {
1236 pis = read_reg(info, CHA + PIS);
1237 if (pis & BIT1)
1238 dsr_change(info);
1239 if (pis & BIT2)
1240 ri_change(info);
1241 }
1242 }
d12341f9
JG		 1243
1244 /* Request bottom half processing if there's something
1da177e4
LT		 1245 * for it to do and the bh is not already running
1246 */
1247
1248 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
3d553993 1249 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1250 printk("%s(%d):%s queueing bh task.\n",
1251 __FILE__,__LINE__,info->device_name);
1252 schedule_work(&info->task);
0fab6de0 1253 info->bh_requested = true;
1da177e4
LT		 1254 }
1255
1256 spin_unlock(&info->lock);
eeb46134 1257 tty_kref_put(tty);
d12341f9
JG		 1258
1259 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4 1260 printk("%s(%d):mgslpc_isr(%d)exit.\n",
a6f97b29 1261 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 1262
1263 return IRQ_HANDLED;
1264}
1265
1266/* Initialize and start device.
1267 */
eeb46134 1268static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1269{
1270 int retval = 0;
d12341f9 1271
1da177e4 1272 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 1273 printk("%s(%d):startup(%s)\n", __FILE__, __LINE__, info->device_name);
d12341f9 1274
eeb46134 1275 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4 1276 return 0;
d12341f9 1277
1da177e4
LT		 1278 if (!info->tx_buf) {
1279 /* allocate a page of memory for a transmit buffer */
1280 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1281 if (!info->tx_buf) {
1282 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
3d553993 1283 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1284 return -ENOMEM;
1285 }
1286 }
1287
1288 info->pending_bh = 0;
d12341f9 1289
a7482a2e
PF		 1290 memset(&info->icount, 0, sizeof(info->icount));
1291
40565f19 1292 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
1da177e4
LT		 1293
1294 /* Allocate and claim adapter resources */
1295 retval = claim_resources(info);
d12341f9 1296
25985edc 1297 /* perform existence check and diagnostics */
3d553993 1298 if (!retval)
1da177e4 1299 retval = adapter_test(info);
d12341f9 1300
3d553993
AK		 1301 if (retval) {
1302 if (capable(CAP_SYS_ADMIN) && tty)
eeb46134 1303 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1304 release_resources(info);
3d553993
AK		 1305 return retval;
1306 }
1da177e4
LT		 1307
1308 /* program hardware for current parameters */
eeb46134 1309 mgslpc_change_params(info, tty);
d12341f9 1310
eeb46134
AC		 1311 if (tty)
1312 clear_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1313
eeb46134 1314 info->port.flags |= ASYNC_INITIALIZED;
d12341f9 1315
1da177e4
LT		 1316 return 0;
1317}
1318
1319/* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1320 */
eeb46134 1321static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1322{
1323 unsigned long flags;
d12341f9 1324
eeb46134 1325 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1326 return;
1327
1328 if (debug_level >= DEBUG_LEVEL_INFO)
1329 printk("%s(%d):mgslpc_shutdown(%s)\n",
3d553993 1330 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1331
1332 /* clear status wait queue because status changes */
1333 /* can't happen after shutting down the hardware */
1334 wake_up_interruptible(&info->status_event_wait_q);
1335 wake_up_interruptible(&info->event_wait_q);
1336
40565f19 1337 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1338
1339 if (info->tx_buf) {
1340 free_page((unsigned long) info->tx_buf);
1341 info->tx_buf = NULL;
1342 }
1343
3d553993 1344 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1345
1346 rx_stop(info);
1347 tx_stop(info);
1348
1349 /* TODO:disable interrupts instead of reset to preserve signal states */
1350 reset_device(info);
d12341f9 1351
9db276f8 1352 if (!tty || C_HUPCL(tty)) {
9fe8074b 1353 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 1354 set_signals(info);
1355 }
d12341f9 1356
3d553993 1357 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 1358
d12341f9
JG		 1359 release_resources(info);
1360
eeb46134
AC		 1361 if (tty)
1362 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1363
eeb46134 1364 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 1365}
1366
eeb46134 1367static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1368{
1369 unsigned long flags;
1370
3d553993 1371 spin_lock_irqsave(&info->lock, flags);
d12341f9 1372
1da177e4
LT		 1373 rx_stop(info);
1374 tx_stop(info);
1375 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1376
1da177e4
LT		 1377 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1378 hdlc_mode(info);
1379 else
1380 async_mode(info);
d12341f9 1381
1da177e4 1382 set_signals(info);
d12341f9 1383
1da177e4
LT		 1384 info->dcd_chkcount = 0;
1385 info->cts_chkcount = 0;
1386 info->ri_chkcount = 0;
1387 info->dsr_chkcount = 0;
1388
1389 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1390 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1391 get_signals(info);
d12341f9 1392
9db276f8 1393 if (info->netcount || (tty && C_CREAD(tty)))
1da177e4 1394 rx_start(info);
d12341f9 1395
3d553993 1396 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1397}
1398
1399/* Reconfigure adapter based on new parameters
1400 */
eeb46134 1401static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1402{
1403 unsigned cflag;
1404 int bits_per_char;
1405
373f5aed 1406 if (!tty)
1da177e4 1407 return;
d12341f9 1408
1da177e4
LT		 1409 if (debug_level >= DEBUG_LEVEL_INFO)
1410 printk("%s(%d):mgslpc_change_params(%s)\n",
3d553993 1411 __FILE__, __LINE__, info->device_name);
d12341f9 1412
373f5aed 1413 cflag = tty->termios.c_cflag;
1da177e4 1414
9fe8074b
JP		 1415 /* if B0 rate (hangup) specified then negate RTS and DTR */
1416 /* otherwise assert RTS and DTR */
3d553993 1417 if (cflag & CBAUD)
9fe8074b 1418 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4 1419 else
9fe8074b 1420 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
d12341f9 1421
1da177e4 1422 /* byte size and parity */
d12341f9 1423
1da177e4
LT		 1424 switch (cflag & CSIZE) {
1425 case CS5: info->params.data_bits = 5; break;
1426 case CS6: info->params.data_bits = 6; break;
1427 case CS7: info->params.data_bits = 7; break;
1428 case CS8: info->params.data_bits = 8; break;
1429 default: info->params.data_bits = 7; break;
1430 }
d12341f9 1431
1da177e4
LT		 1432 if (cflag & CSTOPB)
1433 info->params.stop_bits = 2;
1434 else
1435 info->params.stop_bits = 1;
1436
1437 info->params.parity = ASYNC_PARITY_NONE;
1438 if (cflag & PARENB) {
1439 if (cflag & PARODD)
1440 info->params.parity = ASYNC_PARITY_ODD;
1441 else
1442 info->params.parity = ASYNC_PARITY_EVEN;
1443#ifdef CMSPAR
1444 if (cflag & CMSPAR)
1445 info->params.parity = ASYNC_PARITY_SPACE;
1446#endif
1447 }
1448
1449 /* calculate number of jiffies to transmit a full
1450 * FIFO (32 bytes) at specified data rate
1451 */
d12341f9 1452 bits_per_char = info->params.data_bits +
1da177e4
LT		 1453 info->params.stop_bits + 1;
1454
1455 /* if port data rate is set to 460800 or less then
1456 * allow tty settings to override, otherwise keep the
1457 * current data rate.
1458 */
1459 if (info->params.data_rate <= 460800) {
eeb46134 1460 info->params.data_rate = tty_get_baud_rate(tty);
1da177e4 1461 }
d12341f9 1462
3d553993 1463 if (info->params.data_rate) {
d12341f9 1464 info->timeout = (32*HZ*bits_per_char) /
1da177e4
LT		 1465 info->params.data_rate;
1466 }
1467 info->timeout += HZ/50; /* Add .02 seconds of slop */
1468
1469 if (cflag & CRTSCTS)
eeb46134 1470 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 1471 else
eeb46134 1472 info->port.flags &= ~ASYNC_CTS_FLOW;
d12341f9 1473
1da177e4 1474 if (cflag & CLOCAL)
eeb46134 1475 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 1476 else
eeb46134 1477 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 1478
1479 /* process tty input control flags */
d12341f9 1480
1da177e4 1481 info->read_status_mask = 0;
eeb46134 1482 if (I_INPCK(tty))
1da177e4 1483 info->read_status_mask |= BIT7 | BIT6;
eeb46134 1484 if (I_IGNPAR(tty))
1da177e4
LT		 1485 info->ignore_status_mask |= BIT7 | BIT6;
1486
eeb46134 1487 mgslpc_program_hw(info, tty);
1da177e4
LT		 1488}
1489
1490/* Add a character to the transmit buffer
1491 */
d7e752e2 1492static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4
LT		 1493{
1494 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1495 unsigned long flags;
1496
1497 if (debug_level >= DEBUG_LEVEL_INFO) {
3d553993
AK		 1498 printk("%s(%d):mgslpc_put_char(%d) on %s\n",
1499 __FILE__, __LINE__, ch, info->device_name);
1da177e4
LT		 1500 }
1501
1502 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
d7e752e2 1503 return 0;
1da177e4 1504
326f28e9 1505 if (!info->tx_buf)
d7e752e2 1506 return 0;
1da177e4 1507
3d553993 1508 spin_lock_irqsave(&info->lock, flags);
d12341f9 1509
1da177e4
LT		 1510 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1511 if (info->tx_count < TXBUFSIZE - 1) {
1512 info->tx_buf[info->tx_put++] = ch;
1513 info->tx_put &= TXBUFSIZE-1;
1514 info->tx_count++;
1515 }
1516 }
d12341f9 1517
3d553993 1518 spin_unlock_irqrestore(&info->lock, flags);
d7e752e2 1519 return 1;
1da177e4
LT		 1520}
1521
1522/* Enable transmitter so remaining characters in the
1523 * transmit buffer are sent.
1524 */
1525static void mgslpc_flush_chars(struct tty_struct *tty)
1526{
1527 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1528 unsigned long flags;
d12341f9 1529
1da177e4 1530 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1531 printk("%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1532 __FILE__, __LINE__, info->device_name, info->tx_count);
d12341f9 1533
1da177e4
LT		 1534 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1535 return;
1536
1537 if (info->tx_count <= 0 || tty->stopped ||
1538 tty->hw_stopped || !info->tx_buf)
1539 return;
1540
1541 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1542 printk("%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1543 __FILE__, __LINE__, info->device_name);
1da177e4 1544
3d553993 1545 spin_lock_irqsave(&info->lock, flags);
1da177e4 1546 if (!info->tx_active)
3d553993
AK		 1547 tx_start(info, tty);
1548 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1549}
1550
1551/* Send a block of data
d12341f9 1552 *
1da177e4 1553 * Arguments:
d12341f9 1554 *
1da177e4
LT		 1555 * tty pointer to tty information structure
1556 * buf pointer to buffer containing send data
1557 * count size of send data in bytes
d12341f9 1558 *
1da177e4
LT		 1559 * Returns: number of characters written
1560 */
1561static int mgslpc_write(struct tty_struct * tty,
1562 const unsigned char *buf, int count)
1563{
1564 int c, ret = 0;
1565 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1566 unsigned long flags;
d12341f9 1567
1da177e4 1568 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1569 printk("%s(%d):mgslpc_write(%s) count=%d\n",
1570 __FILE__, __LINE__, info->device_name, count);
d12341f9 1571
1da177e4 1572 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
326f28e9 1573 !info->tx_buf)
1da177e4
LT		 1574 goto cleanup;
1575
1576 if (info->params.mode == MGSL_MODE_HDLC) {
1577 if (count > TXBUFSIZE) {
1578 ret = -EIO;
1579 goto cleanup;
1580 }
1581 if (info->tx_active)
1582 goto cleanup;
1583 else if (info->tx_count)
1584 goto start;
1585 }
1586
1587 for (;;) {
1588 c = min(count,
1589 min(TXBUFSIZE - info->tx_count - 1,
1590 TXBUFSIZE - info->tx_put));
1591 if (c <= 0)
1592 break;
d12341f9 1593
1da177e4
LT		 1594 memcpy(info->tx_buf + info->tx_put, buf, c);
1595
3d553993 1596 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1597 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1598 info->tx_count += c;
3d553993 1599 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1600
1601 buf += c;
1602 count -= c;
1603 ret += c;
1604 }
1605start:
3d553993
AK		 1606 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1607 spin_lock_irqsave(&info->lock, flags);
1da177e4 1608 if (!info->tx_active)
3d553993
AK		 1609 tx_start(info, tty);
1610 spin_unlock_irqrestore(&info->lock, flags);
1611 }
d12341f9 1612cleanup:
1da177e4 1613 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 1614 printk("%s(%d):mgslpc_write(%s) returning=%d\n",
1615 __FILE__, __LINE__, info->device_name, ret);
1da177e4
LT		 1616 return ret;
1617}
1618
1619/* Return the count of free bytes in transmit buffer
1620 */
1621static int mgslpc_write_room(struct tty_struct *tty)
1622{
1623 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1624 int ret;
d12341f9 1625
1da177e4
LT		 1626 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1627 return 0;
1628
1629 if (info->params.mode == MGSL_MODE_HDLC) {
1630 /* HDLC (frame oriented) mode */
1631 if (info->tx_active)
1632 return 0;
1633 else
1634 return HDLC_MAX_FRAME_SIZE;
1635 } else {
1636 ret = TXBUFSIZE - info->tx_count - 1;
1637 if (ret < 0)
1638 ret = 0;
1639 }
d12341f9 1640
1da177e4
LT		 1641 if (debug_level >= DEBUG_LEVEL_INFO)
1642 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
3d553993 1643 __FILE__, __LINE__, info->device_name, ret);
1da177e4
LT		 1644 return ret;
1645}
1646
1647/* Return the count of bytes in transmit buffer
1648 */
1649static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1650{
1651 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1652 int rc;
d12341f9 1653
1da177e4
LT		 1654 if (debug_level >= DEBUG_LEVEL_INFO)
1655 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
3d553993 1656 __FILE__, __LINE__, info->device_name);
d12341f9 1657
1da177e4
LT		 1658 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1659 return 0;
d12341f9 1660
1da177e4
LT		 1661 if (info->params.mode == MGSL_MODE_HDLC)
1662 rc = info->tx_active ? info->max_frame_size : 0;
1663 else
1664 rc = info->tx_count;
1665
1666 if (debug_level >= DEBUG_LEVEL_INFO)
1667 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
3d553993 1668 __FILE__, __LINE__, info->device_name, rc);
d12341f9 1669
1da177e4
LT		 1670 return rc;
1671}
1672
1673/* Discard all data in the send buffer
1674 */
1675static void mgslpc_flush_buffer(struct tty_struct *tty)
1676{
1677 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1678 unsigned long flags;
d12341f9 1679
1da177e4
LT		 1680 if (debug_level >= DEBUG_LEVEL_INFO)
1681 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
3d553993 1682 __FILE__, __LINE__, info->device_name);
d12341f9 1683
1da177e4
LT		 1684 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1685 return;
d12341f9 1686
3d553993 1687 spin_lock_irqsave(&info->lock, flags);
1da177e4 1688 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1689 del_timer(&info->tx_timer);
3d553993 1690 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1691
1692 wake_up_interruptible(&tty->write_wait);
1693 tty_wakeup(tty);
1694}
1695
1696/* Send a high-priority XON/XOFF character
1697 */
1698static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1699{
1700 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1701 unsigned long flags;
1702
1703 if (debug_level >= DEBUG_LEVEL_INFO)
1704 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
3d553993 1705 __FILE__, __LINE__, info->device_name, ch);
d12341f9 1706
1da177e4
LT		 1707 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1708 return;
1709
1710 info->x_char = ch;
1711 if (ch) {
3d553993 1712 spin_lock_irqsave(&info->lock, flags);
1da177e4 1713 if (!info->tx_enabled)
3d553993
AK		 1714 tx_start(info, tty);
1715 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1716 }
1717}
1718
1719/* Signal remote device to throttle send data (our receive data)
1720 */
1721static void mgslpc_throttle(struct tty_struct * tty)
1722{
1723 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1724 unsigned long flags;
d12341f9 1725
1da177e4
LT		 1726 if (debug_level >= DEBUG_LEVEL_INFO)
1727 printk("%s(%d):mgslpc_throttle(%s) entry\n",
3d553993 1728 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1729
1730 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1731 return;
d12341f9 1732
1da177e4
LT		 1733 if (I_IXOFF(tty))
1734 mgslpc_send_xchar(tty, STOP_CHAR(tty));
d12341f9 1735
9db276f8 1736 if (C_CRTSCTS(tty)) {
3d553993 1737 spin_lock_irqsave(&info->lock, flags);
1da177e4 1738 info->serial_signals &= ~SerialSignal_RTS;
3d553993
AK		 1739 set_signals(info);
1740 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1741 }
1742}
1743
1744/* Signal remote device to stop throttling send data (our receive data)
1745 */
1746static void mgslpc_unthrottle(struct tty_struct * tty)
1747{
1748 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1749 unsigned long flags;
d12341f9 1750
1da177e4
LT		 1751 if (debug_level >= DEBUG_LEVEL_INFO)
1752 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
3d553993 1753 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1754
1755 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1756 return;
d12341f9 1757
1da177e4
LT		 1758 if (I_IXOFF(tty)) {
1759 if (info->x_char)
1760 info->x_char = 0;
1761 else
1762 mgslpc_send_xchar(tty, START_CHAR(tty));
1763 }
d12341f9 1764
9db276f8 1765 if (C_CRTSCTS(tty)) {
3d553993 1766 spin_lock_irqsave(&info->lock, flags);
1da177e4 1767 info->serial_signals |= SerialSignal_RTS;
3d553993
AK		 1768 set_signals(info);
1769 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1770 }
1771}
1772
1773/* get the current serial statistics
1774 */
1775static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1776{
1777 int err;
1778 if (debug_level >= DEBUG_LEVEL_INFO)
1779 printk("get_params(%s)\n", info->device_name);
a7482a2e
PF		 1780 if (!user_icount) {
1781 memset(&info->icount, 0, sizeof(info->icount));
1782 } else {
1783 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
1784 if (err)
1785 return -EFAULT;
1786 }
1da177e4
LT		 1787 return 0;
1788}
1789
1790/* get the current serial parameters
1791 */
1792static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1793{
1794 int err;
1795 if (debug_level >= DEBUG_LEVEL_INFO)
1796 printk("get_params(%s)\n", info->device_name);
1797 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1798 if (err)
1799 return -EFAULT;
1800 return 0;
1801}
1802
1803/* set the serial parameters
d12341f9 1804 *
1da177e4 1805 * Arguments:
d12341f9 1806 *
3d553993
AK		 1807 * info pointer to device instance data
1808 * new_params user buffer containing new serial params
1da177e4
LT		 1809 *
1810 * Returns: 0 if success, otherwise error code
1811 */
eeb46134 1812static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
1da177e4 1813{
3d553993 1814 unsigned long flags;
1da177e4
LT		 1815 MGSL_PARAMS tmp_params;
1816 int err;
d12341f9 1817
1da177e4
LT		 1818 if (debug_level >= DEBUG_LEVEL_INFO)
1819 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
3d553993 1820 info->device_name);
1da177e4
LT		 1821 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1822 if (err) {
3d553993
AK		 1823 if (debug_level >= DEBUG_LEVEL_INFO)
1824 printk("%s(%d):set_params(%s) user buffer copy failed\n",
1825 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 1826 return -EFAULT;
1827 }
d12341f9 1828
3d553993 1829 spin_lock_irqsave(&info->lock, flags);
1da177e4 1830 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3d553993 1831 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 1832
3d553993 1833 mgslpc_change_params(info, tty);
d12341f9 1834
1da177e4
LT		 1835 return 0;
1836}
1837
1838static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
1839{
1840 int err;
1841 if (debug_level >= DEBUG_LEVEL_INFO)
1842 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
1843 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
1844 if (err)
1845 return -EFAULT;
1846 return 0;
1847}
1848
1849static int set_txidle(MGSLPC_INFO * info, int idle_mode)
1850{
3d553993 1851 unsigned long flags;
1da177e4
LT		 1852 if (debug_level >= DEBUG_LEVEL_INFO)
1853 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
3d553993 1854 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1855 info->idle_mode = idle_mode;
1856 tx_set_idle(info);
3d553993 1857 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1858 return 0;
1859}
1860
1861static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
1862{
1863 int err;
1864 if (debug_level >= DEBUG_LEVEL_INFO)
1865 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
1866 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
1867 if (err)
1868 return -EFAULT;
1869 return 0;
1870}
1871
1872static int set_interface(MGSLPC_INFO * info, int if_mode)
1873{
3d553993 1874 unsigned long flags;
1da177e4
LT		 1875 unsigned char val;
1876 if (debug_level >= DEBUG_LEVEL_INFO)
1877 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
3d553993 1878 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1879 info->if_mode = if_mode;
1880
1881 val = read_reg(info, PVR) & 0x0f;
1882 switch (info->if_mode)
1883 {
1884 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
1885 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
1886 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
1887 }
1888 write_reg(info, PVR, val);
1889
3d553993 1890 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1891 return 0;
1892}
1893
eeb46134 1894static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
1da177e4 1895{
3d553993 1896 unsigned long flags;
d12341f9 1897
1da177e4
LT		 1898 if (debug_level >= DEBUG_LEVEL_INFO)
1899 printk("set_txenable(%s,%d)\n", info->device_name, enable);
d12341f9 1900
3d553993 1901 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1902 if (enable) {
1903 if (!info->tx_enabled)
eeb46134 1904 tx_start(info, tty);
1da177e4
LT		 1905 } else {
1906 if (info->tx_enabled)
1907 tx_stop(info);
1908 }
3d553993 1909 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1910 return 0;
1911}
1912
1913static int tx_abort(MGSLPC_INFO * info)
1914{
3d553993 1915 unsigned long flags;
d12341f9 1916
1da177e4
LT		 1917 if (debug_level >= DEBUG_LEVEL_INFO)
1918 printk("tx_abort(%s)\n", info->device_name);
d12341f9 1919
3d553993 1920 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1921 if (info->tx_active && info->tx_count &&
1922 info->params.mode == MGSL_MODE_HDLC) {
1923 /* clear data count so FIFO is not filled on next IRQ.
1924 * This results in underrun and abort transmission.
1925 */
1926 info->tx_count = info->tx_put = info->tx_get = 0;
0fab6de0 1927 info->tx_aborting = true;
1da177e4 1928 }
3d553993 1929 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1930 return 0;
1931}
1932
1933static int set_rxenable(MGSLPC_INFO * info, int enable)
1934{
3d553993 1935 unsigned long flags;
d12341f9 1936
1da177e4
LT		 1937 if (debug_level >= DEBUG_LEVEL_INFO)
1938 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
d12341f9 1939
3d553993 1940 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1941 if (enable) {
1942 if (!info->rx_enabled)
1943 rx_start(info);
1944 } else {
1945 if (info->rx_enabled)
1946 rx_stop(info);
1947 }
3d553993 1948 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1949 return 0;
1950}
1951
1952/* wait for specified event to occur
d12341f9 1953 *
3d553993
AK		 1954 * Arguments: info pointer to device instance data
1955 * mask pointer to bitmask of events to wait for
1956 * Return Value: 0 if successful and bit mask updated with
1da177e4 1957 * of events triggerred,
3d553993 1958 * otherwise error code
1da177e4
LT		 1959 */
1960static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
1961{
3d553993 1962 unsigned long flags;
1da177e4
LT		 1963 int s;
1964 int rc=0;
1965 struct mgsl_icount cprev, cnow;
1966 int events;
1967 int mask;
1968 struct _input_signal_events oldsigs, newsigs;
1969 DECLARE_WAITQUEUE(wait, current);
1970
1971 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
1972 if (rc)
1973 return -EFAULT;
d12341f9 1974
1da177e4
LT		 1975 if (debug_level >= DEBUG_LEVEL_INFO)
1976 printk("wait_events(%s,%d)\n", info->device_name, mask);
1977
3d553993 1978 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 1979
1980 /* return immediately if state matches requested events */
1981 get_signals(info);
1982 s = info->serial_signals;
1983 events = mask &
1984 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3d553993 1985 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
1da177e4
LT		 1986 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
1987 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
1988 if (events) {
3d553993 1989 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 1990 goto exit;
1991 }
1992
1993 /* save current irq counts */
1994 cprev = info->icount;
1995 oldsigs = info->input_signal_events;
d12341f9 1996
1da177e4
LT		 1997 if ((info->params.mode == MGSL_MODE_HDLC) &&
1998 (mask & MgslEvent_ExitHuntMode))
1999 irq_enable(info, CHA, IRQ_EXITHUNT);
d12341f9 2000
1da177e4
LT		 2001 set_current_state(TASK_INTERRUPTIBLE);
2002 add_wait_queue(&info->event_wait_q, &wait);
d12341f9 2003
3d553993 2004 spin_unlock_irqrestore(&info->lock, flags);
d12341f9
JG		 2005
2006
1da177e4
LT		 2007 for(;;) {
2008 schedule();
2009 if (signal_pending(current)) {
2010 rc = -ERESTARTSYS;
2011 break;
2012 }
d12341f9 2013
1da177e4 2014 /* get current irq counts */
3d553993 2015 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2016 cnow = info->icount;
2017 newsigs = info->input_signal_events;
2018 set_current_state(TASK_INTERRUPTIBLE);
3d553993 2019 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2020
2021 /* if no change, wait aborted for some reason */
2022 if (newsigs.dsr_up == oldsigs.dsr_up &&
2023 newsigs.dsr_down == oldsigs.dsr_down &&
2024 newsigs.dcd_up == oldsigs.dcd_up &&
2025 newsigs.dcd_down == oldsigs.dcd_down &&
2026 newsigs.cts_up == oldsigs.cts_up &&
2027 newsigs.cts_down == oldsigs.cts_down &&
2028 newsigs.ri_up == oldsigs.ri_up &&
2029 newsigs.ri_down == oldsigs.ri_down &&
2030 cnow.exithunt == cprev.exithunt &&
2031 cnow.rxidle == cprev.rxidle) {
2032 rc = -EIO;
2033 break;
2034 }
2035
2036 events = mask &
2037 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2038 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2039 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2040 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2041 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2042 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2043 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2044 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2045 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2046 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2047 if (events)
2048 break;
d12341f9 2049
1da177e4
LT		 2050 cprev = cnow;
2051 oldsigs = newsigs;
2052 }
d12341f9 2053
1da177e4
LT		 2054 remove_wait_queue(&info->event_wait_q, &wait);
2055 set_current_state(TASK_RUNNING);
2056
2057 if (mask & MgslEvent_ExitHuntMode) {
3d553993 2058 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2059 if (!waitqueue_active(&info->event_wait_q))
2060 irq_disable(info, CHA, IRQ_EXITHUNT);
3d553993 2061 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2062 }
2063exit:
2064 if (rc == 0)
2065 PUT_USER(rc, events, mask_ptr);
2066 return rc;
2067}
2068
2069static int modem_input_wait(MGSLPC_INFO *info,int arg)
2070{
3d553993 2071 unsigned long flags;
1da177e4
LT		 2072 int rc;
2073 struct mgsl_icount cprev, cnow;
2074 DECLARE_WAITQUEUE(wait, current);
2075
2076 /* save current irq counts */
3d553993 2077 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2078 cprev = info->icount;
2079 add_wait_queue(&info->status_event_wait_q, &wait);
2080 set_current_state(TASK_INTERRUPTIBLE);
3d553993 2081 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2082
2083 for(;;) {
2084 schedule();
2085 if (signal_pending(current)) {
2086 rc = -ERESTARTSYS;
2087 break;
2088 }
2089
2090 /* get new irq counts */
3d553993 2091 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 2092 cnow = info->icount;
2093 set_current_state(TASK_INTERRUPTIBLE);
3d553993 2094 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2095
2096 /* if no change, wait aborted for some reason */
2097 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2098 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2099 rc = -EIO;
2100 break;
2101 }
2102
2103 /* check for change in caller specified modem input */
2104 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2105 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2106 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2107 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2108 rc = 0;
2109 break;
2110 }
2111
2112 cprev = cnow;
2113 }
2114 remove_wait_queue(&info->status_event_wait_q, &wait);
2115 set_current_state(TASK_RUNNING);
2116 return rc;
2117}
2118
2119/* return the state of the serial control and status signals
2120 */
60b33c13 2121static int tiocmget(struct tty_struct *tty)
1da177e4
LT		 2122{
2123 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2124 unsigned int result;
3d553993 2125 unsigned long flags;
1da177e4 2126
3d553993
AK		 2127 spin_lock_irqsave(&info->lock, flags);
2128 get_signals(info);
2129 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2130
2131 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2132 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2133 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2134 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2135 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2136 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2137
2138 if (debug_level >= DEBUG_LEVEL_INFO)
2139 printk("%s(%d):%s tiocmget() value=%08X\n",
3d553993 2140 __FILE__, __LINE__, info->device_name, result);
1da177e4
LT		 2141 return result;
2142}
2143
2144/* set modem control signals (DTR/RTS)
2145 */
20b9d177 2146static int tiocmset(struct tty_struct *tty,
1da177e4
LT		 2147 unsigned int set, unsigned int clear)
2148{
2149 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
3d553993 2150 unsigned long flags;
1da177e4
LT		 2151
2152 if (debug_level >= DEBUG_LEVEL_INFO)
2153 printk("%s(%d):%s tiocmset(%x,%x)\n",
3d553993 2154 __FILE__, __LINE__, info->device_name, set, clear);
1da177e4
LT		 2155
2156 if (set & TIOCM_RTS)
2157 info->serial_signals |= SerialSignal_RTS;
2158 if (set & TIOCM_DTR)
2159 info->serial_signals |= SerialSignal_DTR;
2160 if (clear & TIOCM_RTS)
2161 info->serial_signals &= ~SerialSignal_RTS;
2162 if (clear & TIOCM_DTR)
2163 info->serial_signals &= ~SerialSignal_DTR;
2164
3d553993
AK		 2165 spin_lock_irqsave(&info->lock, flags);
2166 set_signals(info);
2167 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2168
2169 return 0;
2170}
2171
2172/* Set or clear transmit break condition
2173 *
2174 * Arguments: tty pointer to tty instance data
2175 * break_state -1=set break condition, 0=clear
2176 */
9e98966c 2177static int mgslpc_break(struct tty_struct *tty, int break_state)
1da177e4
LT		 2178{
2179 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2180 unsigned long flags;
d12341f9 2181
1da177e4
LT		 2182 if (debug_level >= DEBUG_LEVEL_INFO)
2183 printk("%s(%d):mgslpc_break(%s,%d)\n",
3d553993 2184 __FILE__, __LINE__, info->device_name, break_state);
d12341f9 2185
1da177e4 2186 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
9e98966c 2187 return -EINVAL;
1da177e4 2188
3d553993
AK		 2189 spin_lock_irqsave(&info->lock, flags);
2190 if (break_state == -1)
1da177e4 2191 set_reg_bits(info, CHA+DAFO, BIT6);
d12341f9 2192 else
1da177e4 2193 clear_reg_bits(info, CHA+DAFO, BIT6);
3d553993 2194 spin_unlock_irqrestore(&info->lock, flags);
9e98966c 2195 return 0;
1da177e4
LT		 2196}
2197
0587102c
AC		 2198static int mgslpc_get_icount(struct tty_struct *tty,
2199 struct serial_icounter_struct *icount)
2200{
2201 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2202 struct mgsl_icount cnow; /* kernel counter temps */
2203 unsigned long flags;
2204
3d553993 2205 spin_lock_irqsave(&info->lock, flags);
0587102c 2206 cnow = info->icount;
3d553993 2207 spin_unlock_irqrestore(&info->lock, flags);
0587102c
AC		 2208
2209 icount->cts = cnow.cts;
2210 icount->dsr = cnow.dsr;
2211 icount->rng = cnow.rng;
2212 icount->dcd = cnow.dcd;
2213 icount->rx = cnow.rx;
2214 icount->tx = cnow.tx;
2215 icount->frame = cnow.frame;
2216 icount->overrun = cnow.overrun;
2217 icount->parity = cnow.parity;
2218 icount->brk = cnow.brk;
2219 icount->buf_overrun = cnow.buf_overrun;
2220
2221 return 0;
2222}
2223
1da177e4 2224/* Service an IOCTL request
d12341f9 2225 *
1da177e4 2226 * Arguments:
d12341f9 2227 *
3d553993
AK		 2228 * tty pointer to tty instance data
2229 * cmd IOCTL command code
2230 * arg command argument/context
d12341f9 2231 *
1da177e4
LT		 2232 * Return Value: 0 if success, otherwise error code
2233 */
751b3840 2234static int mgslpc_ioctl(struct tty_struct *tty,
1da177e4
LT		 2235 unsigned int cmd, unsigned long arg)
2236{
2237 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2238 void __user *argp = (void __user *)arg;
d12341f9 2239
1da177e4 2240 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 2241 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__, __LINE__,
2242 info->device_name, cmd);
d12341f9 2243
1da177e4
LT		 2244 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2245 return -ENODEV;
2246
2247 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2248 (cmd != TIOCMIWAIT)) {
18900ca6 2249 if (tty_io_error(tty))
1da177e4
LT		 2250 return -EIO;
2251 }
2252
1da177e4
LT		 2253 switch (cmd) {
2254 case MGSL_IOCGPARAMS:
2255 return get_params(info, argp);
2256 case MGSL_IOCSPARAMS:
eeb46134 2257 return set_params(info, argp, tty);
1da177e4
LT		 2258 case MGSL_IOCGTXIDLE:
2259 return get_txidle(info, argp);
2260 case MGSL_IOCSTXIDLE:
2261 return set_txidle(info, (int)arg);
2262 case MGSL_IOCGIF:
2263 return get_interface(info, argp);
2264 case MGSL_IOCSIF:
2265 return set_interface(info,(int)arg);
2266 case MGSL_IOCTXENABLE:
eeb46134 2267 return set_txenable(info,(int)arg, tty);
1da177e4
LT		 2268 case MGSL_IOCRXENABLE:
2269 return set_rxenable(info,(int)arg);
2270 case MGSL_IOCTXABORT:
2271 return tx_abort(info);
2272 case MGSL_IOCGSTATS:
2273 return get_stats(info, argp);
2274 case MGSL_IOCWAITEVENT:
2275 return wait_events(info, argp);
2276 case TIOCMIWAIT:
2277 return modem_input_wait(info,(int)arg);
1da177e4
LT		 2278 default:
2279 return -ENOIOCTLCMD;
2280 }
2281 return 0;
2282}
2283
2284/* Set new termios settings
d12341f9 2285 *
1da177e4 2286 * Arguments:
d12341f9 2287 *
3d553993
AK		 2288 * tty pointer to tty structure
2289 * termios pointer to buffer to hold returned old termios
1da177e4 2290 */
606d099c 2291static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 2292{
2293 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2294 unsigned long flags;
d12341f9 2295
1da177e4 2296 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993
AK		 2297 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__, __LINE__,
2298 tty->driver->name);
d12341f9 2299
1da177e4 2300 /* just return if nothing has changed */
373f5aed
AC		 2301 if ((tty->termios.c_cflag == old_termios->c_cflag)
2302 && (RELEVANT_IFLAG(tty->termios.c_iflag)
1da177e4
LT		 2303 == RELEVANT_IFLAG(old_termios->c_iflag)))
2304 return;
2305
eeb46134 2306 mgslpc_change_params(info, tty);
1da177e4
LT		 2307
2308 /* Handle transition to B0 status */
9db276f8 2309 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
9fe8074b 2310 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3d553993
AK		 2311 spin_lock_irqsave(&info->lock, flags);
2312 set_signals(info);
2313 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 2314 }
d12341f9 2315
1da177e4 2316 /* Handle transition away from B0 status */
9db276f8 2317 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1da177e4 2318 info->serial_signals |= SerialSignal_DTR;
9db276f8 2319 if (!C_CRTSCTS(tty) || !test_bit(TTY_THROTTLED, &tty->flags))
1da177e4 2320 info->serial_signals |= SerialSignal_RTS;
3d553993
AK		 2321 spin_lock_irqsave(&info->lock, flags);
2322 set_signals(info);
2323 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 2324 }
d12341f9 2325
1da177e4 2326 /* Handle turning off CRTSCTS */
9db276f8 2327 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
1da177e4
LT		 2328 tty->hw_stopped = 0;
2329 tx_release(tty);
2330 }
2331}
2332
2333static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2334{
2335 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2336 struct tty_port *port = &info->port;
1da177e4
LT		 2337
2338 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2339 return;
d12341f9 2340
1da177e4
LT		 2341 if (debug_level >= DEBUG_LEVEL_INFO)
2342 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
3d553993 2343 __FILE__, __LINE__, info->device_name, port->count);
1da177e4 2344
eeb46134 2345 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 2346 goto cleanup;
d12341f9 2347
3d553993
AK		 2348 if (port->flags & ASYNC_INITIALIZED)
2349 mgslpc_wait_until_sent(tty, info->timeout);
1da177e4 2350
978e595f 2351 mgslpc_flush_buffer(tty);
1da177e4 2352
978e595f 2353 tty_ldisc_flush(tty);
eeb46134
AC		 2354 shutdown(info, tty);
2355
2356 tty_port_close_end(port, tty);
2357 tty_port_tty_set(port, NULL);
d12341f9 2358cleanup:
1da177e4 2359 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 2360 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__, __LINE__,
eeb46134 2361 tty->driver->name, port->count);
1da177e4
LT		 2362}
2363
2364/* Wait until the transmitter is empty.
2365 */
2366static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2367{
2368 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2369 unsigned long orig_jiffies, char_time;
2370
3d553993 2371 if (!info)
1da177e4
LT		 2372 return;
2373
2374 if (debug_level >= DEBUG_LEVEL_INFO)
2375 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
3d553993 2376 __FILE__, __LINE__, info->device_name);
d12341f9 2377
1da177e4
LT		 2378 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2379 return;
2380
eeb46134 2381 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4 2382 goto exit;
d12341f9 2383
1da177e4 2384 orig_jiffies = jiffies;
d12341f9 2385
1da177e4
LT		 2386 /* Set check interval to 1/5 of estimated time to
2387 * send a character, and make it at least 1. The check
2388 * interval should also be less than the timeout.
2389 * Note: use tight timings here to satisfy the NIST-PCTS.
d12341f9
JG		 2390 */
2391
3d553993
AK		 2392 if (info->params.data_rate) {
2393 char_time = info->timeout/(32 * 5);
1da177e4
LT		 2394 if (!char_time)
2395 char_time++;
2396 } else
2397 char_time = 1;
d12341f9 2398
1da177e4
LT		 2399 if (timeout)
2400 char_time = min_t(unsigned long, char_time, timeout);
d12341f9 2401
1da177e4
LT		 2402 if (info->params.mode == MGSL_MODE_HDLC) {
2403 while (info->tx_active) {
2404 msleep_interruptible(jiffies_to_msecs(char_time));
2405 if (signal_pending(current))
2406 break;
2407 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2408 break;
2409 }
2410 } else {
2411 while ((info->tx_count || info->tx_active) &&
2412 info->tx_enabled) {
2413 msleep_interruptible(jiffies_to_msecs(char_time));
2414 if (signal_pending(current))
2415 break;
2416 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2417 break;
2418 }
2419 }
d12341f9 2420
1da177e4
LT		 2421exit:
2422 if (debug_level >= DEBUG_LEVEL_INFO)
2423 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
3d553993 2424 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 2425}
2426
2427/* Called by tty_hangup() when a hangup is signaled.
2428 * This is the same as closing all open files for the port.
2429 */
2430static void mgslpc_hangup(struct tty_struct *tty)
2431{
2432 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
d12341f9 2433
1da177e4
LT		 2434 if (debug_level >= DEBUG_LEVEL_INFO)
2435 printk("%s(%d):mgslpc_hangup(%s)\n",
3d553993 2436 __FILE__, __LINE__, info->device_name);
d12341f9 2437
1da177e4
LT		 2438 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2439 return;
2440
2441 mgslpc_flush_buffer(tty);
eeb46134
AC		 2442 shutdown(info, tty);
2443 tty_port_hangup(&info->port);
1da177e4
LT		 2444}
2445
eeb46134 2446static int carrier_raised(struct tty_port *port)
1da177e4 2447{
eeb46134
AC		 2448 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2449 unsigned long flags;
d12341f9 2450
3d553993
AK		 2451 spin_lock_irqsave(&info->lock, flags);
2452 get_signals(info);
2453 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 2454
eeb46134
AC		 2455 if (info->serial_signals & SerialSignal_DCD)
2456 return 1;
2457 return 0;
2458}
d12341f9 2459
fcc8ac18 2460static void dtr_rts(struct tty_port *port, int onoff)
eeb46134
AC		 2461{
2462 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2463 unsigned long flags;
d12341f9 2464
3d553993 2465 spin_lock_irqsave(&info->lock, flags);
fcc8ac18 2466 if (onoff)
9fe8074b 2467 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
fcc8ac18 2468 else
9fe8074b 2469 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
eeb46134 2470 set_signals(info);
3d553993 2471 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 2472}
2473
eeb46134 2474
1da177e4
LT		 2475static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2476{
2477 MGSLPC_INFO *info;
eeb46134 2478 struct tty_port *port;
3d553993
AK		 2479 int retval, line;
2480 unsigned long flags;
1da177e4 2481
d12341f9 2482 /* verify range of specified line number */
1da177e4 2483 line = tty->index;
410235fd 2484 if (line >= mgslpc_device_count) {
1da177e4 2485 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
3d553993 2486 __FILE__, __LINE__, line);
1da177e4
LT		 2487 return -ENODEV;
2488 }
2489
2490 /* find the info structure for the specified line */
2491 info = mgslpc_device_list;
2492 while(info && info->line != line)
2493 info = info->next_device;
2494 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2495 return -ENODEV;
d12341f9 2496
eeb46134 2497 port = &info->port;
1da177e4 2498 tty->driver_data = info;
eeb46134 2499 tty_port_tty_set(port, tty);
d12341f9 2500
1da177e4
LT		 2501 if (debug_level >= DEBUG_LEVEL_INFO)
2502 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
3d553993 2503 __FILE__, __LINE__, tty->driver->name, port->count);
1da177e4 2504
d6c53c0e 2505 port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 2506
2507 spin_lock_irqsave(&info->netlock, flags);
2508 if (info->netcount) {
2509 retval = -EBUSY;
2510 spin_unlock_irqrestore(&info->netlock, flags);
2511 goto cleanup;
2512 }
eeb46134
AC		 2513 spin_lock(&port->lock);
2514 port->count++;
2515 spin_unlock(&port->lock);
1da177e4
LT		 2516 spin_unlock_irqrestore(&info->netlock, flags);
2517
eeb46134 2518 if (port->count == 1) {
1da177e4 2519 /* 1st open on this device, init hardware */
eeb46134 2520 retval = startup(info, tty);
1da177e4
LT		 2521 if (retval < 0)
2522 goto cleanup;
2523 }
2524
eeb46134 2525 retval = tty_port_block_til_ready(&info->port, tty, filp);
1da177e4
LT		 2526 if (retval) {
2527 if (debug_level >= DEBUG_LEVEL_INFO)
2528 printk("%s(%d):block_til_ready(%s) returned %d\n",
3d553993 2529 __FILE__, __LINE__, info->device_name, retval);
1da177e4
LT		 2530 goto cleanup;
2531 }
2532
2533 if (debug_level >= DEBUG_LEVEL_INFO)
2534 printk("%s(%d):mgslpc_open(%s) success\n",
3d553993 2535 __FILE__, __LINE__, info->device_name);
1da177e4 2536 retval = 0;
d12341f9
JG		 2537
2538cleanup:
1da177e4
LT		 2539 return retval;
2540}
2541
2542/*
2543 * /proc fs routines....
2544 */
2545
87687144 2546static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
1da177e4
LT		 2547{
2548 char stat_buf[30];
1da177e4
LT		 2549 unsigned long flags;
2550
87687144 2551 seq_printf(m, "%s:io:%04X irq:%d",
1da177e4
LT		 2552 info->device_name, info->io_base, info->irq_level);
2553
2554 /* output current serial signal states */
3d553993
AK		 2555 spin_lock_irqsave(&info->lock, flags);
2556 get_signals(info);
2557 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 2558
1da177e4
LT		 2559 stat_buf[0] = 0;
2560 stat_buf[1] = 0;
2561 if (info->serial_signals & SerialSignal_RTS)
2562 strcat(stat_buf, "|RTS");
2563 if (info->serial_signals & SerialSignal_CTS)
2564 strcat(stat_buf, "|CTS");
2565 if (info->serial_signals & SerialSignal_DTR)
2566 strcat(stat_buf, "|DTR");
2567 if (info->serial_signals & SerialSignal_DSR)
2568 strcat(stat_buf, "|DSR");
2569 if (info->serial_signals & SerialSignal_DCD)
2570 strcat(stat_buf, "|CD");
2571 if (info->serial_signals & SerialSignal_RI)
2572 strcat(stat_buf, "|RI");
2573
2574 if (info->params.mode == MGSL_MODE_HDLC) {
87687144 2575 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 2576 info->icount.txok, info->icount.rxok);
2577 if (info->icount.txunder)
87687144 2578 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 2579 if (info->icount.txabort)
87687144 2580 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 2581 if (info->icount.rxshort)
87687144 2582 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 2583 if (info->icount.rxlong)
87687144 2584 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 2585 if (info->icount.rxover)
87687144 2586 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 2587 if (info->icount.rxcrc)
87687144 2588 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 2589 } else {
87687144 2590 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 2591 info->icount.tx, info->icount.rx);
2592 if (info->icount.frame)
87687144 2593 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 2594 if (info->icount.parity)
87687144 2595 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 2596 if (info->icount.brk)
87687144 2597 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 2598 if (info->icount.overrun)
87687144 2599 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4 2600 }
d12341f9 2601
1da177e4 2602 /* Append serial signal status to end */
87687144 2603 seq_printf(m, " %s\n", stat_buf+1);
d12341f9 2604
87687144 2605 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 2606 info->tx_active,info->bh_requested,info->bh_running,
2607 info->pending_bh);
1da177e4
LT		 2608}
2609
2610/* Called to print information about devices
2611 */
87687144 2612static int mgslpc_proc_show(struct seq_file *m, void *v)
1da177e4 2613{
1da177e4 2614 MGSLPC_INFO *info;
d12341f9 2615
87687144 2616 seq_printf(m, "synclink driver:%s\n", driver_version);
d12341f9 2617
1da177e4 2618 info = mgslpc_device_list;
3d553993 2619 while (info) {
87687144 2620 line_info(m, info);
1da177e4
LT		 2621 info = info->next_device;
2622 }
87687144
AD		 2623 return 0;
2624}
1da177e4 2625
87687144
AD		 2626static int mgslpc_proc_open(struct inode *inode, struct file *file)
2627{
2628 return single_open(file, mgslpc_proc_show, NULL);
1da177e4
LT		 2629}
2630
87687144
AD		 2631static const struct file_operations mgslpc_proc_fops = {
2632 .owner = THIS_MODULE,
2633 .open = mgslpc_proc_open,
2634 .read = seq_read,
2635 .llseek = seq_lseek,
2636 .release = single_release,
2637};
2638
cdaad343 2639static int rx_alloc_buffers(MGSLPC_INFO *info)
1da177e4
LT		 2640{
2641 /* each buffer has header and data */
2642 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2643
2644 /* calculate total allocation size for 8 buffers */
2645 info->rx_buf_total_size = info->rx_buf_size * 8;
2646
2647 /* limit total allocated memory */
2648 if (info->rx_buf_total_size > 0x10000)
2649 info->rx_buf_total_size = 0x10000;
2650
2651 /* calculate number of buffers */
2652 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2653
2654 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2655 if (info->rx_buf == NULL)
2656 return -ENOMEM;
2657
a6b68a69
PF		 2658 /* unused flag buffer to satisfy receive_buf calling interface */
2659 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
2660 if (!info->flag_buf) {
2661 kfree(info->rx_buf);
2662 info->rx_buf = NULL;
2663 return -ENOMEM;
2664 }
2665
1da177e4
LT		 2666 rx_reset_buffers(info);
2667 return 0;
2668}
2669
cdaad343 2670static void rx_free_buffers(MGSLPC_INFO *info)
1da177e4 2671{
735d5661 2672 kfree(info->rx_buf);
1da177e4 2673 info->rx_buf = NULL;
a6b68a69
PF		 2674 kfree(info->flag_buf);
2675 info->flag_buf = NULL;
1da177e4
LT		 2676}
2677
cdaad343 2678static int claim_resources(MGSLPC_INFO *info)
1da177e4 2679{
3d553993
AK		 2680 if (rx_alloc_buffers(info) < 0) {
2681 printk("Can't allocate rx buffer %s\n", info->device_name);
1da177e4
LT		 2682 release_resources(info);
2683 return -ENODEV;
d12341f9 2684 }
1da177e4
LT		 2685 return 0;
2686}
2687
cdaad343 2688static void release_resources(MGSLPC_INFO *info)
1da177e4
LT		 2689{
2690 if (debug_level >= DEBUG_LEVEL_INFO)
2691 printk("release_resources(%s)\n", info->device_name);
2692 rx_free_buffers(info);
2693}
2694
2695/* Add the specified device instance data structure to the
2696 * global linked list of devices and increment the device count.
d12341f9 2697 *
1da177e4
LT		 2698 * Arguments: info pointer to device instance data
2699 */
d34138d0 2700static int mgslpc_add_device(MGSLPC_INFO *info)
1da177e4 2701{
d34138d0
AK		 2702 MGSLPC_INFO *current_dev = NULL;
2703 struct device *tty_dev;
2704 int ret;
2705
1da177e4
LT		 2706 info->next_device = NULL;
2707 info->line = mgslpc_device_count;
2708 sprintf(info->device_name,"ttySLP%d",info->line);
d12341f9 2709
1da177e4
LT		 2710 if (info->line < MAX_DEVICE_COUNT) {
2711 if (maxframe[info->line])
2712 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 2713 }
2714
2715 mgslpc_device_count++;
d12341f9 2716
1da177e4
LT		 2717 if (!mgslpc_device_list)
2718 mgslpc_device_list = info;
d12341f9 2719 else {
d34138d0 2720 current_dev = mgslpc_device_list;
3d553993 2721 while (current_dev->next_device)
1da177e4
LT		 2722 current_dev = current_dev->next_device;
2723 current_dev->next_device = info;
2724 }
d12341f9 2725
1da177e4
LT		 2726 if (info->max_frame_size < 4096)
2727 info->max_frame_size = 4096;
2728 else if (info->max_frame_size > 65535)
2729 info->max_frame_size = 65535;
d12341f9 2730
3d553993 2731 printk("SyncLink PC Card %s:IO=%04X IRQ=%d\n",
1da177e4
LT		 2732 info->device_name, info->io_base, info->irq_level);
2733
af69c7f9 2734#if SYNCLINK_GENERIC_HDLC
d34138d0
AK		 2735 ret = hdlcdev_init(info);
2736 if (ret != 0)
2737 goto failed;
1da177e4 2738#endif
d34138d0
AK		 2739
2740 tty_dev = tty_port_register_device(&info->port, serial_driver, info->line,
a33ba827 2741 &info->p_dev->dev);
d34138d0
AK		 2742 if (IS_ERR(tty_dev)) {
2743 ret = PTR_ERR(tty_dev);
2744#if SYNCLINK_GENERIC_HDLC
2745 hdlcdev_exit(info);
2746#endif
2747 goto failed;
2748 }
2749
2750 return 0;
2751
2752failed:
2753 if (current_dev)
2754 current_dev->next_device = NULL;
2755 else
2756 mgslpc_device_list = NULL;
2757 mgslpc_device_count--;
2758 return ret;
1da177e4
LT		 2759}
2760
cdaad343 2761static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
1da177e4
LT		 2762{
2763 MGSLPC_INFO *info = mgslpc_device_list;
2764 MGSLPC_INFO *last = NULL;
2765
2766 while(info) {
2767 if (info == remove_info) {
2768 if (last)
2769 last->next_device = info->next_device;
2770 else
2771 mgslpc_device_list = info->next_device;
16a1065f 2772 tty_unregister_device(serial_driver, info->line);
af69c7f9 2773#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2774 hdlcdev_exit(info);
2775#endif
2776 release_resources(info);
191c5f10 2777 tty_port_destroy(&info->port);
1da177e4
LT		 2778 kfree(info);
2779 mgslpc_device_count--;
2780 return;
2781 }
2782 last = info;
2783 info = info->next_device;
2784 }
2785}
2786
25f8f54f 2787static const struct pcmcia_device_id mgslpc_ids[] = {
4af48c8c
DB		 2788 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
2789 PCMCIA_DEVICE_NULL
2790};
2791MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
2792
1da177e4
LT		 2793static struct pcmcia_driver mgslpc_driver = {
2794 .owner = THIS_MODULE,
2e9b981a 2795 .name = "synclink_cs",
15b99ac1 2796 .probe = mgslpc_probe,
cc3b4866 2797 .remove = mgslpc_detach,
4af48c8c 2798 .id_table = mgslpc_ids,
98e4c28b
DB		 2799 .suspend = mgslpc_suspend,
2800 .resume = mgslpc_resume,
1da177e4
LT		 2801};
2802
b68e31d0 2803static const struct tty_operations mgslpc_ops = {
1da177e4
LT		 2804 .open = mgslpc_open,
2805 .close = mgslpc_close,
2806 .write = mgslpc_write,
2807 .put_char = mgslpc_put_char,
2808 .flush_chars = mgslpc_flush_chars,
2809 .write_room = mgslpc_write_room,
2810 .chars_in_buffer = mgslpc_chars_in_buffer,
2811 .flush_buffer = mgslpc_flush_buffer,
2812 .ioctl = mgslpc_ioctl,
2813 .throttle = mgslpc_throttle,
2814 .unthrottle = mgslpc_unthrottle,
2815 .send_xchar = mgslpc_send_xchar,
2816 .break_ctl = mgslpc_break,
2817 .wait_until_sent = mgslpc_wait_until_sent,
1da177e4
LT		 2818 .set_termios = mgslpc_set_termios,
2819 .stop = tx_pause,
2820 .start = tx_release,
2821 .hangup = mgslpc_hangup,
2822 .tiocmget = tiocmget,
2823 .tiocmset = tiocmset,
dc98d965 2824 .get_icount = mgslpc_get_icount,
87687144 2825 .proc_fops = &mgslpc_proc_fops,
1da177e4
LT		 2826};
2827
1da177e4 2828static int __init synclink_cs_init(void)
1da177e4
LT		 2829{
2830 int rc;
2831
cc93441e
JS		 2832 if (break_on_load) {
2833 mgslpc_get_text_ptr();
2834 BREAKPOINT();
1da177e4
LT		 2835 }
2836
cc93441e
JS		 2837 serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT,
2838 TTY_DRIVER_REAL_RAW |
2839 TTY_DRIVER_DYNAMIC_DEV);
c3a6344a
DC		 2840 if (IS_ERR(serial_driver)) {
2841 rc = PTR_ERR(serial_driver);
cc93441e
JS		 2842 goto err;
2843 }
1da177e4 2844
cc93441e
JS		 2845 /* Initialize the tty_driver structure */
2846 serial_driver->driver_name = "synclink_cs";
2847 serial_driver->name = "ttySLP";
2848 serial_driver->major = ttymajor;
2849 serial_driver->minor_start = 64;
2850 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2851 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2852 serial_driver->init_termios = tty_std_termios;
2853 serial_driver->init_termios.c_cflag =
2854 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2855 tty_set_operations(serial_driver, &mgslpc_ops);
1da177e4 2856
cc93441e
JS		 2857 rc = tty_register_driver(serial_driver);
2858 if (rc < 0) {
2859 printk(KERN_ERR "%s(%d):Couldn't register serial driver\n",
2860 __FILE__, __LINE__);
2861 goto err_put_tty;
2862 }
1da177e4 2863
16a1065f
JS		 2864 rc = pcmcia_register_driver(&mgslpc_driver);
2865 if (rc < 0)
2866 goto err_unreg_tty;
d12341f9 2867
cc93441e
JS		 2868 printk(KERN_INFO "%s %s, tty major#%d\n", driver_name, driver_version,
2869 serial_driver->major);
d12341f9 2870
737586fe 2871 return 0;
16a1065f
JS		 2872err_unreg_tty:
2873 tty_unregister_driver(serial_driver);
737586fe
JS		 2874err_put_tty:
2875 put_tty_driver(serial_driver);
16a1065f 2876err:
737586fe 2877 return rc;
1da177e4
LT		 2878}
2879
d12341f9 2880static void __exit synclink_cs_exit(void)
1da177e4 2881{
16a1065f 2882 pcmcia_unregister_driver(&mgslpc_driver);
737586fe
JS		 2883 tty_unregister_driver(serial_driver);
2884 put_tty_driver(serial_driver);
1da177e4
LT		 2885}
2886
2887module_init(synclink_cs_init);
2888module_exit(synclink_cs_exit);
2889
2890static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2891{
2892 unsigned int M, N;
2893 unsigned char val;
2894
d12341f9
JG		 2895 /* note:standard BRG mode is broken in V3.2 chip
2896 * so enhanced mode is always used
1da177e4
LT		 2897 */
2898
2899 if (rate) {
2900 N = 3686400 / rate;
2901 if (!N)
2902 N = 1;
2903 N >>= 1;
2904 for (M = 1; N > 64 && M < 16; M++)
2905 N >>= 1;
2906 N--;
2907
2908 /* BGR[5..0] = N
2909 * BGR[9..6] = M
2910 * BGR[7..0] contained in BGR register
2911 * BGR[9..8] contained in CCR2[7..6]
2912 * divisor = (N+1)*2^M
2913 *
2914 * Note: M *must* not be zero (causes asymetric duty cycle)
d12341f9 2915 */
1da177e4
LT		 2916 write_reg(info, (unsigned char) (channel + BGR),
2917 (unsigned char) ((M << 6) + N));
2918 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2919 val |= ((M << 4) & 0xc0);
2920 write_reg(info, (unsigned char) (channel + CCR2), val);
2921 }
2922}
2923
2924/* Enabled the AUX clock output at the specified frequency.
2925 */
2926static void enable_auxclk(MGSLPC_INFO *info)
2927{
2928 unsigned char val;
d12341f9 2929
1da177e4
LT		 2930 /* MODE
2931 *
2932 * 07..06 MDS[1..0] 10 = transparent HDLC mode
2933 * 05 ADM Address Mode, 0 = no addr recognition
2934 * 04 TMD Timer Mode, 0 = external
2935 * 03 RAC Receiver Active, 0 = inactive
2936 * 02 RTS 0=RTS active during xmit, 1=RTS always active
2937 * 01 TRS Timer Resolution, 1=512
2938 * 00 TLP Test Loop, 0 = no loop
2939 *
2940 * 1000 0010
d12341f9 2941 */
1da177e4 2942 val = 0x82;
d12341f9
JG		 2943
2944 /* channel B RTS is used to enable AUXCLK driver on SP505 */
1da177e4
LT		 2945 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2946 val |= BIT2;
2947 write_reg(info, CHB + MODE, val);
d12341f9 2948
1da177e4
LT		 2949 /* CCR0
2950 *
2951 * 07 PU Power Up, 1=active, 0=power down
2952 * 06 MCE Master Clock Enable, 1=enabled
2953 * 05 Reserved, 0
2954 * 04..02 SC[2..0] Encoding
2955 * 01..00 SM[1..0] Serial Mode, 00=HDLC
2956 *
2957 * 11000000
d12341f9 2958 */
1da177e4 2959 write_reg(info, CHB + CCR0, 0xc0);
d12341f9 2960
1da177e4
LT		 2961 /* CCR1
2962 *
2963 * 07 SFLG Shared Flag, 0 = disable shared flags
2964 * 06 GALP Go Active On Loop, 0 = not used
2965 * 05 GLP Go On Loop, 0 = not used
2966 * 04 ODS Output Driver Select, 1=TxD is push-pull output
2967 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
2968 * 02..00 CM[2..0] Clock Mode
2969 *
2970 * 0001 0111
d12341f9 2971 */
1da177e4 2972 write_reg(info, CHB + CCR1, 0x17);
d12341f9 2973
1da177e4
LT		 2974 /* CCR2 (Channel B)
2975 *
2976 * 07..06 BGR[9..8] Baud rate bits 9..8
2977 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
2978 * 04 SSEL Clock source select, 1=submode b
2979 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
2980 * 02 RWX Read/Write Exchange 0=disabled
2981 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
2982 * 00 DIV, data inversion 0=disabled, 1=enabled
2983 *
2984 * 0011 1000
d12341f9 2985 */
1da177e4
LT		 2986 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2987 write_reg(info, CHB + CCR2, 0x38);
2988 else
2989 write_reg(info, CHB + CCR2, 0x30);
d12341f9 2990
1da177e4
LT		 2991 /* CCR4
2992 *
2993 * 07 MCK4 Master Clock Divide by 4, 1=enabled
2994 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
2995 * 05 TST1 Test Pin, 0=normal operation
2996 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
2997 * 03..02 Reserved, must be 0
2998 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
2999 *
3000 * 0101 0000
d12341f9 3001 */
1da177e4 3002 write_reg(info, CHB + CCR4, 0x50);
d12341f9 3003
1da177e4
LT		 3004 /* if auxclk not enabled, set internal BRG so
3005 * CTS transitions can be detected (requires TxC)
d12341f9 3006 */
1da177e4
LT		 3007 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3008 mgslpc_set_rate(info, CHB, info->params.clock_speed);
3009 else
3010 mgslpc_set_rate(info, CHB, 921600);
3011}
3012
d12341f9 3013static void loopback_enable(MGSLPC_INFO *info)
1da177e4
LT		 3014{
3015 unsigned char val;
d12341f9
JG		 3016
3017 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
ecda040f 3018 val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);
1da177e4 3019 write_reg(info, CHA + CCR1, val);
d12341f9
JG		 3020
3021 /* CCR2:04 SSEL Clock source select, 1=submode b */
ecda040f 3022 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);
1da177e4 3023 write_reg(info, CHA + CCR2, val);
d12341f9
JG		 3024
3025 /* set LinkSpeed if available, otherwise default to 2Mbps */
1da177e4
LT		 3026 if (info->params.clock_speed)
3027 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3028 else
3029 mgslpc_set_rate(info, CHA, 1843200);
d12341f9
JG		 3030
3031 /* MODE:00 TLP Test Loop, 1=loopback enabled */
1da177e4
LT		 3032 val = read_reg(info, CHA + MODE) | BIT0;
3033 write_reg(info, CHA + MODE, val);
3034}
3035
cdaad343 3036static void hdlc_mode(MGSLPC_INFO *info)
1da177e4
LT		 3037{
3038 unsigned char val;
3039 unsigned char clkmode, clksubmode;
3040
d12341f9 3041 /* disable all interrupts */
1da177e4
LT		 3042 irq_disable(info, CHA, 0xffff);
3043 irq_disable(info, CHB, 0xffff);
3044 port_irq_disable(info, 0xff);
d12341f9
JG		 3045
3046 /* assume clock mode 0a, rcv=RxC xmt=TxC */
1da177e4
LT		 3047 clkmode = clksubmode = 0;
3048 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3049 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
d12341f9 3050 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
1da177e4
LT		 3051 clkmode = 7;
3052 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3053 && info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3054 /* clock mode 7b, rcv = BRG, xmt = BRG */
1da177e4
LT		 3055 clkmode = 7;
3056 clksubmode = 1;
3057 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3058 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3059 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
1da177e4
LT		 3060 clkmode = 6;
3061 clksubmode = 1;
3062 } else {
d12341f9 3063 /* clock mode 6a, rcv = DPLL, xmt = TxC */
1da177e4
LT		 3064 clkmode = 6;
3065 }
3066 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3067 /* clock mode 0b, rcv = RxC, xmt = BRG */
1da177e4
LT		 3068 clksubmode = 1;
3069 }
d12341f9 3070
1da177e4
LT		 3071 /* MODE
3072 *
3073 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3074 * 05 ADM Address Mode, 0 = no addr recognition
3075 * 04 TMD Timer Mode, 0 = external
3076 * 03 RAC Receiver Active, 0 = inactive
3077 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3078 * 01 TRS Timer Resolution, 1=512
3079 * 00 TLP Test Loop, 0 = no loop
3080 *
3081 * 1000 0010
d12341f9 3082 */
1da177e4
LT		 3083 val = 0x82;
3084 if (info->params.loopback)
3085 val |= BIT0;
d12341f9
JG		 3086
3087 /* preserve RTS state */
1da177e4
LT		 3088 if (info->serial_signals & SerialSignal_RTS)
3089 val |= BIT2;
3090 write_reg(info, CHA + MODE, val);
d12341f9 3091
1da177e4
LT		 3092 /* CCR0
3093 *
3094 * 07 PU Power Up, 1=active, 0=power down
3095 * 06 MCE Master Clock Enable, 1=enabled
3096 * 05 Reserved, 0
3097 * 04..02 SC[2..0] Encoding
3098 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3099 *
3100 * 11000000
d12341f9 3101 */
1da177e4
LT		 3102 val = 0xc0;
3103 switch (info->params.encoding)
3104 {
3105 case HDLC_ENCODING_NRZI:
3106 val |= BIT3;
3107 break;
3108 case HDLC_ENCODING_BIPHASE_SPACE:
3109 val |= BIT4;
3110 break; // FM0
3111 case HDLC_ENCODING_BIPHASE_MARK:
ecda040f 3112 val |= BIT4 | BIT2;
1da177e4
LT		 3113 break; // FM1
3114 case HDLC_ENCODING_BIPHASE_LEVEL:
ecda040f 3115 val |= BIT4 | BIT3;
1da177e4
LT		 3116 break; // Manchester
3117 }
3118 write_reg(info, CHA + CCR0, val);
d12341f9 3119
1da177e4
LT		 3120 /* CCR1
3121 *
3122 * 07 SFLG Shared Flag, 0 = disable shared flags
3123 * 06 GALP Go Active On Loop, 0 = not used
3124 * 05 GLP Go On Loop, 0 = not used
3125 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3126 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3127 * 02..00 CM[2..0] Clock Mode
3128 *
3129 * 0001 0000
d12341f9 3130 */
1da177e4
LT		 3131 val = 0x10 + clkmode;
3132 write_reg(info, CHA + CCR1, val);
d12341f9 3133
1da177e4
LT		 3134 /* CCR2
3135 *
3136 * 07..06 BGR[9..8] Baud rate bits 9..8
3137 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3138 * 04 SSEL Clock source select, 1=submode b
3139 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3140 * 02 RWX Read/Write Exchange 0=disabled
3141 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3142 * 00 DIV, data inversion 0=disabled, 1=enabled
3143 *
3144 * 0000 0000
d12341f9 3145 */
1da177e4
LT		 3146 val = 0x00;
3147 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3148 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3149 val |= BIT5;
3150 if (clksubmode)
3151 val |= BIT4;
3152 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3153 val |= BIT1;
3154 if (info->params.encoding == HDLC_ENCODING_NRZB)
3155 val |= BIT0;
3156 write_reg(info, CHA + CCR2, val);
d12341f9 3157
1da177e4
LT		 3158 /* CCR3
3159 *
3160 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3161 * 05 EPT Enable preamble transmission, 1=enabled
3162 * 04 RADD Receive address pushed to FIFO, 0=disabled
3163 * 03 CRL CRC Reset Level, 0=FFFF
3164 * 02 RCRC Rx CRC 0=On 1=Off
3165 * 01 TCRC Tx CRC 0=On 1=Off
3166 * 00 PSD DPLL Phase Shift Disable
3167 *
3168 * 0000 0000
d12341f9 3169 */
1da177e4
LT		 3170 val = 0x00;
3171 if (info->params.crc_type == HDLC_CRC_NONE)
ecda040f 3172 val |= BIT2 | BIT1;
1da177e4
LT		 3173 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3174 val |= BIT5;
3175 switch (info->params.preamble_length)
3176 {
3177 case HDLC_PREAMBLE_LENGTH_16BITS:
3178 val |= BIT6;
3179 break;
3180 case HDLC_PREAMBLE_LENGTH_32BITS:
3181 val |= BIT6;
3182 break;
3183 case HDLC_PREAMBLE_LENGTH_64BITS:
ecda040f 3184 val |= BIT7 | BIT6;
1da177e4
LT		 3185 break;
3186 }
3187 write_reg(info, CHA + CCR3, val);
d12341f9
JG		 3188
3189 /* PRE - Preamble pattern */
1da177e4
LT		 3190 val = 0;
3191 switch (info->params.preamble)
3192 {
3193 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3194 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3195 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3196 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3197 }
3198 write_reg(info, CHA + PRE, val);
d12341f9 3199
1da177e4
LT		 3200 /* CCR4
3201 *
3202 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3203 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3204 * 05 TST1 Test Pin, 0=normal operation
3205 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3206 * 03..02 Reserved, must be 0
3207 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3208 *
3209 * 0101 0000
d12341f9 3210 */
1da177e4
LT		 3211 val = 0x50;
3212 write_reg(info, CHA + CCR4, val);
3213 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3214 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3215 else
3216 mgslpc_set_rate(info, CHA, info->params.clock_speed);
d12341f9 3217
1da177e4
LT		 3218 /* RLCR Receive length check register
3219 *
3220 * 7 1=enable receive length check
3221 * 6..0 Max frame length = (RL + 1) * 32
d12341f9 3222 */
1da177e4 3223 write_reg(info, CHA + RLCR, 0);
d12341f9 3224
1da177e4
LT		 3225 /* XBCH Transmit Byte Count High
3226 *
3227 * 07 DMA mode, 0 = interrupt driven
3228 * 06 NRM, 0=ABM (ignored)
3229 * 05 CAS Carrier Auto Start
3230 * 04 XC Transmit Continuously (ignored)
3231 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3232 *
3233 * 0000 0000
d12341f9 3234 */
1da177e4
LT		 3235 val = 0x00;
3236 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3237 val |= BIT5;
3238 write_reg(info, CHA + XBCH, val);
3239 enable_auxclk(info);
3240 if (info->params.loopback || info->testing_irq)
3241 loopback_enable(info);
3242 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3243 {
3244 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3245 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3246 set_reg_bits(info, CHA + PVR, BIT3);
3247 } else
3248 clear_reg_bits(info, CHA + PVR, BIT3);
3249
3250 irq_enable(info, CHA,
ecda040f
AJ		 3251 IRQ_RXEOM | IRQ_RXFIFO | IRQ_ALLSENT |
3252 IRQ_UNDERRUN | IRQ_TXFIFO);
1da177e4
LT		 3253 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3254 wait_command_complete(info, CHA);
3255 read_reg16(info, CHA + ISR); /* clear pending IRQs */
d12341f9 3256
1da177e4
LT		 3257 /* Master clock mode enabled above to allow reset commands
3258 * to complete even if no data clocks are present.
3259 *
3260 * Disable master clock mode for normal communications because
3261 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3262 * IRQ when in master clock mode.
3263 *
3264 * Leave master clock mode enabled for IRQ test because the
3265 * timer IRQ used by the test can only happen in master clock mode.
d12341f9 3266 */
1da177e4
LT		 3267 if (!info->testing_irq)
3268 clear_reg_bits(info, CHA + CCR0, BIT6);
3269
3270 tx_set_idle(info);
3271
3272 tx_stop(info);
3273 rx_stop(info);
3274}
3275
cdaad343 3276static void rx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3277{
3278 if (debug_level >= DEBUG_LEVEL_ISR)
3279 printk("%s(%d):rx_stop(%s)\n",
3d553993 3280 __FILE__, __LINE__, info->device_name);
d12341f9
JG		 3281
3282 /* MODE:03 RAC Receiver Active, 0=inactive */
1da177e4
LT		 3283 clear_reg_bits(info, CHA + MODE, BIT3);
3284
0fab6de0
JP		 3285 info->rx_enabled = false;
3286 info->rx_overflow = false;
1da177e4
LT		 3287}
3288
cdaad343 3289static void rx_start(MGSLPC_INFO *info)
1da177e4
LT		 3290{
3291 if (debug_level >= DEBUG_LEVEL_ISR)
3292 printk("%s(%d):rx_start(%s)\n",
3d553993 3293 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 3294
3295 rx_reset_buffers(info);
0fab6de0
JP		 3296 info->rx_enabled = false;
3297 info->rx_overflow = false;
1da177e4 3298
d12341f9 3299 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3300 set_reg_bits(info, CHA + MODE, BIT3);
3301
0fab6de0 3302 info->rx_enabled = true;
1da177e4
LT		 3303}
3304
eeb46134 3305static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3306{
3307 if (debug_level >= DEBUG_LEVEL_ISR)
3308 printk("%s(%d):tx_start(%s)\n",
3d553993 3309 __FILE__, __LINE__, info->device_name);
d12341f9 3310
1da177e4
LT		 3311 if (info->tx_count) {
3312 /* If auto RTS enabled and RTS is inactive, then assert */
3313 /* RTS and set a flag indicating that the driver should */
3314 /* negate RTS when the transmission completes. */
0fab6de0 3315 info->drop_rts_on_tx_done = false;
1da177e4
LT		 3316
3317 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3318 get_signals(info);
3319 if (!(info->serial_signals & SerialSignal_RTS)) {
3320 info->serial_signals |= SerialSignal_RTS;
3321 set_signals(info);
0fab6de0 3322 info->drop_rts_on_tx_done = true;
1da177e4
LT		 3323 }
3324 }
3325
3326 if (info->params.mode == MGSL_MODE_ASYNC) {
3327 if (!info->tx_active) {
0fab6de0 3328 info->tx_active = true;
eeb46134 3329 tx_ready(info, tty);
1da177e4
LT		 3330 }
3331 } else {
0fab6de0 3332 info->tx_active = true;
eeb46134 3333 tx_ready(info, tty);
40565f19
JS		 3334 mod_timer(&info->tx_timer, jiffies +
3335 msecs_to_jiffies(5000));
1da177e4
LT		 3336 }
3337 }
3338
3339 if (!info->tx_enabled)
0fab6de0 3340 info->tx_enabled = true;
1da177e4
LT		 3341}
3342
cdaad343 3343static void tx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3344{
3345 if (debug_level >= DEBUG_LEVEL_ISR)
3346 printk("%s(%d):tx_stop(%s)\n",
3d553993 3347 __FILE__, __LINE__, info->device_name);
d12341f9
JG		 3348
3349 del_timer(&info->tx_timer);
1da177e4 3350
0fab6de0
JP		 3351 info->tx_enabled = false;
3352 info->tx_active = false;
1da177e4
LT		 3353}
3354
3355/* Reset the adapter to a known state and prepare it for further use.
3356 */
cdaad343 3357static void reset_device(MGSLPC_INFO *info)
1da177e4 3358{
d12341f9 3359 /* power up both channels (set BIT7) */
1da177e4
LT		 3360 write_reg(info, CHA + CCR0, 0x80);
3361 write_reg(info, CHB + CCR0, 0x80);
3362 write_reg(info, CHA + MODE, 0);
3363 write_reg(info, CHB + MODE, 0);
d12341f9
JG		 3364
3365 /* disable all interrupts */
1da177e4
LT		 3366 irq_disable(info, CHA, 0xffff);
3367 irq_disable(info, CHB, 0xffff);
3368 port_irq_disable(info, 0xff);
d12341f9 3369
1da177e4
LT		 3370 /* PCR Port Configuration Register
3371 *
3372 * 07..04 DEC[3..0] Serial I/F select outputs
3373 * 03 output, 1=AUTO CTS control enabled
3374 * 02 RI Ring Indicator input 0=active
3375 * 01 DSR input 0=active
3376 * 00 DTR output 0=active
3377 *
3378 * 0000 0110
d12341f9 3379 */
1da177e4 3380 write_reg(info, PCR, 0x06);
d12341f9 3381
1da177e4
LT		 3382 /* PVR Port Value Register
3383 *
3384 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3385 * 03 AUTO CTS output 1=enabled
3386 * 02 RI Ring Indicator input
3387 * 01 DSR input
3388 * 00 DTR output (1=inactive)
3389 *
3390 * 0000 0001
3391 */
3392// write_reg(info, PVR, PVR_DTR);
d12341f9 3393
1da177e4
LT		 3394 /* IPC Interrupt Port Configuration
3395 *
3396 * 07 VIS 1=Masked interrupts visible
3397 * 06..05 Reserved, 0
3398 * 04..03 SLA Slave address, 00 ignored
3399 * 02 CASM Cascading Mode, 1=daisy chain
3400 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3401 *
3402 * 0000 0101
d12341f9 3403 */
1da177e4
LT		 3404 write_reg(info, IPC, 0x05);
3405}
3406
cdaad343 3407static void async_mode(MGSLPC_INFO *info)
1da177e4
LT		 3408{
3409 unsigned char val;
3410
d12341f9 3411 /* disable all interrupts */
1da177e4
LT		 3412 irq_disable(info, CHA, 0xffff);
3413 irq_disable(info, CHB, 0xffff);
3414 port_irq_disable(info, 0xff);
d12341f9 3415
1da177e4
LT		 3416 /* MODE
3417 *
3418 * 07 Reserved, 0
3419 * 06 FRTS RTS State, 0=active
3420 * 05 FCTS Flow Control on CTS
3421 * 04 FLON Flow Control Enable
3422 * 03 RAC Receiver Active, 0 = inactive
3423 * 02 RTS 0=Auto RTS, 1=manual RTS
3424 * 01 TRS Timer Resolution, 1=512
3425 * 00 TLP Test Loop, 0 = no loop
3426 *
3427 * 0000 0110
d12341f9 3428 */
1da177e4
LT		 3429 val = 0x06;
3430 if (info->params.loopback)
3431 val |= BIT0;
d12341f9
JG		 3432
3433 /* preserve RTS state */
1da177e4
LT		 3434 if (!(info->serial_signals & SerialSignal_RTS))
3435 val |= BIT6;
3436 write_reg(info, CHA + MODE, val);
d12341f9 3437
1da177e4
LT		 3438 /* CCR0
3439 *
3440 * 07 PU Power Up, 1=active, 0=power down
3441 * 06 MCE Master Clock Enable, 1=enabled
3442 * 05 Reserved, 0
3443 * 04..02 SC[2..0] Encoding, 000=NRZ
3444 * 01..00 SM[1..0] Serial Mode, 11=Async
3445 *
3446 * 1000 0011
d12341f9 3447 */
1da177e4 3448 write_reg(info, CHA + CCR0, 0x83);
d12341f9 3449
1da177e4
LT		 3450 /* CCR1
3451 *
3452 * 07..05 Reserved, 0
3453 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3454 * 03 BCR Bit Clock Rate, 1=16x
3455 * 02..00 CM[2..0] Clock Mode, 111=BRG
3456 *
3457 * 0001 1111
d12341f9 3458 */
1da177e4 3459 write_reg(info, CHA + CCR1, 0x1f);
d12341f9 3460
1da177e4
LT		 3461 /* CCR2 (channel A)
3462 *
3463 * 07..06 BGR[9..8] Baud rate bits 9..8
3464 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3465 * 04 SSEL Clock source select, 1=submode b
3466 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3467 * 02 RWX Read/Write Exchange 0=disabled
3468 * 01 Reserved, 0
3469 * 00 DIV, data inversion 0=disabled, 1=enabled
3470 *
3471 * 0001 0000
d12341f9 3472 */
1da177e4 3473 write_reg(info, CHA + CCR2, 0x10);
d12341f9 3474
1da177e4
LT		 3475 /* CCR3
3476 *
3477 * 07..01 Reserved, 0
3478 * 00 PSD DPLL Phase Shift Disable
3479 *
3480 * 0000 0000
d12341f9 3481 */
1da177e4 3482 write_reg(info, CHA + CCR3, 0);
d12341f9 3483
1da177e4
LT		 3484 /* CCR4
3485 *
3486 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3487 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3488 * 05 TST1 Test Pin, 0=normal operation
3489 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3490 * 03..00 Reserved, must be 0
3491 *
3492 * 0101 0000
d12341f9 3493 */
1da177e4
LT		 3494 write_reg(info, CHA + CCR4, 0x50);
3495 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
d12341f9 3496
1da177e4
LT		 3497 /* DAFO Data Format
3498 *
3499 * 07 Reserved, 0
3500 * 06 XBRK transmit break, 0=normal operation
3501 * 05 Stop bits (0=1, 1=2)
3502 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3503 * 02 PAREN Parity Enable
3504 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3505 *
d12341f9 3506 */
1da177e4
LT		 3507 val = 0x00;
3508 if (info->params.data_bits != 8)
3509 val |= BIT0; /* 7 bits */
3510 if (info->params.stop_bits != 1)
3511 val |= BIT5;
3512 if (info->params.parity != ASYNC_PARITY_NONE)
3513 {
3514 val |= BIT2; /* Parity enable */
3515 if (info->params.parity == ASYNC_PARITY_ODD)
3516 val |= BIT3;
3517 else
3518 val |= BIT4;
3519 }
3520 write_reg(info, CHA + DAFO, val);
d12341f9 3521
1da177e4
LT		 3522 /* RFC Rx FIFO Control
3523 *
3524 * 07 Reserved, 0
3525 * 06 DPS, 1=parity bit not stored in data byte
3526 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3527 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3528 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3529 * 01 Reserved, 0
3530 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3531 *
3532 * 0101 1100
d12341f9 3533 */
1da177e4 3534 write_reg(info, CHA + RFC, 0x5c);
d12341f9 3535
1da177e4
LT		 3536 /* RLCR Receive length check register
3537 *
3538 * Max frame length = (RL + 1) * 32
d12341f9 3539 */
1da177e4 3540 write_reg(info, CHA + RLCR, 0);
d12341f9 3541
1da177e4
LT		 3542 /* XBCH Transmit Byte Count High
3543 *
3544 * 07 DMA mode, 0 = interrupt driven
3545 * 06 NRM, 0=ABM (ignored)
3546 * 05 CAS Carrier Auto Start
3547 * 04 XC Transmit Continuously (ignored)
3548 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3549 *
3550 * 0000 0000
d12341f9 3551 */
1da177e4
LT		 3552 val = 0x00;
3553 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3554 val |= BIT5;
3555 write_reg(info, CHA + XBCH, val);
3556 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3557 irq_enable(info, CHA, IRQ_CTS);
d12341f9
JG		 3558
3559 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3560 set_reg_bits(info, CHA + MODE, BIT3);
3561 enable_auxclk(info);
3562 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3563 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3564 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3565 set_reg_bits(info, CHA + PVR, BIT3);
3566 } else
3567 clear_reg_bits(info, CHA + PVR, BIT3);
3568 irq_enable(info, CHA,
ecda040f
AJ		 3569 IRQ_RXEOM | IRQ_RXFIFO | IRQ_BREAK_ON | IRQ_RXTIME |
3570 IRQ_ALLSENT | IRQ_TXFIFO);
1da177e4
LT		 3571 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3572 wait_command_complete(info, CHA);
3573 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3574}
3575
3576/* Set the HDLC idle mode for the transmitter.
3577 */
cdaad343 3578static void tx_set_idle(MGSLPC_INFO *info)
1da177e4 3579{
d12341f9 3580 /* Note: ESCC2 only supports flags and one idle modes */
1da177e4
LT		 3581 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3582 set_reg_bits(info, CHA + CCR1, BIT3);
3583 else
3584 clear_reg_bits(info, CHA + CCR1, BIT3);
3585}
3586
3587/* get state of the V24 status (input) signals.
3588 */
cdaad343 3589static void get_signals(MGSLPC_INFO *info)
1da177e4
LT		 3590{
3591 unsigned char status = 0;
d12341f9 3592
9fe8074b
JP		 3593 /* preserve RTS and DTR */
3594 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 3595
3596 if (read_reg(info, CHB + VSTR) & BIT7)
3597 info->serial_signals |= SerialSignal_DCD;
3598 if (read_reg(info, CHB + STAR) & BIT1)
3599 info->serial_signals |= SerialSignal_CTS;
3600
3601 status = read_reg(info, CHA + PVR);
3602 if (!(status & PVR_RI))
3603 info->serial_signals |= SerialSignal_RI;
3604 if (!(status & PVR_DSR))
3605 info->serial_signals |= SerialSignal_DSR;
3606}
3607
9fe8074b 3608/* Set the state of RTS and DTR based on contents of
1da177e4
LT		 3609 * serial_signals member of device extension.
3610 */
cdaad343 3611static void set_signals(MGSLPC_INFO *info)
1da177e4
LT		 3612{
3613 unsigned char val;
3614
3615 val = read_reg(info, CHA + MODE);
3616 if (info->params.mode == MGSL_MODE_ASYNC) {
3617 if (info->serial_signals & SerialSignal_RTS)
3618 val &= ~BIT6;
3619 else
3620 val |= BIT6;
3621 } else {
3622 if (info->serial_signals & SerialSignal_RTS)
3623 val |= BIT2;
3624 else
3625 val &= ~BIT2;
3626 }
3627 write_reg(info, CHA + MODE, val);
3628
3629 if (info->serial_signals & SerialSignal_DTR)
3630 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3631 else
3632 set_reg_bits(info, CHA + PVR, PVR_DTR);
3633}
3634
cdaad343 3635static void rx_reset_buffers(MGSLPC_INFO *info)
1da177e4
LT		 3636{
3637 RXBUF *buf;
3638 int i;
3639
3640 info->rx_put = 0;
3641 info->rx_get = 0;
3642 info->rx_frame_count = 0;
3643 for (i=0 ; i < info->rx_buf_count ; i++) {
3644 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3645 buf->status = buf->count = 0;
3646 }
3647}
3648
3649/* Attempt to return a received HDLC frame
3650 * Only frames received without errors are returned.
3651 *
0fab6de0 3652 * Returns true if frame returned, otherwise false
1da177e4 3653 */
eeb46134 3654static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3655{
3656 unsigned short status;
3657 RXBUF *buf;
3658 unsigned int framesize = 0;
3659 unsigned long flags;
0fab6de0 3660 bool return_frame = false;
d12341f9 3661
1da177e4 3662 if (info->rx_frame_count == 0)
0fab6de0 3663 return false;
1da177e4
LT		 3664
3665 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3666
3667 status = buf->status;
3668
3669 /* 07 VFR 1=valid frame
3670 * 06 RDO 1=data overrun
3671 * 05 CRC 1=OK, 0=error
3672 * 04 RAB 1=frame aborted
3673 */
3674 if ((status & 0xf0) != 0xA0) {
3675 if (!(status & BIT7) || (status & BIT4))
3676 info->icount.rxabort++;
3677 else if (status & BIT6)
3678 info->icount.rxover++;
3679 else if (!(status & BIT5)) {
3680 info->icount.rxcrc++;
3681 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
0fab6de0 3682 return_frame = true;
1da177e4
LT		 3683 }
3684 framesize = 0;
af69c7f9 3685#if SYNCLINK_GENERIC_HDLC
1da177e4 3686 {
198191c4
KH		 3687 info->netdev->stats.rx_errors++;
3688 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 3689 }
3690#endif
3691 } else
0fab6de0 3692 return_frame = true;
1da177e4
LT		 3693
3694 if (return_frame)
3695 framesize = buf->count;
3696
3697 if (debug_level >= DEBUG_LEVEL_BH)
3698 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
3d553993 3699 __FILE__, __LINE__, info->device_name, status, framesize);
d12341f9 3700
1da177e4 3701 if (debug_level >= DEBUG_LEVEL_DATA)
d12341f9
JG		 3702 trace_block(info, buf->data, framesize, 0);
3703
1da177e4
LT		 3704 if (framesize) {
3705 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
3706 framesize+1 > info->max_frame_size) ||
3707 framesize > info->max_frame_size)
3708 info->icount.rxlong++;
3709 else {
3710 if (status & BIT5)
3711 info->icount.rxok++;
3712
3713 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
3714 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
3715 ++framesize;
3716 }
3717
af69c7f9 3718#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3719 if (info->netcount)
3720 hdlcdev_rx(info, buf->data, framesize);
3721 else
3722#endif
3723 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
3724 }
3725 }
3726
3d553993 3727 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 3728 buf->status = buf->count = 0;
3729 info->rx_frame_count--;
3730 info->rx_get++;
3731 if (info->rx_get >= info->rx_buf_count)
3732 info->rx_get = 0;
3d553993 3733 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 3734
0fab6de0 3735 return true;
1da177e4
LT		 3736}
3737
0fab6de0 3738static bool register_test(MGSLPC_INFO *info)
1da177e4 3739{
d12341f9 3740 static unsigned char patterns[] =
1da177e4 3741 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
fe971071 3742 static unsigned int count = ARRAY_SIZE(patterns);
1da177e4 3743 unsigned int i;
0fab6de0 3744 bool rc = true;
1da177e4
LT		 3745 unsigned long flags;
3746
3d553993 3747 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 3748 reset_device(info);
3749
3750 for (i = 0; i < count; i++) {
3751 write_reg(info, XAD1, patterns[i]);
3752 write_reg(info, XAD2, patterns[(i + 1) % count]);
fe971071 3753 if ((read_reg(info, XAD1) != patterns[i]) ||
1da177e4 3754 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
0fab6de0 3755 rc = false;
1da177e4
LT		 3756 break;
3757 }
3758 }
3759
3d553993 3760 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 3761 return rc;
3762}
3763
0fab6de0 3764static bool irq_test(MGSLPC_INFO *info)
1da177e4
LT		 3765{
3766 unsigned long end_time;
3767 unsigned long flags;
3768
3d553993 3769 spin_lock_irqsave(&info->lock, flags);
1da177e4
LT		 3770 reset_device(info);
3771
0fab6de0 3772 info->testing_irq = true;
1da177e4
LT		 3773 hdlc_mode(info);
3774
0fab6de0 3775 info->irq_occurred = false;
1da177e4
LT		 3776
3777 /* init hdlc mode */
3778
3779 irq_enable(info, CHA, IRQ_TIMER);
3780 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
3781 issue_command(info, CHA, CMD_START_TIMER);
3782
3d553993 3783 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 3784
3785 end_time=100;
3786 while(end_time-- && !info->irq_occurred) {
3787 msleep_interruptible(10);
3788 }
d12341f9 3789
0fab6de0 3790 info->testing_irq = false;
1da177e4 3791
3d553993 3792 spin_lock_irqsave(&info->lock, flags);
1da177e4 3793 reset_device(info);
3d553993 3794 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 3795
0fab6de0 3796 return info->irq_occurred;
1da177e4
LT		 3797}
3798
cdaad343 3799static int adapter_test(MGSLPC_INFO *info)
1da177e4
LT		 3800{
3801 if (!register_test(info)) {
3802 info->init_error = DiagStatus_AddressFailure;
3d553993
AK		 3803 printk("%s(%d):Register test failure for device %s Addr=%04X\n",
3804 __FILE__, __LINE__, info->device_name, (unsigned short)(info->io_base));
1da177e4
LT		 3805 return -ENODEV;
3806 }
3807
3808 if (!irq_test(info)) {
3809 info->init_error = DiagStatus_IrqFailure;
3d553993
AK		 3810 printk("%s(%d):Interrupt test failure for device %s IRQ=%d\n",
3811 __FILE__, __LINE__, info->device_name, (unsigned short)(info->irq_level));
1da177e4
LT		 3812 return -ENODEV;
3813 }
3814
3815 if (debug_level >= DEBUG_LEVEL_INFO)
3816 printk("%s(%d):device %s passed diagnostics\n",
3d553993 3817 __FILE__, __LINE__, info->device_name);
1da177e4
LT		 3818 return 0;
3819}
3820
cdaad343 3821static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 3822{
3823 int i;
3824 int linecount;
3825 if (xmit)
3d553993 3826 printk("%s tx data:\n", info->device_name);
1da177e4 3827 else
3d553993 3828 printk("%s rx data:\n", info->device_name);
d12341f9 3829
1da177e4
LT		 3830 while(count) {
3831 if (count > 16)
3832 linecount = 16;
3833 else
3834 linecount = count;
d12341f9 3835
1da177e4 3836 for(i=0;i<linecount;i++)
3d553993 3837 printk("%02X ", (unsigned char)data[i]);
1da177e4
LT		 3838 for(;i<17;i++)
3839 printk(" ");
3840 for(i=0;i<linecount;i++) {
3841 if (data[i]>=040 && data[i]<=0176)
3d553993 3842 printk("%c", data[i]);
1da177e4
LT		 3843 else
3844 printk(".");
3845 }
3846 printk("\n");
d12341f9 3847
1da177e4
LT		 3848 data += linecount;
3849 count -= linecount;
3850 }
3851}
3852
3853/* HDLC frame time out
3854 * update stats and do tx completion processing
3855 */
cdaad343 3856static void tx_timeout(unsigned long context)
1da177e4
LT		 3857{
3858 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
3859 unsigned long flags;
d12341f9 3860
3d553993
AK		 3861 if (debug_level >= DEBUG_LEVEL_INFO)
3862 printk("%s(%d):tx_timeout(%s)\n",
3863 __FILE__, __LINE__, info->device_name);
3864 if (info->tx_active &&
3865 info->params.mode == MGSL_MODE_HDLC) {
1da177e4
LT		 3866 info->icount.txtimeout++;
3867 }
3d553993 3868 spin_lock_irqsave(&info->lock, flags);
0fab6de0 3869 info->tx_active = false;
1da177e4
LT		 3870 info->tx_count = info->tx_put = info->tx_get = 0;
3871
3d553993 3872 spin_unlock_irqrestore(&info->lock, flags);
d12341f9 3873
af69c7f9 3874#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3875 if (info->netcount)
3876 hdlcdev_tx_done(info);
3877 else
3878#endif
eeb46134
AC		 3879 {
3880 struct tty_struct *tty = tty_port_tty_get(&info->port);
3881 bh_transmit(info, tty);
3882 tty_kref_put(tty);
3883 }
1da177e4
LT		 3884}
3885
af69c7f9 3886#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3887
3888/**
3889 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3890 * set encoding and frame check sequence (FCS) options
3891 *
3892 * dev pointer to network device structure
3893 * encoding serial encoding setting
3894 * parity FCS setting
3895 *
3896 * returns 0 if success, otherwise error code
3897 */
3898static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
3899 unsigned short parity)
3900{
3901 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3902 struct tty_struct *tty;
1da177e4
LT		 3903 unsigned char new_encoding;
3904 unsigned short new_crctype;
3905
3906 /* return error if TTY interface open */
eeb46134 3907 if (info->port.count)
1da177e4
LT		 3908 return -EBUSY;
3909
3910 switch (encoding)
3911 {
3912 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
3913 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
3914 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
3915 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
3916 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
3917 default: return -EINVAL;
3918 }
3919
3920 switch (parity)
3921 {
3922 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
3923 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
3924 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
3925 default: return -EINVAL;
3926 }
3927
3928 info->params.encoding = new_encoding;
53b3531b 3929 info->params.crc_type = new_crctype;
1da177e4
LT		 3930
3931 /* if network interface up, reprogram hardware */
eeb46134
AC		 3932 if (info->netcount) {
3933 tty = tty_port_tty_get(&info->port);
3934 mgslpc_program_hw(info, tty);
3935 tty_kref_put(tty);
3936 }
1da177e4
LT		 3937
3938 return 0;
3939}
3940
3941/**
3942 * called by generic HDLC layer to send frame
3943 *
3944 * skb socket buffer containing HDLC frame
3945 * dev pointer to network device structure
1da177e4 3946 */
4c5d502d
SH		 3947static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
3948 struct net_device *dev)
1da177e4
LT		 3949{
3950 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 3951 unsigned long flags;
3952
3953 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 3954 printk(KERN_INFO "%s:hdlc_xmit(%s)\n", __FILE__, dev->name);
1da177e4
LT		 3955
3956 /* stop sending until this frame completes */
3957 netif_stop_queue(dev);
3958
3959 /* copy data to device buffers */
d626f62b 3960 skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
1da177e4
LT		 3961 info->tx_get = 0;
3962 info->tx_put = info->tx_count = skb->len;
3963
3964 /* update network statistics */
198191c4
KH		 3965 dev->stats.tx_packets++;
3966 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 3967
3968 /* done with socket buffer, so free it */
3969 dev_kfree_skb(skb);
3970
3971 /* save start time for transmit timeout detection */
3972 dev->trans_start = jiffies;
3973
3974 /* start hardware transmitter if necessary */
3d553993 3975 spin_lock_irqsave(&info->lock, flags);
eeb46134
AC		 3976 if (!info->tx_active) {
3977 struct tty_struct *tty = tty_port_tty_get(&info->port);
3d553993
AK		 3978 tx_start(info, tty);
3979 tty_kref_put(tty);
eeb46134 3980 }
3d553993 3981 spin_unlock_irqrestore(&info->lock, flags);
1da177e4 3982
4c5d502d 3983 return NETDEV_TX_OK;
1da177e4
LT		 3984}
3985
3986/**
3987 * called by network layer when interface enabled
3988 * claim resources and initialize hardware
3989 *
3990 * dev pointer to network device structure
3991 *
3992 * returns 0 if success, otherwise error code
3993 */
3994static int hdlcdev_open(struct net_device *dev)
3995{
3996 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3997 struct tty_struct *tty;
1da177e4
LT		 3998 int rc;
3999 unsigned long flags;
4000
4001 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4002 printk("%s:hdlcdev_open(%s)\n", __FILE__, dev->name);
1da177e4
LT		 4003
4004 /* generic HDLC layer open processing */
3d553993
AK		 4005 rc = hdlc_open(dev);
4006 if (rc != 0)
1da177e4
LT		 4007 return rc;
4008
4009 /* arbitrate between network and tty opens */
4010 spin_lock_irqsave(&info->netlock, flags);
eeb46134 4011 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 4012 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
4013 spin_unlock_irqrestore(&info->netlock, flags);
4014 return -EBUSY;
4015 }
4016 info->netcount=1;
4017 spin_unlock_irqrestore(&info->netlock, flags);
4018
eeb46134 4019 tty = tty_port_tty_get(&info->port);
1da177e4 4020 /* claim resources and init adapter */
3d553993
AK		 4021 rc = startup(info, tty);
4022 if (rc != 0) {
eeb46134 4023 tty_kref_put(tty);
1da177e4
LT		 4024 spin_lock_irqsave(&info->netlock, flags);
4025 info->netcount=0;
4026 spin_unlock_irqrestore(&info->netlock, flags);
4027 return rc;
4028 }
9fe8074b
JP		 4029 /* assert RTS and DTR, apply hardware settings */
4030 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
eeb46134
AC		 4031 mgslpc_program_hw(info, tty);
4032 tty_kref_put(tty);
1da177e4
LT		 4033
4034 /* enable network layer transmit */
4035 dev->trans_start = jiffies;
4036 netif_start_queue(dev);
4037
4038 /* inform generic HDLC layer of current DCD status */
4039 spin_lock_irqsave(&info->lock, flags);
4040 get_signals(info);
4041 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 4042 if (info->serial_signals & SerialSignal_DCD)
4043 netif_carrier_on(dev);
4044 else
4045 netif_carrier_off(dev);
1da177e4
LT		 4046 return 0;
4047}
4048
4049/**
4050 * called by network layer when interface is disabled
4051 * shutdown hardware and release resources
4052 *
4053 * dev pointer to network device structure
4054 *
4055 * returns 0 if success, otherwise error code
4056 */
4057static int hdlcdev_close(struct net_device *dev)
4058{
4059 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 4060 struct tty_struct *tty = tty_port_tty_get(&info->port);
1da177e4
LT		 4061 unsigned long flags;
4062
4063 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4064 printk("%s:hdlcdev_close(%s)\n", __FILE__, dev->name);
1da177e4
LT		 4065
4066 netif_stop_queue(dev);
4067
4068 /* shutdown adapter and release resources */
eeb46134
AC		 4069 shutdown(info, tty);
4070 tty_kref_put(tty);
1da177e4
LT		 4071 hdlc_close(dev);
4072
4073 spin_lock_irqsave(&info->netlock, flags);
4074 info->netcount=0;
4075 spin_unlock_irqrestore(&info->netlock, flags);
4076
4077 return 0;
4078}
4079
4080/**
4081 * called by network layer to process IOCTL call to network device
4082 *
4083 * dev pointer to network device structure
4084 * ifr pointer to network interface request structure
4085 * cmd IOCTL command code
4086 *
4087 * returns 0 if success, otherwise error code
4088 */
4089static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4090{
4091 const size_t size = sizeof(sync_serial_settings);
4092 sync_serial_settings new_line;
4093 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4094 MGSLPC_INFO *info = dev_to_port(dev);
4095 unsigned int flags;
4096
4097 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4098 printk("%s:hdlcdev_ioctl(%s)\n", __FILE__, dev->name);
1da177e4
LT		 4099
4100 /* return error if TTY interface open */
eeb46134 4101 if (info->port.count)
1da177e4
LT		 4102 return -EBUSY;
4103
4104 if (cmd != SIOCWANDEV)
4105 return hdlc_ioctl(dev, ifr, cmd);
4106
5b917a14
VK		 4107 memset(&new_line, 0, size);
4108
1da177e4
LT		 4109 switch(ifr->ifr_settings.type) {
4110 case IF_GET_IFACE: /* return current sync_serial_settings */
4111
4112 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4113 if (ifr->ifr_settings.size < size) {
4114 ifr->ifr_settings.size = size; /* data size wanted */
4115 return -ENOBUFS;
4116 }
4117
4118 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4119 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4120 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4121 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4122
4123 switch (flags){
4124 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4125 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4126 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4127 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4128 default: new_line.clock_type = CLOCK_DEFAULT;
4129 }
4130
4131 new_line.clock_rate = info->params.clock_speed;
4132 new_line.loopback = info->params.loopback ? 1:0;
4133
4134 if (copy_to_user(line, &new_line, size))
4135 return -EFAULT;
4136 return 0;
4137
4138 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4139
4140 if(!capable(CAP_NET_ADMIN))
4141 return -EPERM;
4142 if (copy_from_user(&new_line, line, size))
4143 return -EFAULT;
4144
4145 switch (new_line.clock_type)
4146 {
4147 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4148 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4149 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4150 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4151 case CLOCK_DEFAULT: flags = info->params.flags &
4152 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4153 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4154 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4155 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4156 default: return -EINVAL;
4157 }
4158
4159 if (new_line.loopback != 0 && new_line.loopback != 1)
4160 return -EINVAL;
4161
4162 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4163 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4164 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4165 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4166 info->params.flags |= flags;
4167
4168 info->params.loopback = new_line.loopback;
4169
4170 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4171 info->params.clock_speed = new_line.clock_rate;
4172 else
4173 info->params.clock_speed = 0;
4174
4175 /* if network interface up, reprogram hardware */
eeb46134
AC		 4176 if (info->netcount) {
4177 struct tty_struct *tty = tty_port_tty_get(&info->port);
4178 mgslpc_program_hw(info, tty);
4179 tty_kref_put(tty);
4180 }
1da177e4
LT		 4181 return 0;
4182
4183 default:
4184 return hdlc_ioctl(dev, ifr, cmd);
4185 }
4186}
4187
4188/**
4189 * called by network layer when transmit timeout is detected
4190 *
4191 * dev pointer to network device structure
4192 */
4193static void hdlcdev_tx_timeout(struct net_device *dev)
4194{
4195 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 4196 unsigned long flags;
4197
4198 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4199 printk("hdlcdev_tx_timeout(%s)\n", dev->name);
1da177e4 4200
198191c4
KH		 4201 dev->stats.tx_errors++;
4202 dev->stats.tx_aborted_errors++;
1da177e4 4203
3d553993 4204 spin_lock_irqsave(&info->lock, flags);
1da177e4 4205 tx_stop(info);
3d553993 4206 spin_unlock_irqrestore(&info->lock, flags);
1da177e4
LT		 4207
4208 netif_wake_queue(dev);
4209}
4210
4211/**
4212 * called by device driver when transmit completes
4213 * reenable network layer transmit if stopped
4214 *
4215 * info pointer to device instance information
4216 */
4217static void hdlcdev_tx_done(MGSLPC_INFO *info)
4218{
4219 if (netif_queue_stopped(info->netdev))
4220 netif_wake_queue(info->netdev);
4221}
4222
4223/**
4224 * called by device driver when frame received
4225 * pass frame to network layer
4226 *
4227 * info pointer to device instance information
4228 * buf pointer to buffer contianing frame data
4229 * size count of data bytes in buf
4230 */
4231static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4232{
4233 struct sk_buff *skb = dev_alloc_skb(size);
4234 struct net_device *dev = info->netdev;
1da177e4
LT		 4235
4236 if (debug_level >= DEBUG_LEVEL_INFO)
3d553993 4237 printk("hdlcdev_rx(%s)\n", dev->name);
1da177e4
LT		 4238
4239 if (skb == NULL) {
4240 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
198191c4 4241 dev->stats.rx_dropped++;
1da177e4
LT		 4242 return;
4243 }
4244
198191c4 4245 memcpy(skb_put(skb, size), buf, size);
1da177e4 4246
198191c4 4247 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 4248
198191c4
KH		 4249 dev->stats.rx_packets++;
4250 dev->stats.rx_bytes += size;
1da177e4
LT		 4251
4252 netif_rx(skb);
1da177e4
LT		 4253}
4254
991990a1
KH		 4255static const struct net_device_ops hdlcdev_ops = {
4256 .ndo_open = hdlcdev_open,
4257 .ndo_stop = hdlcdev_close,
4258 .ndo_change_mtu = hdlc_change_mtu,
4259 .ndo_start_xmit = hdlc_start_xmit,
4260 .ndo_do_ioctl = hdlcdev_ioctl,
4261 .ndo_tx_timeout = hdlcdev_tx_timeout,
4262};
4263
1da177e4
LT		 4264/**
4265 * called by device driver when adding device instance
4266 * do generic HDLC initialization
4267 *
4268 * info pointer to device instance information
4269 *
4270 * returns 0 if success, otherwise error code
4271 */
4272static int hdlcdev_init(MGSLPC_INFO *info)
4273{
4274 int rc;
4275 struct net_device *dev;
4276 hdlc_device *hdlc;
4277
4278 /* allocate and initialize network and HDLC layer objects */
4279
3d553993
AK		 4280 dev = alloc_hdlcdev(info);
4281 if (dev == NULL) {
4282 printk(KERN_ERR "%s:hdlc device allocation failure\n", __FILE__);
1da177e4
LT		 4283 return -ENOMEM;
4284 }
4285
4286 /* for network layer reporting purposes only */
4287 dev->base_addr = info->io_base;
4288 dev->irq = info->irq_level;
4289
4290 /* network layer callbacks and settings */
991990a1
KH		 4291 dev->netdev_ops = &hdlcdev_ops;
4292 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 4293 dev->tx_queue_len = 50;
4294
4295 /* generic HDLC layer callbacks and settings */
4296 hdlc = dev_to_hdlc(dev);
4297 hdlc->attach = hdlcdev_attach;
4298 hdlc->xmit = hdlcdev_xmit;
4299
4300 /* register objects with HDLC layer */
3d553993
AK		 4301 rc = register_hdlc_device(dev);
4302 if (rc) {
4303 printk(KERN_WARNING "%s:unable to register hdlc device\n", __FILE__);
1da177e4
LT		 4304 free_netdev(dev);
4305 return rc;
4306 }
4307
4308 info->netdev = dev;
4309 return 0;
4310}
4311
4312/**
4313 * called by device driver when removing device instance
4314 * do generic HDLC cleanup
4315 *
4316 * info pointer to device instance information
4317 */
4318static void hdlcdev_exit(MGSLPC_INFO *info)
4319{
4320 unregister_hdlc_device(info->netdev);
4321 free_netdev(info->netdev);
4322 info->netdev = NULL;
4323}
4324
4325#endif /* CONFIG_HDLC */
4326
Linux kernel - Deliverables
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