projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pcmcia: do not use io_req_t when calling pcmcia_request_io()
[deliverable/linux.git] / drivers / char / pcmcia / synclink_cs.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
a7482a2e 4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
1da177e4
LT		 5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30#if defined(__i386__)
31# define BREAKPOINT() asm(" int $3");
32#else
33# define BREAKPOINT() { }
34#endif
35
36#define MAX_DEVICE_COUNT 4
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/errno.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/timer.h>
43#include <linux/time.h>
44#include <linux/interrupt.h>
1da177e4
LT		 45#include <linux/tty.h>
46#include <linux/tty_flip.h>
47#include <linux/serial.h>
48#include <linux/major.h>
49#include <linux/string.h>
50#include <linux/fcntl.h>
51#include <linux/ptrace.h>
52#include <linux/ioport.h>
53#include <linux/mm.h>
87687144 54#include <linux/seq_file.h>
1da177e4
LT		 55#include <linux/slab.h>
56#include <linux/netdevice.h>
57#include <linux/vmalloc.h>
58#include <linux/init.h>
1da177e4
LT		 59#include <linux/delay.h>
60#include <linux/ioctl.h>
3dd1247f 61#include <linux/synclink.h>
1da177e4
LT		 62
63#include <asm/system.h>
64#include <asm/io.h>
65#include <asm/irq.h>
66#include <asm/dma.h>
67#include <linux/bitops.h>
68#include <asm/types.h>
69#include <linux/termios.h>
70#include <linux/workqueue.h>
71#include <linux/hdlc.h>
72
1da177e4
LT		 73#include <pcmcia/cs.h>
74#include <pcmcia/cistpl.h>
75#include <pcmcia/cisreg.h>
76#include <pcmcia/ds.h>
77
af69c7f9
PF		 78#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
79#define SYNCLINK_GENERIC_HDLC 1
80#else
81#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 82#endif
83
84#define GET_USER(error,value,addr) error = get_user(value,addr)
85#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
86#define PUT_USER(error,value,addr) error = put_user(value,addr)
87#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
88
89#include <asm/uaccess.h>
90
1da177e4
LT		 91static MGSL_PARAMS default_params = {
92 MGSL_MODE_HDLC, /* unsigned long mode */
93 0, /* unsigned char loopback; */
94 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
95 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
96 0, /* unsigned long clock_speed; */
97 0xff, /* unsigned char addr_filter; */
98 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
99 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
100 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
101 9600, /* unsigned long data_rate; */
102 8, /* unsigned char data_bits; */
103 1, /* unsigned char stop_bits; */
104 ASYNC_PARITY_NONE /* unsigned char parity; */
105};
106
107typedef struct
108{
109 int count;
110 unsigned char status;
111 char data[1];
112} RXBUF;
113
114/* The queue of BH actions to be performed */
115
116#define BH_RECEIVE 1
117#define BH_TRANSMIT 2
118#define BH_STATUS 4
119
120#define IO_PIN_SHUTDOWN_LIMIT 100
121
122#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
123
124struct _input_signal_events {
d12341f9 125 int ri_up;
1da177e4
LT		 126 int ri_down;
127 int dsr_up;
128 int dsr_down;
129 int dcd_up;
130 int dcd_down;
131 int cts_up;
132 int cts_down;
133};
134
135
136/*
137 * Device instance data structure
138 */
d12341f9 139
1da177e4 140typedef struct _mgslpc_info {
eeb46134 141 struct tty_port port;
1da177e4
LT		 142 void *if_ptr; /* General purpose pointer (used by SPPP) */
143 int magic;
1da177e4 144 int line;
d12341f9 145
1da177e4 146 struct mgsl_icount icount;
d12341f9 147
1da177e4
LT		 148 int timeout;
149 int x_char; /* xon/xoff character */
1da177e4 150 unsigned char read_status_mask;
d12341f9 151 unsigned char ignore_status_mask;
1da177e4
LT		 152
153 unsigned char *tx_buf;
154 int tx_put;
155 int tx_get;
156 int tx_count;
157
158 /* circular list of fixed length rx buffers */
159
160 unsigned char *rx_buf; /* memory allocated for all rx buffers */
161 int rx_buf_total_size; /* size of memory allocated for rx buffers */
162 int rx_put; /* index of next empty rx buffer */
163 int rx_get; /* index of next full rx buffer */
164 int rx_buf_size; /* size in bytes of single rx buffer */
165 int rx_buf_count; /* total number of rx buffers */
166 int rx_frame_count; /* number of full rx buffers */
d12341f9 167
1da177e4
LT		 168 wait_queue_head_t status_event_wait_q;
169 wait_queue_head_t event_wait_q;
170 struct timer_list tx_timer; /* HDLC transmit timeout timer */
171 struct _mgslpc_info *next_device; /* device list link */
172
173 unsigned short imra_value;
174 unsigned short imrb_value;
175 unsigned char pim_value;
176
177 spinlock_t lock;
178 struct work_struct task; /* task structure for scheduling bh */
179
180 u32 max_frame_size;
181
182 u32 pending_bh;
183
0fab6de0
JP		 184 bool bh_running;
185 bool bh_requested;
d12341f9 186
1da177e4
LT		 187 int dcd_chkcount; /* check counts to prevent */
188 int cts_chkcount; /* too many IRQs if a signal */
189 int dsr_chkcount; /* is floating */
190 int ri_chkcount;
191
0fab6de0
JP		 192 bool rx_enabled;
193 bool rx_overflow;
1da177e4 194
0fab6de0
JP		 195 bool tx_enabled;
196 bool tx_active;
197 bool tx_aborting;
1da177e4
LT		 198 u32 idle_mode;
199
200 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
201
202 char device_name[25]; /* device instance name */
203
204 unsigned int io_base; /* base I/O address of adapter */
205 unsigned int irq_level;
d12341f9 206
1da177e4
LT		 207 MGSL_PARAMS params; /* communications parameters */
208
209 unsigned char serial_signals; /* current serial signal states */
210
0fab6de0 211 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 212 char testing_irq;
213 unsigned int init_error; /* startup error (DIAGS) */
214
215 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
0fab6de0 216 bool drop_rts_on_tx_done;
1da177e4
LT		 217
218 struct _input_signal_events input_signal_events;
219
220 /* PCMCIA support */
fd238232 221 struct pcmcia_device *p_dev;
1da177e4
LT		 222 int stop;
223
224 /* SPPP/Cisco HDLC device parts */
225 int netcount;
1da177e4
LT		 226 spinlock_t netlock;
227
af69c7f9 228#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 229 struct net_device *netdev;
230#endif
231
232} MGSLPC_INFO;
233
234#define MGSLPC_MAGIC 0x5402
235
236/*
237 * The size of the serial xmit buffer is 1 page, or 4096 bytes
238 */
239#define TXBUFSIZE 4096
240
d12341f9 241
1da177e4
LT		 242#define CHA 0x00 /* channel A offset */
243#define CHB 0x40 /* channel B offset */
244
245/*
246 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
247 */
248#undef PVR
249
250#define RXFIFO 0
251#define TXFIFO 0
252#define STAR 0x20
253#define CMDR 0x20
254#define RSTA 0x21
255#define PRE 0x21
256#define MODE 0x22
257#define TIMR 0x23
258#define XAD1 0x24
259#define XAD2 0x25
260#define RAH1 0x26
261#define RAH2 0x27
262#define DAFO 0x27
263#define RAL1 0x28
264#define RFC 0x28
265#define RHCR 0x29
266#define RAL2 0x29
267#define RBCL 0x2a
268#define XBCL 0x2a
269#define RBCH 0x2b
270#define XBCH 0x2b
271#define CCR0 0x2c
272#define CCR1 0x2d
273#define CCR2 0x2e
274#define CCR3 0x2f
275#define VSTR 0x34
276#define BGR 0x34
277#define RLCR 0x35
278#define AML 0x36
279#define AMH 0x37
280#define GIS 0x38
281#define IVA 0x38
282#define IPC 0x39
283#define ISR 0x3a
284#define IMR 0x3a
285#define PVR 0x3c
286#define PIS 0x3d
287#define PIM 0x3d
288#define PCR 0x3e
289#define CCR4 0x3f
d12341f9 290
1da177e4 291// IMR/ISR
d12341f9 292
1da177e4
LT		 293#define IRQ_BREAK_ON BIT15 // rx break detected
294#define IRQ_DATAOVERRUN BIT14 // receive data overflow
295#define IRQ_ALLSENT BIT13 // all sent
296#define IRQ_UNDERRUN BIT12 // transmit data underrun
297#define IRQ_TIMER BIT11 // timer interrupt
298#define IRQ_CTS BIT10 // CTS status change
299#define IRQ_TXREPEAT BIT9 // tx message repeat
300#define IRQ_TXFIFO BIT8 // transmit pool ready
301#define IRQ_RXEOM BIT7 // receive message end
302#define IRQ_EXITHUNT BIT6 // receive frame start
303#define IRQ_RXTIME BIT6 // rx char timeout
304#define IRQ_DCD BIT2 // carrier detect status change
305#define IRQ_OVERRUN BIT1 // receive frame overflow
306#define IRQ_RXFIFO BIT0 // receive pool full
d12341f9 307
1da177e4 308// STAR
d12341f9 309
1da177e4
LT		 310#define XFW BIT6 // transmit FIFO write enable
311#define CEC BIT2 // command executing
312#define CTS BIT1 // CTS state
d12341f9 313
1da177e4
LT		 314#define PVR_DTR BIT0
315#define PVR_DSR BIT1
316#define PVR_RI BIT2
317#define PVR_AUTOCTS BIT3
318#define PVR_RS232 0x20 /* 0010b */
319#define PVR_V35 0xe0 /* 1110b */
320#define PVR_RS422 0x40 /* 0100b */
d12341f9
JG		 321
322/* Register access functions */
323
1da177e4
LT		 324#define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
325#define read_reg(info, reg) inb((info)->io_base + (reg))
326
d12341f9 327#define read_reg16(info, reg) inw((info)->io_base + (reg))
1da177e4 328#define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
d12341f9 329
1da177e4
LT		 330#define set_reg_bits(info, reg, mask) \
331 write_reg(info, (reg), \
d12341f9 332 (unsigned char) (read_reg(info, (reg)) | (mask)))
1da177e4
LT		 333#define clear_reg_bits(info, reg, mask) \
334 write_reg(info, (reg), \
d12341f9 335 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
1da177e4
LT		 336/*
337 * interrupt enable/disable routines
d12341f9
JG		 338 */
339static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 340{
341 if (channel == CHA) {
342 info->imra_value |= mask;
343 write_reg16(info, CHA + IMR, info->imra_value);
344 } else {
345 info->imrb_value |= mask;
346 write_reg16(info, CHB + IMR, info->imrb_value);
347 }
348}
d12341f9 349static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 350{
351 if (channel == CHA) {
352 info->imra_value &= ~mask;
353 write_reg16(info, CHA + IMR, info->imra_value);
354 } else {
355 info->imrb_value &= ~mask;
356 write_reg16(info, CHB + IMR, info->imrb_value);
357 }
358}
359
360#define port_irq_disable(info, mask) \
361 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
362
363#define port_irq_enable(info, mask) \
364 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
365
366static void rx_start(MGSLPC_INFO *info);
367static void rx_stop(MGSLPC_INFO *info);
368
eeb46134 369static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 370static void tx_stop(MGSLPC_INFO *info);
371static void tx_set_idle(MGSLPC_INFO *info);
372
373static void get_signals(MGSLPC_INFO *info);
374static void set_signals(MGSLPC_INFO *info);
375
376static void reset_device(MGSLPC_INFO *info);
377
378static void hdlc_mode(MGSLPC_INFO *info);
379static void async_mode(MGSLPC_INFO *info);
380
381static void tx_timeout(unsigned long context);
382
eeb46134 383static int carrier_raised(struct tty_port *port);
fcc8ac18 384static void dtr_rts(struct tty_port *port, int onoff);
1da177e4 385
af69c7f9 386#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 387#define dev_to_port(D) (dev_to_hdlc(D)->priv)
388static void hdlcdev_tx_done(MGSLPC_INFO *info);
389static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
390static int hdlcdev_init(MGSLPC_INFO *info);
391static void hdlcdev_exit(MGSLPC_INFO *info);
392#endif
393
394static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
395
0fab6de0
JP		 396static bool register_test(MGSLPC_INFO *info);
397static bool irq_test(MGSLPC_INFO *info);
1da177e4
LT		 398static int adapter_test(MGSLPC_INFO *info);
399
400static int claim_resources(MGSLPC_INFO *info);
401static void release_resources(MGSLPC_INFO *info);
402static void mgslpc_add_device(MGSLPC_INFO *info);
403static void mgslpc_remove_device(MGSLPC_INFO *info);
404
eeb46134 405static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 406static void rx_reset_buffers(MGSLPC_INFO *info);
407static int rx_alloc_buffers(MGSLPC_INFO *info);
408static void rx_free_buffers(MGSLPC_INFO *info);
409
7d12e780 410static irqreturn_t mgslpc_isr(int irq, void *dev_id);
1da177e4
LT		 411
412/*
413 * Bottom half interrupt handlers
414 */
c4028958 415static void bh_handler(struct work_struct *work);
eeb46134 416static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 417static void bh_status(MGSLPC_INFO *info);
418
419/*
420 * ioctl handlers
421 */
422static int tiocmget(struct tty_struct *tty, struct file *file);
423static int tiocmset(struct tty_struct *tty, struct file *file,
424 unsigned int set, unsigned int clear);
425static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
426static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
eeb46134 427static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
1da177e4
LT		 428static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
429static int set_txidle(MGSLPC_INFO *info, int idle_mode);
eeb46134 430static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
1da177e4
LT		 431static int tx_abort(MGSLPC_INFO *info);
432static int set_rxenable(MGSLPC_INFO *info, int enable);
433static int wait_events(MGSLPC_INFO *info, int __user *mask);
434
435static MGSLPC_INFO *mgslpc_device_list = NULL;
436static int mgslpc_device_count = 0;
437
438/*
439 * Set this param to non-zero to load eax with the
440 * .text section address and breakpoint on module load.
441 * This is useful for use with gdb and add-symbol-file command.
442 */
443static int break_on_load=0;
444
445/*
446 * Driver major number, defaults to zero to get auto
447 * assigned major number. May be forced as module parameter.
448 */
449static int ttymajor=0;
450
451static int debug_level = 0;
452static int maxframe[MAX_DEVICE_COUNT] = {0,};
1da177e4
LT		 453
454module_param(break_on_load, bool, 0);
455module_param(ttymajor, int, 0);
456module_param(debug_level, int, 0);
457module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 458
459MODULE_LICENSE("GPL");
460
461static char *driver_name = "SyncLink PC Card driver";
a7482a2e 462static char *driver_version = "$Revision: 4.34 $";
1da177e4
LT		 463
464static struct tty_driver *serial_driver;
465
466/* number of characters left in xmit buffer before we ask for more */
467#define WAKEUP_CHARS 256
468
eeb46134 469static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 470static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
471
472/* PCMCIA prototypes */
473
15b99ac1 474static int mgslpc_config(struct pcmcia_device *link);
1da177e4 475static void mgslpc_release(u_long arg);
cc3b4866 476static void mgslpc_detach(struct pcmcia_device *p_dev);
1da177e4 477
1da177e4
LT		 478/*
479 * 1st function defined in .text section. Calling this function in
480 * init_module() followed by a breakpoint allows a remote debugger
481 * (gdb) to get the .text address for the add-symbol-file command.
482 * This allows remote debugging of dynamically loadable modules.
483 */
484static void* mgslpc_get_text_ptr(void)
485{
486 return mgslpc_get_text_ptr;
487}
488
489/**
490 * line discipline callback wrappers
491 *
492 * The wrappers maintain line discipline references
493 * while calling into the line discipline.
494 *
1da177e4
LT		 495 * ldisc_receive_buf - pass receive data to line discipline
496 */
497
1da177e4
LT		 498static void ldisc_receive_buf(struct tty_struct *tty,
499 const __u8 *data, char *flags, int count)
500{
501 struct tty_ldisc *ld;
502 if (!tty)
503 return;
504 ld = tty_ldisc_ref(tty);
505 if (ld) {
a352def2
AC		 506 if (ld->ops->receive_buf)
507 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 508 tty_ldisc_deref(ld);
509 }
510}
511
eeb46134
AC		 512static const struct tty_port_operations mgslpc_port_ops = {
513 .carrier_raised = carrier_raised,
fcc8ac18 514 .dtr_rts = dtr_rts
eeb46134
AC		 515};
516
15b99ac1 517static int mgslpc_probe(struct pcmcia_device *link)
1da177e4
LT		 518{
519 MGSLPC_INFO *info;
15b99ac1 520 int ret;
fd238232 521
1da177e4
LT		 522 if (debug_level >= DEBUG_LEVEL_INFO)
523 printk("mgslpc_attach\n");
fd238232 524
dd00cc48 525 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
1da177e4
LT		 526 if (!info) {
527 printk("Error can't allocate device instance data\n");
f8cfa618 528 return -ENOMEM;
1da177e4
LT		 529 }
530
1da177e4 531 info->magic = MGSLPC_MAGIC;
eeb46134
AC		 532 tty_port_init(&info->port);
533 info->port.ops = &mgslpc_port_ops;
c4028958 534 INIT_WORK(&info->task, bh_handler);
1da177e4 535 info->max_frame_size = 4096;
eeb46134
AC		 536 info->port.close_delay = 5*HZ/10;
537 info->port.closing_wait = 30*HZ;
1da177e4
LT		 538 init_waitqueue_head(&info->status_event_wait_q);
539 init_waitqueue_head(&info->event_wait_q);
540 spin_lock_init(&info->lock);
541 spin_lock_init(&info->netlock);
542 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
d12341f9 543 info->idle_mode = HDLC_TXIDLE_FLAGS;
1da177e4
LT		 544 info->imra_value = 0xffff;
545 info->imrb_value = 0xffff;
546 info->pim_value = 0xff;
547
fba395ee 548 info->p_dev = link;
1da177e4 549 link->priv = info;
fd238232 550
fba395ee 551 /* Initialize the struct pcmcia_device structure */
1da177e4 552
1da177e4 553 link->conf.Attributes = 0;
1da177e4
LT		 554 link->conf.IntType = INT_MEMORY_AND_IO;
555
15b99ac1
DB		 556 ret = mgslpc_config(link);
557 if (ret)
558 return ret;
1da177e4
LT		 559
560 mgslpc_add_device(info);
561
f8cfa618 562 return 0;
1da177e4
LT		 563}
564
565/* Card has been inserted.
566 */
567
aaa8cfda
DB		 568static int mgslpc_ioprobe(struct pcmcia_device *p_dev,
569 cistpl_cftable_entry_t *cfg,
570 cistpl_cftable_entry_t *dflt,
571 unsigned int vcc,
572 void *priv_data)
573{
90abdc3b
DB		 574 if (!cfg->io.nwin)
575 return -ENODEV;
576
577 p_dev->resource[0]->start = cfg->io.win[0].base;
578 p_dev->resource[0]->end = cfg->io.win[0].len;
579 p_dev->resource[0]->flags |= pcmcia_io_cfg_data_width(cfg->io.flags);
580 p_dev->io_lines = cfg->io.flags & CISTPL_IO_LINES_MASK;
581
582 return pcmcia_request_io(p_dev);
aaa8cfda
DB		 583}
584
15b99ac1 585static int mgslpc_config(struct pcmcia_device *link)
1da177e4 586{
1da177e4 587 MGSLPC_INFO *info = link->priv;
cbf624f0 588 int ret;
d12341f9 589
1da177e4
LT		 590 if (debug_level >= DEBUG_LEVEL_INFO)
591 printk("mgslpc_config(0x%p)\n", link);
592
cbf624f0
DB		 593 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
594 if (ret != 0)
595 goto failed;
1da177e4 596
1da177e4 597 link->conf.Attributes = CONF_ENABLE_IRQ;
1da177e4
LT		 598 link->conf.IntType = INT_MEMORY_AND_IO;
599 link->conf.ConfigIndex = 8;
600 link->conf.Present = PRESENT_OPTION;
d12341f9 601
eb14120f 602 ret = pcmcia_request_irq(link, mgslpc_isr);
cbf624f0
DB		 603 if (ret)
604 goto failed;
605 ret = pcmcia_request_configuration(link, &link->conf);
606 if (ret)
607 goto failed;
1da177e4 608
9a017a91 609 info->io_base = link->resource[0]->start;
eb14120f 610 info->irq_level = link->irq;
1da177e4 611
ded6a1a3
DB		 612 dev_info(&link->dev, "index 0x%02x:",
613 link->conf.ConfigIndex);
1da177e4 614 if (link->conf.Attributes & CONF_ENABLE_IRQ)
eb14120f 615 printk(", irq %d", link->irq);
9a017a91
DB		 616 if (link->resource[0])
617 printk(", io %pR", link->resource[0]);
1da177e4 618 printk("\n");
15b99ac1 619 return 0;
1da177e4 620
cbf624f0 621failed:
1da177e4 622 mgslpc_release((u_long)link);
15b99ac1 623 return -ENODEV;
1da177e4
LT		 624}
625
626/* Card has been removed.
627 * Unregister device and release PCMCIA configuration.
628 * If device is open, postpone until it is closed.
629 */
630static void mgslpc_release(u_long arg)
631{
e2d40963 632 struct pcmcia_device *link = (struct pcmcia_device *)arg;
1da177e4 633
e2d40963
DB		 634 if (debug_level >= DEBUG_LEVEL_INFO)
635 printk("mgslpc_release(0x%p)\n", link);
1da177e4 636
e2d40963 637 pcmcia_disable_device(link);
1da177e4
LT		 638}
639
fba395ee 640static void mgslpc_detach(struct pcmcia_device *link)
1da177e4 641{
e2d40963
DB		 642 if (debug_level >= DEBUG_LEVEL_INFO)
643 printk("mgslpc_detach(0x%p)\n", link);
cc3b4866 644
e2d40963
DB		 645 ((MGSLPC_INFO *)link->priv)->stop = 1;
646 mgslpc_release((u_long)link);
1da177e4 647
e2d40963 648 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
1da177e4
LT		 649}
650
fba395ee 651static int mgslpc_suspend(struct pcmcia_device *link)
98e4c28b 652{
98e4c28b
DB		 653 MGSLPC_INFO *info = link->priv;
654
98e4c28b 655 info->stop = 1;
98e4c28b
DB		 656
657 return 0;
658}
659
fba395ee 660static int mgslpc_resume(struct pcmcia_device *link)
98e4c28b 661{
98e4c28b
DB		 662 MGSLPC_INFO *info = link->priv;
663
98e4c28b
DB		 664 info->stop = 0;
665
666 return 0;
667}
668
669
0fab6de0 670static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
1da177e4
LT		 671 char *name, const char *routine)
672{
673#ifdef MGSLPC_PARANOIA_CHECK
674 static const char *badmagic =
675 "Warning: bad magic number for mgsl struct (%s) in %s\n";
676 static const char *badinfo =
677 "Warning: null mgslpc_info for (%s) in %s\n";
678
679 if (!info) {
680 printk(badinfo, name, routine);
0fab6de0 681 return true;
1da177e4
LT		 682 }
683 if (info->magic != MGSLPC_MAGIC) {
684 printk(badmagic, name, routine);
0fab6de0 685 return true;
1da177e4
LT		 686 }
687#else
688 if (!info)
0fab6de0 689 return true;
1da177e4 690#endif
0fab6de0 691 return false;
1da177e4
LT		 692}
693
694
695#define CMD_RXFIFO BIT7 // release current rx FIFO
696#define CMD_RXRESET BIT6 // receiver reset
697#define CMD_RXFIFO_READ BIT5
698#define CMD_START_TIMER BIT4
699#define CMD_TXFIFO BIT3 // release current tx FIFO
700#define CMD_TXEOM BIT1 // transmit end message
701#define CMD_TXRESET BIT0 // transmit reset
702
0fab6de0 703static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
1da177e4
LT		 704{
705 int i = 0;
d12341f9 706 /* wait for command completion */
1da177e4
LT		 707 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
708 udelay(1);
709 if (i++ == 1000)
0fab6de0 710 return false;
1da177e4 711 }
0fab6de0 712 return true;
1da177e4
LT		 713}
714
d12341f9 715static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
1da177e4
LT		 716{
717 wait_command_complete(info, channel);
718 write_reg(info, (unsigned char) (channel + CMDR), cmd);
719}
720
721static void tx_pause(struct tty_struct *tty)
722{
723 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
724 unsigned long flags;
d12341f9 725
1da177e4
LT		 726 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
727 return;
728 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 729 printk("tx_pause(%s)\n",info->device_name);
730
1da177e4
LT		 731 spin_lock_irqsave(&info->lock,flags);
732 if (info->tx_enabled)
733 tx_stop(info);
734 spin_unlock_irqrestore(&info->lock,flags);
735}
736
737static void tx_release(struct tty_struct *tty)
738{
739 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
740 unsigned long flags;
d12341f9 741
1da177e4
LT		 742 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
743 return;
744 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 745 printk("tx_release(%s)\n",info->device_name);
746
1da177e4
LT		 747 spin_lock_irqsave(&info->lock,flags);
748 if (!info->tx_enabled)
eeb46134 749 tx_start(info, tty);
1da177e4
LT		 750 spin_unlock_irqrestore(&info->lock,flags);
751}
752
753/* Return next bottom half action to perform.
754 * or 0 if nothing to do.
755 */
756static int bh_action(MGSLPC_INFO *info)
757{
758 unsigned long flags;
759 int rc = 0;
d12341f9 760
1da177e4
LT		 761 spin_lock_irqsave(&info->lock,flags);
762
763 if (info->pending_bh & BH_RECEIVE) {
764 info->pending_bh &= ~BH_RECEIVE;
765 rc = BH_RECEIVE;
766 } else if (info->pending_bh & BH_TRANSMIT) {
767 info->pending_bh &= ~BH_TRANSMIT;
768 rc = BH_TRANSMIT;
769 } else if (info->pending_bh & BH_STATUS) {
770 info->pending_bh &= ~BH_STATUS;
771 rc = BH_STATUS;
772 }
773
774 if (!rc) {
775 /* Mark BH routine as complete */
0fab6de0
JP		 776 info->bh_running = false;
777 info->bh_requested = false;
1da177e4 778 }
d12341f9 779
1da177e4 780 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 781
1da177e4
LT		 782 return rc;
783}
784
c4028958 785static void bh_handler(struct work_struct *work)
1da177e4 786{
c4028958 787 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
eeb46134 788 struct tty_struct *tty;
1da177e4
LT		 789 int action;
790
791 if (!info)
792 return;
d12341f9 793
1da177e4
LT		 794 if (debug_level >= DEBUG_LEVEL_BH)
795 printk( "%s(%d):bh_handler(%s) entry\n",
796 __FILE__,__LINE__,info->device_name);
d12341f9 797
0fab6de0 798 info->bh_running = true;
eeb46134 799 tty = tty_port_tty_get(&info->port);
1da177e4
LT		 800
801 while((action = bh_action(info)) != 0) {
d12341f9 802
1da177e4
LT		 803 /* Process work item */
804 if ( debug_level >= DEBUG_LEVEL_BH )
805 printk( "%s(%d):bh_handler() work item action=%d\n",
806 __FILE__,__LINE__,action);
807
808 switch (action) {
d12341f9 809
1da177e4 810 case BH_RECEIVE:
eeb46134 811 while(rx_get_frame(info, tty));
1da177e4
LT		 812 break;
813 case BH_TRANSMIT:
eeb46134 814 bh_transmit(info, tty);
1da177e4
LT		 815 break;
816 case BH_STATUS:
817 bh_status(info);
818 break;
819 default:
820 /* unknown work item ID */
821 printk("Unknown work item ID=%08X!\n", action);
822 break;
823 }
824 }
825
eeb46134 826 tty_kref_put(tty);
1da177e4
LT		 827 if (debug_level >= DEBUG_LEVEL_BH)
828 printk( "%s(%d):bh_handler(%s) exit\n",
829 __FILE__,__LINE__,info->device_name);
830}
831
eeb46134 832static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4 833{
1da177e4
LT		 834 if (debug_level >= DEBUG_LEVEL_BH)
835 printk("bh_transmit() entry on %s\n", info->device_name);
836
b963a844 837 if (tty)
1da177e4 838 tty_wakeup(tty);
1da177e4
LT		 839}
840
cdaad343 841static void bh_status(MGSLPC_INFO *info)
1da177e4
LT		 842{
843 info->ri_chkcount = 0;
844 info->dsr_chkcount = 0;
845 info->dcd_chkcount = 0;
846 info->cts_chkcount = 0;
847}
848
d12341f9 849/* eom: non-zero = end of frame */
1da177e4
LT		 850static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
851{
852 unsigned char data[2];
853 unsigned char fifo_count, read_count, i;
854 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
855
856 if (debug_level >= DEBUG_LEVEL_ISR)
857 printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
d12341f9 858
1da177e4
LT		 859 if (!info->rx_enabled)
860 return;
861
862 if (info->rx_frame_count >= info->rx_buf_count) {
863 /* no more free buffers */
864 issue_command(info, CHA, CMD_RXRESET);
865 info->pending_bh |= BH_RECEIVE;
0fab6de0 866 info->rx_overflow = true;
1da177e4
LT		 867 info->icount.buf_overrun++;
868 return;
869 }
870
871 if (eom) {
d12341f9 872 /* end of frame, get FIFO count from RBCL register */
1da177e4
LT		 873 if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
874 fifo_count = 32;
875 } else
876 fifo_count = 32;
d12341f9 877
1da177e4
LT		 878 do {
879 if (fifo_count == 1) {
880 read_count = 1;
881 data[0] = read_reg(info, CHA + RXFIFO);
882 } else {
883 read_count = 2;
884 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
885 }
886 fifo_count -= read_count;
887 if (!fifo_count && eom)
888 buf->status = data[--read_count];
889
890 for (i = 0; i < read_count; i++) {
891 if (buf->count >= info->max_frame_size) {
892 /* frame too large, reset receiver and reset current buffer */
893 issue_command(info, CHA, CMD_RXRESET);
894 buf->count = 0;
895 return;
896 }
897 *(buf->data + buf->count) = data[i];
898 buf->count++;
899 }
900 } while (fifo_count);
901
902 if (eom) {
903 info->pending_bh |= BH_RECEIVE;
904 info->rx_frame_count++;
905 info->rx_put++;
906 if (info->rx_put >= info->rx_buf_count)
907 info->rx_put = 0;
908 }
909 issue_command(info, CHA, CMD_RXFIFO);
910}
911
eeb46134 912static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
1da177e4 913{
33f0f88f 914 unsigned char data, status, flag;
1da177e4 915 int fifo_count;
33f0f88f 916 int work = 0;
1da177e4
LT		 917 struct mgsl_icount *icount = &info->icount;
918
919 if (tcd) {
d12341f9 920 /* early termination, get FIFO count from RBCL register */
1da177e4
LT		 921 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
922
923 /* Zero fifo count could mean 0 or 32 bytes available.
924 * If BIT5 of STAR is set then at least 1 byte is available.
925 */
926 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
927 fifo_count = 32;
928 } else
929 fifo_count = 32;
33f0f88f
AC		 930
931 tty_buffer_request_room(tty, fifo_count);
d12341f9 932 /* Flush received async data to receive data buffer. */
1da177e4
LT		 933 while (fifo_count) {
934 data = read_reg(info, CHA + RXFIFO);
935 status = read_reg(info, CHA + RXFIFO);
936 fifo_count -= 2;
937
1da177e4 938 icount->rx++;
33f0f88f 939 flag = TTY_NORMAL;
1da177e4
LT		 940
941 // if no frameing/crc error then save data
942 // BIT7:parity error
943 // BIT6:framing error
944
945 if (status & (BIT7 + BIT6)) {
d12341f9 946 if (status & BIT7)
1da177e4
LT		 947 icount->parity++;
948 else
949 icount->frame++;
950
951 /* discard char if tty control flags say so */
952 if (status & info->ignore_status_mask)
953 continue;
d12341f9 954
1da177e4
LT		 955 status &= info->read_status_mask;
956
957 if (status & BIT7)
33f0f88f 958 flag = TTY_PARITY;
1da177e4 959 else if (status & BIT6)
33f0f88f 960 flag = TTY_FRAME;
1da177e4 961 }
33f0f88f 962 work += tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 963 }
964 issue_command(info, CHA, CMD_RXFIFO);
965
966 if (debug_level >= DEBUG_LEVEL_ISR) {
33f0f88f
AC		 967 printk("%s(%d):rx_ready_async",
968 __FILE__,__LINE__);
1da177e4
LT		 969 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
970 __FILE__,__LINE__,icount->rx,icount->brk,
971 icount->parity,icount->frame,icount->overrun);
972 }
d12341f9 973
33f0f88f 974 if (work)
1da177e4
LT		 975 tty_flip_buffer_push(tty);
976}
977
978
eeb46134 979static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 980{
981 if (!info->tx_active)
982 return;
d12341f9 983
0fab6de0
JP		 984 info->tx_active = false;
985 info->tx_aborting = false;
1da177e4
LT		 986
987 if (info->params.mode == MGSL_MODE_ASYNC)
988 return;
989
990 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9
JG		 991 del_timer(&info->tx_timer);
992
1da177e4
LT		 993 if (info->drop_rts_on_tx_done) {
994 get_signals(info);
995 if (info->serial_signals & SerialSignal_RTS) {
996 info->serial_signals &= ~SerialSignal_RTS;
997 set_signals(info);
998 }
0fab6de0 999 info->drop_rts_on_tx_done = false;
1da177e4
LT		 1000 }
1001
af69c7f9 1002#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 1003 if (info->netcount)
1004 hdlcdev_tx_done(info);
d12341f9 1005 else
1da177e4
LT		 1006#endif
1007 {
eeb46134 1008 if (tty->stopped || tty->hw_stopped) {
1da177e4
LT		 1009 tx_stop(info);
1010 return;
1011 }
1012 info->pending_bh |= BH_TRANSMIT;
1013 }
1014}
1015
eeb46134 1016static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1017{
1018 unsigned char fifo_count = 32;
1019 int c;
1020
1021 if (debug_level >= DEBUG_LEVEL_ISR)
1022 printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
1023
1024 if (info->params.mode == MGSL_MODE_HDLC) {
1025 if (!info->tx_active)
1026 return;
1027 } else {
eeb46134 1028 if (tty->stopped || tty->hw_stopped) {
1da177e4
LT		 1029 tx_stop(info);
1030 return;
1031 }
1032 if (!info->tx_count)
0fab6de0 1033 info->tx_active = false;
1da177e4
LT		 1034 }
1035
1036 if (!info->tx_count)
1037 return;
1038
1039 while (info->tx_count && fifo_count) {
1040 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
d12341f9 1041
1da177e4
LT		 1042 if (c == 1) {
1043 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1044 } else {
1045 write_reg16(info, CHA + TXFIFO,
1046 *((unsigned short*)(info->tx_buf + info->tx_get)));
1047 }
1048 info->tx_count -= c;
1049 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1050 fifo_count -= c;
1051 }
1052
1053 if (info->params.mode == MGSL_MODE_ASYNC) {
1054 if (info->tx_count < WAKEUP_CHARS)
1055 info->pending_bh |= BH_TRANSMIT;
1056 issue_command(info, CHA, CMD_TXFIFO);
1057 } else {
1058 if (info->tx_count)
1059 issue_command(info, CHA, CMD_TXFIFO);
1060 else
1061 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1062 }
1063}
1064
eeb46134 1065static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1066{
1067 get_signals(info);
1068 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1069 irq_disable(info, CHB, IRQ_CTS);
1070 info->icount.cts++;
1071 if (info->serial_signals & SerialSignal_CTS)
1072 info->input_signal_events.cts_up++;
1073 else
1074 info->input_signal_events.cts_down++;
1075 wake_up_interruptible(&info->status_event_wait_q);
1076 wake_up_interruptible(&info->event_wait_q);
1077
eeb46134
AC		 1078 if (info->port.flags & ASYNC_CTS_FLOW) {
1079 if (tty->hw_stopped) {
1da177e4
LT		 1080 if (info->serial_signals & SerialSignal_CTS) {
1081 if (debug_level >= DEBUG_LEVEL_ISR)
1082 printk("CTS tx start...");
eeb46134
AC		 1083 if (tty)
1084 tty->hw_stopped = 0;
1085 tx_start(info, tty);
1da177e4
LT		 1086 info->pending_bh |= BH_TRANSMIT;
1087 return;
1088 }
1089 } else {
1090 if (!(info->serial_signals & SerialSignal_CTS)) {
1091 if (debug_level >= DEBUG_LEVEL_ISR)
1092 printk("CTS tx stop...");
eeb46134
AC		 1093 if (tty)
1094 tty->hw_stopped = 1;
1da177e4
LT		 1095 tx_stop(info);
1096 }
1097 }
1098 }
1099 info->pending_bh |= BH_STATUS;
1100}
1101
eeb46134 1102static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1103{
1104 get_signals(info);
1105 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1106 irq_disable(info, CHB, IRQ_DCD);
1107 info->icount.dcd++;
1108 if (info->serial_signals & SerialSignal_DCD) {
1109 info->input_signal_events.dcd_up++;
1110 }
1111 else
1112 info->input_signal_events.dcd_down++;
af69c7f9 1113#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1114 if (info->netcount) {
1115 if (info->serial_signals & SerialSignal_DCD)
1116 netif_carrier_on(info->netdev);
1117 else
1118 netif_carrier_off(info->netdev);
1119 }
1da177e4
LT		 1120#endif
1121 wake_up_interruptible(&info->status_event_wait_q);
1122 wake_up_interruptible(&info->event_wait_q);
1123
eeb46134 1124 if (info->port.flags & ASYNC_CHECK_CD) {
1da177e4
LT		 1125 if (debug_level >= DEBUG_LEVEL_ISR)
1126 printk("%s CD now %s...", info->device_name,
1127 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1128 if (info->serial_signals & SerialSignal_DCD)
eeb46134 1129 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1130 else {
1131 if (debug_level >= DEBUG_LEVEL_ISR)
1132 printk("doing serial hangup...");
eeb46134
AC		 1133 if (tty)
1134 tty_hangup(tty);
1da177e4
LT		 1135 }
1136 }
1137 info->pending_bh |= BH_STATUS;
1138}
1139
1140static void dsr_change(MGSLPC_INFO *info)
1141{
1142 get_signals(info);
1143 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1144 port_irq_disable(info, PVR_DSR);
1145 info->icount.dsr++;
1146 if (info->serial_signals & SerialSignal_DSR)
1147 info->input_signal_events.dsr_up++;
1148 else
1149 info->input_signal_events.dsr_down++;
1150 wake_up_interruptible(&info->status_event_wait_q);
1151 wake_up_interruptible(&info->event_wait_q);
1152 info->pending_bh |= BH_STATUS;
1153}
1154
1155static void ri_change(MGSLPC_INFO *info)
1156{
1157 get_signals(info);
1158 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1159 port_irq_disable(info, PVR_RI);
1160 info->icount.rng++;
1161 if (info->serial_signals & SerialSignal_RI)
1162 info->input_signal_events.ri_up++;
1163 else
1164 info->input_signal_events.ri_down++;
1165 wake_up_interruptible(&info->status_event_wait_q);
1166 wake_up_interruptible(&info->event_wait_q);
1167 info->pending_bh |= BH_STATUS;
1168}
1169
1170/* Interrupt service routine entry point.
d12341f9 1171 *
1da177e4 1172 * Arguments:
d12341f9 1173 *
1da177e4
LT		 1174 * irq interrupt number that caused interrupt
1175 * dev_id device ID supplied during interrupt registration
1da177e4 1176 */
a6f97b29 1177static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
1da177e4 1178{
a6f97b29 1179 MGSLPC_INFO *info = dev_id;
eeb46134 1180 struct tty_struct *tty;
1da177e4
LT		 1181 unsigned short isr;
1182 unsigned char gis, pis;
1183 int count=0;
1184
d12341f9 1185 if (debug_level >= DEBUG_LEVEL_ISR)
a6f97b29 1186 printk("mgslpc_isr(%d) entry.\n", info->irq_level);
d12341f9 1187
e2d40963 1188 if (!(info->p_dev->_locked))
1da177e4
LT		 1189 return IRQ_HANDLED;
1190
eeb46134
AC		 1191 tty = tty_port_tty_get(&info->port);
1192
1da177e4
LT		 1193 spin_lock(&info->lock);
1194
1195 while ((gis = read_reg(info, CHA + GIS))) {
d12341f9 1196 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1197 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1198
1199 if ((gis & 0x70) || count > 1000) {
1200 printk("synclink_cs:hardware failed or ejected\n");
1201 break;
1202 }
1203 count++;
1204
1205 if (gis & (BIT1 + BIT0)) {
1206 isr = read_reg16(info, CHB + ISR);
1207 if (isr & IRQ_DCD)
eeb46134 1208 dcd_change(info, tty);
1da177e4 1209 if (isr & IRQ_CTS)
eeb46134 1210 cts_change(info, tty);
1da177e4
LT		 1211 }
1212 if (gis & (BIT3 + BIT2))
1213 {
1214 isr = read_reg16(info, CHA + ISR);
1215 if (isr & IRQ_TIMER) {
0fab6de0 1216 info->irq_occurred = true;
1da177e4
LT		 1217 irq_disable(info, CHA, IRQ_TIMER);
1218 }
1219
d12341f9 1220 /* receive IRQs */
1da177e4
LT		 1221 if (isr & IRQ_EXITHUNT) {
1222 info->icount.exithunt++;
1223 wake_up_interruptible(&info->event_wait_q);
1224 }
1225 if (isr & IRQ_BREAK_ON) {
1226 info->icount.brk++;
eeb46134
AC		 1227 if (info->port.flags & ASYNC_SAK)
1228 do_SAK(tty);
1da177e4
LT		 1229 }
1230 if (isr & IRQ_RXTIME) {
1231 issue_command(info, CHA, CMD_RXFIFO_READ);
1232 }
1233 if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
1234 if (info->params.mode == MGSL_MODE_HDLC)
d12341f9 1235 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1da177e4 1236 else
eeb46134 1237 rx_ready_async(info, isr & IRQ_RXEOM, tty);
1da177e4
LT		 1238 }
1239
d12341f9 1240 /* transmit IRQs */
1da177e4
LT		 1241 if (isr & IRQ_UNDERRUN) {
1242 if (info->tx_aborting)
1243 info->icount.txabort++;
1244 else
1245 info->icount.txunder++;
eeb46134 1246 tx_done(info, tty);
1da177e4
LT		 1247 }
1248 else if (isr & IRQ_ALLSENT) {
1249 info->icount.txok++;
eeb46134 1250 tx_done(info, tty);
1da177e4
LT		 1251 }
1252 else if (isr & IRQ_TXFIFO)
eeb46134 1253 tx_ready(info, tty);
1da177e4
LT		 1254 }
1255 if (gis & BIT7) {
1256 pis = read_reg(info, CHA + PIS);
1257 if (pis & BIT1)
1258 dsr_change(info);
1259 if (pis & BIT2)
1260 ri_change(info);
1261 }
1262 }
d12341f9
JG		 1263
1264 /* Request bottom half processing if there's something
1da177e4
LT		 1265 * for it to do and the bh is not already running
1266 */
1267
1268 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
d12341f9 1269 if ( debug_level >= DEBUG_LEVEL_ISR )
1da177e4
LT		 1270 printk("%s(%d):%s queueing bh task.\n",
1271 __FILE__,__LINE__,info->device_name);
1272 schedule_work(&info->task);
0fab6de0 1273 info->bh_requested = true;
1da177e4
LT		 1274 }
1275
1276 spin_unlock(&info->lock);
eeb46134 1277 tty_kref_put(tty);
d12341f9
JG		 1278
1279 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4 1280 printk("%s(%d):mgslpc_isr(%d)exit.\n",
a6f97b29 1281 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 1282
1283 return IRQ_HANDLED;
1284}
1285
1286/* Initialize and start device.
1287 */
eeb46134 1288static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1289{
1290 int retval = 0;
d12341f9 1291
1da177e4
LT		 1292 if (debug_level >= DEBUG_LEVEL_INFO)
1293 printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
d12341f9 1294
eeb46134 1295 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4 1296 return 0;
d12341f9 1297
1da177e4
LT		 1298 if (!info->tx_buf) {
1299 /* allocate a page of memory for a transmit buffer */
1300 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1301 if (!info->tx_buf) {
1302 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1303 __FILE__,__LINE__,info->device_name);
1304 return -ENOMEM;
1305 }
1306 }
1307
1308 info->pending_bh = 0;
d12341f9 1309
a7482a2e
PF		 1310 memset(&info->icount, 0, sizeof(info->icount));
1311
40565f19 1312 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
1da177e4
LT		 1313
1314 /* Allocate and claim adapter resources */
1315 retval = claim_resources(info);
d12341f9 1316
1da177e4
LT		 1317 /* perform existance check and diagnostics */
1318 if ( !retval )
1319 retval = adapter_test(info);
d12341f9 1320
1da177e4 1321 if ( retval ) {
eeb46134
AC		 1322 if (capable(CAP_SYS_ADMIN) && tty)
1323 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4
LT		 1324 release_resources(info);
1325 return retval;
1326 }
1327
1328 /* program hardware for current parameters */
eeb46134 1329 mgslpc_change_params(info, tty);
d12341f9 1330
eeb46134
AC		 1331 if (tty)
1332 clear_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1333
eeb46134 1334 info->port.flags |= ASYNC_INITIALIZED;
d12341f9 1335
1da177e4
LT		 1336 return 0;
1337}
1338
1339/* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1340 */
eeb46134 1341static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1342{
1343 unsigned long flags;
d12341f9 1344
eeb46134 1345 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1346 return;
1347
1348 if (debug_level >= DEBUG_LEVEL_INFO)
1349 printk("%s(%d):mgslpc_shutdown(%s)\n",
1350 __FILE__,__LINE__, info->device_name );
1351
1352 /* clear status wait queue because status changes */
1353 /* can't happen after shutting down the hardware */
1354 wake_up_interruptible(&info->status_event_wait_q);
1355 wake_up_interruptible(&info->event_wait_q);
1356
40565f19 1357 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1358
1359 if (info->tx_buf) {
1360 free_page((unsigned long) info->tx_buf);
1361 info->tx_buf = NULL;
1362 }
1363
1364 spin_lock_irqsave(&info->lock,flags);
1365
1366 rx_stop(info);
1367 tx_stop(info);
1368
1369 /* TODO:disable interrupts instead of reset to preserve signal states */
1370 reset_device(info);
d12341f9 1371
eeb46134 1372 if (!tty || tty->termios->c_cflag & HUPCL) {
1da177e4
LT		 1373 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1374 set_signals(info);
1375 }
d12341f9 1376
1da177e4
LT		 1377 spin_unlock_irqrestore(&info->lock,flags);
1378
d12341f9
JG		 1379 release_resources(info);
1380
eeb46134
AC		 1381 if (tty)
1382 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1383
eeb46134 1384 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 1385}
1386
eeb46134 1387static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1388{
1389 unsigned long flags;
1390
1391 spin_lock_irqsave(&info->lock,flags);
d12341f9 1392
1da177e4
LT		 1393 rx_stop(info);
1394 tx_stop(info);
1395 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1396
1da177e4
LT		 1397 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1398 hdlc_mode(info);
1399 else
1400 async_mode(info);
d12341f9 1401
1da177e4 1402 set_signals(info);
d12341f9 1403
1da177e4
LT		 1404 info->dcd_chkcount = 0;
1405 info->cts_chkcount = 0;
1406 info->ri_chkcount = 0;
1407 info->dsr_chkcount = 0;
1408
1409 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1410 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1411 get_signals(info);
d12341f9 1412
eeb46134 1413 if (info->netcount || (tty && (tty->termios->c_cflag & CREAD)))
1da177e4 1414 rx_start(info);
d12341f9 1415
1da177e4
LT		 1416 spin_unlock_irqrestore(&info->lock,flags);
1417}
1418
1419/* Reconfigure adapter based on new parameters
1420 */
eeb46134 1421static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1422{
1423 unsigned cflag;
1424 int bits_per_char;
1425
eeb46134 1426 if (!tty || !tty->termios)
1da177e4 1427 return;
d12341f9 1428
1da177e4
LT		 1429 if (debug_level >= DEBUG_LEVEL_INFO)
1430 printk("%s(%d):mgslpc_change_params(%s)\n",
1431 __FILE__,__LINE__, info->device_name );
d12341f9 1432
eeb46134 1433 cflag = tty->termios->c_cflag;
1da177e4
LT		 1434
1435 /* if B0 rate (hangup) specified then negate DTR and RTS */
1436 /* otherwise assert DTR and RTS */
1437 if (cflag & CBAUD)
1438 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1439 else
1440 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
d12341f9 1441
1da177e4 1442 /* byte size and parity */
d12341f9 1443
1da177e4
LT		 1444 switch (cflag & CSIZE) {
1445 case CS5: info->params.data_bits = 5; break;
1446 case CS6: info->params.data_bits = 6; break;
1447 case CS7: info->params.data_bits = 7; break;
1448 case CS8: info->params.data_bits = 8; break;
1449 default: info->params.data_bits = 7; break;
1450 }
d12341f9 1451
1da177e4
LT		 1452 if (cflag & CSTOPB)
1453 info->params.stop_bits = 2;
1454 else
1455 info->params.stop_bits = 1;
1456
1457 info->params.parity = ASYNC_PARITY_NONE;
1458 if (cflag & PARENB) {
1459 if (cflag & PARODD)
1460 info->params.parity = ASYNC_PARITY_ODD;
1461 else
1462 info->params.parity = ASYNC_PARITY_EVEN;
1463#ifdef CMSPAR
1464 if (cflag & CMSPAR)
1465 info->params.parity = ASYNC_PARITY_SPACE;
1466#endif
1467 }
1468
1469 /* calculate number of jiffies to transmit a full
1470 * FIFO (32 bytes) at specified data rate
1471 */
d12341f9 1472 bits_per_char = info->params.data_bits +
1da177e4
LT		 1473 info->params.stop_bits + 1;
1474
1475 /* if port data rate is set to 460800 or less then
1476 * allow tty settings to override, otherwise keep the
1477 * current data rate.
1478 */
1479 if (info->params.data_rate <= 460800) {
eeb46134 1480 info->params.data_rate = tty_get_baud_rate(tty);
1da177e4 1481 }
d12341f9 1482
1da177e4 1483 if ( info->params.data_rate ) {
d12341f9 1484 info->timeout = (32*HZ*bits_per_char) /
1da177e4
LT		 1485 info->params.data_rate;
1486 }
1487 info->timeout += HZ/50; /* Add .02 seconds of slop */
1488
1489 if (cflag & CRTSCTS)
eeb46134 1490 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 1491 else
eeb46134 1492 info->port.flags &= ~ASYNC_CTS_FLOW;
d12341f9 1493
1da177e4 1494 if (cflag & CLOCAL)
eeb46134 1495 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 1496 else
eeb46134 1497 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 1498
1499 /* process tty input control flags */
d12341f9 1500
1da177e4 1501 info->read_status_mask = 0;
eeb46134 1502 if (I_INPCK(tty))
1da177e4 1503 info->read_status_mask |= BIT7 | BIT6;
eeb46134 1504 if (I_IGNPAR(tty))
1da177e4
LT		 1505 info->ignore_status_mask |= BIT7 | BIT6;
1506
eeb46134 1507 mgslpc_program_hw(info, tty);
1da177e4
LT		 1508}
1509
1510/* Add a character to the transmit buffer
1511 */
d7e752e2 1512static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4
LT		 1513{
1514 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1515 unsigned long flags;
1516
1517 if (debug_level >= DEBUG_LEVEL_INFO) {
1518 printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
1519 __FILE__,__LINE__,ch,info->device_name);
1520 }
1521
1522 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
d7e752e2 1523 return 0;
1da177e4 1524
326f28e9 1525 if (!info->tx_buf)
d7e752e2 1526 return 0;
1da177e4
LT		 1527
1528 spin_lock_irqsave(&info->lock,flags);
d12341f9 1529
1da177e4
LT		 1530 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1531 if (info->tx_count < TXBUFSIZE - 1) {
1532 info->tx_buf[info->tx_put++] = ch;
1533 info->tx_put &= TXBUFSIZE-1;
1534 info->tx_count++;
1535 }
1536 }
d12341f9 1537
1da177e4 1538 spin_unlock_irqrestore(&info->lock,flags);
d7e752e2 1539 return 1;
1da177e4
LT		 1540}
1541
1542/* Enable transmitter so remaining characters in the
1543 * transmit buffer are sent.
1544 */
1545static void mgslpc_flush_chars(struct tty_struct *tty)
1546{
1547 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1548 unsigned long flags;
d12341f9 1549
1da177e4
LT		 1550 if (debug_level >= DEBUG_LEVEL_INFO)
1551 printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1552 __FILE__,__LINE__,info->device_name,info->tx_count);
d12341f9 1553
1da177e4
LT		 1554 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1555 return;
1556
1557 if (info->tx_count <= 0 || tty->stopped ||
1558 tty->hw_stopped || !info->tx_buf)
1559 return;
1560
1561 if (debug_level >= DEBUG_LEVEL_INFO)
1562 printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1563 __FILE__,__LINE__,info->device_name);
1564
1565 spin_lock_irqsave(&info->lock,flags);
1566 if (!info->tx_active)
eeb46134 1567 tx_start(info, tty);
1da177e4
LT		 1568 spin_unlock_irqrestore(&info->lock,flags);
1569}
1570
1571/* Send a block of data
d12341f9 1572 *
1da177e4 1573 * Arguments:
d12341f9 1574 *
1da177e4
LT		 1575 * tty pointer to tty information structure
1576 * buf pointer to buffer containing send data
1577 * count size of send data in bytes
d12341f9 1578 *
1da177e4
LT		 1579 * Returns: number of characters written
1580 */
1581static int mgslpc_write(struct tty_struct * tty,
1582 const unsigned char *buf, int count)
1583{
1584 int c, ret = 0;
1585 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1586 unsigned long flags;
d12341f9 1587
1da177e4
LT		 1588 if (debug_level >= DEBUG_LEVEL_INFO)
1589 printk( "%s(%d):mgslpc_write(%s) count=%d\n",
1590 __FILE__,__LINE__,info->device_name,count);
d12341f9 1591
1da177e4 1592 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
326f28e9 1593 !info->tx_buf)
1da177e4
LT		 1594 goto cleanup;
1595
1596 if (info->params.mode == MGSL_MODE_HDLC) {
1597 if (count > TXBUFSIZE) {
1598 ret = -EIO;
1599 goto cleanup;
1600 }
1601 if (info->tx_active)
1602 goto cleanup;
1603 else if (info->tx_count)
1604 goto start;
1605 }
1606
1607 for (;;) {
1608 c = min(count,
1609 min(TXBUFSIZE - info->tx_count - 1,
1610 TXBUFSIZE - info->tx_put));
1611 if (c <= 0)
1612 break;
d12341f9 1613
1da177e4
LT		 1614 memcpy(info->tx_buf + info->tx_put, buf, c);
1615
1616 spin_lock_irqsave(&info->lock,flags);
1617 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1618 info->tx_count += c;
1619 spin_unlock_irqrestore(&info->lock,flags);
1620
1621 buf += c;
1622 count -= c;
1623 ret += c;
1624 }
1625start:
1626 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1627 spin_lock_irqsave(&info->lock,flags);
1628 if (!info->tx_active)
eeb46134 1629 tx_start(info, tty);
1da177e4
LT		 1630 spin_unlock_irqrestore(&info->lock,flags);
1631 }
d12341f9 1632cleanup:
1da177e4
LT		 1633 if (debug_level >= DEBUG_LEVEL_INFO)
1634 printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
1635 __FILE__,__LINE__,info->device_name,ret);
1636 return ret;
1637}
1638
1639/* Return the count of free bytes in transmit buffer
1640 */
1641static int mgslpc_write_room(struct tty_struct *tty)
1642{
1643 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1644 int ret;
d12341f9 1645
1da177e4
LT		 1646 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1647 return 0;
1648
1649 if (info->params.mode == MGSL_MODE_HDLC) {
1650 /* HDLC (frame oriented) mode */
1651 if (info->tx_active)
1652 return 0;
1653 else
1654 return HDLC_MAX_FRAME_SIZE;
1655 } else {
1656 ret = TXBUFSIZE - info->tx_count - 1;
1657 if (ret < 0)
1658 ret = 0;
1659 }
d12341f9 1660
1da177e4
LT		 1661 if (debug_level >= DEBUG_LEVEL_INFO)
1662 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
1663 __FILE__,__LINE__, info->device_name, ret);
1664 return ret;
1665}
1666
1667/* Return the count of bytes in transmit buffer
1668 */
1669static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1670{
1671 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1672 int rc;
d12341f9 1673
1da177e4
LT		 1674 if (debug_level >= DEBUG_LEVEL_INFO)
1675 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
1676 __FILE__,__LINE__, info->device_name );
d12341f9 1677
1da177e4
LT		 1678 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1679 return 0;
d12341f9 1680
1da177e4
LT		 1681 if (info->params.mode == MGSL_MODE_HDLC)
1682 rc = info->tx_active ? info->max_frame_size : 0;
1683 else
1684 rc = info->tx_count;
1685
1686 if (debug_level >= DEBUG_LEVEL_INFO)
1687 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
1688 __FILE__,__LINE__, info->device_name, rc);
d12341f9 1689
1da177e4
LT		 1690 return rc;
1691}
1692
1693/* Discard all data in the send buffer
1694 */
1695static void mgslpc_flush_buffer(struct tty_struct *tty)
1696{
1697 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1698 unsigned long flags;
d12341f9 1699
1da177e4
LT		 1700 if (debug_level >= DEBUG_LEVEL_INFO)
1701 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
1702 __FILE__,__LINE__, info->device_name );
d12341f9 1703
1da177e4
LT		 1704 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1705 return;
d12341f9
JG		 1706
1707 spin_lock_irqsave(&info->lock,flags);
1da177e4 1708 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1709 del_timer(&info->tx_timer);
1da177e4
LT		 1710 spin_unlock_irqrestore(&info->lock,flags);
1711
1712 wake_up_interruptible(&tty->write_wait);
1713 tty_wakeup(tty);
1714}
1715
1716/* Send a high-priority XON/XOFF character
1717 */
1718static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1719{
1720 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1721 unsigned long flags;
1722
1723 if (debug_level >= DEBUG_LEVEL_INFO)
1724 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
1725 __FILE__,__LINE__, info->device_name, ch );
d12341f9 1726
1da177e4
LT		 1727 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1728 return;
1729
1730 info->x_char = ch;
1731 if (ch) {
1732 spin_lock_irqsave(&info->lock,flags);
1733 if (!info->tx_enabled)
eeb46134 1734 tx_start(info, tty);
1da177e4
LT		 1735 spin_unlock_irqrestore(&info->lock,flags);
1736 }
1737}
1738
1739/* Signal remote device to throttle send data (our receive data)
1740 */
1741static void mgslpc_throttle(struct tty_struct * tty)
1742{
1743 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1744 unsigned long flags;
d12341f9 1745
1da177e4
LT		 1746 if (debug_level >= DEBUG_LEVEL_INFO)
1747 printk("%s(%d):mgslpc_throttle(%s) entry\n",
1748 __FILE__,__LINE__, info->device_name );
1749
1750 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1751 return;
d12341f9 1752
1da177e4
LT		 1753 if (I_IXOFF(tty))
1754 mgslpc_send_xchar(tty, STOP_CHAR(tty));
d12341f9 1755
1da177e4
LT		 1756 if (tty->termios->c_cflag & CRTSCTS) {
1757 spin_lock_irqsave(&info->lock,flags);
1758 info->serial_signals &= ~SerialSignal_RTS;
1759 set_signals(info);
1760 spin_unlock_irqrestore(&info->lock,flags);
1761 }
1762}
1763
1764/* Signal remote device to stop throttling send data (our receive data)
1765 */
1766static void mgslpc_unthrottle(struct tty_struct * tty)
1767{
1768 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1769 unsigned long flags;
d12341f9 1770
1da177e4
LT		 1771 if (debug_level >= DEBUG_LEVEL_INFO)
1772 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
1773 __FILE__,__LINE__, info->device_name );
1774
1775 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1776 return;
d12341f9 1777
1da177e4
LT		 1778 if (I_IXOFF(tty)) {
1779 if (info->x_char)
1780 info->x_char = 0;
1781 else
1782 mgslpc_send_xchar(tty, START_CHAR(tty));
1783 }
d12341f9 1784
1da177e4
LT		 1785 if (tty->termios->c_cflag & CRTSCTS) {
1786 spin_lock_irqsave(&info->lock,flags);
1787 info->serial_signals |= SerialSignal_RTS;
1788 set_signals(info);
1789 spin_unlock_irqrestore(&info->lock,flags);
1790 }
1791}
1792
1793/* get the current serial statistics
1794 */
1795static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1796{
1797 int err;
1798 if (debug_level >= DEBUG_LEVEL_INFO)
1799 printk("get_params(%s)\n", info->device_name);
a7482a2e
PF		 1800 if (!user_icount) {
1801 memset(&info->icount, 0, sizeof(info->icount));
1802 } else {
1803 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
1804 if (err)
1805 return -EFAULT;
1806 }
1da177e4
LT		 1807 return 0;
1808}
1809
1810/* get the current serial parameters
1811 */
1812static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1813{
1814 int err;
1815 if (debug_level >= DEBUG_LEVEL_INFO)
1816 printk("get_params(%s)\n", info->device_name);
1817 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1818 if (err)
1819 return -EFAULT;
1820 return 0;
1821}
1822
1823/* set the serial parameters
d12341f9 1824 *
1da177e4 1825 * Arguments:
d12341f9 1826 *
1da177e4
LT		 1827 * info pointer to device instance data
1828 * new_params user buffer containing new serial params
1829 *
1830 * Returns: 0 if success, otherwise error code
1831 */
eeb46134 1832static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
1da177e4
LT		 1833{
1834 unsigned long flags;
1835 MGSL_PARAMS tmp_params;
1836 int err;
d12341f9 1837
1da177e4
LT		 1838 if (debug_level >= DEBUG_LEVEL_INFO)
1839 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
1840 info->device_name );
1841 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1842 if (err) {
1843 if ( debug_level >= DEBUG_LEVEL_INFO )
1844 printk( "%s(%d):set_params(%s) user buffer copy failed\n",
1845 __FILE__,__LINE__,info->device_name);
1846 return -EFAULT;
1847 }
d12341f9 1848
1da177e4
LT		 1849 spin_lock_irqsave(&info->lock,flags);
1850 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
1851 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 1852
eeb46134 1853 mgslpc_change_params(info, tty);
d12341f9 1854
1da177e4
LT		 1855 return 0;
1856}
1857
1858static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
1859{
1860 int err;
1861 if (debug_level >= DEBUG_LEVEL_INFO)
1862 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
1863 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
1864 if (err)
1865 return -EFAULT;
1866 return 0;
1867}
1868
1869static int set_txidle(MGSLPC_INFO * info, int idle_mode)
1870{
1871 unsigned long flags;
1872 if (debug_level >= DEBUG_LEVEL_INFO)
1873 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
1874 spin_lock_irqsave(&info->lock,flags);
1875 info->idle_mode = idle_mode;
1876 tx_set_idle(info);
1877 spin_unlock_irqrestore(&info->lock,flags);
1878 return 0;
1879}
1880
1881static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
1882{
1883 int err;
1884 if (debug_level >= DEBUG_LEVEL_INFO)
1885 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
1886 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
1887 if (err)
1888 return -EFAULT;
1889 return 0;
1890}
1891
1892static int set_interface(MGSLPC_INFO * info, int if_mode)
1893{
1894 unsigned long flags;
1895 unsigned char val;
1896 if (debug_level >= DEBUG_LEVEL_INFO)
1897 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
1898 spin_lock_irqsave(&info->lock,flags);
1899 info->if_mode = if_mode;
1900
1901 val = read_reg(info, PVR) & 0x0f;
1902 switch (info->if_mode)
1903 {
1904 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
1905 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
1906 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
1907 }
1908 write_reg(info, PVR, val);
1909
1910 spin_unlock_irqrestore(&info->lock,flags);
1911 return 0;
1912}
1913
eeb46134 1914static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
1da177e4
LT		 1915{
1916 unsigned long flags;
d12341f9 1917
1da177e4
LT		 1918 if (debug_level >= DEBUG_LEVEL_INFO)
1919 printk("set_txenable(%s,%d)\n", info->device_name, enable);
d12341f9 1920
1da177e4
LT		 1921 spin_lock_irqsave(&info->lock,flags);
1922 if (enable) {
1923 if (!info->tx_enabled)
eeb46134 1924 tx_start(info, tty);
1da177e4
LT		 1925 } else {
1926 if (info->tx_enabled)
1927 tx_stop(info);
1928 }
1929 spin_unlock_irqrestore(&info->lock,flags);
1930 return 0;
1931}
1932
1933static int tx_abort(MGSLPC_INFO * info)
1934{
1935 unsigned long flags;
d12341f9 1936
1da177e4
LT		 1937 if (debug_level >= DEBUG_LEVEL_INFO)
1938 printk("tx_abort(%s)\n", info->device_name);
d12341f9 1939
1da177e4
LT		 1940 spin_lock_irqsave(&info->lock,flags);
1941 if (info->tx_active && info->tx_count &&
1942 info->params.mode == MGSL_MODE_HDLC) {
1943 /* clear data count so FIFO is not filled on next IRQ.
1944 * This results in underrun and abort transmission.
1945 */
1946 info->tx_count = info->tx_put = info->tx_get = 0;
0fab6de0 1947 info->tx_aborting = true;
1da177e4
LT		 1948 }
1949 spin_unlock_irqrestore(&info->lock,flags);
1950 return 0;
1951}
1952
1953static int set_rxenable(MGSLPC_INFO * info, int enable)
1954{
1955 unsigned long flags;
d12341f9 1956
1da177e4
LT		 1957 if (debug_level >= DEBUG_LEVEL_INFO)
1958 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
d12341f9 1959
1da177e4
LT		 1960 spin_lock_irqsave(&info->lock,flags);
1961 if (enable) {
1962 if (!info->rx_enabled)
1963 rx_start(info);
1964 } else {
1965 if (info->rx_enabled)
1966 rx_stop(info);
1967 }
1968 spin_unlock_irqrestore(&info->lock,flags);
1969 return 0;
1970}
1971
1972/* wait for specified event to occur
d12341f9 1973 *
1da177e4
LT		 1974 * Arguments: info pointer to device instance data
1975 * mask pointer to bitmask of events to wait for
1976 * Return Value: 0 if successful and bit mask updated with
1977 * of events triggerred,
1978 * otherwise error code
1979 */
1980static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
1981{
1982 unsigned long flags;
1983 int s;
1984 int rc=0;
1985 struct mgsl_icount cprev, cnow;
1986 int events;
1987 int mask;
1988 struct _input_signal_events oldsigs, newsigs;
1989 DECLARE_WAITQUEUE(wait, current);
1990
1991 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
1992 if (rc)
1993 return -EFAULT;
d12341f9 1994
1da177e4
LT		 1995 if (debug_level >= DEBUG_LEVEL_INFO)
1996 printk("wait_events(%s,%d)\n", info->device_name, mask);
1997
1998 spin_lock_irqsave(&info->lock,flags);
1999
2000 /* return immediately if state matches requested events */
2001 get_signals(info);
2002 s = info->serial_signals;
2003 events = mask &
2004 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2005 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2006 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2007 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2008 if (events) {
2009 spin_unlock_irqrestore(&info->lock,flags);
2010 goto exit;
2011 }
2012
2013 /* save current irq counts */
2014 cprev = info->icount;
2015 oldsigs = info->input_signal_events;
d12341f9 2016
1da177e4
LT		 2017 if ((info->params.mode == MGSL_MODE_HDLC) &&
2018 (mask & MgslEvent_ExitHuntMode))
2019 irq_enable(info, CHA, IRQ_EXITHUNT);
d12341f9 2020
1da177e4
LT		 2021 set_current_state(TASK_INTERRUPTIBLE);
2022 add_wait_queue(&info->event_wait_q, &wait);
d12341f9 2023
1da177e4 2024 spin_unlock_irqrestore(&info->lock,flags);
d12341f9
JG		 2025
2026
1da177e4
LT		 2027 for(;;) {
2028 schedule();
2029 if (signal_pending(current)) {
2030 rc = -ERESTARTSYS;
2031 break;
2032 }
d12341f9 2033
1da177e4
LT		 2034 /* get current irq counts */
2035 spin_lock_irqsave(&info->lock,flags);
2036 cnow = info->icount;
2037 newsigs = info->input_signal_events;
2038 set_current_state(TASK_INTERRUPTIBLE);
2039 spin_unlock_irqrestore(&info->lock,flags);
2040
2041 /* if no change, wait aborted for some reason */
2042 if (newsigs.dsr_up == oldsigs.dsr_up &&
2043 newsigs.dsr_down == oldsigs.dsr_down &&
2044 newsigs.dcd_up == oldsigs.dcd_up &&
2045 newsigs.dcd_down == oldsigs.dcd_down &&
2046 newsigs.cts_up == oldsigs.cts_up &&
2047 newsigs.cts_down == oldsigs.cts_down &&
2048 newsigs.ri_up == oldsigs.ri_up &&
2049 newsigs.ri_down == oldsigs.ri_down &&
2050 cnow.exithunt == cprev.exithunt &&
2051 cnow.rxidle == cprev.rxidle) {
2052 rc = -EIO;
2053 break;
2054 }
2055
2056 events = mask &
2057 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2058 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2059 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2060 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2061 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2062 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2063 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2064 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2065 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2066 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2067 if (events)
2068 break;
d12341f9 2069
1da177e4
LT		 2070 cprev = cnow;
2071 oldsigs = newsigs;
2072 }
d12341f9 2073
1da177e4
LT		 2074 remove_wait_queue(&info->event_wait_q, &wait);
2075 set_current_state(TASK_RUNNING);
2076
2077 if (mask & MgslEvent_ExitHuntMode) {
2078 spin_lock_irqsave(&info->lock,flags);
2079 if (!waitqueue_active(&info->event_wait_q))
2080 irq_disable(info, CHA, IRQ_EXITHUNT);
2081 spin_unlock_irqrestore(&info->lock,flags);
2082 }
2083exit:
2084 if (rc == 0)
2085 PUT_USER(rc, events, mask_ptr);
2086 return rc;
2087}
2088
2089static int modem_input_wait(MGSLPC_INFO *info,int arg)
2090{
2091 unsigned long flags;
2092 int rc;
2093 struct mgsl_icount cprev, cnow;
2094 DECLARE_WAITQUEUE(wait, current);
2095
2096 /* save current irq counts */
2097 spin_lock_irqsave(&info->lock,flags);
2098 cprev = info->icount;
2099 add_wait_queue(&info->status_event_wait_q, &wait);
2100 set_current_state(TASK_INTERRUPTIBLE);
2101 spin_unlock_irqrestore(&info->lock,flags);
2102
2103 for(;;) {
2104 schedule();
2105 if (signal_pending(current)) {
2106 rc = -ERESTARTSYS;
2107 break;
2108 }
2109
2110 /* get new irq counts */
2111 spin_lock_irqsave(&info->lock,flags);
2112 cnow = info->icount;
2113 set_current_state(TASK_INTERRUPTIBLE);
2114 spin_unlock_irqrestore(&info->lock,flags);
2115
2116 /* if no change, wait aborted for some reason */
2117 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2118 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2119 rc = -EIO;
2120 break;
2121 }
2122
2123 /* check for change in caller specified modem input */
2124 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2125 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2126 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2127 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2128 rc = 0;
2129 break;
2130 }
2131
2132 cprev = cnow;
2133 }
2134 remove_wait_queue(&info->status_event_wait_q, &wait);
2135 set_current_state(TASK_RUNNING);
2136 return rc;
2137}
2138
2139/* return the state of the serial control and status signals
2140 */
2141static int tiocmget(struct tty_struct *tty, struct file *file)
2142{
2143 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2144 unsigned int result;
2145 unsigned long flags;
2146
2147 spin_lock_irqsave(&info->lock,flags);
2148 get_signals(info);
2149 spin_unlock_irqrestore(&info->lock,flags);
2150
2151 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2152 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2153 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2154 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2155 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2156 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2157
2158 if (debug_level >= DEBUG_LEVEL_INFO)
2159 printk("%s(%d):%s tiocmget() value=%08X\n",
2160 __FILE__,__LINE__, info->device_name, result );
2161 return result;
2162}
2163
2164/* set modem control signals (DTR/RTS)
2165 */
2166static int tiocmset(struct tty_struct *tty, struct file *file,
2167 unsigned int set, unsigned int clear)
2168{
2169 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2170 unsigned long flags;
2171
2172 if (debug_level >= DEBUG_LEVEL_INFO)
2173 printk("%s(%d):%s tiocmset(%x,%x)\n",
2174 __FILE__,__LINE__,info->device_name, set, clear);
2175
2176 if (set & TIOCM_RTS)
2177 info->serial_signals |= SerialSignal_RTS;
2178 if (set & TIOCM_DTR)
2179 info->serial_signals |= SerialSignal_DTR;
2180 if (clear & TIOCM_RTS)
2181 info->serial_signals &= ~SerialSignal_RTS;
2182 if (clear & TIOCM_DTR)
2183 info->serial_signals &= ~SerialSignal_DTR;
2184
2185 spin_lock_irqsave(&info->lock,flags);
2186 set_signals(info);
2187 spin_unlock_irqrestore(&info->lock,flags);
2188
2189 return 0;
2190}
2191
2192/* Set or clear transmit break condition
2193 *
2194 * Arguments: tty pointer to tty instance data
2195 * break_state -1=set break condition, 0=clear
2196 */
9e98966c 2197static int mgslpc_break(struct tty_struct *tty, int break_state)
1da177e4
LT		 2198{
2199 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2200 unsigned long flags;
d12341f9 2201
1da177e4
LT		 2202 if (debug_level >= DEBUG_LEVEL_INFO)
2203 printk("%s(%d):mgslpc_break(%s,%d)\n",
2204 __FILE__,__LINE__, info->device_name, break_state);
d12341f9 2205
1da177e4 2206 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
9e98966c 2207 return -EINVAL;
1da177e4
LT		 2208
2209 spin_lock_irqsave(&info->lock,flags);
2210 if (break_state == -1)
2211 set_reg_bits(info, CHA+DAFO, BIT6);
d12341f9 2212 else
1da177e4
LT		 2213 clear_reg_bits(info, CHA+DAFO, BIT6);
2214 spin_unlock_irqrestore(&info->lock,flags);
9e98966c 2215 return 0;
1da177e4
LT		 2216}
2217
2218/* Service an IOCTL request
d12341f9 2219 *
1da177e4 2220 * Arguments:
d12341f9 2221 *
1da177e4
LT		 2222 * tty pointer to tty instance data
2223 * file pointer to associated file object for device
2224 * cmd IOCTL command code
2225 * arg command argument/context
d12341f9 2226 *
1da177e4
LT		 2227 * Return Value: 0 if success, otherwise error code
2228 */
2229static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
2230 unsigned int cmd, unsigned long arg)
2231{
2232 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134
AC		 2233 int error;
2234 struct mgsl_icount cnow; /* kernel counter temps */
2235 struct serial_icounter_struct __user *p_cuser; /* user space */
2236 void __user *argp = (void __user *)arg;
2237 unsigned long flags;
d12341f9 2238
1da177e4
LT		 2239 if (debug_level >= DEBUG_LEVEL_INFO)
2240 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2241 info->device_name, cmd );
d12341f9 2242
1da177e4
LT		 2243 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2244 return -ENODEV;
2245
2246 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2247 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2248 if (tty->flags & (1 << TTY_IO_ERROR))
2249 return -EIO;
2250 }
2251
1da177e4
LT		 2252 switch (cmd) {
2253 case MGSL_IOCGPARAMS:
2254 return get_params(info, argp);
2255 case MGSL_IOCSPARAMS:
eeb46134 2256 return set_params(info, argp, tty);
1da177e4
LT		 2257 case MGSL_IOCGTXIDLE:
2258 return get_txidle(info, argp);
2259 case MGSL_IOCSTXIDLE:
2260 return set_txidle(info, (int)arg);
2261 case MGSL_IOCGIF:
2262 return get_interface(info, argp);
2263 case MGSL_IOCSIF:
2264 return set_interface(info,(int)arg);
2265 case MGSL_IOCTXENABLE:
eeb46134 2266 return set_txenable(info,(int)arg, tty);
1da177e4
LT		 2267 case MGSL_IOCRXENABLE:
2268 return set_rxenable(info,(int)arg);
2269 case MGSL_IOCTXABORT:
2270 return tx_abort(info);
2271 case MGSL_IOCGSTATS:
2272 return get_stats(info, argp);
2273 case MGSL_IOCWAITEVENT:
2274 return wait_events(info, argp);
2275 case TIOCMIWAIT:
2276 return modem_input_wait(info,(int)arg);
2277 case TIOCGICOUNT:
2278 spin_lock_irqsave(&info->lock,flags);
2279 cnow = info->icount;
2280 spin_unlock_irqrestore(&info->lock,flags);
2281 p_cuser = argp;
2282 PUT_USER(error,cnow.cts, &p_cuser->cts);
2283 if (error) return error;
2284 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
2285 if (error) return error;
2286 PUT_USER(error,cnow.rng, &p_cuser->rng);
2287 if (error) return error;
2288 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
2289 if (error) return error;
2290 PUT_USER(error,cnow.rx, &p_cuser->rx);
2291 if (error) return error;
2292 PUT_USER(error,cnow.tx, &p_cuser->tx);
2293 if (error) return error;
2294 PUT_USER(error,cnow.frame, &p_cuser->frame);
2295 if (error) return error;
2296 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
2297 if (error) return error;
2298 PUT_USER(error,cnow.parity, &p_cuser->parity);
2299 if (error) return error;
2300 PUT_USER(error,cnow.brk, &p_cuser->brk);
2301 if (error) return error;
2302 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
2303 if (error) return error;
2304 return 0;
2305 default:
2306 return -ENOIOCTLCMD;
2307 }
2308 return 0;
2309}
2310
2311/* Set new termios settings
d12341f9 2312 *
1da177e4 2313 * Arguments:
d12341f9 2314 *
1da177e4
LT		 2315 * tty pointer to tty structure
2316 * termios pointer to buffer to hold returned old termios
2317 */
606d099c 2318static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 2319{
2320 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2321 unsigned long flags;
d12341f9 2322
1da177e4
LT		 2323 if (debug_level >= DEBUG_LEVEL_INFO)
2324 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
2325 tty->driver->name );
d12341f9 2326
1da177e4
LT		 2327 /* just return if nothing has changed */
2328 if ((tty->termios->c_cflag == old_termios->c_cflag)
d12341f9 2329 && (RELEVANT_IFLAG(tty->termios->c_iflag)
1da177e4
LT		 2330 == RELEVANT_IFLAG(old_termios->c_iflag)))
2331 return;
2332
eeb46134 2333 mgslpc_change_params(info, tty);
1da177e4
LT		 2334
2335 /* Handle transition to B0 status */
2336 if (old_termios->c_cflag & CBAUD &&
2337 !(tty->termios->c_cflag & CBAUD)) {
2338 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2339 spin_lock_irqsave(&info->lock,flags);
2340 set_signals(info);
2341 spin_unlock_irqrestore(&info->lock,flags);
2342 }
d12341f9 2343
1da177e4
LT		 2344 /* Handle transition away from B0 status */
2345 if (!(old_termios->c_cflag & CBAUD) &&
2346 tty->termios->c_cflag & CBAUD) {
2347 info->serial_signals |= SerialSignal_DTR;
d12341f9 2348 if (!(tty->termios->c_cflag & CRTSCTS) ||
1da177e4
LT		 2349 !test_bit(TTY_THROTTLED, &tty->flags)) {
2350 info->serial_signals |= SerialSignal_RTS;
2351 }
2352 spin_lock_irqsave(&info->lock,flags);
2353 set_signals(info);
2354 spin_unlock_irqrestore(&info->lock,flags);
2355 }
d12341f9 2356
1da177e4
LT		 2357 /* Handle turning off CRTSCTS */
2358 if (old_termios->c_cflag & CRTSCTS &&
2359 !(tty->termios->c_cflag & CRTSCTS)) {
2360 tty->hw_stopped = 0;
2361 tx_release(tty);
2362 }
2363}
2364
2365static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2366{
2367 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2368 struct tty_port *port = &info->port;
1da177e4
LT		 2369
2370 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2371 return;
d12341f9 2372
1da177e4
LT		 2373 if (debug_level >= DEBUG_LEVEL_INFO)
2374 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
eeb46134 2375 __FILE__,__LINE__, info->device_name, port->count);
1da177e4 2376
eeb46134 2377 WARN_ON(!port->count);
d12341f9 2378
eeb46134 2379 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 2380 goto cleanup;
d12341f9 2381
eeb46134 2382 if (port->flags & ASYNC_INITIALIZED)
1da177e4
LT		 2383 mgslpc_wait_until_sent(tty, info->timeout);
2384
978e595f 2385 mgslpc_flush_buffer(tty);
1da177e4 2386
978e595f 2387 tty_ldisc_flush(tty);
eeb46134
AC		 2388 shutdown(info, tty);
2389
2390 tty_port_close_end(port, tty);
2391 tty_port_tty_set(port, NULL);
d12341f9 2392cleanup:
1da177e4
LT		 2393 if (debug_level >= DEBUG_LEVEL_INFO)
2394 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
eeb46134 2395 tty->driver->name, port->count);
1da177e4
LT		 2396}
2397
2398/* Wait until the transmitter is empty.
2399 */
2400static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2401{
2402 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2403 unsigned long orig_jiffies, char_time;
2404
2405 if (!info )
2406 return;
2407
2408 if (debug_level >= DEBUG_LEVEL_INFO)
2409 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
2410 __FILE__,__LINE__, info->device_name );
d12341f9 2411
1da177e4
LT		 2412 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2413 return;
2414
eeb46134 2415 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4 2416 goto exit;
d12341f9 2417
1da177e4 2418 orig_jiffies = jiffies;
d12341f9 2419
1da177e4
LT		 2420 /* Set check interval to 1/5 of estimated time to
2421 * send a character, and make it at least 1. The check
2422 * interval should also be less than the timeout.
2423 * Note: use tight timings here to satisfy the NIST-PCTS.
d12341f9
JG		 2424 */
2425
1da177e4
LT		 2426 if ( info->params.data_rate ) {
2427 char_time = info->timeout/(32 * 5);
2428 if (!char_time)
2429 char_time++;
2430 } else
2431 char_time = 1;
d12341f9 2432
1da177e4
LT		 2433 if (timeout)
2434 char_time = min_t(unsigned long, char_time, timeout);
d12341f9 2435
1da177e4
LT		 2436 if (info->params.mode == MGSL_MODE_HDLC) {
2437 while (info->tx_active) {
2438 msleep_interruptible(jiffies_to_msecs(char_time));
2439 if (signal_pending(current))
2440 break;
2441 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2442 break;
2443 }
2444 } else {
2445 while ((info->tx_count || info->tx_active) &&
2446 info->tx_enabled) {
2447 msleep_interruptible(jiffies_to_msecs(char_time));
2448 if (signal_pending(current))
2449 break;
2450 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2451 break;
2452 }
2453 }
d12341f9 2454
1da177e4
LT		 2455exit:
2456 if (debug_level >= DEBUG_LEVEL_INFO)
2457 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
2458 __FILE__,__LINE__, info->device_name );
2459}
2460
2461/* Called by tty_hangup() when a hangup is signaled.
2462 * This is the same as closing all open files for the port.
2463 */
2464static void mgslpc_hangup(struct tty_struct *tty)
2465{
2466 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
d12341f9 2467
1da177e4
LT		 2468 if (debug_level >= DEBUG_LEVEL_INFO)
2469 printk("%s(%d):mgslpc_hangup(%s)\n",
2470 __FILE__,__LINE__, info->device_name );
d12341f9 2471
1da177e4
LT		 2472 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2473 return;
2474
2475 mgslpc_flush_buffer(tty);
eeb46134
AC		 2476 shutdown(info, tty);
2477 tty_port_hangup(&info->port);
1da177e4
LT		 2478}
2479
eeb46134 2480static int carrier_raised(struct tty_port *port)
1da177e4 2481{
eeb46134
AC		 2482 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2483 unsigned long flags;
d12341f9 2484
eeb46134
AC		 2485 spin_lock_irqsave(&info->lock,flags);
2486 get_signals(info);
2487 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2488
eeb46134
AC		 2489 if (info->serial_signals & SerialSignal_DCD)
2490 return 1;
2491 return 0;
2492}
d12341f9 2493
fcc8ac18 2494static void dtr_rts(struct tty_port *port, int onoff)
eeb46134
AC		 2495{
2496 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2497 unsigned long flags;
d12341f9 2498
eeb46134 2499 spin_lock_irqsave(&info->lock,flags);
fcc8ac18
AC		 2500 if (onoff)
2501 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2502 else
2503 info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 2504 set_signals(info);
2505 spin_unlock_irqrestore(&info->lock,flags);
1da177e4
LT		 2506}
2507
eeb46134 2508
1da177e4
LT		 2509static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2510{
2511 MGSLPC_INFO *info;
eeb46134 2512 struct tty_port *port;
1da177e4
LT		 2513 int retval, line;
2514 unsigned long flags;
2515
d12341f9 2516 /* verify range of specified line number */
1da177e4
LT		 2517 line = tty->index;
2518 if ((line < 0) || (line >= mgslpc_device_count)) {
2519 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
2520 __FILE__,__LINE__,line);
2521 return -ENODEV;
2522 }
2523
2524 /* find the info structure for the specified line */
2525 info = mgslpc_device_list;
2526 while(info && info->line != line)
2527 info = info->next_device;
2528 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2529 return -ENODEV;
d12341f9 2530
eeb46134 2531 port = &info->port;
1da177e4 2532 tty->driver_data = info;
eeb46134 2533 tty_port_tty_set(port, tty);
d12341f9 2534
1da177e4
LT		 2535 if (debug_level >= DEBUG_LEVEL_INFO)
2536 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
eeb46134 2537 __FILE__,__LINE__,tty->driver->name, port->count);
1da177e4
LT		 2538
2539 /* If port is closing, signal caller to try again */
eeb46134
AC		 2540 if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
2541 if (port->flags & ASYNC_CLOSING)
2542 interruptible_sleep_on(&port->close_wait);
2543 retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 2544 -EAGAIN : -ERESTARTSYS);
2545 goto cleanup;
2546 }
d12341f9 2547
eeb46134 2548 tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 2549
2550 spin_lock_irqsave(&info->netlock, flags);
2551 if (info->netcount) {
2552 retval = -EBUSY;
2553 spin_unlock_irqrestore(&info->netlock, flags);
2554 goto cleanup;
2555 }
eeb46134
AC		 2556 spin_lock(&port->lock);
2557 port->count++;
2558 spin_unlock(&port->lock);
1da177e4
LT		 2559 spin_unlock_irqrestore(&info->netlock, flags);
2560
eeb46134 2561 if (port->count == 1) {
1da177e4 2562 /* 1st open on this device, init hardware */
eeb46134 2563 retval = startup(info, tty);
1da177e4
LT		 2564 if (retval < 0)
2565 goto cleanup;
2566 }
2567
eeb46134 2568 retval = tty_port_block_til_ready(&info->port, tty, filp);
1da177e4
LT		 2569 if (retval) {
2570 if (debug_level >= DEBUG_LEVEL_INFO)
2571 printk("%s(%d):block_til_ready(%s) returned %d\n",
2572 __FILE__,__LINE__, info->device_name, retval);
2573 goto cleanup;
2574 }
2575
2576 if (debug_level >= DEBUG_LEVEL_INFO)
2577 printk("%s(%d):mgslpc_open(%s) success\n",
2578 __FILE__,__LINE__, info->device_name);
2579 retval = 0;
d12341f9
JG		 2580
2581cleanup:
1da177e4
LT		 2582 return retval;
2583}
2584
2585/*
2586 * /proc fs routines....
2587 */
2588
87687144 2589static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
1da177e4
LT		 2590{
2591 char stat_buf[30];
1da177e4
LT		 2592 unsigned long flags;
2593
87687144 2594 seq_printf(m, "%s:io:%04X irq:%d",
1da177e4
LT		 2595 info->device_name, info->io_base, info->irq_level);
2596
2597 /* output current serial signal states */
2598 spin_lock_irqsave(&info->lock,flags);
2599 get_signals(info);
2600 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2601
1da177e4
LT		 2602 stat_buf[0] = 0;
2603 stat_buf[1] = 0;
2604 if (info->serial_signals & SerialSignal_RTS)
2605 strcat(stat_buf, "|RTS");
2606 if (info->serial_signals & SerialSignal_CTS)
2607 strcat(stat_buf, "|CTS");
2608 if (info->serial_signals & SerialSignal_DTR)
2609 strcat(stat_buf, "|DTR");
2610 if (info->serial_signals & SerialSignal_DSR)
2611 strcat(stat_buf, "|DSR");
2612 if (info->serial_signals & SerialSignal_DCD)
2613 strcat(stat_buf, "|CD");
2614 if (info->serial_signals & SerialSignal_RI)
2615 strcat(stat_buf, "|RI");
2616
2617 if (info->params.mode == MGSL_MODE_HDLC) {
87687144 2618 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 2619 info->icount.txok, info->icount.rxok);
2620 if (info->icount.txunder)
87687144 2621 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 2622 if (info->icount.txabort)
87687144 2623 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 2624 if (info->icount.rxshort)
87687144 2625 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 2626 if (info->icount.rxlong)
87687144 2627 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 2628 if (info->icount.rxover)
87687144 2629 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 2630 if (info->icount.rxcrc)
87687144 2631 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 2632 } else {
87687144 2633 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 2634 info->icount.tx, info->icount.rx);
2635 if (info->icount.frame)
87687144 2636 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 2637 if (info->icount.parity)
87687144 2638 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 2639 if (info->icount.brk)
87687144 2640 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 2641 if (info->icount.overrun)
87687144 2642 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4 2643 }
d12341f9 2644
1da177e4 2645 /* Append serial signal status to end */
87687144 2646 seq_printf(m, " %s\n", stat_buf+1);
d12341f9 2647
87687144 2648 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 2649 info->tx_active,info->bh_requested,info->bh_running,
2650 info->pending_bh);
1da177e4
LT		 2651}
2652
2653/* Called to print information about devices
2654 */
87687144 2655static int mgslpc_proc_show(struct seq_file *m, void *v)
1da177e4 2656{
1da177e4 2657 MGSLPC_INFO *info;
d12341f9 2658
87687144 2659 seq_printf(m, "synclink driver:%s\n", driver_version);
d12341f9 2660
1da177e4
LT		 2661 info = mgslpc_device_list;
2662 while( info ) {
87687144 2663 line_info(m, info);
1da177e4
LT		 2664 info = info->next_device;
2665 }
87687144
AD		 2666 return 0;
2667}
1da177e4 2668
87687144
AD		 2669static int mgslpc_proc_open(struct inode *inode, struct file *file)
2670{
2671 return single_open(file, mgslpc_proc_show, NULL);
1da177e4
LT		 2672}
2673
87687144
AD		 2674static const struct file_operations mgslpc_proc_fops = {
2675 .owner = THIS_MODULE,
2676 .open = mgslpc_proc_open,
2677 .read = seq_read,
2678 .llseek = seq_lseek,
2679 .release = single_release,
2680};
2681
cdaad343 2682static int rx_alloc_buffers(MGSLPC_INFO *info)
1da177e4
LT		 2683{
2684 /* each buffer has header and data */
2685 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2686
2687 /* calculate total allocation size for 8 buffers */
2688 info->rx_buf_total_size = info->rx_buf_size * 8;
2689
2690 /* limit total allocated memory */
2691 if (info->rx_buf_total_size > 0x10000)
2692 info->rx_buf_total_size = 0x10000;
2693
2694 /* calculate number of buffers */
2695 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2696
2697 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2698 if (info->rx_buf == NULL)
2699 return -ENOMEM;
2700
2701 rx_reset_buffers(info);
2702 return 0;
2703}
2704
cdaad343 2705static void rx_free_buffers(MGSLPC_INFO *info)
1da177e4 2706{
735d5661 2707 kfree(info->rx_buf);
1da177e4
LT		 2708 info->rx_buf = NULL;
2709}
2710
cdaad343 2711static int claim_resources(MGSLPC_INFO *info)
1da177e4
LT		 2712{
2713 if (rx_alloc_buffers(info) < 0 ) {
2714 printk( "Cant allocate rx buffer %s\n", info->device_name);
2715 release_resources(info);
2716 return -ENODEV;
d12341f9 2717 }
1da177e4
LT		 2718 return 0;
2719}
2720
cdaad343 2721static void release_resources(MGSLPC_INFO *info)
1da177e4
LT		 2722{
2723 if (debug_level >= DEBUG_LEVEL_INFO)
2724 printk("release_resources(%s)\n", info->device_name);
2725 rx_free_buffers(info);
2726}
2727
2728/* Add the specified device instance data structure to the
2729 * global linked list of devices and increment the device count.
d12341f9 2730 *
1da177e4
LT		 2731 * Arguments: info pointer to device instance data
2732 */
cdaad343 2733static void mgslpc_add_device(MGSLPC_INFO *info)
1da177e4
LT		 2734{
2735 info->next_device = NULL;
2736 info->line = mgslpc_device_count;
2737 sprintf(info->device_name,"ttySLP%d",info->line);
d12341f9 2738
1da177e4
LT		 2739 if (info->line < MAX_DEVICE_COUNT) {
2740 if (maxframe[info->line])
2741 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 2742 }
2743
2744 mgslpc_device_count++;
d12341f9 2745
1da177e4
LT		 2746 if (!mgslpc_device_list)
2747 mgslpc_device_list = info;
d12341f9 2748 else {
1da177e4
LT		 2749 MGSLPC_INFO *current_dev = mgslpc_device_list;
2750 while( current_dev->next_device )
2751 current_dev = current_dev->next_device;
2752 current_dev->next_device = info;
2753 }
d12341f9 2754
1da177e4
LT		 2755 if (info->max_frame_size < 4096)
2756 info->max_frame_size = 4096;
2757 else if (info->max_frame_size > 65535)
2758 info->max_frame_size = 65535;
d12341f9 2759
1da177e4
LT		 2760 printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
2761 info->device_name, info->io_base, info->irq_level);
2762
af69c7f9 2763#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2764 hdlcdev_init(info);
2765#endif
2766}
2767
cdaad343 2768static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
1da177e4
LT		 2769{
2770 MGSLPC_INFO *info = mgslpc_device_list;
2771 MGSLPC_INFO *last = NULL;
2772
2773 while(info) {
2774 if (info == remove_info) {
2775 if (last)
2776 last->next_device = info->next_device;
2777 else
2778 mgslpc_device_list = info->next_device;
af69c7f9 2779#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2780 hdlcdev_exit(info);
2781#endif
2782 release_resources(info);
2783 kfree(info);
2784 mgslpc_device_count--;
2785 return;
2786 }
2787 last = info;
2788 info = info->next_device;
2789 }
2790}
2791
4af48c8c
DB		 2792static struct pcmcia_device_id mgslpc_ids[] = {
2793 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
2794 PCMCIA_DEVICE_NULL
2795};
2796MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
2797
1da177e4
LT		 2798static struct pcmcia_driver mgslpc_driver = {
2799 .owner = THIS_MODULE,
2800 .drv = {
2801 .name = "synclink_cs",
2802 },
15b99ac1 2803 .probe = mgslpc_probe,
cc3b4866 2804 .remove = mgslpc_detach,
4af48c8c 2805 .id_table = mgslpc_ids,
98e4c28b
DB		 2806 .suspend = mgslpc_suspend,
2807 .resume = mgslpc_resume,
1da177e4
LT		 2808};
2809
b68e31d0 2810static const struct tty_operations mgslpc_ops = {
1da177e4
LT		 2811 .open = mgslpc_open,
2812 .close = mgslpc_close,
2813 .write = mgslpc_write,
2814 .put_char = mgslpc_put_char,
2815 .flush_chars = mgslpc_flush_chars,
2816 .write_room = mgslpc_write_room,
2817 .chars_in_buffer = mgslpc_chars_in_buffer,
2818 .flush_buffer = mgslpc_flush_buffer,
2819 .ioctl = mgslpc_ioctl,
2820 .throttle = mgslpc_throttle,
2821 .unthrottle = mgslpc_unthrottle,
2822 .send_xchar = mgslpc_send_xchar,
2823 .break_ctl = mgslpc_break,
2824 .wait_until_sent = mgslpc_wait_until_sent,
1da177e4
LT		 2825 .set_termios = mgslpc_set_termios,
2826 .stop = tx_pause,
2827 .start = tx_release,
2828 .hangup = mgslpc_hangup,
2829 .tiocmget = tiocmget,
2830 .tiocmset = tiocmset,
87687144 2831 .proc_fops = &mgslpc_proc_fops,
1da177e4
LT		 2832};
2833
2834static void synclink_cs_cleanup(void)
2835{
2836 int rc;
2837
2838 printk("Unloading %s: version %s\n", driver_name, driver_version);
2839
2840 while(mgslpc_device_list)
2841 mgslpc_remove_device(mgslpc_device_list);
2842
2843 if (serial_driver) {
2844 if ((rc = tty_unregister_driver(serial_driver)))
2845 printk("%s(%d) failed to unregister tty driver err=%d\n",
2846 __FILE__,__LINE__,rc);
2847 put_tty_driver(serial_driver);
2848 }
2849
2850 pcmcia_unregister_driver(&mgslpc_driver);
1da177e4
LT		 2851}
2852
2853static int __init synclink_cs_init(void)
2854{
2855 int rc;
2856
2857 if (break_on_load) {
2858 mgslpc_get_text_ptr();
2859 BREAKPOINT();
2860 }
2861
2862 printk("%s %s\n", driver_name, driver_version);
2863
2864 if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
2865 return rc;
2866
2867 serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
2868 if (!serial_driver) {
2869 rc = -ENOMEM;
2870 goto error;
2871 }
2872
2873 /* Initialize the tty_driver structure */
d12341f9 2874
1da177e4
LT		 2875 serial_driver->owner = THIS_MODULE;
2876 serial_driver->driver_name = "synclink_cs";
2877 serial_driver->name = "ttySLP";
2878 serial_driver->major = ttymajor;
2879 serial_driver->minor_start = 64;
2880 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2881 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2882 serial_driver->init_termios = tty_std_termios;
2883 serial_driver->init_termios.c_cflag =
2884 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2885 serial_driver->flags = TTY_DRIVER_REAL_RAW;
2886 tty_set_operations(serial_driver, &mgslpc_ops);
2887
2888 if ((rc = tty_register_driver(serial_driver)) < 0) {
2889 printk("%s(%d):Couldn't register serial driver\n",
2890 __FILE__,__LINE__);
2891 put_tty_driver(serial_driver);
2892 serial_driver = NULL;
2893 goto error;
2894 }
d12341f9 2895
1da177e4
LT		 2896 printk("%s %s, tty major#%d\n",
2897 driver_name, driver_version,
2898 serial_driver->major);
d12341f9 2899
1da177e4
LT		 2900 return 0;
2901
2902error:
2903 synclink_cs_cleanup();
2904 return rc;
2905}
2906
d12341f9 2907static void __exit synclink_cs_exit(void)
1da177e4
LT		 2908{
2909 synclink_cs_cleanup();
2910}
2911
2912module_init(synclink_cs_init);
2913module_exit(synclink_cs_exit);
2914
2915static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2916{
2917 unsigned int M, N;
2918 unsigned char val;
2919
d12341f9
JG		 2920 /* note:standard BRG mode is broken in V3.2 chip
2921 * so enhanced mode is always used
1da177e4
LT		 2922 */
2923
2924 if (rate) {
2925 N = 3686400 / rate;
2926 if (!N)
2927 N = 1;
2928 N >>= 1;
2929 for (M = 1; N > 64 && M < 16; M++)
2930 N >>= 1;
2931 N--;
2932
2933 /* BGR[5..0] = N
2934 * BGR[9..6] = M
2935 * BGR[7..0] contained in BGR register
2936 * BGR[9..8] contained in CCR2[7..6]
2937 * divisor = (N+1)*2^M
2938 *
2939 * Note: M *must* not be zero (causes asymetric duty cycle)
d12341f9 2940 */
1da177e4
LT		 2941 write_reg(info, (unsigned char) (channel + BGR),
2942 (unsigned char) ((M << 6) + N));
2943 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2944 val |= ((M << 4) & 0xc0);
2945 write_reg(info, (unsigned char) (channel + CCR2), val);
2946 }
2947}
2948
2949/* Enabled the AUX clock output at the specified frequency.
2950 */
2951static void enable_auxclk(MGSLPC_INFO *info)
2952{
2953 unsigned char val;
d12341f9 2954
1da177e4
LT		 2955 /* MODE
2956 *
2957 * 07..06 MDS[1..0] 10 = transparent HDLC mode
2958 * 05 ADM Address Mode, 0 = no addr recognition
2959 * 04 TMD Timer Mode, 0 = external
2960 * 03 RAC Receiver Active, 0 = inactive
2961 * 02 RTS 0=RTS active during xmit, 1=RTS always active
2962 * 01 TRS Timer Resolution, 1=512
2963 * 00 TLP Test Loop, 0 = no loop
2964 *
2965 * 1000 0010
d12341f9 2966 */
1da177e4 2967 val = 0x82;
d12341f9
JG		 2968
2969 /* channel B RTS is used to enable AUXCLK driver on SP505 */
1da177e4
LT		 2970 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2971 val |= BIT2;
2972 write_reg(info, CHB + MODE, val);
d12341f9 2973
1da177e4
LT		 2974 /* CCR0
2975 *
2976 * 07 PU Power Up, 1=active, 0=power down
2977 * 06 MCE Master Clock Enable, 1=enabled
2978 * 05 Reserved, 0
2979 * 04..02 SC[2..0] Encoding
2980 * 01..00 SM[1..0] Serial Mode, 00=HDLC
2981 *
2982 * 11000000
d12341f9 2983 */
1da177e4 2984 write_reg(info, CHB + CCR0, 0xc0);
d12341f9 2985
1da177e4
LT		 2986 /* CCR1
2987 *
2988 * 07 SFLG Shared Flag, 0 = disable shared flags
2989 * 06 GALP Go Active On Loop, 0 = not used
2990 * 05 GLP Go On Loop, 0 = not used
2991 * 04 ODS Output Driver Select, 1=TxD is push-pull output
2992 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
2993 * 02..00 CM[2..0] Clock Mode
2994 *
2995 * 0001 0111
d12341f9 2996 */
1da177e4 2997 write_reg(info, CHB + CCR1, 0x17);
d12341f9 2998
1da177e4
LT		 2999 /* CCR2 (Channel B)
3000 *
3001 * 07..06 BGR[9..8] Baud rate bits 9..8
3002 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3003 * 04 SSEL Clock source select, 1=submode b
3004 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
3005 * 02 RWX Read/Write Exchange 0=disabled
3006 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3007 * 00 DIV, data inversion 0=disabled, 1=enabled
3008 *
3009 * 0011 1000
d12341f9 3010 */
1da177e4
LT		 3011 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3012 write_reg(info, CHB + CCR2, 0x38);
3013 else
3014 write_reg(info, CHB + CCR2, 0x30);
d12341f9 3015
1da177e4
LT		 3016 /* CCR4
3017 *
3018 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3019 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3020 * 05 TST1 Test Pin, 0=normal operation
3021 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3022 * 03..02 Reserved, must be 0
3023 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3024 *
3025 * 0101 0000
d12341f9 3026 */
1da177e4 3027 write_reg(info, CHB + CCR4, 0x50);
d12341f9 3028
1da177e4
LT		 3029 /* if auxclk not enabled, set internal BRG so
3030 * CTS transitions can be detected (requires TxC)
d12341f9 3031 */
1da177e4
LT		 3032 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3033 mgslpc_set_rate(info, CHB, info->params.clock_speed);
3034 else
3035 mgslpc_set_rate(info, CHB, 921600);
3036}
3037
d12341f9 3038static void loopback_enable(MGSLPC_INFO *info)
1da177e4
LT		 3039{
3040 unsigned char val;
d12341f9
JG		 3041
3042 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
1da177e4
LT		 3043 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3044 write_reg(info, CHA + CCR1, val);
d12341f9
JG		 3045
3046 /* CCR2:04 SSEL Clock source select, 1=submode b */
1da177e4
LT		 3047 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
3048 write_reg(info, CHA + CCR2, val);
d12341f9
JG		 3049
3050 /* set LinkSpeed if available, otherwise default to 2Mbps */
1da177e4
LT		 3051 if (info->params.clock_speed)
3052 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3053 else
3054 mgslpc_set_rate(info, CHA, 1843200);
d12341f9
JG		 3055
3056 /* MODE:00 TLP Test Loop, 1=loopback enabled */
1da177e4
LT		 3057 val = read_reg(info, CHA + MODE) | BIT0;
3058 write_reg(info, CHA + MODE, val);
3059}
3060
cdaad343 3061static void hdlc_mode(MGSLPC_INFO *info)
1da177e4
LT		 3062{
3063 unsigned char val;
3064 unsigned char clkmode, clksubmode;
3065
d12341f9 3066 /* disable all interrupts */
1da177e4
LT		 3067 irq_disable(info, CHA, 0xffff);
3068 irq_disable(info, CHB, 0xffff);
3069 port_irq_disable(info, 0xff);
d12341f9
JG		 3070
3071 /* assume clock mode 0a, rcv=RxC xmt=TxC */
1da177e4
LT		 3072 clkmode = clksubmode = 0;
3073 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3074 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
d12341f9 3075 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
1da177e4
LT		 3076 clkmode = 7;
3077 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3078 && info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3079 /* clock mode 7b, rcv = BRG, xmt = BRG */
1da177e4
LT		 3080 clkmode = 7;
3081 clksubmode = 1;
3082 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3083 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3084 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
1da177e4
LT		 3085 clkmode = 6;
3086 clksubmode = 1;
3087 } else {
d12341f9 3088 /* clock mode 6a, rcv = DPLL, xmt = TxC */
1da177e4
LT		 3089 clkmode = 6;
3090 }
3091 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3092 /* clock mode 0b, rcv = RxC, xmt = BRG */
1da177e4
LT		 3093 clksubmode = 1;
3094 }
d12341f9 3095
1da177e4
LT		 3096 /* MODE
3097 *
3098 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3099 * 05 ADM Address Mode, 0 = no addr recognition
3100 * 04 TMD Timer Mode, 0 = external
3101 * 03 RAC Receiver Active, 0 = inactive
3102 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3103 * 01 TRS Timer Resolution, 1=512
3104 * 00 TLP Test Loop, 0 = no loop
3105 *
3106 * 1000 0010
d12341f9 3107 */
1da177e4
LT		 3108 val = 0x82;
3109 if (info->params.loopback)
3110 val |= BIT0;
d12341f9
JG		 3111
3112 /* preserve RTS state */
1da177e4
LT		 3113 if (info->serial_signals & SerialSignal_RTS)
3114 val |= BIT2;
3115 write_reg(info, CHA + MODE, val);
d12341f9 3116
1da177e4
LT		 3117 /* CCR0
3118 *
3119 * 07 PU Power Up, 1=active, 0=power down
3120 * 06 MCE Master Clock Enable, 1=enabled
3121 * 05 Reserved, 0
3122 * 04..02 SC[2..0] Encoding
3123 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3124 *
3125 * 11000000
d12341f9 3126 */
1da177e4
LT		 3127 val = 0xc0;
3128 switch (info->params.encoding)
3129 {
3130 case HDLC_ENCODING_NRZI:
3131 val |= BIT3;
3132 break;
3133 case HDLC_ENCODING_BIPHASE_SPACE:
3134 val |= BIT4;
3135 break; // FM0
3136 case HDLC_ENCODING_BIPHASE_MARK:
3137 val |= BIT4 + BIT2;
3138 break; // FM1
3139 case HDLC_ENCODING_BIPHASE_LEVEL:
3140 val |= BIT4 + BIT3;
3141 break; // Manchester
3142 }
3143 write_reg(info, CHA + CCR0, val);
d12341f9 3144
1da177e4
LT		 3145 /* CCR1
3146 *
3147 * 07 SFLG Shared Flag, 0 = disable shared flags
3148 * 06 GALP Go Active On Loop, 0 = not used
3149 * 05 GLP Go On Loop, 0 = not used
3150 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3151 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3152 * 02..00 CM[2..0] Clock Mode
3153 *
3154 * 0001 0000
d12341f9 3155 */
1da177e4
LT		 3156 val = 0x10 + clkmode;
3157 write_reg(info, CHA + CCR1, val);
d12341f9 3158
1da177e4
LT		 3159 /* CCR2
3160 *
3161 * 07..06 BGR[9..8] Baud rate bits 9..8
3162 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3163 * 04 SSEL Clock source select, 1=submode b
3164 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3165 * 02 RWX Read/Write Exchange 0=disabled
3166 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3167 * 00 DIV, data inversion 0=disabled, 1=enabled
3168 *
3169 * 0000 0000
d12341f9 3170 */
1da177e4
LT		 3171 val = 0x00;
3172 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3173 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3174 val |= BIT5;
3175 if (clksubmode)
3176 val |= BIT4;
3177 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3178 val |= BIT1;
3179 if (info->params.encoding == HDLC_ENCODING_NRZB)
3180 val |= BIT0;
3181 write_reg(info, CHA + CCR2, val);
d12341f9 3182
1da177e4
LT		 3183 /* CCR3
3184 *
3185 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3186 * 05 EPT Enable preamble transmission, 1=enabled
3187 * 04 RADD Receive address pushed to FIFO, 0=disabled
3188 * 03 CRL CRC Reset Level, 0=FFFF
3189 * 02 RCRC Rx CRC 0=On 1=Off
3190 * 01 TCRC Tx CRC 0=On 1=Off
3191 * 00 PSD DPLL Phase Shift Disable
3192 *
3193 * 0000 0000
d12341f9 3194 */
1da177e4
LT		 3195 val = 0x00;
3196 if (info->params.crc_type == HDLC_CRC_NONE)
3197 val |= BIT2 + BIT1;
3198 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3199 val |= BIT5;
3200 switch (info->params.preamble_length)
3201 {
3202 case HDLC_PREAMBLE_LENGTH_16BITS:
3203 val |= BIT6;
3204 break;
3205 case HDLC_PREAMBLE_LENGTH_32BITS:
3206 val |= BIT6;
3207 break;
3208 case HDLC_PREAMBLE_LENGTH_64BITS:
3209 val |= BIT7 + BIT6;
3210 break;
3211 }
3212 write_reg(info, CHA + CCR3, val);
d12341f9
JG		 3213
3214 /* PRE - Preamble pattern */
1da177e4
LT		 3215 val = 0;
3216 switch (info->params.preamble)
3217 {
3218 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3219 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3220 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3221 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3222 }
3223 write_reg(info, CHA + PRE, val);
d12341f9 3224
1da177e4
LT		 3225 /* CCR4
3226 *
3227 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3228 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3229 * 05 TST1 Test Pin, 0=normal operation
3230 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3231 * 03..02 Reserved, must be 0
3232 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3233 *
3234 * 0101 0000
d12341f9 3235 */
1da177e4
LT		 3236 val = 0x50;
3237 write_reg(info, CHA + CCR4, val);
3238 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3239 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3240 else
3241 mgslpc_set_rate(info, CHA, info->params.clock_speed);
d12341f9 3242
1da177e4
LT		 3243 /* RLCR Receive length check register
3244 *
3245 * 7 1=enable receive length check
3246 * 6..0 Max frame length = (RL + 1) * 32
d12341f9 3247 */
1da177e4 3248 write_reg(info, CHA + RLCR, 0);
d12341f9 3249
1da177e4
LT		 3250 /* XBCH Transmit Byte Count High
3251 *
3252 * 07 DMA mode, 0 = interrupt driven
3253 * 06 NRM, 0=ABM (ignored)
3254 * 05 CAS Carrier Auto Start
3255 * 04 XC Transmit Continuously (ignored)
3256 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3257 *
3258 * 0000 0000
d12341f9 3259 */
1da177e4
LT		 3260 val = 0x00;
3261 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3262 val |= BIT5;
3263 write_reg(info, CHA + XBCH, val);
3264 enable_auxclk(info);
3265 if (info->params.loopback || info->testing_irq)
3266 loopback_enable(info);
3267 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3268 {
3269 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3270 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3271 set_reg_bits(info, CHA + PVR, BIT3);
3272 } else
3273 clear_reg_bits(info, CHA + PVR, BIT3);
3274
3275 irq_enable(info, CHA,
3276 IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
3277 IRQ_UNDERRUN + IRQ_TXFIFO);
3278 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3279 wait_command_complete(info, CHA);
3280 read_reg16(info, CHA + ISR); /* clear pending IRQs */
d12341f9 3281
1da177e4
LT		 3282 /* Master clock mode enabled above to allow reset commands
3283 * to complete even if no data clocks are present.
3284 *
3285 * Disable master clock mode for normal communications because
3286 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3287 * IRQ when in master clock mode.
3288 *
3289 * Leave master clock mode enabled for IRQ test because the
3290 * timer IRQ used by the test can only happen in master clock mode.
d12341f9 3291 */
1da177e4
LT		 3292 if (!info->testing_irq)
3293 clear_reg_bits(info, CHA + CCR0, BIT6);
3294
3295 tx_set_idle(info);
3296
3297 tx_stop(info);
3298 rx_stop(info);
3299}
3300
cdaad343 3301static void rx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3302{
3303 if (debug_level >= DEBUG_LEVEL_ISR)
3304 printk("%s(%d):rx_stop(%s)\n",
3305 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3306
3307 /* MODE:03 RAC Receiver Active, 0=inactive */
1da177e4
LT		 3308 clear_reg_bits(info, CHA + MODE, BIT3);
3309
0fab6de0
JP		 3310 info->rx_enabled = false;
3311 info->rx_overflow = false;
1da177e4
LT		 3312}
3313
cdaad343 3314static void rx_start(MGSLPC_INFO *info)
1da177e4
LT		 3315{
3316 if (debug_level >= DEBUG_LEVEL_ISR)
3317 printk("%s(%d):rx_start(%s)\n",
3318 __FILE__,__LINE__, info->device_name );
3319
3320 rx_reset_buffers(info);
0fab6de0
JP		 3321 info->rx_enabled = false;
3322 info->rx_overflow = false;
1da177e4 3323
d12341f9 3324 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3325 set_reg_bits(info, CHA + MODE, BIT3);
3326
0fab6de0 3327 info->rx_enabled = true;
1da177e4
LT		 3328}
3329
eeb46134 3330static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3331{
3332 if (debug_level >= DEBUG_LEVEL_ISR)
3333 printk("%s(%d):tx_start(%s)\n",
3334 __FILE__,__LINE__, info->device_name );
d12341f9 3335
1da177e4
LT		 3336 if (info->tx_count) {
3337 /* If auto RTS enabled and RTS is inactive, then assert */
3338 /* RTS and set a flag indicating that the driver should */
3339 /* negate RTS when the transmission completes. */
0fab6de0 3340 info->drop_rts_on_tx_done = false;
1da177e4
LT		 3341
3342 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3343 get_signals(info);
3344 if (!(info->serial_signals & SerialSignal_RTS)) {
3345 info->serial_signals |= SerialSignal_RTS;
3346 set_signals(info);
0fab6de0 3347 info->drop_rts_on_tx_done = true;
1da177e4
LT		 3348 }
3349 }
3350
3351 if (info->params.mode == MGSL_MODE_ASYNC) {
3352 if (!info->tx_active) {
0fab6de0 3353 info->tx_active = true;
eeb46134 3354 tx_ready(info, tty);
1da177e4
LT		 3355 }
3356 } else {
0fab6de0 3357 info->tx_active = true;
eeb46134 3358 tx_ready(info, tty);
40565f19
JS		 3359 mod_timer(&info->tx_timer, jiffies +
3360 msecs_to_jiffies(5000));
1da177e4
LT		 3361 }
3362 }
3363
3364 if (!info->tx_enabled)
0fab6de0 3365 info->tx_enabled = true;
1da177e4
LT		 3366}
3367
cdaad343 3368static void tx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3369{
3370 if (debug_level >= DEBUG_LEVEL_ISR)
3371 printk("%s(%d):tx_stop(%s)\n",
3372 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3373
3374 del_timer(&info->tx_timer);
1da177e4 3375
0fab6de0
JP		 3376 info->tx_enabled = false;
3377 info->tx_active = false;
1da177e4
LT		 3378}
3379
3380/* Reset the adapter to a known state and prepare it for further use.
3381 */
cdaad343 3382static void reset_device(MGSLPC_INFO *info)
1da177e4 3383{
d12341f9 3384 /* power up both channels (set BIT7) */
1da177e4
LT		 3385 write_reg(info, CHA + CCR0, 0x80);
3386 write_reg(info, CHB + CCR0, 0x80);
3387 write_reg(info, CHA + MODE, 0);
3388 write_reg(info, CHB + MODE, 0);
d12341f9
JG		 3389
3390 /* disable all interrupts */
1da177e4
LT		 3391 irq_disable(info, CHA, 0xffff);
3392 irq_disable(info, CHB, 0xffff);
3393 port_irq_disable(info, 0xff);
d12341f9 3394
1da177e4
LT		 3395 /* PCR Port Configuration Register
3396 *
3397 * 07..04 DEC[3..0] Serial I/F select outputs
3398 * 03 output, 1=AUTO CTS control enabled
3399 * 02 RI Ring Indicator input 0=active
3400 * 01 DSR input 0=active
3401 * 00 DTR output 0=active
3402 *
3403 * 0000 0110
d12341f9 3404 */
1da177e4 3405 write_reg(info, PCR, 0x06);
d12341f9 3406
1da177e4
LT		 3407 /* PVR Port Value Register
3408 *
3409 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3410 * 03 AUTO CTS output 1=enabled
3411 * 02 RI Ring Indicator input
3412 * 01 DSR input
3413 * 00 DTR output (1=inactive)
3414 *
3415 * 0000 0001
3416 */
3417// write_reg(info, PVR, PVR_DTR);
d12341f9 3418
1da177e4
LT		 3419 /* IPC Interrupt Port Configuration
3420 *
3421 * 07 VIS 1=Masked interrupts visible
3422 * 06..05 Reserved, 0
3423 * 04..03 SLA Slave address, 00 ignored
3424 * 02 CASM Cascading Mode, 1=daisy chain
3425 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3426 *
3427 * 0000 0101
d12341f9 3428 */
1da177e4
LT		 3429 write_reg(info, IPC, 0x05);
3430}
3431
cdaad343 3432static void async_mode(MGSLPC_INFO *info)
1da177e4
LT		 3433{
3434 unsigned char val;
3435
d12341f9 3436 /* disable all interrupts */
1da177e4
LT		 3437 irq_disable(info, CHA, 0xffff);
3438 irq_disable(info, CHB, 0xffff);
3439 port_irq_disable(info, 0xff);
d12341f9 3440
1da177e4
LT		 3441 /* MODE
3442 *
3443 * 07 Reserved, 0
3444 * 06 FRTS RTS State, 0=active
3445 * 05 FCTS Flow Control on CTS
3446 * 04 FLON Flow Control Enable
3447 * 03 RAC Receiver Active, 0 = inactive
3448 * 02 RTS 0=Auto RTS, 1=manual RTS
3449 * 01 TRS Timer Resolution, 1=512
3450 * 00 TLP Test Loop, 0 = no loop
3451 *
3452 * 0000 0110
d12341f9 3453 */
1da177e4
LT		 3454 val = 0x06;
3455 if (info->params.loopback)
3456 val |= BIT0;
d12341f9
JG		 3457
3458 /* preserve RTS state */
1da177e4
LT		 3459 if (!(info->serial_signals & SerialSignal_RTS))
3460 val |= BIT6;
3461 write_reg(info, CHA + MODE, val);
d12341f9 3462
1da177e4
LT		 3463 /* CCR0
3464 *
3465 * 07 PU Power Up, 1=active, 0=power down
3466 * 06 MCE Master Clock Enable, 1=enabled
3467 * 05 Reserved, 0
3468 * 04..02 SC[2..0] Encoding, 000=NRZ
3469 * 01..00 SM[1..0] Serial Mode, 11=Async
3470 *
3471 * 1000 0011
d12341f9 3472 */
1da177e4 3473 write_reg(info, CHA + CCR0, 0x83);
d12341f9 3474
1da177e4
LT		 3475 /* CCR1
3476 *
3477 * 07..05 Reserved, 0
3478 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3479 * 03 BCR Bit Clock Rate, 1=16x
3480 * 02..00 CM[2..0] Clock Mode, 111=BRG
3481 *
3482 * 0001 1111
d12341f9 3483 */
1da177e4 3484 write_reg(info, CHA + CCR1, 0x1f);
d12341f9 3485
1da177e4
LT		 3486 /* CCR2 (channel A)
3487 *
3488 * 07..06 BGR[9..8] Baud rate bits 9..8
3489 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3490 * 04 SSEL Clock source select, 1=submode b
3491 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3492 * 02 RWX Read/Write Exchange 0=disabled
3493 * 01 Reserved, 0
3494 * 00 DIV, data inversion 0=disabled, 1=enabled
3495 *
3496 * 0001 0000
d12341f9 3497 */
1da177e4 3498 write_reg(info, CHA + CCR2, 0x10);
d12341f9 3499
1da177e4
LT		 3500 /* CCR3
3501 *
3502 * 07..01 Reserved, 0
3503 * 00 PSD DPLL Phase Shift Disable
3504 *
3505 * 0000 0000
d12341f9 3506 */
1da177e4 3507 write_reg(info, CHA + CCR3, 0);
d12341f9 3508
1da177e4
LT		 3509 /* CCR4
3510 *
3511 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3512 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3513 * 05 TST1 Test Pin, 0=normal operation
3514 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3515 * 03..00 Reserved, must be 0
3516 *
3517 * 0101 0000
d12341f9 3518 */
1da177e4
LT		 3519 write_reg(info, CHA + CCR4, 0x50);
3520 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
d12341f9 3521
1da177e4
LT		 3522 /* DAFO Data Format
3523 *
3524 * 07 Reserved, 0
3525 * 06 XBRK transmit break, 0=normal operation
3526 * 05 Stop bits (0=1, 1=2)
3527 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3528 * 02 PAREN Parity Enable
3529 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3530 *
d12341f9 3531 */
1da177e4
LT		 3532 val = 0x00;
3533 if (info->params.data_bits != 8)
3534 val |= BIT0; /* 7 bits */
3535 if (info->params.stop_bits != 1)
3536 val |= BIT5;
3537 if (info->params.parity != ASYNC_PARITY_NONE)
3538 {
3539 val |= BIT2; /* Parity enable */
3540 if (info->params.parity == ASYNC_PARITY_ODD)
3541 val |= BIT3;
3542 else
3543 val |= BIT4;
3544 }
3545 write_reg(info, CHA + DAFO, val);
d12341f9 3546
1da177e4
LT		 3547 /* RFC Rx FIFO Control
3548 *
3549 * 07 Reserved, 0
3550 * 06 DPS, 1=parity bit not stored in data byte
3551 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3552 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3553 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3554 * 01 Reserved, 0
3555 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3556 *
3557 * 0101 1100
d12341f9 3558 */
1da177e4 3559 write_reg(info, CHA + RFC, 0x5c);
d12341f9 3560
1da177e4
LT		 3561 /* RLCR Receive length check register
3562 *
3563 * Max frame length = (RL + 1) * 32
d12341f9 3564 */
1da177e4 3565 write_reg(info, CHA + RLCR, 0);
d12341f9 3566
1da177e4
LT		 3567 /* XBCH Transmit Byte Count High
3568 *
3569 * 07 DMA mode, 0 = interrupt driven
3570 * 06 NRM, 0=ABM (ignored)
3571 * 05 CAS Carrier Auto Start
3572 * 04 XC Transmit Continuously (ignored)
3573 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3574 *
3575 * 0000 0000
d12341f9 3576 */
1da177e4
LT		 3577 val = 0x00;
3578 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3579 val |= BIT5;
3580 write_reg(info, CHA + XBCH, val);
3581 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3582 irq_enable(info, CHA, IRQ_CTS);
d12341f9
JG		 3583
3584 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3585 set_reg_bits(info, CHA + MODE, BIT3);
3586 enable_auxclk(info);
3587 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3588 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3589 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3590 set_reg_bits(info, CHA + PVR, BIT3);
3591 } else
3592 clear_reg_bits(info, CHA + PVR, BIT3);
3593 irq_enable(info, CHA,
3594 IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
3595 IRQ_ALLSENT + IRQ_TXFIFO);
3596 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3597 wait_command_complete(info, CHA);
3598 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3599}
3600
3601/* Set the HDLC idle mode for the transmitter.
3602 */
cdaad343 3603static void tx_set_idle(MGSLPC_INFO *info)
1da177e4 3604{
d12341f9 3605 /* Note: ESCC2 only supports flags and one idle modes */
1da177e4
LT		 3606 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3607 set_reg_bits(info, CHA + CCR1, BIT3);
3608 else
3609 clear_reg_bits(info, CHA + CCR1, BIT3);
3610}
3611
3612/* get state of the V24 status (input) signals.
3613 */
cdaad343 3614static void get_signals(MGSLPC_INFO *info)
1da177e4
LT		 3615{
3616 unsigned char status = 0;
d12341f9
JG		 3617
3618 /* preserve DTR and RTS */
1da177e4
LT		 3619 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
3620
3621 if (read_reg(info, CHB + VSTR) & BIT7)
3622 info->serial_signals |= SerialSignal_DCD;
3623 if (read_reg(info, CHB + STAR) & BIT1)
3624 info->serial_signals |= SerialSignal_CTS;
3625
3626 status = read_reg(info, CHA + PVR);
3627 if (!(status & PVR_RI))
3628 info->serial_signals |= SerialSignal_RI;
3629 if (!(status & PVR_DSR))
3630 info->serial_signals |= SerialSignal_DSR;
3631}
3632
3633/* Set the state of DTR and RTS based on contents of
3634 * serial_signals member of device extension.
3635 */
cdaad343 3636static void set_signals(MGSLPC_INFO *info)
1da177e4
LT		 3637{
3638 unsigned char val;
3639
3640 val = read_reg(info, CHA + MODE);
3641 if (info->params.mode == MGSL_MODE_ASYNC) {
3642 if (info->serial_signals & SerialSignal_RTS)
3643 val &= ~BIT6;
3644 else
3645 val |= BIT6;
3646 } else {
3647 if (info->serial_signals & SerialSignal_RTS)
3648 val |= BIT2;
3649 else
3650 val &= ~BIT2;
3651 }
3652 write_reg(info, CHA + MODE, val);
3653
3654 if (info->serial_signals & SerialSignal_DTR)
3655 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3656 else
3657 set_reg_bits(info, CHA + PVR, PVR_DTR);
3658}
3659
cdaad343 3660static void rx_reset_buffers(MGSLPC_INFO *info)
1da177e4
LT		 3661{
3662 RXBUF *buf;
3663 int i;
3664
3665 info->rx_put = 0;
3666 info->rx_get = 0;
3667 info->rx_frame_count = 0;
3668 for (i=0 ; i < info->rx_buf_count ; i++) {
3669 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3670 buf->status = buf->count = 0;
3671 }
3672}
3673
3674/* Attempt to return a received HDLC frame
3675 * Only frames received without errors are returned.
3676 *
0fab6de0 3677 * Returns true if frame returned, otherwise false
1da177e4 3678 */
eeb46134 3679static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3680{
3681 unsigned short status;
3682 RXBUF *buf;
3683 unsigned int framesize = 0;
3684 unsigned long flags;
0fab6de0 3685 bool return_frame = false;
d12341f9 3686
1da177e4 3687 if (info->rx_frame_count == 0)
0fab6de0 3688 return false;
1da177e4
LT		 3689
3690 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3691
3692 status = buf->status;
3693
3694 /* 07 VFR 1=valid frame
3695 * 06 RDO 1=data overrun
3696 * 05 CRC 1=OK, 0=error
3697 * 04 RAB 1=frame aborted
3698 */
3699 if ((status & 0xf0) != 0xA0) {
3700 if (!(status & BIT7) || (status & BIT4))
3701 info->icount.rxabort++;
3702 else if (status & BIT6)
3703 info->icount.rxover++;
3704 else if (!(status & BIT5)) {
3705 info->icount.rxcrc++;
3706 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
0fab6de0 3707 return_frame = true;
1da177e4
LT		 3708 }
3709 framesize = 0;
af69c7f9 3710#if SYNCLINK_GENERIC_HDLC
1da177e4 3711 {
198191c4
KH		 3712 info->netdev->stats.rx_errors++;
3713 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 3714 }
3715#endif
3716 } else
0fab6de0 3717 return_frame = true;
1da177e4
LT		 3718
3719 if (return_frame)
3720 framesize = buf->count;
3721
3722 if (debug_level >= DEBUG_LEVEL_BH)
3723 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
3724 __FILE__,__LINE__,info->device_name,status,framesize);
d12341f9 3725
1da177e4 3726 if (debug_level >= DEBUG_LEVEL_DATA)
d12341f9
JG		 3727 trace_block(info, buf->data, framesize, 0);
3728
1da177e4
LT		 3729 if (framesize) {
3730 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
3731 framesize+1 > info->max_frame_size) ||
3732 framesize > info->max_frame_size)
3733 info->icount.rxlong++;
3734 else {
3735 if (status & BIT5)
3736 info->icount.rxok++;
3737
3738 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
3739 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
3740 ++framesize;
3741 }
3742
af69c7f9 3743#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3744 if (info->netcount)
3745 hdlcdev_rx(info, buf->data, framesize);
3746 else
3747#endif
3748 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
3749 }
3750 }
3751
3752 spin_lock_irqsave(&info->lock,flags);
3753 buf->status = buf->count = 0;
3754 info->rx_frame_count--;
3755 info->rx_get++;
3756 if (info->rx_get >= info->rx_buf_count)
3757 info->rx_get = 0;
3758 spin_unlock_irqrestore(&info->lock,flags);
3759
0fab6de0 3760 return true;
1da177e4
LT		 3761}
3762
0fab6de0 3763static bool register_test(MGSLPC_INFO *info)
1da177e4 3764{
d12341f9 3765 static unsigned char patterns[] =
1da177e4 3766 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
fe971071 3767 static unsigned int count = ARRAY_SIZE(patterns);
1da177e4 3768 unsigned int i;
0fab6de0 3769 bool rc = true;
1da177e4
LT		 3770 unsigned long flags;
3771
3772 spin_lock_irqsave(&info->lock,flags);
3773 reset_device(info);
3774
3775 for (i = 0; i < count; i++) {
3776 write_reg(info, XAD1, patterns[i]);
3777 write_reg(info, XAD2, patterns[(i + 1) % count]);
fe971071 3778 if ((read_reg(info, XAD1) != patterns[i]) ||
1da177e4 3779 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
0fab6de0 3780 rc = false;
1da177e4
LT		 3781 break;
3782 }
3783 }
3784
3785 spin_unlock_irqrestore(&info->lock,flags);
3786 return rc;
3787}
3788
0fab6de0 3789static bool irq_test(MGSLPC_INFO *info)
1da177e4
LT		 3790{
3791 unsigned long end_time;
3792 unsigned long flags;
3793
3794 spin_lock_irqsave(&info->lock,flags);
3795 reset_device(info);
3796
0fab6de0 3797 info->testing_irq = true;
1da177e4
LT		 3798 hdlc_mode(info);
3799
0fab6de0 3800 info->irq_occurred = false;
1da177e4
LT		 3801
3802 /* init hdlc mode */
3803
3804 irq_enable(info, CHA, IRQ_TIMER);
3805 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
3806 issue_command(info, CHA, CMD_START_TIMER);
3807
3808 spin_unlock_irqrestore(&info->lock,flags);
3809
3810 end_time=100;
3811 while(end_time-- && !info->irq_occurred) {
3812 msleep_interruptible(10);
3813 }
d12341f9 3814
0fab6de0 3815 info->testing_irq = false;
1da177e4
LT		 3816
3817 spin_lock_irqsave(&info->lock,flags);
3818 reset_device(info);
3819 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3820
0fab6de0 3821 return info->irq_occurred;
1da177e4
LT		 3822}
3823
cdaad343 3824static int adapter_test(MGSLPC_INFO *info)
1da177e4
LT		 3825{
3826 if (!register_test(info)) {
3827 info->init_error = DiagStatus_AddressFailure;
3828 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
3829 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
3830 return -ENODEV;
3831 }
3832
3833 if (!irq_test(info)) {
3834 info->init_error = DiagStatus_IrqFailure;
3835 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
3836 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
3837 return -ENODEV;
3838 }
3839
3840 if (debug_level >= DEBUG_LEVEL_INFO)
3841 printk("%s(%d):device %s passed diagnostics\n",
3842 __FILE__,__LINE__,info->device_name);
3843 return 0;
3844}
3845
cdaad343 3846static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 3847{
3848 int i;
3849 int linecount;
3850 if (xmit)
3851 printk("%s tx data:\n",info->device_name);
3852 else
3853 printk("%s rx data:\n",info->device_name);
d12341f9 3854
1da177e4
LT		 3855 while(count) {
3856 if (count > 16)
3857 linecount = 16;
3858 else
3859 linecount = count;
d12341f9 3860
1da177e4
LT		 3861 for(i=0;i<linecount;i++)
3862 printk("%02X ",(unsigned char)data[i]);
3863 for(;i<17;i++)
3864 printk(" ");
3865 for(i=0;i<linecount;i++) {
3866 if (data[i]>=040 && data[i]<=0176)
3867 printk("%c",data[i]);
3868 else
3869 printk(".");
3870 }
3871 printk("\n");
d12341f9 3872
1da177e4
LT		 3873 data += linecount;
3874 count -= linecount;
3875 }
3876}
3877
3878/* HDLC frame time out
3879 * update stats and do tx completion processing
3880 */
cdaad343 3881static void tx_timeout(unsigned long context)
1da177e4
LT		 3882{
3883 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
3884 unsigned long flags;
d12341f9 3885
1da177e4
LT		 3886 if ( debug_level >= DEBUG_LEVEL_INFO )
3887 printk( "%s(%d):tx_timeout(%s)\n",
3888 __FILE__,__LINE__,info->device_name);
3889 if(info->tx_active &&
3890 info->params.mode == MGSL_MODE_HDLC) {
3891 info->icount.txtimeout++;
3892 }
3893 spin_lock_irqsave(&info->lock,flags);
0fab6de0 3894 info->tx_active = false;
1da177e4
LT		 3895 info->tx_count = info->tx_put = info->tx_get = 0;
3896
3897 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3898
af69c7f9 3899#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3900 if (info->netcount)
3901 hdlcdev_tx_done(info);
3902 else
3903#endif
eeb46134
AC		 3904 {
3905 struct tty_struct *tty = tty_port_tty_get(&info->port);
3906 bh_transmit(info, tty);
3907 tty_kref_put(tty);
3908 }
1da177e4
LT		 3909}
3910
af69c7f9 3911#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3912
3913/**
3914 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3915 * set encoding and frame check sequence (FCS) options
3916 *
3917 * dev pointer to network device structure
3918 * encoding serial encoding setting
3919 * parity FCS setting
3920 *
3921 * returns 0 if success, otherwise error code
3922 */
3923static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
3924 unsigned short parity)
3925{
3926 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3927 struct tty_struct *tty;
1da177e4
LT		 3928 unsigned char new_encoding;
3929 unsigned short new_crctype;
3930
3931 /* return error if TTY interface open */
eeb46134 3932 if (info->port.count)
1da177e4
LT		 3933 return -EBUSY;
3934
3935 switch (encoding)
3936 {
3937 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
3938 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
3939 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
3940 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
3941 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
3942 default: return -EINVAL;
3943 }
3944
3945 switch (parity)
3946 {
3947 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
3948 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
3949 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
3950 default: return -EINVAL;
3951 }
3952
3953 info->params.encoding = new_encoding;
53b3531b 3954 info->params.crc_type = new_crctype;
1da177e4
LT		 3955
3956 /* if network interface up, reprogram hardware */
eeb46134
AC		 3957 if (info->netcount) {
3958 tty = tty_port_tty_get(&info->port);
3959 mgslpc_program_hw(info, tty);
3960 tty_kref_put(tty);
3961 }
1da177e4
LT		 3962
3963 return 0;
3964}
3965
3966/**
3967 * called by generic HDLC layer to send frame
3968 *
3969 * skb socket buffer containing HDLC frame
3970 * dev pointer to network device structure
1da177e4 3971 */
4c5d502d
SH		 3972static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
3973 struct net_device *dev)
1da177e4
LT		 3974{
3975 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 3976 unsigned long flags;
3977
3978 if (debug_level >= DEBUG_LEVEL_INFO)
3979 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
3980
3981 /* stop sending until this frame completes */
3982 netif_stop_queue(dev);
3983
3984 /* copy data to device buffers */
d626f62b 3985 skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
1da177e4
LT		 3986 info->tx_get = 0;
3987 info->tx_put = info->tx_count = skb->len;
3988
3989 /* update network statistics */
198191c4
KH		 3990 dev->stats.tx_packets++;
3991 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 3992
3993 /* done with socket buffer, so free it */
3994 dev_kfree_skb(skb);
3995
3996 /* save start time for transmit timeout detection */
3997 dev->trans_start = jiffies;
3998
3999 /* start hardware transmitter if necessary */
4000 spin_lock_irqsave(&info->lock,flags);
eeb46134
AC		 4001 if (!info->tx_active) {
4002 struct tty_struct *tty = tty_port_tty_get(&info->port);
4003 tx_start(info, tty);
4004 tty_kref_put(tty);
4005 }
1da177e4
LT		 4006 spin_unlock_irqrestore(&info->lock,flags);
4007
4c5d502d 4008 return NETDEV_TX_OK;
1da177e4
LT		 4009}
4010
4011/**
4012 * called by network layer when interface enabled
4013 * claim resources and initialize hardware
4014 *
4015 * dev pointer to network device structure
4016 *
4017 * returns 0 if success, otherwise error code
4018 */
4019static int hdlcdev_open(struct net_device *dev)
4020{
4021 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 4022 struct tty_struct *tty;
1da177e4
LT		 4023 int rc;
4024 unsigned long flags;
4025
4026 if (debug_level >= DEBUG_LEVEL_INFO)
4027 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
4028
4029 /* generic HDLC layer open processing */
4030 if ((rc = hdlc_open(dev)))
4031 return rc;
4032
4033 /* arbitrate between network and tty opens */
4034 spin_lock_irqsave(&info->netlock, flags);
eeb46134 4035 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 4036 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
4037 spin_unlock_irqrestore(&info->netlock, flags);
4038 return -EBUSY;
4039 }
4040 info->netcount=1;
4041 spin_unlock_irqrestore(&info->netlock, flags);
4042
eeb46134 4043 tty = tty_port_tty_get(&info->port);
1da177e4 4044 /* claim resources and init adapter */
eeb46134
AC		 4045 if ((rc = startup(info, tty)) != 0) {
4046 tty_kref_put(tty);
1da177e4
LT		 4047 spin_lock_irqsave(&info->netlock, flags);
4048 info->netcount=0;
4049 spin_unlock_irqrestore(&info->netlock, flags);
4050 return rc;
4051 }
1da177e4
LT		 4052 /* assert DTR and RTS, apply hardware settings */
4053 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 4054 mgslpc_program_hw(info, tty);
4055 tty_kref_put(tty);
1da177e4
LT		 4056
4057 /* enable network layer transmit */
4058 dev->trans_start = jiffies;
4059 netif_start_queue(dev);
4060
4061 /* inform generic HDLC layer of current DCD status */
4062 spin_lock_irqsave(&info->lock, flags);
4063 get_signals(info);
4064 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 4065 if (info->serial_signals & SerialSignal_DCD)
4066 netif_carrier_on(dev);
4067 else
4068 netif_carrier_off(dev);
1da177e4
LT		 4069 return 0;
4070}
4071
4072/**
4073 * called by network layer when interface is disabled
4074 * shutdown hardware and release resources
4075 *
4076 * dev pointer to network device structure
4077 *
4078 * returns 0 if success, otherwise error code
4079 */
4080static int hdlcdev_close(struct net_device *dev)
4081{
4082 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 4083 struct tty_struct *tty = tty_port_tty_get(&info->port);
1da177e4
LT		 4084 unsigned long flags;
4085
4086 if (debug_level >= DEBUG_LEVEL_INFO)
4087 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
4088
4089 netif_stop_queue(dev);
4090
4091 /* shutdown adapter and release resources */
eeb46134
AC		 4092 shutdown(info, tty);
4093 tty_kref_put(tty);
1da177e4
LT		 4094 hdlc_close(dev);
4095
4096 spin_lock_irqsave(&info->netlock, flags);
4097 info->netcount=0;
4098 spin_unlock_irqrestore(&info->netlock, flags);
4099
4100 return 0;
4101}
4102
4103/**
4104 * called by network layer to process IOCTL call to network device
4105 *
4106 * dev pointer to network device structure
4107 * ifr pointer to network interface request structure
4108 * cmd IOCTL command code
4109 *
4110 * returns 0 if success, otherwise error code
4111 */
4112static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4113{
4114 const size_t size = sizeof(sync_serial_settings);
4115 sync_serial_settings new_line;
4116 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4117 MGSLPC_INFO *info = dev_to_port(dev);
4118 unsigned int flags;
4119
4120 if (debug_level >= DEBUG_LEVEL_INFO)
4121 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
4122
4123 /* return error if TTY interface open */
eeb46134 4124 if (info->port.count)
1da177e4
LT		 4125 return -EBUSY;
4126
4127 if (cmd != SIOCWANDEV)
4128 return hdlc_ioctl(dev, ifr, cmd);
4129
4130 switch(ifr->ifr_settings.type) {
4131 case IF_GET_IFACE: /* return current sync_serial_settings */
4132
4133 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4134 if (ifr->ifr_settings.size < size) {
4135 ifr->ifr_settings.size = size; /* data size wanted */
4136 return -ENOBUFS;
4137 }
4138
4139 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4140 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4141 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4142 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4143
4144 switch (flags){
4145 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4146 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4147 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4148 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4149 default: new_line.clock_type = CLOCK_DEFAULT;
4150 }
4151
4152 new_line.clock_rate = info->params.clock_speed;
4153 new_line.loopback = info->params.loopback ? 1:0;
4154
4155 if (copy_to_user(line, &new_line, size))
4156 return -EFAULT;
4157 return 0;
4158
4159 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4160
4161 if(!capable(CAP_NET_ADMIN))
4162 return -EPERM;
4163 if (copy_from_user(&new_line, line, size))
4164 return -EFAULT;
4165
4166 switch (new_line.clock_type)
4167 {
4168 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4169 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4170 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4171 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4172 case CLOCK_DEFAULT: flags = info->params.flags &
4173 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4174 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4175 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4176 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4177 default: return -EINVAL;
4178 }
4179
4180 if (new_line.loopback != 0 && new_line.loopback != 1)
4181 return -EINVAL;
4182
4183 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4184 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4185 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4186 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4187 info->params.flags |= flags;
4188
4189 info->params.loopback = new_line.loopback;
4190
4191 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4192 info->params.clock_speed = new_line.clock_rate;
4193 else
4194 info->params.clock_speed = 0;
4195
4196 /* if network interface up, reprogram hardware */
eeb46134
AC		 4197 if (info->netcount) {
4198 struct tty_struct *tty = tty_port_tty_get(&info->port);
4199 mgslpc_program_hw(info, tty);
4200 tty_kref_put(tty);
4201 }
1da177e4
LT		 4202 return 0;
4203
4204 default:
4205 return hdlc_ioctl(dev, ifr, cmd);
4206 }
4207}
4208
4209/**
4210 * called by network layer when transmit timeout is detected
4211 *
4212 * dev pointer to network device structure
4213 */
4214static void hdlcdev_tx_timeout(struct net_device *dev)
4215{
4216 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 4217 unsigned long flags;
4218
4219 if (debug_level >= DEBUG_LEVEL_INFO)
4220 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
4221
198191c4
KH		 4222 dev->stats.tx_errors++;
4223 dev->stats.tx_aborted_errors++;
1da177e4
LT		 4224
4225 spin_lock_irqsave(&info->lock,flags);
4226 tx_stop(info);
4227 spin_unlock_irqrestore(&info->lock,flags);
4228
4229 netif_wake_queue(dev);
4230}
4231
4232/**
4233 * called by device driver when transmit completes
4234 * reenable network layer transmit if stopped
4235 *
4236 * info pointer to device instance information
4237 */
4238static void hdlcdev_tx_done(MGSLPC_INFO *info)
4239{
4240 if (netif_queue_stopped(info->netdev))
4241 netif_wake_queue(info->netdev);
4242}
4243
4244/**
4245 * called by device driver when frame received
4246 * pass frame to network layer
4247 *
4248 * info pointer to device instance information
4249 * buf pointer to buffer contianing frame data
4250 * size count of data bytes in buf
4251 */
4252static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4253{
4254 struct sk_buff *skb = dev_alloc_skb(size);
4255 struct net_device *dev = info->netdev;
1da177e4
LT		 4256
4257 if (debug_level >= DEBUG_LEVEL_INFO)
4258 printk("hdlcdev_rx(%s)\n",dev->name);
4259
4260 if (skb == NULL) {
4261 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
198191c4 4262 dev->stats.rx_dropped++;
1da177e4
LT		 4263 return;
4264 }
4265
198191c4 4266 memcpy(skb_put(skb, size), buf, size);
1da177e4 4267
198191c4 4268 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 4269
198191c4
KH		 4270 dev->stats.rx_packets++;
4271 dev->stats.rx_bytes += size;
1da177e4
LT		 4272
4273 netif_rx(skb);
1da177e4
LT		 4274}
4275
991990a1
KH		 4276static const struct net_device_ops hdlcdev_ops = {
4277 .ndo_open = hdlcdev_open,
4278 .ndo_stop = hdlcdev_close,
4279 .ndo_change_mtu = hdlc_change_mtu,
4280 .ndo_start_xmit = hdlc_start_xmit,
4281 .ndo_do_ioctl = hdlcdev_ioctl,
4282 .ndo_tx_timeout = hdlcdev_tx_timeout,
4283};
4284
1da177e4
LT		 4285/**
4286 * called by device driver when adding device instance
4287 * do generic HDLC initialization
4288 *
4289 * info pointer to device instance information
4290 *
4291 * returns 0 if success, otherwise error code
4292 */
4293static int hdlcdev_init(MGSLPC_INFO *info)
4294{
4295 int rc;
4296 struct net_device *dev;
4297 hdlc_device *hdlc;
4298
4299 /* allocate and initialize network and HDLC layer objects */
4300
4301 if (!(dev = alloc_hdlcdev(info))) {
4302 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
4303 return -ENOMEM;
4304 }
4305
4306 /* for network layer reporting purposes only */
4307 dev->base_addr = info->io_base;
4308 dev->irq = info->irq_level;
4309
4310 /* network layer callbacks and settings */
991990a1
KH		 4311 dev->netdev_ops = &hdlcdev_ops;
4312 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 4313 dev->tx_queue_len = 50;
4314
4315 /* generic HDLC layer callbacks and settings */
4316 hdlc = dev_to_hdlc(dev);
4317 hdlc->attach = hdlcdev_attach;
4318 hdlc->xmit = hdlcdev_xmit;
4319
4320 /* register objects with HDLC layer */
4321 if ((rc = register_hdlc_device(dev))) {
4322 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
4323 free_netdev(dev);
4324 return rc;
4325 }
4326
4327 info->netdev = dev;
4328 return 0;
4329}
4330
4331/**
4332 * called by device driver when removing device instance
4333 * do generic HDLC cleanup
4334 *
4335 * info pointer to device instance information
4336 */
4337static void hdlcdev_exit(MGSLPC_INFO *info)
4338{
4339 unregister_hdlc_device(info->netdev);
4340 free_netdev(info->netdev);
4341 info->netdev = NULL;
4342}
4343
4344#endif /* CONFIG_HDLC */
4345
Linux kernel - Deliverables
This page took 0.824773 seconds and 5 git commands to generate.