Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/riscom8_reg.h -- RISCom/8 multiport serial driver. | |
3 | */ | |
4 | ||
5 | /* | |
6 | * Definitions for RISCom/8 Async Mux card by SDL Communications, Inc. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Address mapping between Cirrus Logic CD180 chip internal registers | |
11 | * and ISA port addresses: | |
12 | * | |
13 | * CL-CD180 A6 A5 A4 A3 A2 A1 A0 | |
14 | * ISA A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 | |
15 | */ | |
16 | #define RC_TO_ISA(r) ((((r)&0x07)<<1) | (((r)&~0x07)<<7)) | |
17 | ||
18 | ||
19 | /* RISCom/8 On-Board Registers (assuming address translation) */ | |
20 | ||
21 | #define RC_RI 0x100 /* Ring Indicator Register (R/O) */ | |
22 | #define RC_DTR 0x100 /* DTR Register (W/O) */ | |
23 | #define RC_BSR 0x101 /* Board Status Register (R/O) */ | |
24 | #define RC_CTOUT 0x101 /* Clear Timeout (W/O) */ | |
25 | ||
26 | ||
27 | /* Board Status Register */ | |
28 | ||
29 | #define RC_BSR_TOUT 0x08 /* Hardware Timeout */ | |
30 | #define RC_BSR_RINT 0x04 /* Receiver Interrupt */ | |
31 | #define RC_BSR_TINT 0x02 /* Transmitter Interrupt */ | |
32 | #define RC_BSR_MINT 0x01 /* Modem Ctl Interrupt */ | |
33 | ||
34 | ||
35 | /* On-board oscillator frequency (in Hz) */ | |
36 | #define RC_OSCFREQ 9830400 | |
37 | ||
38 | /* Values of choice for Interrupt ACKs */ | |
39 | #define RC_ACK_MINT 0x81 /* goes to PILR1 */ | |
40 | #define RC_ACK_RINT 0x82 /* goes to PILR3 */ | |
41 | #define RC_ACK_TINT 0x84 /* goes to PILR2 */ | |
42 | ||
43 | /* Chip ID (sorry, only one chip now) */ | |
44 | #define RC_ID 0x10 | |
45 | ||
46 | /* Definitions for Cirrus Logic CL-CD180 8-port async mux chip */ | |
47 | ||
48 | #define CD180_NCH 8 /* Total number of channels */ | |
49 | #define CD180_TPC 16 /* Ticks per character */ | |
50 | #define CD180_NFIFO 8 /* TX FIFO size */ | |
51 | ||
52 | ||
53 | /* Global registers */ | |
54 | ||
55 | #define CD180_GIVR 0x40 /* Global Interrupt Vector Register */ | |
56 | #define CD180_GICR 0x41 /* Global Interrupting Channel Register */ | |
57 | #define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */ | |
58 | #define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */ | |
59 | #define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */ | |
60 | #define CD180_CAR 0x64 /* Channel Access Register */ | |
61 | #define CD180_GFRCR 0x6b /* Global Firmware Revision Code Register */ | |
62 | #define CD180_PPRH 0x70 /* Prescaler Period Register High */ | |
63 | #define CD180_PPRL 0x71 /* Prescaler Period Register Low */ | |
64 | #define CD180_RDR 0x78 /* Receiver Data Register */ | |
65 | #define CD180_RCSR 0x7a /* Receiver Character Status Register */ | |
66 | #define CD180_TDR 0x7b /* Transmit Data Register */ | |
67 | #define CD180_EOIR 0x7f /* End of Interrupt Register */ | |
68 | ||
69 | ||
70 | /* Channel Registers */ | |
71 | ||
72 | #define CD180_CCR 0x01 /* Channel Command Register */ | |
73 | #define CD180_IER 0x02 /* Interrupt Enable Register */ | |
74 | #define CD180_COR1 0x03 /* Channel Option Register 1 */ | |
75 | #define CD180_COR2 0x04 /* Channel Option Register 2 */ | |
76 | #define CD180_COR3 0x05 /* Channel Option Register 3 */ | |
77 | #define CD180_CCSR 0x06 /* Channel Control Status Register */ | |
78 | #define CD180_RDCR 0x07 /* Receive Data Count Register */ | |
79 | #define CD180_SCHR1 0x09 /* Special Character Register 1 */ | |
80 | #define CD180_SCHR2 0x0a /* Special Character Register 2 */ | |
81 | #define CD180_SCHR3 0x0b /* Special Character Register 3 */ | |
82 | #define CD180_SCHR4 0x0c /* Special Character Register 4 */ | |
83 | #define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */ | |
84 | #define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */ | |
85 | #define CD180_MCR 0x12 /* Modem Change Register */ | |
86 | #define CD180_RTPR 0x18 /* Receive Timeout Period Register */ | |
87 | #define CD180_MSVR 0x28 /* Modem Signal Value Register */ | |
88 | #define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register High */ | |
89 | #define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register Low */ | |
90 | #define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register High */ | |
91 | #define CD180_TBPRL 0x3a /* Transmit Baud Rate Period Register Low */ | |
92 | ||
93 | ||
94 | /* Global Interrupt Vector Register (R/W) */ | |
95 | ||
96 | #define GIVR_ITMASK 0x07 /* Interrupt type mask */ | |
97 | #define GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt */ | |
98 | #define GIVR_IT_TX 0x02 /* Transmit Data Interrupt */ | |
99 | #define GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt */ | |
100 | #define GIVR_IT_REXC 0x07 /* Receive Exception Interrupt */ | |
101 | ||
102 | ||
103 | /* Global Interrupt Channel Register (R/W) */ | |
104 | ||
105 | #define GICR_CHAN 0x1c /* Channel Number Mask */ | |
106 | #define GICR_CHAN_OFF 2 /* Channel Number Offset */ | |
107 | ||
108 | ||
109 | /* Channel Address Register (R/W) */ | |
110 | ||
111 | #define CAR_CHAN 0x07 /* Channel Number Mask */ | |
112 | #define CAR_A7 0x08 /* A7 Address Extension (unused) */ | |
113 | ||
114 | ||
115 | /* Receive Character Status Register (R/O) */ | |
116 | ||
117 | #define RCSR_TOUT 0x80 /* Rx Timeout */ | |
118 | #define RCSR_SCDET 0x70 /* Special Character Detected Mask */ | |
119 | #define RCSR_NO_SC 0x00 /* No Special Characters Detected */ | |
120 | #define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */ | |
121 | #define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */ | |
122 | #define RCSR_SC_3 0x30 /* Special Char 3 Detected */ | |
123 | #define RCSR_SC_4 0x40 /* Special Char 4 Detected */ | |
124 | #define RCSR_BREAK 0x08 /* Break has been detected */ | |
125 | #define RCSR_PE 0x04 /* Parity Error */ | |
126 | #define RCSR_FE 0x02 /* Frame Error */ | |
127 | #define RCSR_OE 0x01 /* Overrun Error */ | |
128 | ||
129 | ||
130 | /* Channel Command Register (R/W) (commands in groups can be OR-ed) */ | |
131 | ||
132 | #define CCR_HARDRESET 0x81 /* Reset the chip */ | |
133 | ||
134 | #define CCR_SOFTRESET 0x80 /* Soft Channel Reset */ | |
135 | ||
136 | #define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */ | |
137 | #define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */ | |
138 | #define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */ | |
139 | ||
140 | #define CCR_SSCH1 0x21 /* Send Special Character 1 */ | |
141 | ||
142 | #define CCR_SSCH2 0x22 /* Send Special Character 2 */ | |
143 | ||
144 | #define CCR_SSCH3 0x23 /* Send Special Character 3 */ | |
145 | ||
146 | #define CCR_SSCH4 0x24 /* Send Special Character 4 */ | |
147 | ||
148 | #define CCR_TXEN 0x18 /* Enable Transmitter */ | |
149 | #define CCR_RXEN 0x12 /* Enable Receiver */ | |
150 | ||
151 | #define CCR_TXDIS 0x14 /* Disable Transmitter */ | |
152 | #define CCR_RXDIS 0x11 /* Disable Receiver */ | |
153 | ||
154 | ||
155 | /* Interrupt Enable Register (R/W) */ | |
156 | ||
157 | #define IER_DSR 0x80 /* Enable interrupt on DSR change */ | |
158 | #define IER_CD 0x40 /* Enable interrupt on CD change */ | |
159 | #define IER_CTS 0x20 /* Enable interrupt on CTS change */ | |
160 | #define IER_RXD 0x10 /* Enable interrupt on Receive Data */ | |
161 | #define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */ | |
162 | #define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */ | |
163 | #define IER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */ | |
164 | #define IER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */ | |
165 | ||
166 | ||
167 | /* Channel Option Register 1 (R/W) */ | |
168 | ||
169 | #define COR1_ODDP 0x80 /* Odd Parity */ | |
170 | #define COR1_PARMODE 0x60 /* Parity Mode mask */ | |
171 | #define COR1_NOPAR 0x00 /* No Parity */ | |
172 | #define COR1_FORCEPAR 0x20 /* Force Parity */ | |
173 | #define COR1_NORMPAR 0x40 /* Normal Parity */ | |
174 | #define COR1_IGNORE 0x10 /* Ignore Parity on RX */ | |
175 | #define COR1_STOPBITS 0x0c /* Number of Stop Bits */ | |
176 | #define COR1_1SB 0x00 /* 1 Stop Bit */ | |
177 | #define COR1_15SB 0x04 /* 1.5 Stop Bits */ | |
178 | #define COR1_2SB 0x08 /* 2 Stop Bits */ | |
179 | #define COR1_CHARLEN 0x03 /* Character Length */ | |
180 | #define COR1_5BITS 0x00 /* 5 bits */ | |
181 | #define COR1_6BITS 0x01 /* 6 bits */ | |
182 | #define COR1_7BITS 0x02 /* 7 bits */ | |
183 | #define COR1_8BITS 0x03 /* 8 bits */ | |
184 | ||
185 | ||
186 | /* Channel Option Register 2 (R/W) */ | |
187 | ||
188 | #define COR2_IXM 0x80 /* Implied XON mode */ | |
189 | #define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */ | |
190 | #define COR2_ETC 0x20 /* Embedded Tx Commands Enable */ | |
191 | #define COR2_LLM 0x10 /* Local Loopback Mode */ | |
192 | #define COR2_RLM 0x08 /* Remote Loopback Mode */ | |
193 | #define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */ | |
194 | #define COR2_CTSAE 0x02 /* CTS Automatic Enable */ | |
195 | #define COR2_DSRAE 0x01 /* DSR Automatic Enable */ | |
196 | ||
197 | ||
198 | /* Channel Option Register 3 (R/W) */ | |
199 | ||
200 | #define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */ | |
201 | #define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */ | |
202 | #define COR3_FCT 0x20 /* Flow-Control Transparency Mode */ | |
203 | #define COR3_SCDE 0x10 /* Special Character Detection Enable */ | |
204 | #define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */ | |
205 | ||
206 | ||
207 | /* Channel Control Status Register (R/O) */ | |
208 | ||
209 | #define CCSR_RXEN 0x80 /* Receiver Enabled */ | |
210 | #define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */ | |
211 | #define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */ | |
212 | #define CCSR_TXEN 0x08 /* Transmitter Enabled */ | |
213 | #define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */ | |
214 | #define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */ | |
215 | ||
216 | ||
217 | /* Modem Change Option Register 1 (R/W) */ | |
218 | ||
219 | #define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */ | |
220 | #define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */ | |
221 | #define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */ | |
222 | #define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */ | |
223 | #define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */ | |
224 | ||
225 | ||
226 | /* Modem Change Option Register 2 (R/W) */ | |
227 | ||
228 | #define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */ | |
229 | #define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */ | |
230 | #define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */ | |
231 | ||
232 | ||
233 | /* Modem Change Register (R/W) */ | |
234 | ||
235 | #define MCR_DSRCHG 0x80 /* DSR Changed */ | |
236 | #define MCR_CDCHG 0x40 /* CD Changed */ | |
237 | #define MCR_CTSCHG 0x20 /* CTS Changed */ | |
238 | ||
239 | ||
240 | /* Modem Signal Value Register (R/W) */ | |
241 | ||
242 | #define MSVR_DSR 0x80 /* Current state of DSR input */ | |
243 | #define MSVR_CD 0x40 /* Current state of CD input */ | |
244 | #define MSVR_CTS 0x20 /* Current state of CTS input */ | |
245 | #define MSVR_DTR 0x02 /* Current state of DTR output */ | |
246 | #define MSVR_RTS 0x01 /* Current state of RTS output */ | |
247 | ||
248 | ||
249 | /* Escape characters */ | |
250 | ||
251 | #define CD180_C_ESC 0x00 /* Escape character */ | |
252 | #define CD180_C_SBRK 0x81 /* Start sending BREAK */ | |
253 | #define CD180_C_DELAY 0x82 /* Delay output */ | |
254 | #define CD180_C_EBRK 0x83 /* Stop sending BREAK */ |