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705b6c7b | 1 | /* |
bb029c67 | 2 | * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $ |
705b6c7b PF |
3 | * |
4 | * Device driver for Microgate SyncLink GT serial adapters. | |
5 | * | |
6 | * written by Paul Fulghum for Microgate Corporation | |
7 | * paulkf@microgate.com | |
8 | * | |
9 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
10 | * | |
11 | * This code is released under the GNU General Public License (GPL) | |
12 | * | |
13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
15 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
16 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
17 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
18 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
19 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
21 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
22 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
23 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
24 | */ | |
25 | ||
26 | /* | |
27 | * DEBUG OUTPUT DEFINITIONS | |
28 | * | |
29 | * uncomment lines below to enable specific types of debug output | |
30 | * | |
31 | * DBGINFO information - most verbose output | |
32 | * DBGERR serious errors | |
33 | * DBGBH bottom half service routine debugging | |
34 | * DBGISR interrupt service routine debugging | |
35 | * DBGDATA output receive and transmit data | |
36 | * DBGTBUF output transmit DMA buffers and registers | |
37 | * DBGRBUF output receive DMA buffers and registers | |
38 | */ | |
39 | ||
40 | #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt | |
41 | #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt | |
42 | #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt | |
43 | #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt | |
44 | #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) | |
45 | //#define DBGTBUF(info) dump_tbufs(info) | |
46 | //#define DBGRBUF(info) dump_rbufs(info) | |
47 | ||
48 | ||
705b6c7b PF |
49 | #include <linux/module.h> |
50 | #include <linux/version.h> | |
51 | #include <linux/errno.h> | |
52 | #include <linux/signal.h> | |
53 | #include <linux/sched.h> | |
54 | #include <linux/timer.h> | |
55 | #include <linux/interrupt.h> | |
56 | #include <linux/pci.h> | |
57 | #include <linux/tty.h> | |
58 | #include <linux/tty_flip.h> | |
59 | #include <linux/serial.h> | |
60 | #include <linux/major.h> | |
61 | #include <linux/string.h> | |
62 | #include <linux/fcntl.h> | |
63 | #include <linux/ptrace.h> | |
64 | #include <linux/ioport.h> | |
65 | #include <linux/mm.h> | |
66 | #include <linux/slab.h> | |
67 | #include <linux/netdevice.h> | |
68 | #include <linux/vmalloc.h> | |
69 | #include <linux/init.h> | |
70 | #include <linux/delay.h> | |
71 | #include <linux/ioctl.h> | |
72 | #include <linux/termios.h> | |
73 | #include <linux/bitops.h> | |
74 | #include <linux/workqueue.h> | |
75 | #include <linux/hdlc.h> | |
3dd1247f | 76 | #include <linux/synclink.h> |
705b6c7b | 77 | |
705b6c7b PF |
78 | #include <asm/system.h> |
79 | #include <asm/io.h> | |
80 | #include <asm/irq.h> | |
81 | #include <asm/dma.h> | |
82 | #include <asm/types.h> | |
83 | #include <asm/uaccess.h> | |
84 | ||
af69c7f9 PF |
85 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) |
86 | #define SYNCLINK_GENERIC_HDLC 1 | |
87 | #else | |
88 | #define SYNCLINK_GENERIC_HDLC 0 | |
705b6c7b PF |
89 | #endif |
90 | ||
91 | /* | |
92 | * module identification | |
93 | */ | |
94 | static char *driver_name = "SyncLink GT"; | |
bb029c67 | 95 | static char *driver_version = "$Revision: 4.50 $"; |
705b6c7b PF |
96 | static char *tty_driver_name = "synclink_gt"; |
97 | static char *tty_dev_prefix = "ttySLG"; | |
98 | MODULE_LICENSE("GPL"); | |
99 | #define MGSL_MAGIC 0x5401 | |
a077c1a0 | 100 | #define MAX_DEVICES 32 |
705b6c7b PF |
101 | |
102 | static struct pci_device_id pci_table[] = { | |
103 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
6f84be84 | 104 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
705b6c7b PF |
105 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
106 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
107 | {0,}, /* terminate list */ | |
108 | }; | |
109 | MODULE_DEVICE_TABLE(pci, pci_table); | |
110 | ||
111 | static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); | |
112 | static void remove_one(struct pci_dev *dev); | |
113 | static struct pci_driver pci_driver = { | |
114 | .name = "synclink_gt", | |
115 | .id_table = pci_table, | |
116 | .probe = init_one, | |
117 | .remove = __devexit_p(remove_one), | |
118 | }; | |
119 | ||
120 | static int pci_registered; | |
121 | ||
122 | /* | |
123 | * module configuration and status | |
124 | */ | |
125 | static struct slgt_info *slgt_device_list; | |
126 | static int slgt_device_count; | |
127 | ||
128 | static int ttymajor; | |
129 | static int debug_level; | |
130 | static int maxframe[MAX_DEVICES]; | |
131 | static int dosyncppp[MAX_DEVICES]; | |
132 | ||
133 | module_param(ttymajor, int, 0); | |
134 | module_param(debug_level, int, 0); | |
135 | module_param_array(maxframe, int, NULL, 0); | |
136 | module_param_array(dosyncppp, int, NULL, 0); | |
137 | ||
138 | MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); | |
139 | MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); | |
140 | MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); | |
141 | MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable"); | |
142 | ||
143 | /* | |
144 | * tty support and callbacks | |
145 | */ | |
705b6c7b PF |
146 | static struct tty_driver *serial_driver; |
147 | ||
148 | static int open(struct tty_struct *tty, struct file * filp); | |
149 | static void close(struct tty_struct *tty, struct file * filp); | |
150 | static void hangup(struct tty_struct *tty); | |
606d099c | 151 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); |
705b6c7b PF |
152 | |
153 | static int write(struct tty_struct *tty, const unsigned char *buf, int count); | |
154 | static void put_char(struct tty_struct *tty, unsigned char ch); | |
155 | static void send_xchar(struct tty_struct *tty, char ch); | |
156 | static void wait_until_sent(struct tty_struct *tty, int timeout); | |
157 | static int write_room(struct tty_struct *tty); | |
158 | static void flush_chars(struct tty_struct *tty); | |
159 | static void flush_buffer(struct tty_struct *tty); | |
160 | static void tx_hold(struct tty_struct *tty); | |
161 | static void tx_release(struct tty_struct *tty); | |
162 | ||
163 | static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg); | |
164 | static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data); | |
165 | static int chars_in_buffer(struct tty_struct *tty); | |
166 | static void throttle(struct tty_struct * tty); | |
167 | static void unthrottle(struct tty_struct * tty); | |
168 | static void set_break(struct tty_struct *tty, int break_state); | |
169 | ||
170 | /* | |
171 | * generic HDLC support and callbacks | |
172 | */ | |
af69c7f9 | 173 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
174 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
175 | static void hdlcdev_tx_done(struct slgt_info *info); | |
176 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); | |
177 | static int hdlcdev_init(struct slgt_info *info); | |
178 | static void hdlcdev_exit(struct slgt_info *info); | |
179 | #endif | |
180 | ||
181 | ||
182 | /* | |
183 | * device specific structures, macros and functions | |
184 | */ | |
185 | ||
186 | #define SLGT_MAX_PORTS 4 | |
187 | #define SLGT_REG_SIZE 256 | |
188 | ||
0080b7aa PF |
189 | /* |
190 | * conditional wait facility | |
191 | */ | |
192 | struct cond_wait { | |
193 | struct cond_wait *next; | |
194 | wait_queue_head_t q; | |
195 | wait_queue_t wait; | |
196 | unsigned int data; | |
197 | }; | |
198 | static void init_cond_wait(struct cond_wait *w, unsigned int data); | |
199 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
200 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
201 | static void flush_cond_wait(struct cond_wait **head); | |
202 | ||
705b6c7b PF |
203 | /* |
204 | * DMA buffer descriptor and access macros | |
205 | */ | |
206 | struct slgt_desc | |
207 | { | |
51ef9c57 AV |
208 | __le16 count; |
209 | __le16 status; | |
210 | __le32 pbuf; /* physical address of data buffer */ | |
211 | __le32 next; /* physical address of next descriptor */ | |
705b6c7b PF |
212 | |
213 | /* driver book keeping */ | |
214 | char *buf; /* virtual address of data buffer */ | |
215 | unsigned int pdesc; /* physical address of this descriptor */ | |
216 | dma_addr_t buf_dma_addr; | |
217 | }; | |
218 | ||
219 | #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) | |
220 | #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) | |
221 | #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) | |
222 | #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) | |
223 | #define desc_count(a) (le16_to_cpu((a).count)) | |
224 | #define desc_status(a) (le16_to_cpu((a).status)) | |
225 | #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) | |
226 | #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) | |
227 | #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) | |
228 | #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) | |
229 | #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) | |
230 | ||
231 | struct _input_signal_events { | |
232 | int ri_up; | |
233 | int ri_down; | |
234 | int dsr_up; | |
235 | int dsr_down; | |
236 | int dcd_up; | |
237 | int dcd_down; | |
238 | int cts_up; | |
239 | int cts_down; | |
240 | }; | |
241 | ||
242 | /* | |
243 | * device instance data structure | |
244 | */ | |
245 | struct slgt_info { | |
246 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | |
247 | ||
248 | struct slgt_info *next_device; /* device list link */ | |
249 | ||
250 | int magic; | |
251 | int flags; | |
252 | ||
253 | char device_name[25]; | |
254 | struct pci_dev *pdev; | |
255 | ||
256 | int port_count; /* count of ports on adapter */ | |
257 | int adapter_num; /* adapter instance number */ | |
258 | int port_num; /* port instance number */ | |
259 | ||
260 | /* array of pointers to port contexts on this adapter */ | |
261 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
262 | ||
263 | int count; /* count of opens */ | |
264 | int line; /* tty line instance number */ | |
265 | unsigned short close_delay; | |
266 | unsigned short closing_wait; /* time to wait before closing */ | |
267 | ||
268 | struct mgsl_icount icount; | |
269 | ||
270 | struct tty_struct *tty; | |
271 | int timeout; | |
272 | int x_char; /* xon/xoff character */ | |
273 | int blocked_open; /* # of blocked opens */ | |
274 | unsigned int read_status_mask; | |
275 | unsigned int ignore_status_mask; | |
276 | ||
277 | wait_queue_head_t open_wait; | |
278 | wait_queue_head_t close_wait; | |
279 | ||
280 | wait_queue_head_t status_event_wait_q; | |
281 | wait_queue_head_t event_wait_q; | |
282 | struct timer_list tx_timer; | |
283 | struct timer_list rx_timer; | |
284 | ||
0080b7aa PF |
285 | unsigned int gpio_present; |
286 | struct cond_wait *gpio_wait_q; | |
287 | ||
705b6c7b PF |
288 | spinlock_t lock; /* spinlock for synchronizing with ISR */ |
289 | ||
290 | struct work_struct task; | |
291 | u32 pending_bh; | |
292 | int bh_requested; | |
293 | int bh_running; | |
294 | ||
295 | int isr_overflow; | |
296 | int irq_requested; /* nonzero if IRQ requested */ | |
297 | int irq_occurred; /* for diagnostics use */ | |
298 | ||
299 | /* device configuration */ | |
300 | ||
301 | unsigned int bus_type; | |
302 | unsigned int irq_level; | |
303 | unsigned long irq_flags; | |
304 | ||
305 | unsigned char __iomem * reg_addr; /* memory mapped registers address */ | |
306 | u32 phys_reg_addr; | |
705b6c7b PF |
307 | int reg_addr_requested; |
308 | ||
309 | MGSL_PARAMS params; /* communications parameters */ | |
310 | u32 idle_mode; | |
311 | u32 max_frame_size; /* as set by device config */ | |
312 | ||
313 | unsigned int raw_rx_size; | |
314 | unsigned int if_mode; | |
315 | ||
316 | /* device status */ | |
317 | ||
318 | int rx_enabled; | |
319 | int rx_restart; | |
320 | ||
321 | int tx_enabled; | |
322 | int tx_active; | |
323 | ||
324 | unsigned char signals; /* serial signal states */ | |
2641dfd9 | 325 | int init_error; /* initialization error */ |
705b6c7b PF |
326 | |
327 | unsigned char *tx_buf; | |
328 | int tx_count; | |
329 | ||
330 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | |
331 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; | |
332 | BOOLEAN drop_rts_on_tx_done; | |
333 | struct _input_signal_events input_signal_events; | |
334 | ||
335 | int dcd_chkcount; /* check counts to prevent */ | |
336 | int cts_chkcount; /* too many IRQs if a signal */ | |
337 | int dsr_chkcount; /* is floating */ | |
338 | int ri_chkcount; | |
339 | ||
340 | char *bufs; /* virtual address of DMA buffer lists */ | |
341 | dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ | |
342 | ||
343 | unsigned int rbuf_count; | |
344 | struct slgt_desc *rbufs; | |
345 | unsigned int rbuf_current; | |
346 | unsigned int rbuf_index; | |
347 | ||
348 | unsigned int tbuf_count; | |
349 | struct slgt_desc *tbufs; | |
350 | unsigned int tbuf_current; | |
351 | unsigned int tbuf_start; | |
352 | ||
353 | unsigned char *tmp_rbuf; | |
354 | unsigned int tmp_rbuf_count; | |
355 | ||
356 | /* SPPP/Cisco HDLC device parts */ | |
357 | ||
358 | int netcount; | |
359 | int dosyncppp; | |
360 | spinlock_t netlock; | |
af69c7f9 | 361 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
362 | struct net_device *netdev; |
363 | #endif | |
364 | ||
365 | }; | |
366 | ||
367 | static MGSL_PARAMS default_params = { | |
368 | .mode = MGSL_MODE_HDLC, | |
369 | .loopback = 0, | |
370 | .flags = HDLC_FLAG_UNDERRUN_ABORT15, | |
371 | .encoding = HDLC_ENCODING_NRZI_SPACE, | |
372 | .clock_speed = 0, | |
373 | .addr_filter = 0xff, | |
374 | .crc_type = HDLC_CRC_16_CCITT, | |
375 | .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, | |
376 | .preamble = HDLC_PREAMBLE_PATTERN_NONE, | |
377 | .data_rate = 9600, | |
378 | .data_bits = 8, | |
379 | .stop_bits = 1, | |
380 | .parity = ASYNC_PARITY_NONE | |
381 | }; | |
382 | ||
383 | ||
384 | #define BH_RECEIVE 1 | |
385 | #define BH_TRANSMIT 2 | |
386 | #define BH_STATUS 4 | |
387 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
388 | ||
389 | #define DMABUFSIZE 256 | |
390 | #define DESC_LIST_SIZE 4096 | |
391 | ||
392 | #define MASK_PARITY BIT1 | |
202af6d5 PF |
393 | #define MASK_FRAMING BIT0 |
394 | #define MASK_BREAK BIT14 | |
705b6c7b PF |
395 | #define MASK_OVERRUN BIT4 |
396 | ||
397 | #define GSR 0x00 /* global status */ | |
0080b7aa PF |
398 | #define JCR 0x04 /* JTAG control */ |
399 | #define IODR 0x08 /* GPIO direction */ | |
400 | #define IOER 0x0c /* GPIO interrupt enable */ | |
401 | #define IOVR 0x10 /* GPIO value */ | |
402 | #define IOSR 0x14 /* GPIO interrupt status */ | |
705b6c7b PF |
403 | #define TDR 0x80 /* tx data */ |
404 | #define RDR 0x80 /* rx data */ | |
405 | #define TCR 0x82 /* tx control */ | |
406 | #define TIR 0x84 /* tx idle */ | |
407 | #define TPR 0x85 /* tx preamble */ | |
408 | #define RCR 0x86 /* rx control */ | |
409 | #define VCR 0x88 /* V.24 control */ | |
410 | #define CCR 0x89 /* clock control */ | |
411 | #define BDR 0x8a /* baud divisor */ | |
412 | #define SCR 0x8c /* serial control */ | |
413 | #define SSR 0x8e /* serial status */ | |
414 | #define RDCSR 0x90 /* rx DMA control/status */ | |
415 | #define TDCSR 0x94 /* tx DMA control/status */ | |
416 | #define RDDAR 0x98 /* rx DMA descriptor address */ | |
417 | #define TDDAR 0x9c /* tx DMA descriptor address */ | |
418 | ||
419 | #define RXIDLE BIT14 | |
420 | #define RXBREAK BIT14 | |
421 | #define IRQ_TXDATA BIT13 | |
422 | #define IRQ_TXIDLE BIT12 | |
423 | #define IRQ_TXUNDER BIT11 /* HDLC */ | |
424 | #define IRQ_RXDATA BIT10 | |
425 | #define IRQ_RXIDLE BIT9 /* HDLC */ | |
426 | #define IRQ_RXBREAK BIT9 /* async */ | |
427 | #define IRQ_RXOVER BIT8 | |
428 | #define IRQ_DSR BIT7 | |
429 | #define IRQ_CTS BIT6 | |
430 | #define IRQ_DCD BIT5 | |
431 | #define IRQ_RI BIT4 | |
432 | #define IRQ_ALL 0x3ff0 | |
433 | #define IRQ_MASTER BIT0 | |
434 | ||
435 | #define slgt_irq_on(info, mask) \ | |
436 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) | |
437 | #define slgt_irq_off(info, mask) \ | |
438 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) | |
439 | ||
440 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); | |
441 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); | |
442 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); | |
443 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); | |
444 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); | |
445 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); | |
446 | ||
447 | static void msc_set_vcr(struct slgt_info *info); | |
448 | ||
449 | static int startup(struct slgt_info *info); | |
450 | static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); | |
451 | static void shutdown(struct slgt_info *info); | |
452 | static void program_hw(struct slgt_info *info); | |
453 | static void change_params(struct slgt_info *info); | |
454 | ||
455 | static int register_test(struct slgt_info *info); | |
456 | static int irq_test(struct slgt_info *info); | |
457 | static int loopback_test(struct slgt_info *info); | |
458 | static int adapter_test(struct slgt_info *info); | |
459 | ||
460 | static void reset_adapter(struct slgt_info *info); | |
461 | static void reset_port(struct slgt_info *info); | |
462 | static void async_mode(struct slgt_info *info); | |
cb10dc9a | 463 | static void sync_mode(struct slgt_info *info); |
705b6c7b PF |
464 | |
465 | static void rx_stop(struct slgt_info *info); | |
466 | static void rx_start(struct slgt_info *info); | |
467 | static void reset_rbufs(struct slgt_info *info); | |
468 | static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); | |
469 | static void rdma_reset(struct slgt_info *info); | |
470 | static int rx_get_frame(struct slgt_info *info); | |
471 | static int rx_get_buf(struct slgt_info *info); | |
472 | ||
473 | static void tx_start(struct slgt_info *info); | |
474 | static void tx_stop(struct slgt_info *info); | |
475 | static void tx_set_idle(struct slgt_info *info); | |
476 | static unsigned int free_tbuf_count(struct slgt_info *info); | |
477 | static void reset_tbufs(struct slgt_info *info); | |
478 | static void tdma_reset(struct slgt_info *info); | |
bb029c67 | 479 | static void tdma_start(struct slgt_info *info); |
705b6c7b PF |
480 | static void tx_load(struct slgt_info *info, const char *buf, unsigned int count); |
481 | ||
482 | static void get_signals(struct slgt_info *info); | |
483 | static void set_signals(struct slgt_info *info); | |
484 | static void enable_loopback(struct slgt_info *info); | |
485 | static void set_rate(struct slgt_info *info, u32 data_rate); | |
486 | ||
487 | static int bh_action(struct slgt_info *info); | |
c4028958 | 488 | static void bh_handler(struct work_struct *work); |
705b6c7b PF |
489 | static void bh_transmit(struct slgt_info *info); |
490 | static void isr_serial(struct slgt_info *info); | |
491 | static void isr_rdma(struct slgt_info *info); | |
492 | static void isr_txeom(struct slgt_info *info, unsigned short status); | |
493 | static void isr_tdma(struct slgt_info *info); | |
705b6c7b PF |
494 | |
495 | static int alloc_dma_bufs(struct slgt_info *info); | |
496 | static void free_dma_bufs(struct slgt_info *info); | |
497 | static int alloc_desc(struct slgt_info *info); | |
498 | static void free_desc(struct slgt_info *info); | |
499 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
500 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
501 | ||
502 | static int alloc_tmp_rbuf(struct slgt_info *info); | |
503 | static void free_tmp_rbuf(struct slgt_info *info); | |
504 | ||
505 | static void tx_timeout(unsigned long context); | |
506 | static void rx_timeout(unsigned long context); | |
507 | ||
508 | /* | |
509 | * ioctl handlers | |
510 | */ | |
511 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); | |
512 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
513 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
514 | static int get_txidle(struct slgt_info *info, int __user *idle_mode); | |
515 | static int set_txidle(struct slgt_info *info, int idle_mode); | |
516 | static int tx_enable(struct slgt_info *info, int enable); | |
517 | static int tx_abort(struct slgt_info *info); | |
518 | static int rx_enable(struct slgt_info *info, int enable); | |
519 | static int modem_input_wait(struct slgt_info *info,int arg); | |
520 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); | |
521 | static int tiocmget(struct tty_struct *tty, struct file *file); | |
522 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
523 | unsigned int set, unsigned int clear); | |
524 | static void set_break(struct tty_struct *tty, int break_state); | |
525 | static int get_interface(struct slgt_info *info, int __user *if_mode); | |
526 | static int set_interface(struct slgt_info *info, int if_mode); | |
0080b7aa PF |
527 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); |
528 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
529 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
705b6c7b PF |
530 | |
531 | /* | |
532 | * driver functions | |
533 | */ | |
534 | static void add_device(struct slgt_info *info); | |
535 | static void device_init(int adapter_num, struct pci_dev *pdev); | |
536 | static int claim_resources(struct slgt_info *info); | |
537 | static void release_resources(struct slgt_info *info); | |
538 | ||
539 | /* | |
540 | * DEBUG OUTPUT CODE | |
541 | */ | |
542 | #ifndef DBGINFO | |
543 | #define DBGINFO(fmt) | |
544 | #endif | |
545 | #ifndef DBGERR | |
546 | #define DBGERR(fmt) | |
547 | #endif | |
548 | #ifndef DBGBH | |
549 | #define DBGBH(fmt) | |
550 | #endif | |
551 | #ifndef DBGISR | |
552 | #define DBGISR(fmt) | |
553 | #endif | |
554 | ||
555 | #ifdef DBGDATA | |
556 | static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) | |
557 | { | |
558 | int i; | |
559 | int linecount; | |
560 | printk("%s %s data:\n",info->device_name, label); | |
561 | while(count) { | |
562 | linecount = (count > 16) ? 16 : count; | |
563 | for(i=0; i < linecount; i++) | |
564 | printk("%02X ",(unsigned char)data[i]); | |
565 | for(;i<17;i++) | |
566 | printk(" "); | |
567 | for(i=0;i<linecount;i++) { | |
568 | if (data[i]>=040 && data[i]<=0176) | |
569 | printk("%c",data[i]); | |
570 | else | |
571 | printk("."); | |
572 | } | |
573 | printk("\n"); | |
574 | data += linecount; | |
575 | count -= linecount; | |
576 | } | |
577 | } | |
578 | #else | |
579 | #define DBGDATA(info, buf, size, label) | |
580 | #endif | |
581 | ||
582 | #ifdef DBGTBUF | |
583 | static void dump_tbufs(struct slgt_info *info) | |
584 | { | |
585 | int i; | |
586 | printk("tbuf_current=%d\n", info->tbuf_current); | |
587 | for (i=0 ; i < info->tbuf_count ; i++) { | |
588 | printk("%d: count=%04X status=%04X\n", | |
589 | i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); | |
590 | } | |
591 | } | |
592 | #else | |
593 | #define DBGTBUF(info) | |
594 | #endif | |
595 | ||
596 | #ifdef DBGRBUF | |
597 | static void dump_rbufs(struct slgt_info *info) | |
598 | { | |
599 | int i; | |
600 | printk("rbuf_current=%d\n", info->rbuf_current); | |
601 | for (i=0 ; i < info->rbuf_count ; i++) { | |
602 | printk("%d: count=%04X status=%04X\n", | |
603 | i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); | |
604 | } | |
605 | } | |
606 | #else | |
607 | #define DBGRBUF(info) | |
608 | #endif | |
609 | ||
610 | static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) | |
611 | { | |
612 | #ifdef SANITY_CHECK | |
613 | if (!info) { | |
614 | printk("null struct slgt_info for (%s) in %s\n", devname, name); | |
615 | return 1; | |
616 | } | |
617 | if (info->magic != MGSL_MAGIC) { | |
618 | printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); | |
619 | return 1; | |
620 | } | |
621 | #else | |
622 | if (!info) | |
623 | return 1; | |
624 | #endif | |
625 | return 0; | |
626 | } | |
627 | ||
628 | /** | |
629 | * line discipline callback wrappers | |
630 | * | |
631 | * The wrappers maintain line discipline references | |
632 | * while calling into the line discipline. | |
633 | * | |
634 | * ldisc_receive_buf - pass receive data to line discipline | |
635 | */ | |
636 | static void ldisc_receive_buf(struct tty_struct *tty, | |
637 | const __u8 *data, char *flags, int count) | |
638 | { | |
639 | struct tty_ldisc *ld; | |
640 | if (!tty) | |
641 | return; | |
642 | ld = tty_ldisc_ref(tty); | |
643 | if (ld) { | |
644 | if (ld->receive_buf) | |
645 | ld->receive_buf(tty, data, flags, count); | |
646 | tty_ldisc_deref(ld); | |
647 | } | |
648 | } | |
649 | ||
650 | /* tty callbacks */ | |
651 | ||
652 | static int open(struct tty_struct *tty, struct file *filp) | |
653 | { | |
654 | struct slgt_info *info; | |
655 | int retval, line; | |
656 | unsigned long flags; | |
657 | ||
658 | line = tty->index; | |
659 | if ((line < 0) || (line >= slgt_device_count)) { | |
660 | DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); | |
661 | return -ENODEV; | |
662 | } | |
663 | ||
664 | info = slgt_device_list; | |
665 | while(info && info->line != line) | |
666 | info = info->next_device; | |
667 | if (sanity_check(info, tty->name, "open")) | |
668 | return -ENODEV; | |
669 | if (info->init_error) { | |
670 | DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); | |
671 | return -ENODEV; | |
672 | } | |
673 | ||
674 | tty->driver_data = info; | |
675 | info->tty = tty; | |
676 | ||
677 | DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count)); | |
678 | ||
679 | /* If port is closing, signal caller to try again */ | |
680 | if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){ | |
681 | if (info->flags & ASYNC_CLOSING) | |
682 | interruptible_sleep_on(&info->close_wait); | |
683 | retval = ((info->flags & ASYNC_HUP_NOTIFY) ? | |
684 | -EAGAIN : -ERESTARTSYS); | |
685 | goto cleanup; | |
686 | } | |
687 | ||
688 | info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; | |
689 | ||
690 | spin_lock_irqsave(&info->netlock, flags); | |
691 | if (info->netcount) { | |
692 | retval = -EBUSY; | |
693 | spin_unlock_irqrestore(&info->netlock, flags); | |
694 | goto cleanup; | |
695 | } | |
696 | info->count++; | |
697 | spin_unlock_irqrestore(&info->netlock, flags); | |
698 | ||
699 | if (info->count == 1) { | |
700 | /* 1st open on this device, init hardware */ | |
701 | retval = startup(info); | |
702 | if (retval < 0) | |
703 | goto cleanup; | |
704 | } | |
705 | ||
706 | retval = block_til_ready(tty, filp, info); | |
707 | if (retval) { | |
708 | DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); | |
709 | goto cleanup; | |
710 | } | |
711 | ||
712 | retval = 0; | |
713 | ||
714 | cleanup: | |
715 | if (retval) { | |
716 | if (tty->count == 1) | |
717 | info->tty = NULL; /* tty layer will release tty struct */ | |
718 | if(info->count) | |
719 | info->count--; | |
720 | } | |
721 | ||
722 | DBGINFO(("%s open rc=%d\n", info->device_name, retval)); | |
723 | return retval; | |
724 | } | |
725 | ||
726 | static void close(struct tty_struct *tty, struct file *filp) | |
727 | { | |
728 | struct slgt_info *info = tty->driver_data; | |
729 | ||
730 | if (sanity_check(info, tty->name, "close")) | |
731 | return; | |
732 | DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count)); | |
733 | ||
734 | if (!info->count) | |
735 | return; | |
736 | ||
737 | if (tty_hung_up_p(filp)) | |
738 | goto cleanup; | |
739 | ||
740 | if ((tty->count == 1) && (info->count != 1)) { | |
741 | /* | |
742 | * tty->count is 1 and the tty structure will be freed. | |
743 | * info->count should be one in this case. | |
744 | * if it's not, correct it so that the port is shutdown. | |
745 | */ | |
746 | DBGERR(("%s close: bad refcount; tty->count=1, " | |
747 | "info->count=%d\n", info->device_name, info->count)); | |
748 | info->count = 1; | |
749 | } | |
750 | ||
751 | info->count--; | |
752 | ||
753 | /* if at least one open remaining, leave hardware active */ | |
754 | if (info->count) | |
755 | goto cleanup; | |
756 | ||
757 | info->flags |= ASYNC_CLOSING; | |
758 | ||
759 | /* set tty->closing to notify line discipline to | |
760 | * only process XON/XOFF characters. Only the N_TTY | |
761 | * discipline appears to use this (ppp does not). | |
762 | */ | |
763 | tty->closing = 1; | |
764 | ||
765 | /* wait for transmit data to clear all layers */ | |
766 | ||
767 | if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) { | |
768 | DBGINFO(("%s call tty_wait_until_sent\n", info->device_name)); | |
769 | tty_wait_until_sent(tty, info->closing_wait); | |
770 | } | |
771 | ||
772 | if (info->flags & ASYNC_INITIALIZED) | |
773 | wait_until_sent(tty, info->timeout); | |
774 | if (tty->driver->flush_buffer) | |
775 | tty->driver->flush_buffer(tty); | |
776 | tty_ldisc_flush(tty); | |
777 | ||
778 | shutdown(info); | |
779 | ||
780 | tty->closing = 0; | |
781 | info->tty = NULL; | |
782 | ||
783 | if (info->blocked_open) { | |
784 | if (info->close_delay) { | |
785 | msleep_interruptible(jiffies_to_msecs(info->close_delay)); | |
786 | } | |
787 | wake_up_interruptible(&info->open_wait); | |
788 | } | |
789 | ||
790 | info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); | |
791 | ||
792 | wake_up_interruptible(&info->close_wait); | |
793 | ||
794 | cleanup: | |
795 | DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count)); | |
796 | } | |
797 | ||
798 | static void hangup(struct tty_struct *tty) | |
799 | { | |
800 | struct slgt_info *info = tty->driver_data; | |
801 | ||
802 | if (sanity_check(info, tty->name, "hangup")) | |
803 | return; | |
804 | DBGINFO(("%s hangup\n", info->device_name)); | |
805 | ||
806 | flush_buffer(tty); | |
807 | shutdown(info); | |
808 | ||
809 | info->count = 0; | |
810 | info->flags &= ~ASYNC_NORMAL_ACTIVE; | |
811 | info->tty = NULL; | |
812 | ||
813 | wake_up_interruptible(&info->open_wait); | |
814 | } | |
815 | ||
606d099c | 816 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
705b6c7b PF |
817 | { |
818 | struct slgt_info *info = tty->driver_data; | |
819 | unsigned long flags; | |
820 | ||
821 | DBGINFO(("%s set_termios\n", tty->driver->name)); | |
822 | ||
705b6c7b PF |
823 | change_params(info); |
824 | ||
825 | /* Handle transition to B0 status */ | |
826 | if (old_termios->c_cflag & CBAUD && | |
827 | !(tty->termios->c_cflag & CBAUD)) { | |
828 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
829 | spin_lock_irqsave(&info->lock,flags); | |
830 | set_signals(info); | |
831 | spin_unlock_irqrestore(&info->lock,flags); | |
832 | } | |
833 | ||
834 | /* Handle transition away from B0 status */ | |
835 | if (!(old_termios->c_cflag & CBAUD) && | |
836 | tty->termios->c_cflag & CBAUD) { | |
837 | info->signals |= SerialSignal_DTR; | |
838 | if (!(tty->termios->c_cflag & CRTSCTS) || | |
839 | !test_bit(TTY_THROTTLED, &tty->flags)) { | |
840 | info->signals |= SerialSignal_RTS; | |
841 | } | |
842 | spin_lock_irqsave(&info->lock,flags); | |
843 | set_signals(info); | |
844 | spin_unlock_irqrestore(&info->lock,flags); | |
845 | } | |
846 | ||
847 | /* Handle turning off CRTSCTS */ | |
848 | if (old_termios->c_cflag & CRTSCTS && | |
849 | !(tty->termios->c_cflag & CRTSCTS)) { | |
850 | tty->hw_stopped = 0; | |
851 | tx_release(tty); | |
852 | } | |
853 | } | |
854 | ||
855 | static int write(struct tty_struct *tty, | |
856 | const unsigned char *buf, int count) | |
857 | { | |
858 | int ret = 0; | |
859 | struct slgt_info *info = tty->driver_data; | |
860 | unsigned long flags; | |
861 | ||
862 | if (sanity_check(info, tty->name, "write")) | |
863 | goto cleanup; | |
864 | DBGINFO(("%s write count=%d\n", info->device_name, count)); | |
865 | ||
326f28e9 | 866 | if (!info->tx_buf) |
705b6c7b PF |
867 | goto cleanup; |
868 | ||
869 | if (count > info->max_frame_size) { | |
870 | ret = -EIO; | |
871 | goto cleanup; | |
872 | } | |
873 | ||
874 | if (!count) | |
875 | goto cleanup; | |
876 | ||
cb10dc9a PF |
877 | if (info->params.mode == MGSL_MODE_RAW || |
878 | info->params.mode == MGSL_MODE_MONOSYNC || | |
879 | info->params.mode == MGSL_MODE_BISYNC) { | |
705b6c7b PF |
880 | unsigned int bufs_needed = (count/DMABUFSIZE); |
881 | unsigned int bufs_free = free_tbuf_count(info); | |
882 | if (count % DMABUFSIZE) | |
883 | ++bufs_needed; | |
884 | if (bufs_needed > bufs_free) | |
885 | goto cleanup; | |
886 | } else { | |
887 | if (info->tx_active) | |
888 | goto cleanup; | |
889 | if (info->tx_count) { | |
890 | /* send accumulated data from send_char() calls */ | |
891 | /* as frame and wait before accepting more data. */ | |
892 | tx_load(info, info->tx_buf, info->tx_count); | |
893 | goto start; | |
894 | } | |
895 | } | |
896 | ||
897 | ret = info->tx_count = count; | |
898 | tx_load(info, buf, count); | |
899 | goto start; | |
900 | ||
901 | start: | |
902 | if (info->tx_count && !tty->stopped && !tty->hw_stopped) { | |
903 | spin_lock_irqsave(&info->lock,flags); | |
904 | if (!info->tx_active) | |
905 | tx_start(info); | |
bb029c67 PF |
906 | else |
907 | tdma_start(info); | |
705b6c7b PF |
908 | spin_unlock_irqrestore(&info->lock,flags); |
909 | } | |
910 | ||
911 | cleanup: | |
912 | DBGINFO(("%s write rc=%d\n", info->device_name, ret)); | |
913 | return ret; | |
914 | } | |
915 | ||
916 | static void put_char(struct tty_struct *tty, unsigned char ch) | |
917 | { | |
918 | struct slgt_info *info = tty->driver_data; | |
919 | unsigned long flags; | |
920 | ||
921 | if (sanity_check(info, tty->name, "put_char")) | |
922 | return; | |
923 | DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); | |
326f28e9 | 924 | if (!info->tx_buf) |
705b6c7b PF |
925 | return; |
926 | spin_lock_irqsave(&info->lock,flags); | |
927 | if (!info->tx_active && (info->tx_count < info->max_frame_size)) | |
928 | info->tx_buf[info->tx_count++] = ch; | |
929 | spin_unlock_irqrestore(&info->lock,flags); | |
930 | } | |
931 | ||
932 | static void send_xchar(struct tty_struct *tty, char ch) | |
933 | { | |
934 | struct slgt_info *info = tty->driver_data; | |
935 | unsigned long flags; | |
936 | ||
937 | if (sanity_check(info, tty->name, "send_xchar")) | |
938 | return; | |
939 | DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); | |
940 | info->x_char = ch; | |
941 | if (ch) { | |
942 | spin_lock_irqsave(&info->lock,flags); | |
943 | if (!info->tx_enabled) | |
944 | tx_start(info); | |
945 | spin_unlock_irqrestore(&info->lock,flags); | |
946 | } | |
947 | } | |
948 | ||
949 | static void wait_until_sent(struct tty_struct *tty, int timeout) | |
950 | { | |
951 | struct slgt_info *info = tty->driver_data; | |
952 | unsigned long orig_jiffies, char_time; | |
953 | ||
954 | if (!info ) | |
955 | return; | |
956 | if (sanity_check(info, tty->name, "wait_until_sent")) | |
957 | return; | |
958 | DBGINFO(("%s wait_until_sent entry\n", info->device_name)); | |
959 | if (!(info->flags & ASYNC_INITIALIZED)) | |
960 | goto exit; | |
961 | ||
962 | orig_jiffies = jiffies; | |
963 | ||
964 | /* Set check interval to 1/5 of estimated time to | |
965 | * send a character, and make it at least 1. The check | |
966 | * interval should also be less than the timeout. | |
967 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
968 | */ | |
969 | ||
970 | if (info->params.data_rate) { | |
971 | char_time = info->timeout/(32 * 5); | |
972 | if (!char_time) | |
973 | char_time++; | |
974 | } else | |
975 | char_time = 1; | |
976 | ||
977 | if (timeout) | |
978 | char_time = min_t(unsigned long, char_time, timeout); | |
979 | ||
980 | while (info->tx_active) { | |
981 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
982 | if (signal_pending(current)) | |
983 | break; | |
984 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
985 | break; | |
986 | } | |
987 | ||
988 | exit: | |
989 | DBGINFO(("%s wait_until_sent exit\n", info->device_name)); | |
990 | } | |
991 | ||
992 | static int write_room(struct tty_struct *tty) | |
993 | { | |
994 | struct slgt_info *info = tty->driver_data; | |
995 | int ret; | |
996 | ||
997 | if (sanity_check(info, tty->name, "write_room")) | |
998 | return 0; | |
999 | ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; | |
1000 | DBGINFO(("%s write_room=%d\n", info->device_name, ret)); | |
1001 | return ret; | |
1002 | } | |
1003 | ||
1004 | static void flush_chars(struct tty_struct *tty) | |
1005 | { | |
1006 | struct slgt_info *info = tty->driver_data; | |
1007 | unsigned long flags; | |
1008 | ||
1009 | if (sanity_check(info, tty->name, "flush_chars")) | |
1010 | return; | |
1011 | DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); | |
1012 | ||
1013 | if (info->tx_count <= 0 || tty->stopped || | |
1014 | tty->hw_stopped || !info->tx_buf) | |
1015 | return; | |
1016 | ||
1017 | DBGINFO(("%s flush_chars start transmit\n", info->device_name)); | |
1018 | ||
1019 | spin_lock_irqsave(&info->lock,flags); | |
1020 | if (!info->tx_active && info->tx_count) { | |
1021 | tx_load(info, info->tx_buf,info->tx_count); | |
1022 | tx_start(info); | |
1023 | } | |
1024 | spin_unlock_irqrestore(&info->lock,flags); | |
1025 | } | |
1026 | ||
1027 | static void flush_buffer(struct tty_struct *tty) | |
1028 | { | |
1029 | struct slgt_info *info = tty->driver_data; | |
1030 | unsigned long flags; | |
1031 | ||
1032 | if (sanity_check(info, tty->name, "flush_buffer")) | |
1033 | return; | |
1034 | DBGINFO(("%s flush_buffer\n", info->device_name)); | |
1035 | ||
1036 | spin_lock_irqsave(&info->lock,flags); | |
1037 | if (!info->tx_active) | |
1038 | info->tx_count = 0; | |
1039 | spin_unlock_irqrestore(&info->lock,flags); | |
1040 | ||
705b6c7b PF |
1041 | tty_wakeup(tty); |
1042 | } | |
1043 | ||
1044 | /* | |
1045 | * throttle (stop) transmitter | |
1046 | */ | |
1047 | static void tx_hold(struct tty_struct *tty) | |
1048 | { | |
1049 | struct slgt_info *info = tty->driver_data; | |
1050 | unsigned long flags; | |
1051 | ||
1052 | if (sanity_check(info, tty->name, "tx_hold")) | |
1053 | return; | |
1054 | DBGINFO(("%s tx_hold\n", info->device_name)); | |
1055 | spin_lock_irqsave(&info->lock,flags); | |
1056 | if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) | |
1057 | tx_stop(info); | |
1058 | spin_unlock_irqrestore(&info->lock,flags); | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * release (start) transmitter | |
1063 | */ | |
1064 | static void tx_release(struct tty_struct *tty) | |
1065 | { | |
1066 | struct slgt_info *info = tty->driver_data; | |
1067 | unsigned long flags; | |
1068 | ||
1069 | if (sanity_check(info, tty->name, "tx_release")) | |
1070 | return; | |
1071 | DBGINFO(("%s tx_release\n", info->device_name)); | |
1072 | spin_lock_irqsave(&info->lock,flags); | |
1073 | if (!info->tx_active && info->tx_count) { | |
1074 | tx_load(info, info->tx_buf, info->tx_count); | |
1075 | tx_start(info); | |
1076 | } | |
1077 | spin_unlock_irqrestore(&info->lock,flags); | |
1078 | } | |
1079 | ||
1080 | /* | |
1081 | * Service an IOCTL request | |
1082 | * | |
1083 | * Arguments | |
1084 | * | |
1085 | * tty pointer to tty instance data | |
1086 | * file pointer to associated file object for device | |
1087 | * cmd IOCTL command code | |
1088 | * arg command argument/context | |
1089 | * | |
1090 | * Return 0 if success, otherwise error code | |
1091 | */ | |
1092 | static int ioctl(struct tty_struct *tty, struct file *file, | |
1093 | unsigned int cmd, unsigned long arg) | |
1094 | { | |
1095 | struct slgt_info *info = tty->driver_data; | |
1096 | struct mgsl_icount cnow; /* kernel counter temps */ | |
1097 | struct serial_icounter_struct __user *p_cuser; /* user space */ | |
1098 | unsigned long flags; | |
1099 | void __user *argp = (void __user *)arg; | |
1100 | ||
1101 | if (sanity_check(info, tty->name, "ioctl")) | |
1102 | return -ENODEV; | |
1103 | DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1104 | ||
1105 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
1106 | (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { | |
1107 | if (tty->flags & (1 << TTY_IO_ERROR)) | |
1108 | return -EIO; | |
1109 | } | |
1110 | ||
1111 | switch (cmd) { | |
1112 | case MGSL_IOCGPARAMS: | |
1113 | return get_params(info, argp); | |
1114 | case MGSL_IOCSPARAMS: | |
1115 | return set_params(info, argp); | |
1116 | case MGSL_IOCGTXIDLE: | |
1117 | return get_txidle(info, argp); | |
1118 | case MGSL_IOCSTXIDLE: | |
1119 | return set_txidle(info, (int)arg); | |
1120 | case MGSL_IOCTXENABLE: | |
1121 | return tx_enable(info, (int)arg); | |
1122 | case MGSL_IOCRXENABLE: | |
1123 | return rx_enable(info, (int)arg); | |
1124 | case MGSL_IOCTXABORT: | |
1125 | return tx_abort(info); | |
1126 | case MGSL_IOCGSTATS: | |
1127 | return get_stats(info, argp); | |
1128 | case MGSL_IOCWAITEVENT: | |
1129 | return wait_mgsl_event(info, argp); | |
1130 | case TIOCMIWAIT: | |
1131 | return modem_input_wait(info,(int)arg); | |
1132 | case MGSL_IOCGIF: | |
1133 | return get_interface(info, argp); | |
1134 | case MGSL_IOCSIF: | |
1135 | return set_interface(info,(int)arg); | |
0080b7aa PF |
1136 | case MGSL_IOCSGPIO: |
1137 | return set_gpio(info, argp); | |
1138 | case MGSL_IOCGGPIO: | |
1139 | return get_gpio(info, argp); | |
1140 | case MGSL_IOCWAITGPIO: | |
1141 | return wait_gpio(info, argp); | |
705b6c7b PF |
1142 | case TIOCGICOUNT: |
1143 | spin_lock_irqsave(&info->lock,flags); | |
1144 | cnow = info->icount; | |
1145 | spin_unlock_irqrestore(&info->lock,flags); | |
1146 | p_cuser = argp; | |
1147 | if (put_user(cnow.cts, &p_cuser->cts) || | |
1148 | put_user(cnow.dsr, &p_cuser->dsr) || | |
1149 | put_user(cnow.rng, &p_cuser->rng) || | |
1150 | put_user(cnow.dcd, &p_cuser->dcd) || | |
1151 | put_user(cnow.rx, &p_cuser->rx) || | |
1152 | put_user(cnow.tx, &p_cuser->tx) || | |
1153 | put_user(cnow.frame, &p_cuser->frame) || | |
1154 | put_user(cnow.overrun, &p_cuser->overrun) || | |
1155 | put_user(cnow.parity, &p_cuser->parity) || | |
1156 | put_user(cnow.brk, &p_cuser->brk) || | |
1157 | put_user(cnow.buf_overrun, &p_cuser->buf_overrun)) | |
1158 | return -EFAULT; | |
1159 | return 0; | |
1160 | default: | |
1161 | return -ENOIOCTLCMD; | |
1162 | } | |
1163 | return 0; | |
1164 | } | |
1165 | ||
2acdb169 PF |
1166 | /* |
1167 | * support for 32 bit ioctl calls on 64 bit systems | |
1168 | */ | |
1169 | #ifdef CONFIG_COMPAT | |
1170 | static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) | |
1171 | { | |
1172 | struct MGSL_PARAMS32 tmp_params; | |
1173 | ||
1174 | DBGINFO(("%s get_params32\n", info->device_name)); | |
1175 | tmp_params.mode = (compat_ulong_t)info->params.mode; | |
1176 | tmp_params.loopback = info->params.loopback; | |
1177 | tmp_params.flags = info->params.flags; | |
1178 | tmp_params.encoding = info->params.encoding; | |
1179 | tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; | |
1180 | tmp_params.addr_filter = info->params.addr_filter; | |
1181 | tmp_params.crc_type = info->params.crc_type; | |
1182 | tmp_params.preamble_length = info->params.preamble_length; | |
1183 | tmp_params.preamble = info->params.preamble; | |
1184 | tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; | |
1185 | tmp_params.data_bits = info->params.data_bits; | |
1186 | tmp_params.stop_bits = info->params.stop_bits; | |
1187 | tmp_params.parity = info->params.parity; | |
1188 | if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) | |
1189 | return -EFAULT; | |
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) | |
1194 | { | |
1195 | struct MGSL_PARAMS32 tmp_params; | |
1196 | ||
1197 | DBGINFO(("%s set_params32\n", info->device_name)); | |
1198 | if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) | |
1199 | return -EFAULT; | |
1200 | ||
1201 | spin_lock(&info->lock); | |
1202 | info->params.mode = tmp_params.mode; | |
1203 | info->params.loopback = tmp_params.loopback; | |
1204 | info->params.flags = tmp_params.flags; | |
1205 | info->params.encoding = tmp_params.encoding; | |
1206 | info->params.clock_speed = tmp_params.clock_speed; | |
1207 | info->params.addr_filter = tmp_params.addr_filter; | |
1208 | info->params.crc_type = tmp_params.crc_type; | |
1209 | info->params.preamble_length = tmp_params.preamble_length; | |
1210 | info->params.preamble = tmp_params.preamble; | |
1211 | info->params.data_rate = tmp_params.data_rate; | |
1212 | info->params.data_bits = tmp_params.data_bits; | |
1213 | info->params.stop_bits = tmp_params.stop_bits; | |
1214 | info->params.parity = tmp_params.parity; | |
1215 | spin_unlock(&info->lock); | |
1216 | ||
1217 | change_params(info); | |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file, | |
1223 | unsigned int cmd, unsigned long arg) | |
1224 | { | |
1225 | struct slgt_info *info = tty->driver_data; | |
1226 | int rc = -ENOIOCTLCMD; | |
1227 | ||
1228 | if (sanity_check(info, tty->name, "compat_ioctl")) | |
1229 | return -ENODEV; | |
1230 | DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1231 | ||
1232 | switch (cmd) { | |
1233 | ||
1234 | case MGSL_IOCSPARAMS32: | |
1235 | rc = set_params32(info, compat_ptr(arg)); | |
1236 | break; | |
1237 | ||
1238 | case MGSL_IOCGPARAMS32: | |
1239 | rc = get_params32(info, compat_ptr(arg)); | |
1240 | break; | |
1241 | ||
1242 | case MGSL_IOCGPARAMS: | |
1243 | case MGSL_IOCSPARAMS: | |
1244 | case MGSL_IOCGTXIDLE: | |
1245 | case MGSL_IOCGSTATS: | |
1246 | case MGSL_IOCWAITEVENT: | |
1247 | case MGSL_IOCGIF: | |
1248 | case MGSL_IOCSGPIO: | |
1249 | case MGSL_IOCGGPIO: | |
1250 | case MGSL_IOCWAITGPIO: | |
1251 | case TIOCGICOUNT: | |
1252 | rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg))); | |
1253 | break; | |
1254 | ||
1255 | case MGSL_IOCSTXIDLE: | |
1256 | case MGSL_IOCTXENABLE: | |
1257 | case MGSL_IOCRXENABLE: | |
1258 | case MGSL_IOCTXABORT: | |
1259 | case TIOCMIWAIT: | |
1260 | case MGSL_IOCSIF: | |
1261 | rc = ioctl(tty, file, cmd, arg); | |
1262 | break; | |
1263 | } | |
1264 | ||
1265 | DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); | |
1266 | return rc; | |
1267 | } | |
1268 | #else | |
1269 | #define slgt_compat_ioctl NULL | |
1270 | #endif /* ifdef CONFIG_COMPAT */ | |
1271 | ||
705b6c7b PF |
1272 | /* |
1273 | * proc fs support | |
1274 | */ | |
1275 | static inline int line_info(char *buf, struct slgt_info *info) | |
1276 | { | |
1277 | char stat_buf[30]; | |
1278 | int ret; | |
1279 | unsigned long flags; | |
1280 | ||
1281 | ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", | |
1282 | info->device_name, info->phys_reg_addr, | |
1283 | info->irq_level, info->max_frame_size); | |
1284 | ||
1285 | /* output current serial signal states */ | |
1286 | spin_lock_irqsave(&info->lock,flags); | |
1287 | get_signals(info); | |
1288 | spin_unlock_irqrestore(&info->lock,flags); | |
1289 | ||
1290 | stat_buf[0] = 0; | |
1291 | stat_buf[1] = 0; | |
1292 | if (info->signals & SerialSignal_RTS) | |
1293 | strcat(stat_buf, "|RTS"); | |
1294 | if (info->signals & SerialSignal_CTS) | |
1295 | strcat(stat_buf, "|CTS"); | |
1296 | if (info->signals & SerialSignal_DTR) | |
1297 | strcat(stat_buf, "|DTR"); | |
1298 | if (info->signals & SerialSignal_DSR) | |
1299 | strcat(stat_buf, "|DSR"); | |
1300 | if (info->signals & SerialSignal_DCD) | |
1301 | strcat(stat_buf, "|CD"); | |
1302 | if (info->signals & SerialSignal_RI) | |
1303 | strcat(stat_buf, "|RI"); | |
1304 | ||
1305 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
1306 | ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d", | |
1307 | info->icount.txok, info->icount.rxok); | |
1308 | if (info->icount.txunder) | |
1309 | ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder); | |
1310 | if (info->icount.txabort) | |
1311 | ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort); | |
1312 | if (info->icount.rxshort) | |
1313 | ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort); | |
1314 | if (info->icount.rxlong) | |
1315 | ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong); | |
1316 | if (info->icount.rxover) | |
1317 | ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover); | |
1318 | if (info->icount.rxcrc) | |
1319 | ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc); | |
1320 | } else { | |
1321 | ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d", | |
1322 | info->icount.tx, info->icount.rx); | |
1323 | if (info->icount.frame) | |
1324 | ret += sprintf(buf+ret, " fe:%d", info->icount.frame); | |
1325 | if (info->icount.parity) | |
1326 | ret += sprintf(buf+ret, " pe:%d", info->icount.parity); | |
1327 | if (info->icount.brk) | |
1328 | ret += sprintf(buf+ret, " brk:%d", info->icount.brk); | |
1329 | if (info->icount.overrun) | |
1330 | ret += sprintf(buf+ret, " oe:%d", info->icount.overrun); | |
1331 | } | |
1332 | ||
1333 | /* Append serial signal status to end */ | |
1334 | ret += sprintf(buf+ret, " %s\n", stat_buf+1); | |
1335 | ||
1336 | ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", | |
1337 | info->tx_active,info->bh_requested,info->bh_running, | |
1338 | info->pending_bh); | |
1339 | ||
1340 | return ret; | |
1341 | } | |
1342 | ||
1343 | /* Called to print information about devices | |
1344 | */ | |
1345 | static int read_proc(char *page, char **start, off_t off, int count, | |
1346 | int *eof, void *data) | |
1347 | { | |
1348 | int len = 0, l; | |
1349 | off_t begin = 0; | |
1350 | struct slgt_info *info; | |
1351 | ||
1352 | len += sprintf(page, "synclink_gt driver:%s\n", driver_version); | |
1353 | ||
1354 | info = slgt_device_list; | |
1355 | while( info ) { | |
1356 | l = line_info(page + len, info); | |
1357 | len += l; | |
1358 | if (len+begin > off+count) | |
1359 | goto done; | |
1360 | if (len+begin < off) { | |
1361 | begin += len; | |
1362 | len = 0; | |
1363 | } | |
1364 | info = info->next_device; | |
1365 | } | |
1366 | ||
1367 | *eof = 1; | |
1368 | done: | |
1369 | if (off >= len+begin) | |
1370 | return 0; | |
1371 | *start = page + (off-begin); | |
1372 | return ((count < begin+len-off) ? count : begin+len-off); | |
1373 | } | |
1374 | ||
1375 | /* | |
1376 | * return count of bytes in transmit buffer | |
1377 | */ | |
1378 | static int chars_in_buffer(struct tty_struct *tty) | |
1379 | { | |
1380 | struct slgt_info *info = tty->driver_data; | |
1381 | if (sanity_check(info, tty->name, "chars_in_buffer")) | |
1382 | return 0; | |
1383 | DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count)); | |
1384 | return info->tx_count; | |
1385 | } | |
1386 | ||
1387 | /* | |
1388 | * signal remote device to throttle send data (our receive data) | |
1389 | */ | |
1390 | static void throttle(struct tty_struct * tty) | |
1391 | { | |
1392 | struct slgt_info *info = tty->driver_data; | |
1393 | unsigned long flags; | |
1394 | ||
1395 | if (sanity_check(info, tty->name, "throttle")) | |
1396 | return; | |
1397 | DBGINFO(("%s throttle\n", info->device_name)); | |
1398 | if (I_IXOFF(tty)) | |
1399 | send_xchar(tty, STOP_CHAR(tty)); | |
1400 | if (tty->termios->c_cflag & CRTSCTS) { | |
1401 | spin_lock_irqsave(&info->lock,flags); | |
1402 | info->signals &= ~SerialSignal_RTS; | |
1403 | set_signals(info); | |
1404 | spin_unlock_irqrestore(&info->lock,flags); | |
1405 | } | |
1406 | } | |
1407 | ||
1408 | /* | |
1409 | * signal remote device to stop throttling send data (our receive data) | |
1410 | */ | |
1411 | static void unthrottle(struct tty_struct * tty) | |
1412 | { | |
1413 | struct slgt_info *info = tty->driver_data; | |
1414 | unsigned long flags; | |
1415 | ||
1416 | if (sanity_check(info, tty->name, "unthrottle")) | |
1417 | return; | |
1418 | DBGINFO(("%s unthrottle\n", info->device_name)); | |
1419 | if (I_IXOFF(tty)) { | |
1420 | if (info->x_char) | |
1421 | info->x_char = 0; | |
1422 | else | |
1423 | send_xchar(tty, START_CHAR(tty)); | |
1424 | } | |
1425 | if (tty->termios->c_cflag & CRTSCTS) { | |
1426 | spin_lock_irqsave(&info->lock,flags); | |
1427 | info->signals |= SerialSignal_RTS; | |
1428 | set_signals(info); | |
1429 | spin_unlock_irqrestore(&info->lock,flags); | |
1430 | } | |
1431 | } | |
1432 | ||
1433 | /* | |
1434 | * set or clear transmit break condition | |
1435 | * break_state -1=set break condition, 0=clear | |
1436 | */ | |
1437 | static void set_break(struct tty_struct *tty, int break_state) | |
1438 | { | |
1439 | struct slgt_info *info = tty->driver_data; | |
1440 | unsigned short value; | |
1441 | unsigned long flags; | |
1442 | ||
1443 | if (sanity_check(info, tty->name, "set_break")) | |
1444 | return; | |
1445 | DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); | |
1446 | ||
1447 | spin_lock_irqsave(&info->lock,flags); | |
1448 | value = rd_reg16(info, TCR); | |
1449 | if (break_state == -1) | |
1450 | value |= BIT6; | |
1451 | else | |
1452 | value &= ~BIT6; | |
1453 | wr_reg16(info, TCR, value); | |
1454 | spin_unlock_irqrestore(&info->lock,flags); | |
1455 | } | |
1456 | ||
af69c7f9 | 1457 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
1458 | |
1459 | /** | |
1460 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
1461 | * set encoding and frame check sequence (FCS) options | |
1462 | * | |
1463 | * dev pointer to network device structure | |
1464 | * encoding serial encoding setting | |
1465 | * parity FCS setting | |
1466 | * | |
1467 | * returns 0 if success, otherwise error code | |
1468 | */ | |
1469 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
1470 | unsigned short parity) | |
1471 | { | |
1472 | struct slgt_info *info = dev_to_port(dev); | |
1473 | unsigned char new_encoding; | |
1474 | unsigned short new_crctype; | |
1475 | ||
1476 | /* return error if TTY interface open */ | |
1477 | if (info->count) | |
1478 | return -EBUSY; | |
1479 | ||
1480 | DBGINFO(("%s hdlcdev_attach\n", info->device_name)); | |
1481 | ||
1482 | switch (encoding) | |
1483 | { | |
1484 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
1485 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
1486 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
1487 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
1488 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
1489 | default: return -EINVAL; | |
1490 | } | |
1491 | ||
1492 | switch (parity) | |
1493 | { | |
1494 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
1495 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
1496 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
1497 | default: return -EINVAL; | |
1498 | } | |
1499 | ||
1500 | info->params.encoding = new_encoding; | |
53b3531b | 1501 | info->params.crc_type = new_crctype; |
705b6c7b PF |
1502 | |
1503 | /* if network interface up, reprogram hardware */ | |
1504 | if (info->netcount) | |
1505 | program_hw(info); | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | /** | |
1511 | * called by generic HDLC layer to send frame | |
1512 | * | |
1513 | * skb socket buffer containing HDLC frame | |
1514 | * dev pointer to network device structure | |
1515 | * | |
1516 | * returns 0 if success, otherwise error code | |
1517 | */ | |
1518 | static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev) | |
1519 | { | |
1520 | struct slgt_info *info = dev_to_port(dev); | |
1521 | struct net_device_stats *stats = hdlc_stats(dev); | |
1522 | unsigned long flags; | |
1523 | ||
1524 | DBGINFO(("%s hdlc_xmit\n", dev->name)); | |
1525 | ||
1526 | /* stop sending until this frame completes */ | |
1527 | netif_stop_queue(dev); | |
1528 | ||
1529 | /* copy data to device buffers */ | |
1530 | info->tx_count = skb->len; | |
1531 | tx_load(info, skb->data, skb->len); | |
1532 | ||
1533 | /* update network statistics */ | |
1534 | stats->tx_packets++; | |
1535 | stats->tx_bytes += skb->len; | |
1536 | ||
1537 | /* done with socket buffer, so free it */ | |
1538 | dev_kfree_skb(skb); | |
1539 | ||
1540 | /* save start time for transmit timeout detection */ | |
1541 | dev->trans_start = jiffies; | |
1542 | ||
1543 | /* start hardware transmitter if necessary */ | |
1544 | spin_lock_irqsave(&info->lock,flags); | |
1545 | if (!info->tx_active) | |
1546 | tx_start(info); | |
1547 | spin_unlock_irqrestore(&info->lock,flags); | |
1548 | ||
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | /** | |
1553 | * called by network layer when interface enabled | |
1554 | * claim resources and initialize hardware | |
1555 | * | |
1556 | * dev pointer to network device structure | |
1557 | * | |
1558 | * returns 0 if success, otherwise error code | |
1559 | */ | |
1560 | static int hdlcdev_open(struct net_device *dev) | |
1561 | { | |
1562 | struct slgt_info *info = dev_to_port(dev); | |
1563 | int rc; | |
1564 | unsigned long flags; | |
1565 | ||
d4c63b7c PF |
1566 | if (!try_module_get(THIS_MODULE)) |
1567 | return -EBUSY; | |
1568 | ||
705b6c7b PF |
1569 | DBGINFO(("%s hdlcdev_open\n", dev->name)); |
1570 | ||
1571 | /* generic HDLC layer open processing */ | |
1572 | if ((rc = hdlc_open(dev))) | |
1573 | return rc; | |
1574 | ||
1575 | /* arbitrate between network and tty opens */ | |
1576 | spin_lock_irqsave(&info->netlock, flags); | |
1577 | if (info->count != 0 || info->netcount != 0) { | |
1578 | DBGINFO(("%s hdlc_open busy\n", dev->name)); | |
1579 | spin_unlock_irqrestore(&info->netlock, flags); | |
1580 | return -EBUSY; | |
1581 | } | |
1582 | info->netcount=1; | |
1583 | spin_unlock_irqrestore(&info->netlock, flags); | |
1584 | ||
1585 | /* claim resources and init adapter */ | |
1586 | if ((rc = startup(info)) != 0) { | |
1587 | spin_lock_irqsave(&info->netlock, flags); | |
1588 | info->netcount=0; | |
1589 | spin_unlock_irqrestore(&info->netlock, flags); | |
1590 | return rc; | |
1591 | } | |
1592 | ||
1593 | /* assert DTR and RTS, apply hardware settings */ | |
1594 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
1595 | program_hw(info); | |
1596 | ||
1597 | /* enable network layer transmit */ | |
1598 | dev->trans_start = jiffies; | |
1599 | netif_start_queue(dev); | |
1600 | ||
1601 | /* inform generic HDLC layer of current DCD status */ | |
1602 | spin_lock_irqsave(&info->lock, flags); | |
1603 | get_signals(info); | |
1604 | spin_unlock_irqrestore(&info->lock, flags); | |
fbeff3c1 KH |
1605 | if (info->signals & SerialSignal_DCD) |
1606 | netif_carrier_on(dev); | |
1607 | else | |
1608 | netif_carrier_off(dev); | |
705b6c7b PF |
1609 | return 0; |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * called by network layer when interface is disabled | |
1614 | * shutdown hardware and release resources | |
1615 | * | |
1616 | * dev pointer to network device structure | |
1617 | * | |
1618 | * returns 0 if success, otherwise error code | |
1619 | */ | |
1620 | static int hdlcdev_close(struct net_device *dev) | |
1621 | { | |
1622 | struct slgt_info *info = dev_to_port(dev); | |
1623 | unsigned long flags; | |
1624 | ||
1625 | DBGINFO(("%s hdlcdev_close\n", dev->name)); | |
1626 | ||
1627 | netif_stop_queue(dev); | |
1628 | ||
1629 | /* shutdown adapter and release resources */ | |
1630 | shutdown(info); | |
1631 | ||
1632 | hdlc_close(dev); | |
1633 | ||
1634 | spin_lock_irqsave(&info->netlock, flags); | |
1635 | info->netcount=0; | |
1636 | spin_unlock_irqrestore(&info->netlock, flags); | |
1637 | ||
d4c63b7c | 1638 | module_put(THIS_MODULE); |
705b6c7b PF |
1639 | return 0; |
1640 | } | |
1641 | ||
1642 | /** | |
1643 | * called by network layer to process IOCTL call to network device | |
1644 | * | |
1645 | * dev pointer to network device structure | |
1646 | * ifr pointer to network interface request structure | |
1647 | * cmd IOCTL command code | |
1648 | * | |
1649 | * returns 0 if success, otherwise error code | |
1650 | */ | |
1651 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1652 | { | |
1653 | const size_t size = sizeof(sync_serial_settings); | |
1654 | sync_serial_settings new_line; | |
1655 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1656 | struct slgt_info *info = dev_to_port(dev); | |
1657 | unsigned int flags; | |
1658 | ||
1659 | DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); | |
1660 | ||
1661 | /* return error if TTY interface open */ | |
1662 | if (info->count) | |
1663 | return -EBUSY; | |
1664 | ||
1665 | if (cmd != SIOCWANDEV) | |
1666 | return hdlc_ioctl(dev, ifr, cmd); | |
1667 | ||
1668 | switch(ifr->ifr_settings.type) { | |
1669 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
1670 | ||
1671 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1672 | if (ifr->ifr_settings.size < size) { | |
1673 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1674 | return -ENOBUFS; | |
1675 | } | |
1676 | ||
1677 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1678 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1679 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1680 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1681 | ||
1682 | switch (flags){ | |
1683 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
1684 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
1685 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
1686 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
1687 | default: new_line.clock_type = CLOCK_DEFAULT; | |
1688 | } | |
1689 | ||
1690 | new_line.clock_rate = info->params.clock_speed; | |
1691 | new_line.loopback = info->params.loopback ? 1:0; | |
1692 | ||
1693 | if (copy_to_user(line, &new_line, size)) | |
1694 | return -EFAULT; | |
1695 | return 0; | |
1696 | ||
1697 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
1698 | ||
1699 | if(!capable(CAP_NET_ADMIN)) | |
1700 | return -EPERM; | |
1701 | if (copy_from_user(&new_line, line, size)) | |
1702 | return -EFAULT; | |
1703 | ||
1704 | switch (new_line.clock_type) | |
1705 | { | |
1706 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
1707 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
1708 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
1709 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
1710 | case CLOCK_DEFAULT: flags = info->params.flags & | |
1711 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1712 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1713 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1714 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
1715 | default: return -EINVAL; | |
1716 | } | |
1717 | ||
1718 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
1719 | return -EINVAL; | |
1720 | ||
1721 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1722 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1723 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1724 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1725 | info->params.flags |= flags; | |
1726 | ||
1727 | info->params.loopback = new_line.loopback; | |
1728 | ||
1729 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
1730 | info->params.clock_speed = new_line.clock_rate; | |
1731 | else | |
1732 | info->params.clock_speed = 0; | |
1733 | ||
1734 | /* if network interface up, reprogram hardware */ | |
1735 | if (info->netcount) | |
1736 | program_hw(info); | |
1737 | return 0; | |
1738 | ||
1739 | default: | |
1740 | return hdlc_ioctl(dev, ifr, cmd); | |
1741 | } | |
1742 | } | |
1743 | ||
1744 | /** | |
1745 | * called by network layer when transmit timeout is detected | |
1746 | * | |
1747 | * dev pointer to network device structure | |
1748 | */ | |
1749 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
1750 | { | |
1751 | struct slgt_info *info = dev_to_port(dev); | |
1752 | struct net_device_stats *stats = hdlc_stats(dev); | |
1753 | unsigned long flags; | |
1754 | ||
1755 | DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); | |
1756 | ||
1757 | stats->tx_errors++; | |
1758 | stats->tx_aborted_errors++; | |
1759 | ||
1760 | spin_lock_irqsave(&info->lock,flags); | |
1761 | tx_stop(info); | |
1762 | spin_unlock_irqrestore(&info->lock,flags); | |
1763 | ||
1764 | netif_wake_queue(dev); | |
1765 | } | |
1766 | ||
1767 | /** | |
1768 | * called by device driver when transmit completes | |
1769 | * reenable network layer transmit if stopped | |
1770 | * | |
1771 | * info pointer to device instance information | |
1772 | */ | |
1773 | static void hdlcdev_tx_done(struct slgt_info *info) | |
1774 | { | |
1775 | if (netif_queue_stopped(info->netdev)) | |
1776 | netif_wake_queue(info->netdev); | |
1777 | } | |
1778 | ||
1779 | /** | |
1780 | * called by device driver when frame received | |
1781 | * pass frame to network layer | |
1782 | * | |
1783 | * info pointer to device instance information | |
1784 | * buf pointer to buffer contianing frame data | |
1785 | * size count of data bytes in buf | |
1786 | */ | |
1787 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) | |
1788 | { | |
1789 | struct sk_buff *skb = dev_alloc_skb(size); | |
1790 | struct net_device *dev = info->netdev; | |
1791 | struct net_device_stats *stats = hdlc_stats(dev); | |
1792 | ||
1793 | DBGINFO(("%s hdlcdev_rx\n", dev->name)); | |
1794 | ||
1795 | if (skb == NULL) { | |
1796 | DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); | |
1797 | stats->rx_dropped++; | |
1798 | return; | |
1799 | } | |
1800 | ||
1801 | memcpy(skb_put(skb, size),buf,size); | |
1802 | ||
1803 | skb->protocol = hdlc_type_trans(skb, info->netdev); | |
1804 | ||
1805 | stats->rx_packets++; | |
1806 | stats->rx_bytes += size; | |
1807 | ||
1808 | netif_rx(skb); | |
1809 | ||
1810 | info->netdev->last_rx = jiffies; | |
1811 | } | |
1812 | ||
1813 | /** | |
1814 | * called by device driver when adding device instance | |
1815 | * do generic HDLC initialization | |
1816 | * | |
1817 | * info pointer to device instance information | |
1818 | * | |
1819 | * returns 0 if success, otherwise error code | |
1820 | */ | |
1821 | static int hdlcdev_init(struct slgt_info *info) | |
1822 | { | |
1823 | int rc; | |
1824 | struct net_device *dev; | |
1825 | hdlc_device *hdlc; | |
1826 | ||
1827 | /* allocate and initialize network and HDLC layer objects */ | |
1828 | ||
1829 | if (!(dev = alloc_hdlcdev(info))) { | |
1830 | printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); | |
1831 | return -ENOMEM; | |
1832 | } | |
1833 | ||
1834 | /* for network layer reporting purposes only */ | |
1835 | dev->mem_start = info->phys_reg_addr; | |
1836 | dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; | |
1837 | dev->irq = info->irq_level; | |
1838 | ||
1839 | /* network layer callbacks and settings */ | |
1840 | dev->do_ioctl = hdlcdev_ioctl; | |
1841 | dev->open = hdlcdev_open; | |
1842 | dev->stop = hdlcdev_close; | |
1843 | dev->tx_timeout = hdlcdev_tx_timeout; | |
1844 | dev->watchdog_timeo = 10*HZ; | |
1845 | dev->tx_queue_len = 50; | |
1846 | ||
1847 | /* generic HDLC layer callbacks and settings */ | |
1848 | hdlc = dev_to_hdlc(dev); | |
1849 | hdlc->attach = hdlcdev_attach; | |
1850 | hdlc->xmit = hdlcdev_xmit; | |
1851 | ||
1852 | /* register objects with HDLC layer */ | |
1853 | if ((rc = register_hdlc_device(dev))) { | |
1854 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); | |
1855 | free_netdev(dev); | |
1856 | return rc; | |
1857 | } | |
1858 | ||
1859 | info->netdev = dev; | |
1860 | return 0; | |
1861 | } | |
1862 | ||
1863 | /** | |
1864 | * called by device driver when removing device instance | |
1865 | * do generic HDLC cleanup | |
1866 | * | |
1867 | * info pointer to device instance information | |
1868 | */ | |
1869 | static void hdlcdev_exit(struct slgt_info *info) | |
1870 | { | |
1871 | unregister_hdlc_device(info->netdev); | |
1872 | free_netdev(info->netdev); | |
1873 | info->netdev = NULL; | |
1874 | } | |
1875 | ||
1876 | #endif /* ifdef CONFIG_HDLC */ | |
1877 | ||
1878 | /* | |
1879 | * get async data from rx DMA buffers | |
1880 | */ | |
1881 | static void rx_async(struct slgt_info *info) | |
1882 | { | |
1883 | struct tty_struct *tty = info->tty; | |
1884 | struct mgsl_icount *icount = &info->icount; | |
1885 | unsigned int start, end; | |
1886 | unsigned char *p; | |
1887 | unsigned char status; | |
1888 | struct slgt_desc *bufs = info->rbufs; | |
1889 | int i, count; | |
33f0f88f AC |
1890 | int chars = 0; |
1891 | int stat; | |
1892 | unsigned char ch; | |
705b6c7b PF |
1893 | |
1894 | start = end = info->rbuf_current; | |
1895 | ||
1896 | while(desc_complete(bufs[end])) { | |
1897 | count = desc_count(bufs[end]) - info->rbuf_index; | |
1898 | p = bufs[end].buf + info->rbuf_index; | |
1899 | ||
1900 | DBGISR(("%s rx_async count=%d\n", info->device_name, count)); | |
1901 | DBGDATA(info, p, count, "rx"); | |
1902 | ||
1903 | for(i=0 ; i < count; i+=2, p+=2) { | |
33f0f88f | 1904 | ch = *p; |
705b6c7b PF |
1905 | icount->rx++; |
1906 | ||
33f0f88f AC |
1907 | stat = 0; |
1908 | ||
202af6d5 PF |
1909 | if ((status = *(p+1) & (BIT1 + BIT0))) { |
1910 | if (status & BIT1) | |
705b6c7b | 1911 | icount->parity++; |
202af6d5 | 1912 | else if (status & BIT0) |
705b6c7b PF |
1913 | icount->frame++; |
1914 | /* discard char if tty control flags say so */ | |
1915 | if (status & info->ignore_status_mask) | |
1916 | continue; | |
202af6d5 | 1917 | if (status & BIT1) |
33f0f88f | 1918 | stat = TTY_PARITY; |
202af6d5 | 1919 | else if (status & BIT0) |
33f0f88f | 1920 | stat = TTY_FRAME; |
705b6c7b PF |
1921 | } |
1922 | if (tty) { | |
33f0f88f AC |
1923 | tty_insert_flip_char(tty, ch, stat); |
1924 | chars++; | |
705b6c7b PF |
1925 | } |
1926 | } | |
1927 | ||
1928 | if (i < count) { | |
1929 | /* receive buffer not completed */ | |
1930 | info->rbuf_index += i; | |
40565f19 | 1931 | mod_timer(&info->rx_timer, jiffies + 1); |
705b6c7b PF |
1932 | break; |
1933 | } | |
1934 | ||
1935 | info->rbuf_index = 0; | |
1936 | free_rbufs(info, end, end); | |
1937 | ||
1938 | if (++end == info->rbuf_count) | |
1939 | end = 0; | |
1940 | ||
1941 | /* if entire list searched then no frame available */ | |
1942 | if (end == start) | |
1943 | break; | |
1944 | } | |
1945 | ||
33f0f88f | 1946 | if (tty && chars) |
705b6c7b PF |
1947 | tty_flip_buffer_push(tty); |
1948 | } | |
1949 | ||
1950 | /* | |
1951 | * return next bottom half action to perform | |
1952 | */ | |
1953 | static int bh_action(struct slgt_info *info) | |
1954 | { | |
1955 | unsigned long flags; | |
1956 | int rc; | |
1957 | ||
1958 | spin_lock_irqsave(&info->lock,flags); | |
1959 | ||
1960 | if (info->pending_bh & BH_RECEIVE) { | |
1961 | info->pending_bh &= ~BH_RECEIVE; | |
1962 | rc = BH_RECEIVE; | |
1963 | } else if (info->pending_bh & BH_TRANSMIT) { | |
1964 | info->pending_bh &= ~BH_TRANSMIT; | |
1965 | rc = BH_TRANSMIT; | |
1966 | } else if (info->pending_bh & BH_STATUS) { | |
1967 | info->pending_bh &= ~BH_STATUS; | |
1968 | rc = BH_STATUS; | |
1969 | } else { | |
1970 | /* Mark BH routine as complete */ | |
1971 | info->bh_running = 0; | |
1972 | info->bh_requested = 0; | |
1973 | rc = 0; | |
1974 | } | |
1975 | ||
1976 | spin_unlock_irqrestore(&info->lock,flags); | |
1977 | ||
1978 | return rc; | |
1979 | } | |
1980 | ||
1981 | /* | |
1982 | * perform bottom half processing | |
1983 | */ | |
c4028958 | 1984 | static void bh_handler(struct work_struct *work) |
705b6c7b | 1985 | { |
c4028958 | 1986 | struct slgt_info *info = container_of(work, struct slgt_info, task); |
705b6c7b PF |
1987 | int action; |
1988 | ||
1989 | if (!info) | |
1990 | return; | |
1991 | info->bh_running = 1; | |
1992 | ||
1993 | while((action = bh_action(info))) { | |
1994 | switch (action) { | |
1995 | case BH_RECEIVE: | |
1996 | DBGBH(("%s bh receive\n", info->device_name)); | |
1997 | switch(info->params.mode) { | |
1998 | case MGSL_MODE_ASYNC: | |
1999 | rx_async(info); | |
2000 | break; | |
2001 | case MGSL_MODE_HDLC: | |
2002 | while(rx_get_frame(info)); | |
2003 | break; | |
2004 | case MGSL_MODE_RAW: | |
cb10dc9a PF |
2005 | case MGSL_MODE_MONOSYNC: |
2006 | case MGSL_MODE_BISYNC: | |
705b6c7b PF |
2007 | while(rx_get_buf(info)); |
2008 | break; | |
2009 | } | |
2010 | /* restart receiver if rx DMA buffers exhausted */ | |
2011 | if (info->rx_restart) | |
2012 | rx_start(info); | |
2013 | break; | |
2014 | case BH_TRANSMIT: | |
2015 | bh_transmit(info); | |
2016 | break; | |
2017 | case BH_STATUS: | |
2018 | DBGBH(("%s bh status\n", info->device_name)); | |
2019 | info->ri_chkcount = 0; | |
2020 | info->dsr_chkcount = 0; | |
2021 | info->dcd_chkcount = 0; | |
2022 | info->cts_chkcount = 0; | |
2023 | break; | |
2024 | default: | |
2025 | DBGBH(("%s unknown action\n", info->device_name)); | |
2026 | break; | |
2027 | } | |
2028 | } | |
2029 | DBGBH(("%s bh_handler exit\n", info->device_name)); | |
2030 | } | |
2031 | ||
2032 | static void bh_transmit(struct slgt_info *info) | |
2033 | { | |
2034 | struct tty_struct *tty = info->tty; | |
2035 | ||
2036 | DBGBH(("%s bh_transmit\n", info->device_name)); | |
b963a844 | 2037 | if (tty) |
705b6c7b | 2038 | tty_wakeup(tty); |
705b6c7b PF |
2039 | } |
2040 | ||
ed8485fb | 2041 | static void dsr_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2042 | { |
ed8485fb PF |
2043 | if (status & BIT3) { |
2044 | info->signals |= SerialSignal_DSR; | |
2045 | info->input_signal_events.dsr_up++; | |
2046 | } else { | |
2047 | info->signals &= ~SerialSignal_DSR; | |
2048 | info->input_signal_events.dsr_down++; | |
2049 | } | |
705b6c7b PF |
2050 | DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); |
2051 | if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2052 | slgt_irq_off(info, IRQ_DSR); | |
2053 | return; | |
2054 | } | |
2055 | info->icount.dsr++; | |
705b6c7b PF |
2056 | wake_up_interruptible(&info->status_event_wait_q); |
2057 | wake_up_interruptible(&info->event_wait_q); | |
2058 | info->pending_bh |= BH_STATUS; | |
2059 | } | |
2060 | ||
ed8485fb | 2061 | static void cts_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2062 | { |
ed8485fb PF |
2063 | if (status & BIT2) { |
2064 | info->signals |= SerialSignal_CTS; | |
2065 | info->input_signal_events.cts_up++; | |
2066 | } else { | |
2067 | info->signals &= ~SerialSignal_CTS; | |
2068 | info->input_signal_events.cts_down++; | |
2069 | } | |
705b6c7b PF |
2070 | DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); |
2071 | if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2072 | slgt_irq_off(info, IRQ_CTS); | |
2073 | return; | |
2074 | } | |
2075 | info->icount.cts++; | |
705b6c7b PF |
2076 | wake_up_interruptible(&info->status_event_wait_q); |
2077 | wake_up_interruptible(&info->event_wait_q); | |
2078 | info->pending_bh |= BH_STATUS; | |
2079 | ||
2080 | if (info->flags & ASYNC_CTS_FLOW) { | |
2081 | if (info->tty) { | |
2082 | if (info->tty->hw_stopped) { | |
2083 | if (info->signals & SerialSignal_CTS) { | |
2084 | info->tty->hw_stopped = 0; | |
2085 | info->pending_bh |= BH_TRANSMIT; | |
2086 | return; | |
2087 | } | |
2088 | } else { | |
2089 | if (!(info->signals & SerialSignal_CTS)) | |
2090 | info->tty->hw_stopped = 1; | |
2091 | } | |
2092 | } | |
2093 | } | |
2094 | } | |
2095 | ||
ed8485fb | 2096 | static void dcd_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2097 | { |
ed8485fb PF |
2098 | if (status & BIT1) { |
2099 | info->signals |= SerialSignal_DCD; | |
2100 | info->input_signal_events.dcd_up++; | |
2101 | } else { | |
2102 | info->signals &= ~SerialSignal_DCD; | |
2103 | info->input_signal_events.dcd_down++; | |
2104 | } | |
705b6c7b PF |
2105 | DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); |
2106 | if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2107 | slgt_irq_off(info, IRQ_DCD); | |
2108 | return; | |
2109 | } | |
2110 | info->icount.dcd++; | |
af69c7f9 | 2111 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
2112 | if (info->netcount) { |
2113 | if (info->signals & SerialSignal_DCD) | |
2114 | netif_carrier_on(info->netdev); | |
2115 | else | |
2116 | netif_carrier_off(info->netdev); | |
2117 | } | |
705b6c7b PF |
2118 | #endif |
2119 | wake_up_interruptible(&info->status_event_wait_q); | |
2120 | wake_up_interruptible(&info->event_wait_q); | |
2121 | info->pending_bh |= BH_STATUS; | |
2122 | ||
2123 | if (info->flags & ASYNC_CHECK_CD) { | |
2124 | if (info->signals & SerialSignal_DCD) | |
2125 | wake_up_interruptible(&info->open_wait); | |
2126 | else { | |
2127 | if (info->tty) | |
2128 | tty_hangup(info->tty); | |
2129 | } | |
2130 | } | |
2131 | } | |
2132 | ||
ed8485fb | 2133 | static void ri_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2134 | { |
ed8485fb PF |
2135 | if (status & BIT0) { |
2136 | info->signals |= SerialSignal_RI; | |
2137 | info->input_signal_events.ri_up++; | |
2138 | } else { | |
2139 | info->signals &= ~SerialSignal_RI; | |
2140 | info->input_signal_events.ri_down++; | |
2141 | } | |
705b6c7b PF |
2142 | DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); |
2143 | if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2144 | slgt_irq_off(info, IRQ_RI); | |
2145 | return; | |
2146 | } | |
ed8485fb | 2147 | info->icount.rng++; |
705b6c7b PF |
2148 | wake_up_interruptible(&info->status_event_wait_q); |
2149 | wake_up_interruptible(&info->event_wait_q); | |
2150 | info->pending_bh |= BH_STATUS; | |
2151 | } | |
2152 | ||
2153 | static void isr_serial(struct slgt_info *info) | |
2154 | { | |
2155 | unsigned short status = rd_reg16(info, SSR); | |
2156 | ||
2157 | DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); | |
2158 | ||
2159 | wr_reg16(info, SSR, status); /* clear pending */ | |
2160 | ||
2161 | info->irq_occurred = 1; | |
2162 | ||
2163 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
2164 | if (status & IRQ_TXIDLE) { | |
2165 | if (info->tx_count) | |
2166 | isr_txeom(info, status); | |
2167 | } | |
2168 | if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { | |
2169 | info->icount.brk++; | |
2170 | /* process break detection if tty control allows */ | |
2171 | if (info->tty) { | |
2172 | if (!(status & info->ignore_status_mask)) { | |
2173 | if (info->read_status_mask & MASK_BREAK) { | |
33f0f88f | 2174 | tty_insert_flip_char(info->tty, 0, TTY_BREAK); |
705b6c7b PF |
2175 | if (info->flags & ASYNC_SAK) |
2176 | do_SAK(info->tty); | |
2177 | } | |
2178 | } | |
2179 | } | |
2180 | } | |
2181 | } else { | |
2182 | if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) | |
2183 | isr_txeom(info, status); | |
2184 | ||
2185 | if (status & IRQ_RXIDLE) { | |
2186 | if (status & RXIDLE) | |
2187 | info->icount.rxidle++; | |
2188 | else | |
2189 | info->icount.exithunt++; | |
2190 | wake_up_interruptible(&info->event_wait_q); | |
2191 | } | |
2192 | ||
2193 | if (status & IRQ_RXOVER) | |
2194 | rx_start(info); | |
2195 | } | |
2196 | ||
2197 | if (status & IRQ_DSR) | |
ed8485fb | 2198 | dsr_change(info, status); |
705b6c7b | 2199 | if (status & IRQ_CTS) |
ed8485fb | 2200 | cts_change(info, status); |
705b6c7b | 2201 | if (status & IRQ_DCD) |
ed8485fb | 2202 | dcd_change(info, status); |
705b6c7b | 2203 | if (status & IRQ_RI) |
ed8485fb | 2204 | ri_change(info, status); |
705b6c7b PF |
2205 | } |
2206 | ||
2207 | static void isr_rdma(struct slgt_info *info) | |
2208 | { | |
2209 | unsigned int status = rd_reg32(info, RDCSR); | |
2210 | ||
2211 | DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); | |
2212 | ||
2213 | /* RDCSR (rx DMA control/status) | |
2214 | * | |
2215 | * 31..07 reserved | |
2216 | * 06 save status byte to DMA buffer | |
2217 | * 05 error | |
2218 | * 04 eol (end of list) | |
2219 | * 03 eob (end of buffer) | |
2220 | * 02 IRQ enable | |
2221 | * 01 reset | |
2222 | * 00 enable | |
2223 | */ | |
2224 | wr_reg32(info, RDCSR, status); /* clear pending */ | |
2225 | ||
2226 | if (status & (BIT5 + BIT4)) { | |
2227 | DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); | |
2228 | info->rx_restart = 1; | |
2229 | } | |
2230 | info->pending_bh |= BH_RECEIVE; | |
2231 | } | |
2232 | ||
2233 | static void isr_tdma(struct slgt_info *info) | |
2234 | { | |
2235 | unsigned int status = rd_reg32(info, TDCSR); | |
2236 | ||
2237 | DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); | |
2238 | ||
2239 | /* TDCSR (tx DMA control/status) | |
2240 | * | |
2241 | * 31..06 reserved | |
2242 | * 05 error | |
2243 | * 04 eol (end of list) | |
2244 | * 03 eob (end of buffer) | |
2245 | * 02 IRQ enable | |
2246 | * 01 reset | |
2247 | * 00 enable | |
2248 | */ | |
2249 | wr_reg32(info, TDCSR, status); /* clear pending */ | |
2250 | ||
2251 | if (status & (BIT5 + BIT4 + BIT3)) { | |
2252 | // another transmit buffer has completed | |
2253 | // run bottom half to get more send data from user | |
2254 | info->pending_bh |= BH_TRANSMIT; | |
2255 | } | |
2256 | } | |
2257 | ||
2258 | static void isr_txeom(struct slgt_info *info, unsigned short status) | |
2259 | { | |
2260 | DBGISR(("%s txeom status=%04x\n", info->device_name, status)); | |
2261 | ||
2262 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
2263 | tdma_reset(info); | |
2264 | reset_tbufs(info); | |
2265 | if (status & IRQ_TXUNDER) { | |
2266 | unsigned short val = rd_reg16(info, TCR); | |
2267 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
2268 | wr_reg16(info, TCR, val); /* clear reset bit */ | |
2269 | } | |
2270 | ||
2271 | if (info->tx_active) { | |
2272 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2273 | if (status & IRQ_TXUNDER) | |
2274 | info->icount.txunder++; | |
2275 | else if (status & IRQ_TXIDLE) | |
2276 | info->icount.txok++; | |
2277 | } | |
2278 | ||
2279 | info->tx_active = 0; | |
2280 | info->tx_count = 0; | |
2281 | ||
2282 | del_timer(&info->tx_timer); | |
2283 | ||
2284 | if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { | |
2285 | info->signals &= ~SerialSignal_RTS; | |
2286 | info->drop_rts_on_tx_done = 0; | |
2287 | set_signals(info); | |
2288 | } | |
2289 | ||
af69c7f9 | 2290 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
2291 | if (info->netcount) |
2292 | hdlcdev_tx_done(info); | |
2293 | else | |
2294 | #endif | |
2295 | { | |
2296 | if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) { | |
2297 | tx_stop(info); | |
2298 | return; | |
2299 | } | |
2300 | info->pending_bh |= BH_TRANSMIT; | |
2301 | } | |
2302 | } | |
2303 | } | |
2304 | ||
0080b7aa PF |
2305 | static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) |
2306 | { | |
2307 | struct cond_wait *w, *prev; | |
2308 | ||
2309 | /* wake processes waiting for specific transitions */ | |
2310 | for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { | |
2311 | if (w->data & changed) { | |
2312 | w->data = state; | |
2313 | wake_up_interruptible(&w->q); | |
2314 | if (prev != NULL) | |
2315 | prev->next = w->next; | |
2316 | else | |
2317 | info->gpio_wait_q = w->next; | |
2318 | } else | |
2319 | prev = w; | |
2320 | } | |
2321 | } | |
2322 | ||
705b6c7b PF |
2323 | /* interrupt service routine |
2324 | * | |
2325 | * irq interrupt number | |
2326 | * dev_id device ID supplied during interrupt registration | |
705b6c7b | 2327 | */ |
a6f97b29 | 2328 | static irqreturn_t slgt_interrupt(int dummy, void *dev_id) |
705b6c7b | 2329 | { |
a6f97b29 | 2330 | struct slgt_info *info = dev_id; |
705b6c7b PF |
2331 | unsigned int gsr; |
2332 | unsigned int i; | |
2333 | ||
a6f97b29 | 2334 | DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); |
705b6c7b PF |
2335 | |
2336 | spin_lock(&info->lock); | |
2337 | ||
2338 | while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { | |
2339 | DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); | |
2340 | info->irq_occurred = 1; | |
2341 | for(i=0; i < info->port_count ; i++) { | |
2342 | if (info->port_array[i] == NULL) | |
2343 | continue; | |
2344 | if (gsr & (BIT8 << i)) | |
2345 | isr_serial(info->port_array[i]); | |
2346 | if (gsr & (BIT16 << (i*2))) | |
2347 | isr_rdma(info->port_array[i]); | |
2348 | if (gsr & (BIT17 << (i*2))) | |
2349 | isr_tdma(info->port_array[i]); | |
2350 | } | |
2351 | } | |
2352 | ||
0080b7aa PF |
2353 | if (info->gpio_present) { |
2354 | unsigned int state; | |
2355 | unsigned int changed; | |
2356 | while ((changed = rd_reg32(info, IOSR)) != 0) { | |
2357 | DBGISR(("%s iosr=%08x\n", info->device_name, changed)); | |
2358 | /* read latched state of GPIO signals */ | |
2359 | state = rd_reg32(info, IOVR); | |
2360 | /* clear pending GPIO interrupt bits */ | |
2361 | wr_reg32(info, IOSR, changed); | |
2362 | for (i=0 ; i < info->port_count ; i++) { | |
2363 | if (info->port_array[i] != NULL) | |
2364 | isr_gpio(info->port_array[i], changed, state); | |
2365 | } | |
2366 | } | |
2367 | } | |
2368 | ||
705b6c7b PF |
2369 | for(i=0; i < info->port_count ; i++) { |
2370 | struct slgt_info *port = info->port_array[i]; | |
2371 | ||
2372 | if (port && (port->count || port->netcount) && | |
2373 | port->pending_bh && !port->bh_running && | |
2374 | !port->bh_requested) { | |
2375 | DBGISR(("%s bh queued\n", port->device_name)); | |
2376 | schedule_work(&port->task); | |
2377 | port->bh_requested = 1; | |
2378 | } | |
2379 | } | |
2380 | ||
2381 | spin_unlock(&info->lock); | |
2382 | ||
a6f97b29 | 2383 | DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); |
705b6c7b PF |
2384 | return IRQ_HANDLED; |
2385 | } | |
2386 | ||
2387 | static int startup(struct slgt_info *info) | |
2388 | { | |
2389 | DBGINFO(("%s startup\n", info->device_name)); | |
2390 | ||
2391 | if (info->flags & ASYNC_INITIALIZED) | |
2392 | return 0; | |
2393 | ||
2394 | if (!info->tx_buf) { | |
2395 | info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
2396 | if (!info->tx_buf) { | |
2397 | DBGERR(("%s can't allocate tx buffer\n", info->device_name)); | |
2398 | return -ENOMEM; | |
2399 | } | |
2400 | } | |
2401 | ||
2402 | info->pending_bh = 0; | |
2403 | ||
2404 | memset(&info->icount, 0, sizeof(info->icount)); | |
2405 | ||
2406 | /* program hardware for current parameters */ | |
2407 | change_params(info); | |
2408 | ||
2409 | if (info->tty) | |
2410 | clear_bit(TTY_IO_ERROR, &info->tty->flags); | |
2411 | ||
2412 | info->flags |= ASYNC_INITIALIZED; | |
2413 | ||
2414 | return 0; | |
2415 | } | |
2416 | ||
2417 | /* | |
2418 | * called by close() and hangup() to shutdown hardware | |
2419 | */ | |
2420 | static void shutdown(struct slgt_info *info) | |
2421 | { | |
2422 | unsigned long flags; | |
2423 | ||
2424 | if (!(info->flags & ASYNC_INITIALIZED)) | |
2425 | return; | |
2426 | ||
2427 | DBGINFO(("%s shutdown\n", info->device_name)); | |
2428 | ||
2429 | /* clear status wait queue because status changes */ | |
2430 | /* can't happen after shutting down the hardware */ | |
2431 | wake_up_interruptible(&info->status_event_wait_q); | |
2432 | wake_up_interruptible(&info->event_wait_q); | |
2433 | ||
2434 | del_timer_sync(&info->tx_timer); | |
2435 | del_timer_sync(&info->rx_timer); | |
2436 | ||
2437 | kfree(info->tx_buf); | |
2438 | info->tx_buf = NULL; | |
2439 | ||
2440 | spin_lock_irqsave(&info->lock,flags); | |
2441 | ||
2442 | tx_stop(info); | |
2443 | rx_stop(info); | |
2444 | ||
2445 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
2446 | ||
2447 | if (!info->tty || info->tty->termios->c_cflag & HUPCL) { | |
2448 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
2449 | set_signals(info); | |
2450 | } | |
2451 | ||
0080b7aa PF |
2452 | flush_cond_wait(&info->gpio_wait_q); |
2453 | ||
705b6c7b PF |
2454 | spin_unlock_irqrestore(&info->lock,flags); |
2455 | ||
2456 | if (info->tty) | |
2457 | set_bit(TTY_IO_ERROR, &info->tty->flags); | |
2458 | ||
2459 | info->flags &= ~ASYNC_INITIALIZED; | |
2460 | } | |
2461 | ||
2462 | static void program_hw(struct slgt_info *info) | |
2463 | { | |
2464 | unsigned long flags; | |
2465 | ||
2466 | spin_lock_irqsave(&info->lock,flags); | |
2467 | ||
2468 | rx_stop(info); | |
2469 | tx_stop(info); | |
2470 | ||
cb10dc9a | 2471 | if (info->params.mode != MGSL_MODE_ASYNC || |
705b6c7b | 2472 | info->netcount) |
cb10dc9a | 2473 | sync_mode(info); |
705b6c7b PF |
2474 | else |
2475 | async_mode(info); | |
2476 | ||
2477 | set_signals(info); | |
2478 | ||
2479 | info->dcd_chkcount = 0; | |
2480 | info->cts_chkcount = 0; | |
2481 | info->ri_chkcount = 0; | |
2482 | info->dsr_chkcount = 0; | |
2483 | ||
2484 | slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR); | |
2485 | get_signals(info); | |
2486 | ||
2487 | if (info->netcount || | |
2488 | (info->tty && info->tty->termios->c_cflag & CREAD)) | |
2489 | rx_start(info); | |
2490 | ||
2491 | spin_unlock_irqrestore(&info->lock,flags); | |
2492 | } | |
2493 | ||
2494 | /* | |
2495 | * reconfigure adapter based on new parameters | |
2496 | */ | |
2497 | static void change_params(struct slgt_info *info) | |
2498 | { | |
2499 | unsigned cflag; | |
2500 | int bits_per_char; | |
2501 | ||
2502 | if (!info->tty || !info->tty->termios) | |
2503 | return; | |
2504 | DBGINFO(("%s change_params\n", info->device_name)); | |
2505 | ||
2506 | cflag = info->tty->termios->c_cflag; | |
2507 | ||
2508 | /* if B0 rate (hangup) specified then negate DTR and RTS */ | |
2509 | /* otherwise assert DTR and RTS */ | |
2510 | if (cflag & CBAUD) | |
2511 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2512 | else | |
2513 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
2514 | ||
2515 | /* byte size and parity */ | |
2516 | ||
2517 | switch (cflag & CSIZE) { | |
2518 | case CS5: info->params.data_bits = 5; break; | |
2519 | case CS6: info->params.data_bits = 6; break; | |
2520 | case CS7: info->params.data_bits = 7; break; | |
2521 | case CS8: info->params.data_bits = 8; break; | |
2522 | default: info->params.data_bits = 7; break; | |
2523 | } | |
2524 | ||
2525 | info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; | |
2526 | ||
2527 | if (cflag & PARENB) | |
2528 | info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; | |
2529 | else | |
2530 | info->params.parity = ASYNC_PARITY_NONE; | |
2531 | ||
2532 | /* calculate number of jiffies to transmit a full | |
2533 | * FIFO (32 bytes) at specified data rate | |
2534 | */ | |
2535 | bits_per_char = info->params.data_bits + | |
2536 | info->params.stop_bits + 1; | |
2537 | ||
2538 | info->params.data_rate = tty_get_baud_rate(info->tty); | |
2539 | ||
2540 | if (info->params.data_rate) { | |
2541 | info->timeout = (32*HZ*bits_per_char) / | |
2542 | info->params.data_rate; | |
2543 | } | |
2544 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
2545 | ||
2546 | if (cflag & CRTSCTS) | |
2547 | info->flags |= ASYNC_CTS_FLOW; | |
2548 | else | |
2549 | info->flags &= ~ASYNC_CTS_FLOW; | |
2550 | ||
2551 | if (cflag & CLOCAL) | |
2552 | info->flags &= ~ASYNC_CHECK_CD; | |
2553 | else | |
2554 | info->flags |= ASYNC_CHECK_CD; | |
2555 | ||
2556 | /* process tty input control flags */ | |
2557 | ||
2558 | info->read_status_mask = IRQ_RXOVER; | |
2559 | if (I_INPCK(info->tty)) | |
2560 | info->read_status_mask |= MASK_PARITY | MASK_FRAMING; | |
2561 | if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) | |
2562 | info->read_status_mask |= MASK_BREAK; | |
2563 | if (I_IGNPAR(info->tty)) | |
2564 | info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; | |
2565 | if (I_IGNBRK(info->tty)) { | |
2566 | info->ignore_status_mask |= MASK_BREAK; | |
2567 | /* If ignoring parity and break indicators, ignore | |
2568 | * overruns too. (For real raw support). | |
2569 | */ | |
2570 | if (I_IGNPAR(info->tty)) | |
2571 | info->ignore_status_mask |= MASK_OVERRUN; | |
2572 | } | |
2573 | ||
2574 | program_hw(info); | |
2575 | } | |
2576 | ||
2577 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) | |
2578 | { | |
2579 | DBGINFO(("%s get_stats\n", info->device_name)); | |
2580 | if (!user_icount) { | |
2581 | memset(&info->icount, 0, sizeof(info->icount)); | |
2582 | } else { | |
2583 | if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) | |
2584 | return -EFAULT; | |
2585 | } | |
2586 | return 0; | |
2587 | } | |
2588 | ||
2589 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) | |
2590 | { | |
2591 | DBGINFO(("%s get_params\n", info->device_name)); | |
2592 | if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) | |
2593 | return -EFAULT; | |
2594 | return 0; | |
2595 | } | |
2596 | ||
2597 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) | |
2598 | { | |
2599 | unsigned long flags; | |
2600 | MGSL_PARAMS tmp_params; | |
2601 | ||
2602 | DBGINFO(("%s set_params\n", info->device_name)); | |
2603 | if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) | |
2604 | return -EFAULT; | |
2605 | ||
2606 | spin_lock_irqsave(&info->lock, flags); | |
2607 | memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); | |
2608 | spin_unlock_irqrestore(&info->lock, flags); | |
2609 | ||
2610 | change_params(info); | |
2611 | ||
2612 | return 0; | |
2613 | } | |
2614 | ||
2615 | static int get_txidle(struct slgt_info *info, int __user *idle_mode) | |
2616 | { | |
2617 | DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); | |
2618 | if (put_user(info->idle_mode, idle_mode)) | |
2619 | return -EFAULT; | |
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | static int set_txidle(struct slgt_info *info, int idle_mode) | |
2624 | { | |
2625 | unsigned long flags; | |
2626 | DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); | |
2627 | spin_lock_irqsave(&info->lock,flags); | |
2628 | info->idle_mode = idle_mode; | |
643f3319 PF |
2629 | if (info->params.mode != MGSL_MODE_ASYNC) |
2630 | tx_set_idle(info); | |
705b6c7b PF |
2631 | spin_unlock_irqrestore(&info->lock,flags); |
2632 | return 0; | |
2633 | } | |
2634 | ||
2635 | static int tx_enable(struct slgt_info *info, int enable) | |
2636 | { | |
2637 | unsigned long flags; | |
2638 | DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); | |
2639 | spin_lock_irqsave(&info->lock,flags); | |
2640 | if (enable) { | |
2641 | if (!info->tx_enabled) | |
2642 | tx_start(info); | |
2643 | } else { | |
2644 | if (info->tx_enabled) | |
2645 | tx_stop(info); | |
2646 | } | |
2647 | spin_unlock_irqrestore(&info->lock,flags); | |
2648 | return 0; | |
2649 | } | |
2650 | ||
2651 | /* | |
2652 | * abort transmit HDLC frame | |
2653 | */ | |
2654 | static int tx_abort(struct slgt_info *info) | |
2655 | { | |
2656 | unsigned long flags; | |
2657 | DBGINFO(("%s tx_abort\n", info->device_name)); | |
2658 | spin_lock_irqsave(&info->lock,flags); | |
2659 | tdma_reset(info); | |
2660 | spin_unlock_irqrestore(&info->lock,flags); | |
2661 | return 0; | |
2662 | } | |
2663 | ||
2664 | static int rx_enable(struct slgt_info *info, int enable) | |
2665 | { | |
2666 | unsigned long flags; | |
2667 | DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable)); | |
2668 | spin_lock_irqsave(&info->lock,flags); | |
2669 | if (enable) { | |
2670 | if (!info->rx_enabled) | |
2671 | rx_start(info); | |
cb10dc9a PF |
2672 | else if (enable == 2) { |
2673 | /* force hunt mode (write 1 to RCR[3]) */ | |
2674 | wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); | |
2675 | } | |
705b6c7b PF |
2676 | } else { |
2677 | if (info->rx_enabled) | |
2678 | rx_stop(info); | |
2679 | } | |
2680 | spin_unlock_irqrestore(&info->lock,flags); | |
2681 | return 0; | |
2682 | } | |
2683 | ||
2684 | /* | |
2685 | * wait for specified event to occur | |
2686 | */ | |
2687 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) | |
2688 | { | |
2689 | unsigned long flags; | |
2690 | int s; | |
2691 | int rc=0; | |
2692 | struct mgsl_icount cprev, cnow; | |
2693 | int events; | |
2694 | int mask; | |
2695 | struct _input_signal_events oldsigs, newsigs; | |
2696 | DECLARE_WAITQUEUE(wait, current); | |
2697 | ||
2698 | if (get_user(mask, mask_ptr)) | |
2699 | return -EFAULT; | |
2700 | ||
2701 | DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); | |
2702 | ||
2703 | spin_lock_irqsave(&info->lock,flags); | |
2704 | ||
2705 | /* return immediately if state matches requested events */ | |
2706 | get_signals(info); | |
2707 | s = info->signals; | |
2708 | ||
2709 | events = mask & | |
2710 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
2711 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
2712 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
2713 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
2714 | if (events) { | |
2715 | spin_unlock_irqrestore(&info->lock,flags); | |
2716 | goto exit; | |
2717 | } | |
2718 | ||
2719 | /* save current irq counts */ | |
2720 | cprev = info->icount; | |
2721 | oldsigs = info->input_signal_events; | |
2722 | ||
2723 | /* enable hunt and idle irqs if needed */ | |
2724 | if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { | |
2725 | unsigned short val = rd_reg16(info, SCR); | |
2726 | if (!(val & IRQ_RXIDLE)) | |
2727 | wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); | |
2728 | } | |
2729 | ||
2730 | set_current_state(TASK_INTERRUPTIBLE); | |
2731 | add_wait_queue(&info->event_wait_q, &wait); | |
2732 | ||
2733 | spin_unlock_irqrestore(&info->lock,flags); | |
2734 | ||
2735 | for(;;) { | |
2736 | schedule(); | |
2737 | if (signal_pending(current)) { | |
2738 | rc = -ERESTARTSYS; | |
2739 | break; | |
2740 | } | |
2741 | ||
2742 | /* get current irq counts */ | |
2743 | spin_lock_irqsave(&info->lock,flags); | |
2744 | cnow = info->icount; | |
2745 | newsigs = info->input_signal_events; | |
2746 | set_current_state(TASK_INTERRUPTIBLE); | |
2747 | spin_unlock_irqrestore(&info->lock,flags); | |
2748 | ||
2749 | /* if no change, wait aborted for some reason */ | |
2750 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
2751 | newsigs.dsr_down == oldsigs.dsr_down && | |
2752 | newsigs.dcd_up == oldsigs.dcd_up && | |
2753 | newsigs.dcd_down == oldsigs.dcd_down && | |
2754 | newsigs.cts_up == oldsigs.cts_up && | |
2755 | newsigs.cts_down == oldsigs.cts_down && | |
2756 | newsigs.ri_up == oldsigs.ri_up && | |
2757 | newsigs.ri_down == oldsigs.ri_down && | |
2758 | cnow.exithunt == cprev.exithunt && | |
2759 | cnow.rxidle == cprev.rxidle) { | |
2760 | rc = -EIO; | |
2761 | break; | |
2762 | } | |
2763 | ||
2764 | events = mask & | |
2765 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
2766 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
2767 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
2768 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
2769 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
2770 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
2771 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
2772 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
2773 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
2774 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
2775 | if (events) | |
2776 | break; | |
2777 | ||
2778 | cprev = cnow; | |
2779 | oldsigs = newsigs; | |
2780 | } | |
2781 | ||
2782 | remove_wait_queue(&info->event_wait_q, &wait); | |
2783 | set_current_state(TASK_RUNNING); | |
2784 | ||
2785 | ||
2786 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
2787 | spin_lock_irqsave(&info->lock,flags); | |
2788 | if (!waitqueue_active(&info->event_wait_q)) { | |
2789 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
2790 | wr_reg16(info, SCR, | |
2791 | (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); | |
2792 | } | |
2793 | spin_unlock_irqrestore(&info->lock,flags); | |
2794 | } | |
2795 | exit: | |
2796 | if (rc == 0) | |
2797 | rc = put_user(events, mask_ptr); | |
2798 | return rc; | |
2799 | } | |
2800 | ||
2801 | static int get_interface(struct slgt_info *info, int __user *if_mode) | |
2802 | { | |
2803 | DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); | |
2804 | if (put_user(info->if_mode, if_mode)) | |
2805 | return -EFAULT; | |
2806 | return 0; | |
2807 | } | |
2808 | ||
2809 | static int set_interface(struct slgt_info *info, int if_mode) | |
2810 | { | |
2811 | unsigned long flags; | |
35fbd397 | 2812 | unsigned short val; |
705b6c7b PF |
2813 | |
2814 | DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); | |
2815 | spin_lock_irqsave(&info->lock,flags); | |
2816 | info->if_mode = if_mode; | |
2817 | ||
2818 | msc_set_vcr(info); | |
2819 | ||
2820 | /* TCR (tx control) 07 1=RTS driver control */ | |
2821 | val = rd_reg16(info, TCR); | |
2822 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
2823 | val |= BIT7; | |
2824 | else | |
2825 | val &= ~BIT7; | |
2826 | wr_reg16(info, TCR, val); | |
2827 | ||
2828 | spin_unlock_irqrestore(&info->lock,flags); | |
2829 | return 0; | |
2830 | } | |
2831 | ||
0080b7aa PF |
2832 | /* |
2833 | * set general purpose IO pin state and direction | |
2834 | * | |
2835 | * user_gpio fields: | |
2836 | * state each bit indicates a pin state | |
2837 | * smask set bit indicates pin state to set | |
2838 | * dir each bit indicates a pin direction (0=input, 1=output) | |
2839 | * dmask set bit indicates pin direction to set | |
2840 | */ | |
2841 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2842 | { | |
2843 | unsigned long flags; | |
2844 | struct gpio_desc gpio; | |
2845 | __u32 data; | |
2846 | ||
2847 | if (!info->gpio_present) | |
2848 | return -EINVAL; | |
2849 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
2850 | return -EFAULT; | |
2851 | DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", | |
2852 | info->device_name, gpio.state, gpio.smask, | |
2853 | gpio.dir, gpio.dmask)); | |
2854 | ||
2855 | spin_lock_irqsave(&info->lock,flags); | |
2856 | if (gpio.dmask) { | |
2857 | data = rd_reg32(info, IODR); | |
2858 | data |= gpio.dmask & gpio.dir; | |
2859 | data &= ~(gpio.dmask & ~gpio.dir); | |
2860 | wr_reg32(info, IODR, data); | |
2861 | } | |
2862 | if (gpio.smask) { | |
2863 | data = rd_reg32(info, IOVR); | |
2864 | data |= gpio.smask & gpio.state; | |
2865 | data &= ~(gpio.smask & ~gpio.state); | |
2866 | wr_reg32(info, IOVR, data); | |
2867 | } | |
2868 | spin_unlock_irqrestore(&info->lock,flags); | |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | ||
2873 | /* | |
2874 | * get general purpose IO pin state and direction | |
2875 | */ | |
2876 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2877 | { | |
2878 | struct gpio_desc gpio; | |
2879 | if (!info->gpio_present) | |
2880 | return -EINVAL; | |
2881 | gpio.state = rd_reg32(info, IOVR); | |
2882 | gpio.smask = 0xffffffff; | |
2883 | gpio.dir = rd_reg32(info, IODR); | |
2884 | gpio.dmask = 0xffffffff; | |
2885 | if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
2886 | return -EFAULT; | |
2887 | DBGINFO(("%s get_gpio state=%08x dir=%08x\n", | |
2888 | info->device_name, gpio.state, gpio.dir)); | |
2889 | return 0; | |
2890 | } | |
2891 | ||
2892 | /* | |
2893 | * conditional wait facility | |
2894 | */ | |
2895 | static void init_cond_wait(struct cond_wait *w, unsigned int data) | |
2896 | { | |
2897 | init_waitqueue_head(&w->q); | |
2898 | init_waitqueue_entry(&w->wait, current); | |
2899 | w->data = data; | |
2900 | } | |
2901 | ||
2902 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) | |
2903 | { | |
2904 | set_current_state(TASK_INTERRUPTIBLE); | |
2905 | add_wait_queue(&w->q, &w->wait); | |
2906 | w->next = *head; | |
2907 | *head = w; | |
2908 | } | |
2909 | ||
2910 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) | |
2911 | { | |
2912 | struct cond_wait *w, *prev; | |
2913 | remove_wait_queue(&cw->q, &cw->wait); | |
2914 | set_current_state(TASK_RUNNING); | |
2915 | for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { | |
2916 | if (w == cw) { | |
2917 | if (prev != NULL) | |
2918 | prev->next = w->next; | |
2919 | else | |
2920 | *head = w->next; | |
2921 | break; | |
2922 | } | |
2923 | } | |
2924 | } | |
2925 | ||
2926 | static void flush_cond_wait(struct cond_wait **head) | |
2927 | { | |
2928 | while (*head != NULL) { | |
2929 | wake_up_interruptible(&(*head)->q); | |
2930 | *head = (*head)->next; | |
2931 | } | |
2932 | } | |
2933 | ||
2934 | /* | |
2935 | * wait for general purpose I/O pin(s) to enter specified state | |
2936 | * | |
2937 | * user_gpio fields: | |
2938 | * state - bit indicates target pin state | |
2939 | * smask - set bit indicates watched pin | |
2940 | * | |
2941 | * The wait ends when at least one watched pin enters the specified | |
2942 | * state. When 0 (no error) is returned, user_gpio->state is set to the | |
2943 | * state of all GPIO pins when the wait ends. | |
2944 | * | |
2945 | * Note: Each pin may be a dedicated input, dedicated output, or | |
2946 | * configurable input/output. The number and configuration of pins | |
2947 | * varies with the specific adapter model. Only input pins (dedicated | |
2948 | * or configured) can be monitored with this function. | |
2949 | */ | |
2950 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2951 | { | |
2952 | unsigned long flags; | |
2953 | int rc = 0; | |
2954 | struct gpio_desc gpio; | |
2955 | struct cond_wait wait; | |
2956 | u32 state; | |
2957 | ||
2958 | if (!info->gpio_present) | |
2959 | return -EINVAL; | |
2960 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
2961 | return -EFAULT; | |
2962 | DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", | |
2963 | info->device_name, gpio.state, gpio.smask)); | |
2964 | /* ignore output pins identified by set IODR bit */ | |
2965 | if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) | |
2966 | return -EINVAL; | |
2967 | init_cond_wait(&wait, gpio.smask); | |
2968 | ||
2969 | spin_lock_irqsave(&info->lock, flags); | |
2970 | /* enable interrupts for watched pins */ | |
2971 | wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); | |
2972 | /* get current pin states */ | |
2973 | state = rd_reg32(info, IOVR); | |
2974 | ||
2975 | if (gpio.smask & ~(state ^ gpio.state)) { | |
2976 | /* already in target state */ | |
2977 | gpio.state = state; | |
2978 | } else { | |
2979 | /* wait for target state */ | |
2980 | add_cond_wait(&info->gpio_wait_q, &wait); | |
2981 | spin_unlock_irqrestore(&info->lock, flags); | |
2982 | schedule(); | |
2983 | if (signal_pending(current)) | |
2984 | rc = -ERESTARTSYS; | |
2985 | else | |
2986 | gpio.state = wait.data; | |
2987 | spin_lock_irqsave(&info->lock, flags); | |
2988 | remove_cond_wait(&info->gpio_wait_q, &wait); | |
2989 | } | |
2990 | ||
2991 | /* disable all GPIO interrupts if no waiting processes */ | |
2992 | if (info->gpio_wait_q == NULL) | |
2993 | wr_reg32(info, IOER, 0); | |
2994 | spin_unlock_irqrestore(&info->lock,flags); | |
2995 | ||
2996 | if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
2997 | rc = -EFAULT; | |
2998 | return rc; | |
2999 | } | |
3000 | ||
705b6c7b PF |
3001 | static int modem_input_wait(struct slgt_info *info,int arg) |
3002 | { | |
3003 | unsigned long flags; | |
3004 | int rc; | |
3005 | struct mgsl_icount cprev, cnow; | |
3006 | DECLARE_WAITQUEUE(wait, current); | |
3007 | ||
3008 | /* save current irq counts */ | |
3009 | spin_lock_irqsave(&info->lock,flags); | |
3010 | cprev = info->icount; | |
3011 | add_wait_queue(&info->status_event_wait_q, &wait); | |
3012 | set_current_state(TASK_INTERRUPTIBLE); | |
3013 | spin_unlock_irqrestore(&info->lock,flags); | |
3014 | ||
3015 | for(;;) { | |
3016 | schedule(); | |
3017 | if (signal_pending(current)) { | |
3018 | rc = -ERESTARTSYS; | |
3019 | break; | |
3020 | } | |
3021 | ||
3022 | /* get new irq counts */ | |
3023 | spin_lock_irqsave(&info->lock,flags); | |
3024 | cnow = info->icount; | |
3025 | set_current_state(TASK_INTERRUPTIBLE); | |
3026 | spin_unlock_irqrestore(&info->lock,flags); | |
3027 | ||
3028 | /* if no change, wait aborted for some reason */ | |
3029 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
3030 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
3031 | rc = -EIO; | |
3032 | break; | |
3033 | } | |
3034 | ||
3035 | /* check for change in caller specified modem input */ | |
3036 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
3037 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
3038 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
3039 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
3040 | rc = 0; | |
3041 | break; | |
3042 | } | |
3043 | ||
3044 | cprev = cnow; | |
3045 | } | |
3046 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
3047 | set_current_state(TASK_RUNNING); | |
3048 | return rc; | |
3049 | } | |
3050 | ||
3051 | /* | |
3052 | * return state of serial control and status signals | |
3053 | */ | |
3054 | static int tiocmget(struct tty_struct *tty, struct file *file) | |
3055 | { | |
3056 | struct slgt_info *info = tty->driver_data; | |
3057 | unsigned int result; | |
3058 | unsigned long flags; | |
3059 | ||
3060 | spin_lock_irqsave(&info->lock,flags); | |
3061 | get_signals(info); | |
3062 | spin_unlock_irqrestore(&info->lock,flags); | |
3063 | ||
3064 | result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
3065 | ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
3066 | ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
3067 | ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
3068 | ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
3069 | ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
3070 | ||
3071 | DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); | |
3072 | return result; | |
3073 | } | |
3074 | ||
3075 | /* | |
3076 | * set modem control signals (DTR/RTS) | |
3077 | * | |
3078 | * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit | |
3079 | * TIOCMSET = set/clear signal values | |
3080 | * value bit mask for command | |
3081 | */ | |
3082 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
3083 | unsigned int set, unsigned int clear) | |
3084 | { | |
3085 | struct slgt_info *info = tty->driver_data; | |
3086 | unsigned long flags; | |
3087 | ||
3088 | DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); | |
3089 | ||
3090 | if (set & TIOCM_RTS) | |
3091 | info->signals |= SerialSignal_RTS; | |
3092 | if (set & TIOCM_DTR) | |
3093 | info->signals |= SerialSignal_DTR; | |
3094 | if (clear & TIOCM_RTS) | |
3095 | info->signals &= ~SerialSignal_RTS; | |
3096 | if (clear & TIOCM_DTR) | |
3097 | info->signals &= ~SerialSignal_DTR; | |
3098 | ||
3099 | spin_lock_irqsave(&info->lock,flags); | |
3100 | set_signals(info); | |
3101 | spin_unlock_irqrestore(&info->lock,flags); | |
3102 | return 0; | |
3103 | } | |
3104 | ||
3105 | /* | |
3106 | * block current process until the device is ready to open | |
3107 | */ | |
3108 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
3109 | struct slgt_info *info) | |
3110 | { | |
3111 | DECLARE_WAITQUEUE(wait, current); | |
3112 | int retval; | |
3113 | int do_clocal = 0, extra_count = 0; | |
3114 | unsigned long flags; | |
3115 | ||
3116 | DBGINFO(("%s block_til_ready\n", tty->driver->name)); | |
3117 | ||
3118 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
3119 | /* nonblock mode is set or port is not enabled */ | |
3120 | info->flags |= ASYNC_NORMAL_ACTIVE; | |
3121 | return 0; | |
3122 | } | |
3123 | ||
3124 | if (tty->termios->c_cflag & CLOCAL) | |
3125 | do_clocal = 1; | |
3126 | ||
3127 | /* Wait for carrier detect and the line to become | |
3128 | * free (i.e., not in use by the callout). While we are in | |
3129 | * this loop, info->count is dropped by one, so that | |
3130 | * close() knows when to free things. We restore it upon | |
3131 | * exit, either normal or abnormal. | |
3132 | */ | |
3133 | ||
3134 | retval = 0; | |
3135 | add_wait_queue(&info->open_wait, &wait); | |
3136 | ||
3137 | spin_lock_irqsave(&info->lock, flags); | |
3138 | if (!tty_hung_up_p(filp)) { | |
3139 | extra_count = 1; | |
3140 | info->count--; | |
3141 | } | |
3142 | spin_unlock_irqrestore(&info->lock, flags); | |
3143 | info->blocked_open++; | |
3144 | ||
3145 | while (1) { | |
3146 | if ((tty->termios->c_cflag & CBAUD)) { | |
3147 | spin_lock_irqsave(&info->lock,flags); | |
3148 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
3149 | set_signals(info); | |
3150 | spin_unlock_irqrestore(&info->lock,flags); | |
3151 | } | |
3152 | ||
3153 | set_current_state(TASK_INTERRUPTIBLE); | |
3154 | ||
3155 | if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){ | |
3156 | retval = (info->flags & ASYNC_HUP_NOTIFY) ? | |
3157 | -EAGAIN : -ERESTARTSYS; | |
3158 | break; | |
3159 | } | |
3160 | ||
3161 | spin_lock_irqsave(&info->lock,flags); | |
3162 | get_signals(info); | |
3163 | spin_unlock_irqrestore(&info->lock,flags); | |
3164 | ||
3165 | if (!(info->flags & ASYNC_CLOSING) && | |
3166 | (do_clocal || (info->signals & SerialSignal_DCD)) ) { | |
3167 | break; | |
3168 | } | |
3169 | ||
3170 | if (signal_pending(current)) { | |
3171 | retval = -ERESTARTSYS; | |
3172 | break; | |
3173 | } | |
3174 | ||
3175 | DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); | |
3176 | schedule(); | |
3177 | } | |
3178 | ||
3179 | set_current_state(TASK_RUNNING); | |
3180 | remove_wait_queue(&info->open_wait, &wait); | |
3181 | ||
3182 | if (extra_count) | |
3183 | info->count++; | |
3184 | info->blocked_open--; | |
3185 | ||
3186 | if (!retval) | |
3187 | info->flags |= ASYNC_NORMAL_ACTIVE; | |
3188 | ||
3189 | DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); | |
3190 | return retval; | |
3191 | } | |
3192 | ||
3193 | static int alloc_tmp_rbuf(struct slgt_info *info) | |
3194 | { | |
04b374d0 | 3195 | info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); |
705b6c7b PF |
3196 | if (info->tmp_rbuf == NULL) |
3197 | return -ENOMEM; | |
3198 | return 0; | |
3199 | } | |
3200 | ||
3201 | static void free_tmp_rbuf(struct slgt_info *info) | |
3202 | { | |
3203 | kfree(info->tmp_rbuf); | |
3204 | info->tmp_rbuf = NULL; | |
3205 | } | |
3206 | ||
3207 | /* | |
3208 | * allocate DMA descriptor lists. | |
3209 | */ | |
3210 | static int alloc_desc(struct slgt_info *info) | |
3211 | { | |
3212 | unsigned int i; | |
3213 | unsigned int pbufs; | |
3214 | ||
3215 | /* allocate memory to hold descriptor lists */ | |
3216 | info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr); | |
3217 | if (info->bufs == NULL) | |
3218 | return -ENOMEM; | |
3219 | ||
3220 | memset(info->bufs, 0, DESC_LIST_SIZE); | |
3221 | ||
3222 | info->rbufs = (struct slgt_desc*)info->bufs; | |
3223 | info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; | |
3224 | ||
3225 | pbufs = (unsigned int)info->bufs_dma_addr; | |
3226 | ||
3227 | /* | |
3228 | * Build circular lists of descriptors | |
3229 | */ | |
3230 | ||
3231 | for (i=0; i < info->rbuf_count; i++) { | |
3232 | /* physical address of this descriptor */ | |
3233 | info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); | |
3234 | ||
3235 | /* physical address of next descriptor */ | |
3236 | if (i == info->rbuf_count - 1) | |
3237 | info->rbufs[i].next = cpu_to_le32(pbufs); | |
3238 | else | |
3239 | info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); | |
3240 | set_desc_count(info->rbufs[i], DMABUFSIZE); | |
3241 | } | |
3242 | ||
3243 | for (i=0; i < info->tbuf_count; i++) { | |
3244 | /* physical address of this descriptor */ | |
3245 | info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); | |
3246 | ||
3247 | /* physical address of next descriptor */ | |
3248 | if (i == info->tbuf_count - 1) | |
3249 | info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); | |
3250 | else | |
3251 | info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); | |
3252 | } | |
3253 | ||
3254 | return 0; | |
3255 | } | |
3256 | ||
3257 | static void free_desc(struct slgt_info *info) | |
3258 | { | |
3259 | if (info->bufs != NULL) { | |
3260 | pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr); | |
3261 | info->bufs = NULL; | |
3262 | info->rbufs = NULL; | |
3263 | info->tbufs = NULL; | |
3264 | } | |
3265 | } | |
3266 | ||
3267 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3268 | { | |
3269 | int i; | |
3270 | for (i=0; i < count; i++) { | |
3271 | if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL) | |
3272 | return -ENOMEM; | |
3273 | bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); | |
3274 | } | |
3275 | return 0; | |
3276 | } | |
3277 | ||
3278 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3279 | { | |
3280 | int i; | |
3281 | for (i=0; i < count; i++) { | |
3282 | if (bufs[i].buf == NULL) | |
3283 | continue; | |
3284 | pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr); | |
3285 | bufs[i].buf = NULL; | |
3286 | } | |
3287 | } | |
3288 | ||
3289 | static int alloc_dma_bufs(struct slgt_info *info) | |
3290 | { | |
3291 | info->rbuf_count = 32; | |
3292 | info->tbuf_count = 32; | |
3293 | ||
3294 | if (alloc_desc(info) < 0 || | |
3295 | alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || | |
3296 | alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || | |
3297 | alloc_tmp_rbuf(info) < 0) { | |
3298 | DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); | |
3299 | return -ENOMEM; | |
3300 | } | |
3301 | reset_rbufs(info); | |
3302 | return 0; | |
3303 | } | |
3304 | ||
3305 | static void free_dma_bufs(struct slgt_info *info) | |
3306 | { | |
3307 | if (info->bufs) { | |
3308 | free_bufs(info, info->rbufs, info->rbuf_count); | |
3309 | free_bufs(info, info->tbufs, info->tbuf_count); | |
3310 | free_desc(info); | |
3311 | } | |
3312 | free_tmp_rbuf(info); | |
3313 | } | |
3314 | ||
3315 | static int claim_resources(struct slgt_info *info) | |
3316 | { | |
3317 | if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { | |
3318 | DBGERR(("%s reg addr conflict, addr=%08X\n", | |
3319 | info->device_name, info->phys_reg_addr)); | |
3320 | info->init_error = DiagStatus_AddressConflict; | |
3321 | goto errout; | |
3322 | } | |
3323 | else | |
3324 | info->reg_addr_requested = 1; | |
3325 | ||
0c8365ec | 3326 | info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE); |
705b6c7b PF |
3327 | if (!info->reg_addr) { |
3328 | DBGERR(("%s cant map device registers, addr=%08X\n", | |
3329 | info->device_name, info->phys_reg_addr)); | |
3330 | info->init_error = DiagStatus_CantAssignPciResources; | |
3331 | goto errout; | |
3332 | } | |
705b6c7b PF |
3333 | return 0; |
3334 | ||
3335 | errout: | |
3336 | release_resources(info); | |
3337 | return -ENODEV; | |
3338 | } | |
3339 | ||
3340 | static void release_resources(struct slgt_info *info) | |
3341 | { | |
3342 | if (info->irq_requested) { | |
3343 | free_irq(info->irq_level, info); | |
3344 | info->irq_requested = 0; | |
3345 | } | |
3346 | ||
3347 | if (info->reg_addr_requested) { | |
3348 | release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); | |
3349 | info->reg_addr_requested = 0; | |
3350 | } | |
3351 | ||
3352 | if (info->reg_addr) { | |
0c8365ec | 3353 | iounmap(info->reg_addr); |
705b6c7b PF |
3354 | info->reg_addr = NULL; |
3355 | } | |
3356 | } | |
3357 | ||
3358 | /* Add the specified device instance data structure to the | |
3359 | * global linked list of devices and increment the device count. | |
3360 | */ | |
3361 | static void add_device(struct slgt_info *info) | |
3362 | { | |
3363 | char *devstr; | |
3364 | ||
3365 | info->next_device = NULL; | |
3366 | info->line = slgt_device_count; | |
3367 | sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); | |
3368 | ||
3369 | if (info->line < MAX_DEVICES) { | |
3370 | if (maxframe[info->line]) | |
3371 | info->max_frame_size = maxframe[info->line]; | |
3372 | info->dosyncppp = dosyncppp[info->line]; | |
3373 | } | |
3374 | ||
3375 | slgt_device_count++; | |
3376 | ||
3377 | if (!slgt_device_list) | |
3378 | slgt_device_list = info; | |
3379 | else { | |
3380 | struct slgt_info *current_dev = slgt_device_list; | |
3381 | while(current_dev->next_device) | |
3382 | current_dev = current_dev->next_device; | |
3383 | current_dev->next_device = info; | |
3384 | } | |
3385 | ||
3386 | if (info->max_frame_size < 4096) | |
3387 | info->max_frame_size = 4096; | |
3388 | else if (info->max_frame_size > 65535) | |
3389 | info->max_frame_size = 65535; | |
3390 | ||
3391 | switch(info->pdev->device) { | |
3392 | case SYNCLINK_GT_DEVICE_ID: | |
3393 | devstr = "GT"; | |
3394 | break; | |
6f84be84 PF |
3395 | case SYNCLINK_GT2_DEVICE_ID: |
3396 | devstr = "GT2"; | |
3397 | break; | |
705b6c7b PF |
3398 | case SYNCLINK_GT4_DEVICE_ID: |
3399 | devstr = "GT4"; | |
3400 | break; | |
3401 | case SYNCLINK_AC_DEVICE_ID: | |
3402 | devstr = "AC"; | |
3403 | info->params.mode = MGSL_MODE_ASYNC; | |
3404 | break; | |
3405 | default: | |
3406 | devstr = "(unknown model)"; | |
3407 | } | |
3408 | printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", | |
3409 | devstr, info->device_name, info->phys_reg_addr, | |
3410 | info->irq_level, info->max_frame_size); | |
3411 | ||
af69c7f9 | 3412 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3413 | hdlcdev_init(info); |
3414 | #endif | |
3415 | } | |
3416 | ||
3417 | /* | |
3418 | * allocate device instance structure, return NULL on failure | |
3419 | */ | |
3420 | static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) | |
3421 | { | |
3422 | struct slgt_info *info; | |
3423 | ||
dd00cc48 | 3424 | info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); |
705b6c7b PF |
3425 | |
3426 | if (!info) { | |
3427 | DBGERR(("%s device alloc failed adapter=%d port=%d\n", | |
3428 | driver_name, adapter_num, port_num)); | |
3429 | } else { | |
705b6c7b | 3430 | info->magic = MGSL_MAGIC; |
c4028958 | 3431 | INIT_WORK(&info->task, bh_handler); |
705b6c7b PF |
3432 | info->max_frame_size = 4096; |
3433 | info->raw_rx_size = DMABUFSIZE; | |
3434 | info->close_delay = 5*HZ/10; | |
3435 | info->closing_wait = 30*HZ; | |
3436 | init_waitqueue_head(&info->open_wait); | |
3437 | init_waitqueue_head(&info->close_wait); | |
3438 | init_waitqueue_head(&info->status_event_wait_q); | |
3439 | init_waitqueue_head(&info->event_wait_q); | |
3440 | spin_lock_init(&info->netlock); | |
3441 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
3442 | info->idle_mode = HDLC_TXIDLE_FLAGS; | |
3443 | info->adapter_num = adapter_num; | |
3444 | info->port_num = port_num; | |
3445 | ||
40565f19 JS |
3446 | setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); |
3447 | setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info); | |
705b6c7b PF |
3448 | |
3449 | /* Copy configuration info to device instance data */ | |
3450 | info->pdev = pdev; | |
3451 | info->irq_level = pdev->irq; | |
3452 | info->phys_reg_addr = pci_resource_start(pdev,0); | |
3453 | ||
705b6c7b | 3454 | info->bus_type = MGSL_BUS_TYPE_PCI; |
0f2ed4c6 | 3455 | info->irq_flags = IRQF_SHARED; |
705b6c7b PF |
3456 | |
3457 | info->init_error = -1; /* assume error, set to 0 on successful init */ | |
3458 | } | |
3459 | ||
3460 | return info; | |
3461 | } | |
3462 | ||
3463 | static void device_init(int adapter_num, struct pci_dev *pdev) | |
3464 | { | |
3465 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
3466 | int i; | |
3467 | int port_count = 1; | |
3468 | ||
6f84be84 PF |
3469 | if (pdev->device == SYNCLINK_GT2_DEVICE_ID) |
3470 | port_count = 2; | |
3471 | else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) | |
705b6c7b PF |
3472 | port_count = 4; |
3473 | ||
3474 | /* allocate device instances for all ports */ | |
3475 | for (i=0; i < port_count; ++i) { | |
3476 | port_array[i] = alloc_dev(adapter_num, i, pdev); | |
3477 | if (port_array[i] == NULL) { | |
3478 | for (--i; i >= 0; --i) | |
3479 | kfree(port_array[i]); | |
3480 | return; | |
3481 | } | |
3482 | } | |
3483 | ||
3484 | /* give copy of port_array to all ports and add to device list */ | |
3485 | for (i=0; i < port_count; ++i) { | |
3486 | memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); | |
3487 | add_device(port_array[i]); | |
3488 | port_array[i]->port_count = port_count; | |
3489 | spin_lock_init(&port_array[i]->lock); | |
3490 | } | |
3491 | ||
3492 | /* Allocate and claim adapter resources */ | |
3493 | if (!claim_resources(port_array[0])) { | |
3494 | ||
3495 | alloc_dma_bufs(port_array[0]); | |
3496 | ||
3497 | /* copy resource information from first port to others */ | |
3498 | for (i = 1; i < port_count; ++i) { | |
3499 | port_array[i]->lock = port_array[0]->lock; | |
3500 | port_array[i]->irq_level = port_array[0]->irq_level; | |
3501 | port_array[i]->reg_addr = port_array[0]->reg_addr; | |
3502 | alloc_dma_bufs(port_array[i]); | |
3503 | } | |
3504 | ||
3505 | if (request_irq(port_array[0]->irq_level, | |
3506 | slgt_interrupt, | |
3507 | port_array[0]->irq_flags, | |
3508 | port_array[0]->device_name, | |
3509 | port_array[0]) < 0) { | |
3510 | DBGERR(("%s request_irq failed IRQ=%d\n", | |
3511 | port_array[0]->device_name, | |
3512 | port_array[0]->irq_level)); | |
3513 | } else { | |
3514 | port_array[0]->irq_requested = 1; | |
3515 | adapter_test(port_array[0]); | |
0080b7aa | 3516 | for (i=1 ; i < port_count ; i++) { |
705b6c7b | 3517 | port_array[i]->init_error = port_array[0]->init_error; |
0080b7aa PF |
3518 | port_array[i]->gpio_present = port_array[0]->gpio_present; |
3519 | } | |
705b6c7b PF |
3520 | } |
3521 | } | |
62eb5b1f PF |
3522 | |
3523 | for (i=0; i < port_count; ++i) | |
3524 | tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev)); | |
705b6c7b PF |
3525 | } |
3526 | ||
3527 | static int __devinit init_one(struct pci_dev *dev, | |
3528 | const struct pci_device_id *ent) | |
3529 | { | |
3530 | if (pci_enable_device(dev)) { | |
3531 | printk("error enabling pci device %p\n", dev); | |
3532 | return -EIO; | |
3533 | } | |
3534 | pci_set_master(dev); | |
3535 | device_init(slgt_device_count, dev); | |
3536 | return 0; | |
3537 | } | |
3538 | ||
3539 | static void __devexit remove_one(struct pci_dev *dev) | |
3540 | { | |
3541 | } | |
3542 | ||
b68e31d0 | 3543 | static const struct tty_operations ops = { |
705b6c7b PF |
3544 | .open = open, |
3545 | .close = close, | |
3546 | .write = write, | |
3547 | .put_char = put_char, | |
3548 | .flush_chars = flush_chars, | |
3549 | .write_room = write_room, | |
3550 | .chars_in_buffer = chars_in_buffer, | |
3551 | .flush_buffer = flush_buffer, | |
3552 | .ioctl = ioctl, | |
2acdb169 | 3553 | .compat_ioctl = slgt_compat_ioctl, |
705b6c7b PF |
3554 | .throttle = throttle, |
3555 | .unthrottle = unthrottle, | |
3556 | .send_xchar = send_xchar, | |
3557 | .break_ctl = set_break, | |
3558 | .wait_until_sent = wait_until_sent, | |
3559 | .read_proc = read_proc, | |
3560 | .set_termios = set_termios, | |
3561 | .stop = tx_hold, | |
3562 | .start = tx_release, | |
3563 | .hangup = hangup, | |
3564 | .tiocmget = tiocmget, | |
3565 | .tiocmset = tiocmset, | |
3566 | }; | |
3567 | ||
3568 | static void slgt_cleanup(void) | |
3569 | { | |
3570 | int rc; | |
3571 | struct slgt_info *info; | |
3572 | struct slgt_info *tmp; | |
3573 | ||
3574 | printk("unload %s %s\n", driver_name, driver_version); | |
3575 | ||
3576 | if (serial_driver) { | |
62eb5b1f PF |
3577 | for (info=slgt_device_list ; info != NULL ; info=info->next_device) |
3578 | tty_unregister_device(serial_driver, info->line); | |
705b6c7b PF |
3579 | if ((rc = tty_unregister_driver(serial_driver))) |
3580 | DBGERR(("tty_unregister_driver error=%d\n", rc)); | |
3581 | put_tty_driver(serial_driver); | |
3582 | } | |
3583 | ||
3584 | /* reset devices */ | |
3585 | info = slgt_device_list; | |
3586 | while(info) { | |
3587 | reset_port(info); | |
3588 | info = info->next_device; | |
3589 | } | |
3590 | ||
3591 | /* release devices */ | |
3592 | info = slgt_device_list; | |
3593 | while(info) { | |
af69c7f9 | 3594 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3595 | hdlcdev_exit(info); |
3596 | #endif | |
3597 | free_dma_bufs(info); | |
3598 | free_tmp_rbuf(info); | |
3599 | if (info->port_num == 0) | |
3600 | release_resources(info); | |
3601 | tmp = info; | |
3602 | info = info->next_device; | |
3603 | kfree(tmp); | |
3604 | } | |
3605 | ||
3606 | if (pci_registered) | |
3607 | pci_unregister_driver(&pci_driver); | |
3608 | } | |
3609 | ||
3610 | /* | |
3611 | * Driver initialization entry point. | |
3612 | */ | |
3613 | static int __init slgt_init(void) | |
3614 | { | |
3615 | int rc; | |
3616 | ||
3617 | printk("%s %s\n", driver_name, driver_version); | |
3618 | ||
705b6c7b PF |
3619 | serial_driver = alloc_tty_driver(MAX_DEVICES); |
3620 | if (!serial_driver) { | |
62eb5b1f PF |
3621 | printk("%s can't allocate tty driver\n", driver_name); |
3622 | return -ENOMEM; | |
705b6c7b PF |
3623 | } |
3624 | ||
3625 | /* Initialize the tty_driver structure */ | |
3626 | ||
3627 | serial_driver->owner = THIS_MODULE; | |
3628 | serial_driver->driver_name = tty_driver_name; | |
3629 | serial_driver->name = tty_dev_prefix; | |
3630 | serial_driver->major = ttymajor; | |
3631 | serial_driver->minor_start = 64; | |
3632 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
3633 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
3634 | serial_driver->init_termios = tty_std_termios; | |
3635 | serial_driver->init_termios.c_cflag = | |
3636 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
606d099c AC |
3637 | serial_driver->init_termios.c_ispeed = 9600; |
3638 | serial_driver->init_termios.c_ospeed = 9600; | |
62eb5b1f | 3639 | serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; |
705b6c7b PF |
3640 | tty_set_operations(serial_driver, &ops); |
3641 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
3642 | DBGERR(("%s can't register serial driver\n", driver_name)); | |
3643 | put_tty_driver(serial_driver); | |
3644 | serial_driver = NULL; | |
3645 | goto error; | |
3646 | } | |
3647 | ||
3648 | printk("%s %s, tty major#%d\n", | |
3649 | driver_name, driver_version, | |
3650 | serial_driver->major); | |
3651 | ||
62eb5b1f PF |
3652 | slgt_device_count = 0; |
3653 | if ((rc = pci_register_driver(&pci_driver)) < 0) { | |
3654 | printk("%s pci_register_driver error=%d\n", driver_name, rc); | |
3655 | goto error; | |
3656 | } | |
3657 | pci_registered = 1; | |
3658 | ||
3659 | if (!slgt_device_list) | |
3660 | printk("%s no devices found\n",driver_name); | |
3661 | ||
705b6c7b PF |
3662 | return 0; |
3663 | ||
3664 | error: | |
3665 | slgt_cleanup(); | |
3666 | return rc; | |
3667 | } | |
3668 | ||
3669 | static void __exit slgt_exit(void) | |
3670 | { | |
3671 | slgt_cleanup(); | |
3672 | } | |
3673 | ||
3674 | module_init(slgt_init); | |
3675 | module_exit(slgt_exit); | |
3676 | ||
3677 | /* | |
3678 | * register access routines | |
3679 | */ | |
3680 | ||
3681 | #define CALC_REGADDR() \ | |
3682 | unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ | |
3683 | if (addr >= 0x80) \ | |
3684 | reg_addr += (info->port_num) * 32; | |
3685 | ||
3686 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) | |
3687 | { | |
3688 | CALC_REGADDR(); | |
3689 | return readb((void __iomem *)reg_addr); | |
3690 | } | |
3691 | ||
3692 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) | |
3693 | { | |
3694 | CALC_REGADDR(); | |
3695 | writeb(value, (void __iomem *)reg_addr); | |
3696 | } | |
3697 | ||
3698 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) | |
3699 | { | |
3700 | CALC_REGADDR(); | |
3701 | return readw((void __iomem *)reg_addr); | |
3702 | } | |
3703 | ||
3704 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) | |
3705 | { | |
3706 | CALC_REGADDR(); | |
3707 | writew(value, (void __iomem *)reg_addr); | |
3708 | } | |
3709 | ||
3710 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) | |
3711 | { | |
3712 | CALC_REGADDR(); | |
3713 | return readl((void __iomem *)reg_addr); | |
3714 | } | |
3715 | ||
3716 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) | |
3717 | { | |
3718 | CALC_REGADDR(); | |
3719 | writel(value, (void __iomem *)reg_addr); | |
3720 | } | |
3721 | ||
3722 | static void rdma_reset(struct slgt_info *info) | |
3723 | { | |
3724 | unsigned int i; | |
3725 | ||
3726 | /* set reset bit */ | |
3727 | wr_reg32(info, RDCSR, BIT1); | |
3728 | ||
3729 | /* wait for enable bit cleared */ | |
3730 | for(i=0 ; i < 1000 ; i++) | |
3731 | if (!(rd_reg32(info, RDCSR) & BIT0)) | |
3732 | break; | |
3733 | } | |
3734 | ||
3735 | static void tdma_reset(struct slgt_info *info) | |
3736 | { | |
3737 | unsigned int i; | |
3738 | ||
3739 | /* set reset bit */ | |
3740 | wr_reg32(info, TDCSR, BIT1); | |
3741 | ||
3742 | /* wait for enable bit cleared */ | |
3743 | for(i=0 ; i < 1000 ; i++) | |
3744 | if (!(rd_reg32(info, TDCSR) & BIT0)) | |
3745 | break; | |
3746 | } | |
3747 | ||
3748 | /* | |
3749 | * enable internal loopback | |
3750 | * TxCLK and RxCLK are generated from BRG | |
3751 | * and TxD is looped back to RxD internally. | |
3752 | */ | |
3753 | static void enable_loopback(struct slgt_info *info) | |
3754 | { | |
3755 | /* SCR (serial control) BIT2=looopback enable */ | |
3756 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); | |
3757 | ||
3758 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3759 | /* CCR (clock control) | |
3760 | * 07..05 tx clock source (010 = BRG) | |
3761 | * 04..02 rx clock source (010 = BRG) | |
3762 | * 01 auxclk enable (0 = disable) | |
3763 | * 00 BRG enable (1 = enable) | |
3764 | * | |
3765 | * 0100 1001 | |
3766 | */ | |
3767 | wr_reg8(info, CCR, 0x49); | |
3768 | ||
3769 | /* set speed if available, otherwise use default */ | |
3770 | if (info->params.clock_speed) | |
3771 | set_rate(info, info->params.clock_speed); | |
3772 | else | |
3773 | set_rate(info, 3686400); | |
3774 | } | |
3775 | } | |
3776 | ||
3777 | /* | |
3778 | * set baud rate generator to specified rate | |
3779 | */ | |
3780 | static void set_rate(struct slgt_info *info, u32 rate) | |
3781 | { | |
3782 | unsigned int div; | |
3783 | static unsigned int osc = 14745600; | |
3784 | ||
3785 | /* div = osc/rate - 1 | |
3786 | * | |
3787 | * Round div up if osc/rate is not integer to | |
3788 | * force to next slowest rate. | |
3789 | */ | |
3790 | ||
3791 | if (rate) { | |
3792 | div = osc/rate; | |
3793 | if (!(osc % rate) && div) | |
3794 | div--; | |
3795 | wr_reg16(info, BDR, (unsigned short)div); | |
3796 | } | |
3797 | } | |
3798 | ||
3799 | static void rx_stop(struct slgt_info *info) | |
3800 | { | |
3801 | unsigned short val; | |
3802 | ||
3803 | /* disable and reset receiver */ | |
3804 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3805 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3806 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3807 | ||
3808 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); | |
3809 | ||
3810 | /* clear pending rx interrupts */ | |
3811 | wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); | |
3812 | ||
3813 | rdma_reset(info); | |
3814 | ||
3815 | info->rx_enabled = 0; | |
3816 | info->rx_restart = 0; | |
3817 | } | |
3818 | ||
3819 | static void rx_start(struct slgt_info *info) | |
3820 | { | |
3821 | unsigned short val; | |
3822 | ||
3823 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); | |
3824 | ||
3825 | /* clear pending rx overrun IRQ */ | |
3826 | wr_reg16(info, SSR, IRQ_RXOVER); | |
3827 | ||
3828 | /* reset and disable receiver */ | |
3829 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3830 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3831 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3832 | ||
3833 | rdma_reset(info); | |
3834 | reset_rbufs(info); | |
3835 | ||
3836 | /* set 1st descriptor address */ | |
3837 | wr_reg32(info, RDDAR, info->rbufs[0].pdesc); | |
3838 | ||
3839 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3840 | /* enable rx DMA and DMA interrupt */ | |
3841 | wr_reg32(info, RDCSR, (BIT2 + BIT0)); | |
3842 | } else { | |
3843 | /* enable saving of rx status, rx DMA and DMA interrupt */ | |
3844 | wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); | |
3845 | } | |
3846 | ||
3847 | slgt_irq_on(info, IRQ_RXOVER); | |
3848 | ||
3849 | /* enable receiver */ | |
3850 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); | |
3851 | ||
3852 | info->rx_restart = 0; | |
3853 | info->rx_enabled = 1; | |
3854 | } | |
3855 | ||
3856 | static void tx_start(struct slgt_info *info) | |
3857 | { | |
3858 | if (!info->tx_enabled) { | |
3859 | wr_reg16(info, TCR, | |
cb10dc9a | 3860 | (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); |
705b6c7b PF |
3861 | info->tx_enabled = TRUE; |
3862 | } | |
3863 | ||
3864 | if (info->tx_count) { | |
3865 | info->drop_rts_on_tx_done = 0; | |
3866 | ||
3867 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3868 | if (info->params.flags & HDLC_FLAG_AUTO_RTS) { | |
3869 | get_signals(info); | |
3870 | if (!(info->signals & SerialSignal_RTS)) { | |
3871 | info->signals |= SerialSignal_RTS; | |
3872 | set_signals(info); | |
3873 | info->drop_rts_on_tx_done = 1; | |
3874 | } | |
3875 | } | |
3876 | ||
3877 | slgt_irq_off(info, IRQ_TXDATA); | |
3878 | slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); | |
3879 | /* clear tx idle and underrun status bits */ | |
3880 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
40565f19 JS |
3881 | if (info->params.mode == MGSL_MODE_HDLC) |
3882 | mod_timer(&info->tx_timer, jiffies + | |
3883 | msecs_to_jiffies(5000)); | |
705b6c7b | 3884 | } else { |
705b6c7b PF |
3885 | slgt_irq_off(info, IRQ_TXDATA); |
3886 | slgt_irq_on(info, IRQ_TXIDLE); | |
3887 | /* clear tx idle status bit */ | |
3888 | wr_reg16(info, SSR, IRQ_TXIDLE); | |
705b6c7b | 3889 | } |
bb029c67 | 3890 | tdma_start(info); |
705b6c7b PF |
3891 | info->tx_active = 1; |
3892 | } | |
3893 | } | |
3894 | ||
bb029c67 PF |
3895 | /* |
3896 | * start transmit DMA if inactive and there are unsent buffers | |
3897 | */ | |
3898 | static void tdma_start(struct slgt_info *info) | |
3899 | { | |
3900 | unsigned int i; | |
3901 | ||
3902 | if (rd_reg32(info, TDCSR) & BIT0) | |
3903 | return; | |
3904 | ||
3905 | /* transmit DMA inactive, check for unsent buffers */ | |
3906 | i = info->tbuf_start; | |
3907 | while (!desc_count(info->tbufs[i])) { | |
3908 | if (++i == info->tbuf_count) | |
3909 | i = 0; | |
3910 | if (i == info->tbuf_current) | |
3911 | return; | |
3912 | } | |
3913 | info->tbuf_start = i; | |
3914 | ||
3915 | /* there are unsent buffers, start transmit DMA */ | |
3916 | ||
3917 | /* reset needed if previous error condition */ | |
3918 | tdma_reset(info); | |
3919 | ||
3920 | /* set 1st descriptor address */ | |
3921 | wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); | |
3922 | switch(info->params.mode) { | |
3923 | case MGSL_MODE_RAW: | |
3924 | case MGSL_MODE_MONOSYNC: | |
3925 | case MGSL_MODE_BISYNC: | |
3926 | wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */ | |
3927 | break; | |
3928 | default: | |
3929 | wr_reg32(info, TDCSR, BIT0); /* DMA enable */ | |
3930 | } | |
3931 | } | |
3932 | ||
705b6c7b PF |
3933 | static void tx_stop(struct slgt_info *info) |
3934 | { | |
3935 | unsigned short val; | |
3936 | ||
3937 | del_timer(&info->tx_timer); | |
3938 | ||
3939 | tdma_reset(info); | |
3940 | ||
3941 | /* reset and disable transmitter */ | |
3942 | val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ | |
3943 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
705b6c7b PF |
3944 | |
3945 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
3946 | ||
3947 | /* clear tx idle and underrun status bit */ | |
3948 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
3949 | ||
3950 | reset_tbufs(info); | |
3951 | ||
3952 | info->tx_enabled = 0; | |
3953 | info->tx_active = 0; | |
3954 | } | |
3955 | ||
3956 | static void reset_port(struct slgt_info *info) | |
3957 | { | |
3958 | if (!info->reg_addr) | |
3959 | return; | |
3960 | ||
3961 | tx_stop(info); | |
3962 | rx_stop(info); | |
3963 | ||
3964 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
3965 | set_signals(info); | |
3966 | ||
3967 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
3968 | } | |
3969 | ||
3970 | static void reset_adapter(struct slgt_info *info) | |
3971 | { | |
3972 | int i; | |
3973 | for (i=0; i < info->port_count; ++i) { | |
3974 | if (info->port_array[i]) | |
3975 | reset_port(info->port_array[i]); | |
3976 | } | |
3977 | } | |
3978 | ||
3979 | static void async_mode(struct slgt_info *info) | |
3980 | { | |
3981 | unsigned short val; | |
3982 | ||
3983 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
3984 | tx_stop(info); | |
3985 | rx_stop(info); | |
3986 | ||
3987 | /* TCR (tx control) | |
3988 | * | |
3989 | * 15..13 mode, 010=async | |
3990 | * 12..10 encoding, 000=NRZ | |
3991 | * 09 parity enable | |
3992 | * 08 1=odd parity, 0=even parity | |
3993 | * 07 1=RTS driver control | |
3994 | * 06 1=break enable | |
3995 | * 05..04 character length | |
3996 | * 00=5 bits | |
3997 | * 01=6 bits | |
3998 | * 10=7 bits | |
3999 | * 11=8 bits | |
4000 | * 03 0=1 stop bit, 1=2 stop bits | |
4001 | * 02 reset | |
4002 | * 01 enable | |
4003 | * 00 auto-CTS enable | |
4004 | */ | |
4005 | val = 0x4000; | |
4006 | ||
4007 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
4008 | val |= BIT7; | |
4009 | ||
4010 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4011 | val |= BIT9; | |
4012 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4013 | val |= BIT8; | |
4014 | } | |
4015 | ||
4016 | switch (info->params.data_bits) | |
4017 | { | |
4018 | case 6: val |= BIT4; break; | |
4019 | case 7: val |= BIT5; break; | |
4020 | case 8: val |= BIT5 + BIT4; break; | |
4021 | } | |
4022 | ||
4023 | if (info->params.stop_bits != 1) | |
4024 | val |= BIT3; | |
4025 | ||
4026 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4027 | val |= BIT0; | |
4028 | ||
4029 | wr_reg16(info, TCR, val); | |
4030 | ||
4031 | /* RCR (rx control) | |
4032 | * | |
4033 | * 15..13 mode, 010=async | |
4034 | * 12..10 encoding, 000=NRZ | |
4035 | * 09 parity enable | |
4036 | * 08 1=odd parity, 0=even parity | |
4037 | * 07..06 reserved, must be 0 | |
4038 | * 05..04 character length | |
4039 | * 00=5 bits | |
4040 | * 01=6 bits | |
4041 | * 10=7 bits | |
4042 | * 11=8 bits | |
4043 | * 03 reserved, must be zero | |
4044 | * 02 reset | |
4045 | * 01 enable | |
4046 | * 00 auto-DCD enable | |
4047 | */ | |
4048 | val = 0x4000; | |
4049 | ||
4050 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4051 | val |= BIT9; | |
4052 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4053 | val |= BIT8; | |
4054 | } | |
4055 | ||
4056 | switch (info->params.data_bits) | |
4057 | { | |
4058 | case 6: val |= BIT4; break; | |
4059 | case 7: val |= BIT5; break; | |
4060 | case 8: val |= BIT5 + BIT4; break; | |
4061 | } | |
4062 | ||
4063 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4064 | val |= BIT0; | |
4065 | ||
4066 | wr_reg16(info, RCR, val); | |
4067 | ||
4068 | /* CCR (clock control) | |
4069 | * | |
4070 | * 07..05 011 = tx clock source is BRG/16 | |
4071 | * 04..02 010 = rx clock source is BRG | |
4072 | * 01 0 = auxclk disabled | |
4073 | * 00 1 = BRG enabled | |
4074 | * | |
4075 | * 0110 1001 | |
4076 | */ | |
4077 | wr_reg8(info, CCR, 0x69); | |
4078 | ||
4079 | msc_set_vcr(info); | |
4080 | ||
705b6c7b PF |
4081 | /* SCR (serial control) |
4082 | * | |
4083 | * 15 1=tx req on FIFO half empty | |
4084 | * 14 1=rx req on FIFO half full | |
4085 | * 13 tx data IRQ enable | |
4086 | * 12 tx idle IRQ enable | |
4087 | * 11 rx break on IRQ enable | |
4088 | * 10 rx data IRQ enable | |
4089 | * 09 rx break off IRQ enable | |
4090 | * 08 overrun IRQ enable | |
4091 | * 07 DSR IRQ enable | |
4092 | * 06 CTS IRQ enable | |
4093 | * 05 DCD IRQ enable | |
4094 | * 04 RI IRQ enable | |
4095 | * 03 reserved, must be zero | |
4096 | * 02 1=txd->rxd internal loopback enable | |
4097 | * 01 reserved, must be zero | |
4098 | * 00 1=master IRQ enable | |
4099 | */ | |
4100 | val = BIT15 + BIT14 + BIT0; | |
4101 | wr_reg16(info, SCR, val); | |
4102 | ||
4103 | slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); | |
4104 | ||
4105 | set_rate(info, info->params.data_rate * 16); | |
4106 | ||
4107 | if (info->params.loopback) | |
4108 | enable_loopback(info); | |
4109 | } | |
4110 | ||
cb10dc9a | 4111 | static void sync_mode(struct slgt_info *info) |
705b6c7b PF |
4112 | { |
4113 | unsigned short val; | |
4114 | ||
4115 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4116 | tx_stop(info); | |
4117 | rx_stop(info); | |
4118 | ||
4119 | /* TCR (tx control) | |
4120 | * | |
cb10dc9a | 4121 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4122 | * 12..10 encoding |
4123 | * 09 CRC enable | |
4124 | * 08 CRC32 | |
4125 | * 07 1=RTS driver control | |
4126 | * 06 preamble enable | |
4127 | * 05..04 preamble length | |
4128 | * 03 share open/close flag | |
4129 | * 02 reset | |
4130 | * 01 enable | |
4131 | * 00 auto-CTS enable | |
4132 | */ | |
4133 | val = 0; | |
4134 | ||
cb10dc9a PF |
4135 | switch(info->params.mode) { |
4136 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4137 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4138 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4139 | } | |
705b6c7b PF |
4140 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) |
4141 | val |= BIT7; | |
4142 | ||
4143 | switch(info->params.encoding) | |
4144 | { | |
4145 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4146 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4147 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4148 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4149 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4150 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4151 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4152 | } | |
4153 | ||
04b374d0 | 4154 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4155 | { |
4156 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4157 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4158 | } | |
4159 | ||
4160 | if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) | |
4161 | val |= BIT6; | |
4162 | ||
4163 | switch (info->params.preamble_length) | |
4164 | { | |
4165 | case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; | |
4166 | case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; | |
4167 | case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; | |
4168 | } | |
4169 | ||
4170 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4171 | val |= BIT0; | |
4172 | ||
4173 | wr_reg16(info, TCR, val); | |
4174 | ||
4175 | /* TPR (transmit preamble) */ | |
4176 | ||
4177 | switch (info->params.preamble) | |
4178 | { | |
4179 | case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; | |
4180 | case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; | |
4181 | case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; | |
4182 | case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; | |
4183 | case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; | |
4184 | default: val = 0x7e; break; | |
4185 | } | |
4186 | wr_reg8(info, TPR, (unsigned char)val); | |
4187 | ||
4188 | /* RCR (rx control) | |
4189 | * | |
cb10dc9a | 4190 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4191 | * 12..10 encoding |
4192 | * 09 CRC enable | |
4193 | * 08 CRC32 | |
4194 | * 07..03 reserved, must be 0 | |
4195 | * 02 reset | |
4196 | * 01 enable | |
4197 | * 00 auto-DCD enable | |
4198 | */ | |
4199 | val = 0; | |
4200 | ||
cb10dc9a PF |
4201 | switch(info->params.mode) { |
4202 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4203 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4204 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4205 | } | |
705b6c7b PF |
4206 | |
4207 | switch(info->params.encoding) | |
4208 | { | |
4209 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4210 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4211 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4212 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4213 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4214 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4215 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4216 | } | |
4217 | ||
04b374d0 | 4218 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4219 | { |
4220 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4221 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4222 | } | |
4223 | ||
4224 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4225 | val |= BIT0; | |
4226 | ||
4227 | wr_reg16(info, RCR, val); | |
4228 | ||
4229 | /* CCR (clock control) | |
4230 | * | |
4231 | * 07..05 tx clock source | |
4232 | * 04..02 rx clock source | |
4233 | * 01 auxclk enable | |
4234 | * 00 BRG enable | |
4235 | */ | |
4236 | val = 0; | |
4237 | ||
4238 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4239 | { | |
4240 | // when RxC source is DPLL, BRG generates 16X DPLL | |
4241 | // reference clock, so take TxC from BRG/16 to get | |
4242 | // transmit clock at actual data rate | |
4243 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4244 | val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ | |
4245 | else | |
4246 | val |= BIT6; /* 010, txclk = BRG */ | |
4247 | } | |
4248 | else if (info->params.flags & HDLC_FLAG_TXC_DPLL) | |
4249 | val |= BIT7; /* 100, txclk = DPLL Input */ | |
4250 | else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) | |
4251 | val |= BIT5; /* 001, txclk = RXC Input */ | |
4252 | ||
4253 | if (info->params.flags & HDLC_FLAG_RXC_BRG) | |
4254 | val |= BIT3; /* 010, rxclk = BRG */ | |
4255 | else if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4256 | val |= BIT4; /* 100, rxclk = DPLL */ | |
4257 | else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) | |
4258 | val |= BIT2; /* 001, rxclk = TXC Input */ | |
4259 | ||
4260 | if (info->params.clock_speed) | |
4261 | val |= BIT1 + BIT0; | |
4262 | ||
4263 | wr_reg8(info, CCR, (unsigned char)val); | |
4264 | ||
4265 | if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) | |
4266 | { | |
4267 | // program DPLL mode | |
4268 | switch(info->params.encoding) | |
4269 | { | |
4270 | case HDLC_ENCODING_BIPHASE_MARK: | |
4271 | case HDLC_ENCODING_BIPHASE_SPACE: | |
4272 | val = BIT7; break; | |
4273 | case HDLC_ENCODING_BIPHASE_LEVEL: | |
4274 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: | |
4275 | val = BIT7 + BIT6; break; | |
4276 | default: val = BIT6; // NRZ encodings | |
4277 | } | |
4278 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); | |
4279 | ||
4280 | // DPLL requires a 16X reference clock from BRG | |
4281 | set_rate(info, info->params.clock_speed * 16); | |
4282 | } | |
4283 | else | |
4284 | set_rate(info, info->params.clock_speed); | |
4285 | ||
4286 | tx_set_idle(info); | |
4287 | ||
4288 | msc_set_vcr(info); | |
4289 | ||
4290 | /* SCR (serial control) | |
4291 | * | |
4292 | * 15 1=tx req on FIFO half empty | |
4293 | * 14 1=rx req on FIFO half full | |
4294 | * 13 tx data IRQ enable | |
4295 | * 12 tx idle IRQ enable | |
4296 | * 11 underrun IRQ enable | |
4297 | * 10 rx data IRQ enable | |
4298 | * 09 rx idle IRQ enable | |
4299 | * 08 overrun IRQ enable | |
4300 | * 07 DSR IRQ enable | |
4301 | * 06 CTS IRQ enable | |
4302 | * 05 DCD IRQ enable | |
4303 | * 04 RI IRQ enable | |
4304 | * 03 reserved, must be zero | |
4305 | * 02 1=txd->rxd internal loopback enable | |
4306 | * 01 reserved, must be zero | |
4307 | * 00 1=master IRQ enable | |
4308 | */ | |
4309 | wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); | |
4310 | ||
4311 | if (info->params.loopback) | |
4312 | enable_loopback(info); | |
4313 | } | |
4314 | ||
4315 | /* | |
4316 | * set transmit idle mode | |
4317 | */ | |
4318 | static void tx_set_idle(struct slgt_info *info) | |
4319 | { | |
643f3319 PF |
4320 | unsigned char val; |
4321 | unsigned short tcr; | |
705b6c7b | 4322 | |
643f3319 PF |
4323 | /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits |
4324 | * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits | |
4325 | */ | |
4326 | tcr = rd_reg16(info, TCR); | |
4327 | if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { | |
4328 | /* disable preamble, set idle size to 16 bits */ | |
4329 | tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; | |
4330 | /* MSB of 16 bit idle specified in tx preamble register (TPR) */ | |
4331 | wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); | |
4332 | } else if (!(tcr & BIT6)) { | |
4333 | /* preamble is disabled, set idle size to 8 bits */ | |
4334 | tcr &= ~(BIT5 + BIT4); | |
4335 | } | |
4336 | wr_reg16(info, TCR, tcr); | |
4337 | ||
4338 | if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { | |
4339 | /* LSB of custom tx idle specified in tx idle register */ | |
4340 | val = (unsigned char)(info->idle_mode & 0xff); | |
4341 | } else { | |
4342 | /* standard 8 bit idle patterns */ | |
4343 | switch(info->idle_mode) | |
4344 | { | |
4345 | case HDLC_TXIDLE_FLAGS: val = 0x7e; break; | |
4346 | case HDLC_TXIDLE_ALT_ZEROS_ONES: | |
4347 | case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; | |
4348 | case HDLC_TXIDLE_ZEROS: | |
4349 | case HDLC_TXIDLE_SPACE: val = 0x00; break; | |
4350 | default: val = 0xff; | |
4351 | } | |
705b6c7b PF |
4352 | } |
4353 | ||
4354 | wr_reg8(info, TIR, val); | |
4355 | } | |
4356 | ||
4357 | /* | |
4358 | * get state of V24 status (input) signals | |
4359 | */ | |
4360 | static void get_signals(struct slgt_info *info) | |
4361 | { | |
4362 | unsigned short status = rd_reg16(info, SSR); | |
4363 | ||
4364 | /* clear all serial signals except DTR and RTS */ | |
4365 | info->signals &= SerialSignal_DTR + SerialSignal_RTS; | |
4366 | ||
4367 | if (status & BIT3) | |
4368 | info->signals |= SerialSignal_DSR; | |
4369 | if (status & BIT2) | |
4370 | info->signals |= SerialSignal_CTS; | |
4371 | if (status & BIT1) | |
4372 | info->signals |= SerialSignal_DCD; | |
4373 | if (status & BIT0) | |
4374 | info->signals |= SerialSignal_RI; | |
4375 | } | |
4376 | ||
4377 | /* | |
4378 | * set V.24 Control Register based on current configuration | |
4379 | */ | |
4380 | static void msc_set_vcr(struct slgt_info *info) | |
4381 | { | |
4382 | unsigned char val = 0; | |
4383 | ||
4384 | /* VCR (V.24 control) | |
4385 | * | |
4386 | * 07..04 serial IF select | |
4387 | * 03 DTR | |
4388 | * 02 RTS | |
4389 | * 01 LL | |
4390 | * 00 RL | |
4391 | */ | |
4392 | ||
4393 | switch(info->if_mode & MGSL_INTERFACE_MASK) | |
4394 | { | |
4395 | case MGSL_INTERFACE_RS232: | |
4396 | val |= BIT5; /* 0010 */ | |
4397 | break; | |
4398 | case MGSL_INTERFACE_V35: | |
4399 | val |= BIT7 + BIT6 + BIT5; /* 1110 */ | |
4400 | break; | |
4401 | case MGSL_INTERFACE_RS422: | |
4402 | val |= BIT6; /* 0100 */ | |
4403 | break; | |
4404 | } | |
4405 | ||
4406 | if (info->signals & SerialSignal_DTR) | |
4407 | val |= BIT3; | |
4408 | if (info->signals & SerialSignal_RTS) | |
4409 | val |= BIT2; | |
4410 | if (info->if_mode & MGSL_INTERFACE_LL) | |
4411 | val |= BIT1; | |
4412 | if (info->if_mode & MGSL_INTERFACE_RL) | |
4413 | val |= BIT0; | |
4414 | wr_reg8(info, VCR, val); | |
4415 | } | |
4416 | ||
4417 | /* | |
4418 | * set state of V24 control (output) signals | |
4419 | */ | |
4420 | static void set_signals(struct slgt_info *info) | |
4421 | { | |
4422 | unsigned char val = rd_reg8(info, VCR); | |
4423 | if (info->signals & SerialSignal_DTR) | |
4424 | val |= BIT3; | |
4425 | else | |
4426 | val &= ~BIT3; | |
4427 | if (info->signals & SerialSignal_RTS) | |
4428 | val |= BIT2; | |
4429 | else | |
4430 | val &= ~BIT2; | |
4431 | wr_reg8(info, VCR, val); | |
4432 | } | |
4433 | ||
4434 | /* | |
4435 | * free range of receive DMA buffers (i to last) | |
4436 | */ | |
4437 | static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) | |
4438 | { | |
4439 | int done = 0; | |
4440 | ||
4441 | while(!done) { | |
4442 | /* reset current buffer for reuse */ | |
4443 | info->rbufs[i].status = 0; | |
cb10dc9a PF |
4444 | switch(info->params.mode) { |
4445 | case MGSL_MODE_RAW: | |
4446 | case MGSL_MODE_MONOSYNC: | |
4447 | case MGSL_MODE_BISYNC: | |
705b6c7b | 4448 | set_desc_count(info->rbufs[i], info->raw_rx_size); |
cb10dc9a PF |
4449 | break; |
4450 | default: | |
705b6c7b | 4451 | set_desc_count(info->rbufs[i], DMABUFSIZE); |
cb10dc9a | 4452 | } |
705b6c7b PF |
4453 | |
4454 | if (i == last) | |
4455 | done = 1; | |
4456 | if (++i == info->rbuf_count) | |
4457 | i = 0; | |
4458 | } | |
4459 | info->rbuf_current = i; | |
4460 | } | |
4461 | ||
4462 | /* | |
4463 | * mark all receive DMA buffers as free | |
4464 | */ | |
4465 | static void reset_rbufs(struct slgt_info *info) | |
4466 | { | |
4467 | free_rbufs(info, 0, info->rbuf_count - 1); | |
4468 | } | |
4469 | ||
4470 | /* | |
4471 | * pass receive HDLC frame to upper layer | |
4472 | * | |
4473 | * return 1 if frame available, otherwise 0 | |
4474 | */ | |
4475 | static int rx_get_frame(struct slgt_info *info) | |
4476 | { | |
4477 | unsigned int start, end; | |
4478 | unsigned short status; | |
4479 | unsigned int framesize = 0; | |
4480 | int rc = 0; | |
4481 | unsigned long flags; | |
4482 | struct tty_struct *tty = info->tty; | |
4483 | unsigned char addr_field = 0xff; | |
04b374d0 PF |
4484 | unsigned int crc_size = 0; |
4485 | ||
4486 | switch (info->params.crc_type & HDLC_CRC_MASK) { | |
4487 | case HDLC_CRC_16_CCITT: crc_size = 2; break; | |
4488 | case HDLC_CRC_32_CCITT: crc_size = 4; break; | |
4489 | } | |
705b6c7b PF |
4490 | |
4491 | check_again: | |
4492 | ||
4493 | framesize = 0; | |
4494 | addr_field = 0xff; | |
4495 | start = end = info->rbuf_current; | |
4496 | ||
4497 | for (;;) { | |
4498 | if (!desc_complete(info->rbufs[end])) | |
4499 | goto cleanup; | |
4500 | ||
4501 | if (framesize == 0 && info->params.addr_filter != 0xff) | |
4502 | addr_field = info->rbufs[end].buf[0]; | |
4503 | ||
4504 | framesize += desc_count(info->rbufs[end]); | |
4505 | ||
4506 | if (desc_eof(info->rbufs[end])) | |
4507 | break; | |
4508 | ||
4509 | if (++end == info->rbuf_count) | |
4510 | end = 0; | |
4511 | ||
4512 | if (end == info->rbuf_current) { | |
4513 | if (info->rx_enabled){ | |
4514 | spin_lock_irqsave(&info->lock,flags); | |
4515 | rx_start(info); | |
4516 | spin_unlock_irqrestore(&info->lock,flags); | |
4517 | } | |
4518 | goto cleanup; | |
4519 | } | |
4520 | } | |
4521 | ||
4522 | /* status | |
4523 | * | |
4524 | * 15 buffer complete | |
4525 | * 14..06 reserved | |
4526 | * 05..04 residue | |
4527 | * 02 eof (end of frame) | |
4528 | * 01 CRC error | |
4529 | * 00 abort | |
4530 | */ | |
4531 | status = desc_status(info->rbufs[end]); | |
4532 | ||
4533 | /* ignore CRC bit if not using CRC (bit is undefined) */ | |
04b374d0 | 4534 | if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) |
705b6c7b PF |
4535 | status &= ~BIT1; |
4536 | ||
4537 | if (framesize == 0 || | |
4538 | (addr_field != 0xff && addr_field != info->params.addr_filter)) { | |
4539 | free_rbufs(info, start, end); | |
4540 | goto check_again; | |
4541 | } | |
4542 | ||
04b374d0 PF |
4543 | if (framesize < (2 + crc_size) || status & BIT0) { |
4544 | info->icount.rxshort++; | |
705b6c7b | 4545 | framesize = 0; |
04b374d0 PF |
4546 | } else if (status & BIT1) { |
4547 | info->icount.rxcrc++; | |
4548 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) | |
4549 | framesize = 0; | |
4550 | } | |
705b6c7b | 4551 | |
af69c7f9 | 4552 | #if SYNCLINK_GENERIC_HDLC |
04b374d0 PF |
4553 | if (framesize == 0) { |
4554 | struct net_device_stats *stats = hdlc_stats(info->netdev); | |
4555 | stats->rx_errors++; | |
4556 | stats->rx_frame_errors++; | |
705b6c7b | 4557 | } |
04b374d0 | 4558 | #endif |
705b6c7b PF |
4559 | |
4560 | DBGBH(("%s rx frame status=%04X size=%d\n", | |
4561 | info->device_name, status, framesize)); | |
4562 | DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx"); | |
4563 | ||
4564 | if (framesize) { | |
04b374d0 PF |
4565 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { |
4566 | framesize -= crc_size; | |
4567 | crc_size = 0; | |
4568 | } | |
4569 | ||
4570 | if (framesize > info->max_frame_size + crc_size) | |
705b6c7b PF |
4571 | info->icount.rxlong++; |
4572 | else { | |
4573 | /* copy dma buffer(s) to contiguous temp buffer */ | |
4574 | int copy_count = framesize; | |
4575 | int i = start; | |
4576 | unsigned char *p = info->tmp_rbuf; | |
4577 | info->tmp_rbuf_count = framesize; | |
4578 | ||
4579 | info->icount.rxok++; | |
4580 | ||
4581 | while(copy_count) { | |
4582 | int partial_count = min(copy_count, DMABUFSIZE); | |
4583 | memcpy(p, info->rbufs[i].buf, partial_count); | |
4584 | p += partial_count; | |
4585 | copy_count -= partial_count; | |
4586 | if (++i == info->rbuf_count) | |
4587 | i = 0; | |
4588 | } | |
4589 | ||
04b374d0 PF |
4590 | if (info->params.crc_type & HDLC_CRC_RETURN_EX) { |
4591 | *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; | |
4592 | framesize++; | |
4593 | } | |
4594 | ||
af69c7f9 | 4595 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
4596 | if (info->netcount) |
4597 | hdlcdev_rx(info,info->tmp_rbuf, framesize); | |
4598 | else | |
4599 | #endif | |
4600 | ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); | |
4601 | } | |
4602 | } | |
4603 | free_rbufs(info, start, end); | |
4604 | rc = 1; | |
4605 | ||
4606 | cleanup: | |
4607 | return rc; | |
4608 | } | |
4609 | ||
4610 | /* | |
4611 | * pass receive buffer (RAW synchronous mode) to tty layer | |
4612 | * return 1 if buffer available, otherwise 0 | |
4613 | */ | |
4614 | static int rx_get_buf(struct slgt_info *info) | |
4615 | { | |
4616 | unsigned int i = info->rbuf_current; | |
cb10dc9a | 4617 | unsigned int count; |
705b6c7b PF |
4618 | |
4619 | if (!desc_complete(info->rbufs[i])) | |
4620 | return 0; | |
cb10dc9a PF |
4621 | count = desc_count(info->rbufs[i]); |
4622 | switch(info->params.mode) { | |
4623 | case MGSL_MODE_MONOSYNC: | |
4624 | case MGSL_MODE_BISYNC: | |
4625 | /* ignore residue in byte synchronous modes */ | |
4626 | if (desc_residue(info->rbufs[i])) | |
4627 | count--; | |
4628 | break; | |
4629 | } | |
4630 | DBGDATA(info, info->rbufs[i].buf, count, "rx"); | |
4631 | DBGINFO(("rx_get_buf size=%d\n", count)); | |
4632 | if (count) | |
4633 | ldisc_receive_buf(info->tty, info->rbufs[i].buf, | |
4634 | info->flag_buf, count); | |
705b6c7b PF |
4635 | free_rbufs(info, i, i); |
4636 | return 1; | |
4637 | } | |
4638 | ||
4639 | static void reset_tbufs(struct slgt_info *info) | |
4640 | { | |
4641 | unsigned int i; | |
4642 | info->tbuf_current = 0; | |
4643 | for (i=0 ; i < info->tbuf_count ; i++) { | |
4644 | info->tbufs[i].status = 0; | |
4645 | info->tbufs[i].count = 0; | |
4646 | } | |
4647 | } | |
4648 | ||
4649 | /* | |
4650 | * return number of free transmit DMA buffers | |
4651 | */ | |
4652 | static unsigned int free_tbuf_count(struct slgt_info *info) | |
4653 | { | |
4654 | unsigned int count = 0; | |
4655 | unsigned int i = info->tbuf_current; | |
4656 | ||
4657 | do | |
4658 | { | |
4659 | if (desc_count(info->tbufs[i])) | |
4660 | break; /* buffer in use */ | |
4661 | ++count; | |
4662 | if (++i == info->tbuf_count) | |
4663 | i=0; | |
4664 | } while (i != info->tbuf_current); | |
4665 | ||
bb029c67 PF |
4666 | /* if tx DMA active, last zero count buffer is in use */ |
4667 | if (count && (rd_reg32(info, TDCSR) & BIT0)) | |
705b6c7b PF |
4668 | --count; |
4669 | ||
4670 | return count; | |
4671 | } | |
4672 | ||
4673 | /* | |
4674 | * load transmit DMA buffer(s) with data | |
4675 | */ | |
4676 | static void tx_load(struct slgt_info *info, const char *buf, unsigned int size) | |
4677 | { | |
4678 | unsigned short count; | |
4679 | unsigned int i; | |
4680 | struct slgt_desc *d; | |
4681 | ||
4682 | if (size == 0) | |
4683 | return; | |
4684 | ||
4685 | DBGDATA(info, buf, size, "tx"); | |
4686 | ||
4687 | info->tbuf_start = i = info->tbuf_current; | |
4688 | ||
4689 | while (size) { | |
4690 | d = &info->tbufs[i]; | |
4691 | if (++i == info->tbuf_count) | |
4692 | i = 0; | |
4693 | ||
4694 | count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); | |
4695 | memcpy(d->buf, buf, count); | |
4696 | ||
4697 | size -= count; | |
4698 | buf += count; | |
4699 | ||
cb10dc9a PF |
4700 | /* |
4701 | * set EOF bit for last buffer of HDLC frame or | |
4702 | * for every buffer in raw mode | |
4703 | */ | |
4704 | if ((!size && info->params.mode == MGSL_MODE_HDLC) || | |
4705 | info->params.mode == MGSL_MODE_RAW) | |
4706 | set_desc_eof(*d, 1); | |
705b6c7b PF |
4707 | else |
4708 | set_desc_eof(*d, 0); | |
4709 | ||
4710 | set_desc_count(*d, count); | |
4711 | } | |
4712 | ||
4713 | info->tbuf_current = i; | |
4714 | } | |
4715 | ||
4716 | static int register_test(struct slgt_info *info) | |
4717 | { | |
4718 | static unsigned short patterns[] = | |
4719 | {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; | |
4720 | static unsigned int count = sizeof(patterns)/sizeof(patterns[0]); | |
4721 | unsigned int i; | |
4722 | int rc = 0; | |
4723 | ||
4724 | for (i=0 ; i < count ; i++) { | |
4725 | wr_reg16(info, TIR, patterns[i]); | |
4726 | wr_reg16(info, BDR, patterns[(i+1)%count]); | |
4727 | if ((rd_reg16(info, TIR) != patterns[i]) || | |
4728 | (rd_reg16(info, BDR) != patterns[(i+1)%count])) { | |
4729 | rc = -ENODEV; | |
4730 | break; | |
4731 | } | |
4732 | } | |
0080b7aa | 4733 | info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; |
705b6c7b PF |
4734 | info->init_error = rc ? 0 : DiagStatus_AddressFailure; |
4735 | return rc; | |
4736 | } | |
4737 | ||
4738 | static int irq_test(struct slgt_info *info) | |
4739 | { | |
4740 | unsigned long timeout; | |
4741 | unsigned long flags; | |
4742 | struct tty_struct *oldtty = info->tty; | |
4743 | u32 speed = info->params.data_rate; | |
4744 | ||
4745 | info->params.data_rate = 921600; | |
4746 | info->tty = NULL; | |
4747 | ||
4748 | spin_lock_irqsave(&info->lock, flags); | |
4749 | async_mode(info); | |
4750 | slgt_irq_on(info, IRQ_TXIDLE); | |
4751 | ||
4752 | /* enable transmitter */ | |
4753 | wr_reg16(info, TCR, | |
4754 | (unsigned short)(rd_reg16(info, TCR) | BIT1)); | |
4755 | ||
4756 | /* write one byte and wait for tx idle */ | |
4757 | wr_reg16(info, TDR, 0); | |
4758 | ||
4759 | /* assume failure */ | |
4760 | info->init_error = DiagStatus_IrqFailure; | |
4761 | info->irq_occurred = FALSE; | |
4762 | ||
4763 | spin_unlock_irqrestore(&info->lock, flags); | |
4764 | ||
4765 | timeout=100; | |
4766 | while(timeout-- && !info->irq_occurred) | |
4767 | msleep_interruptible(10); | |
4768 | ||
4769 | spin_lock_irqsave(&info->lock,flags); | |
4770 | reset_port(info); | |
4771 | spin_unlock_irqrestore(&info->lock,flags); | |
4772 | ||
4773 | info->params.data_rate = speed; | |
4774 | info->tty = oldtty; | |
4775 | ||
4776 | info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; | |
4777 | return info->irq_occurred ? 0 : -ENODEV; | |
4778 | } | |
4779 | ||
4780 | static int loopback_test_rx(struct slgt_info *info) | |
4781 | { | |
4782 | unsigned char *src, *dest; | |
4783 | int count; | |
4784 | ||
4785 | if (desc_complete(info->rbufs[0])) { | |
4786 | count = desc_count(info->rbufs[0]); | |
4787 | src = info->rbufs[0].buf; | |
4788 | dest = info->tmp_rbuf; | |
4789 | ||
4790 | for( ; count ; count-=2, src+=2) { | |
4791 | /* src=data byte (src+1)=status byte */ | |
4792 | if (!(*(src+1) & (BIT9 + BIT8))) { | |
4793 | *dest = *src; | |
4794 | dest++; | |
4795 | info->tmp_rbuf_count++; | |
4796 | } | |
4797 | } | |
4798 | DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); | |
4799 | return 1; | |
4800 | } | |
4801 | return 0; | |
4802 | } | |
4803 | ||
4804 | static int loopback_test(struct slgt_info *info) | |
4805 | { | |
4806 | #define TESTFRAMESIZE 20 | |
4807 | ||
4808 | unsigned long timeout; | |
4809 | u16 count = TESTFRAMESIZE; | |
4810 | unsigned char buf[TESTFRAMESIZE]; | |
4811 | int rc = -ENODEV; | |
4812 | unsigned long flags; | |
4813 | ||
4814 | struct tty_struct *oldtty = info->tty; | |
4815 | MGSL_PARAMS params; | |
4816 | ||
4817 | memcpy(¶ms, &info->params, sizeof(params)); | |
4818 | ||
4819 | info->params.mode = MGSL_MODE_ASYNC; | |
4820 | info->params.data_rate = 921600; | |
4821 | info->params.loopback = 1; | |
4822 | info->tty = NULL; | |
4823 | ||
4824 | /* build and send transmit frame */ | |
4825 | for (count = 0; count < TESTFRAMESIZE; ++count) | |
4826 | buf[count] = (unsigned char)count; | |
4827 | ||
4828 | info->tmp_rbuf_count = 0; | |
4829 | memset(info->tmp_rbuf, 0, TESTFRAMESIZE); | |
4830 | ||
4831 | /* program hardware for HDLC and enabled receiver */ | |
4832 | spin_lock_irqsave(&info->lock,flags); | |
4833 | async_mode(info); | |
4834 | rx_start(info); | |
4835 | info->tx_count = count; | |
4836 | tx_load(info, buf, count); | |
4837 | tx_start(info); | |
4838 | spin_unlock_irqrestore(&info->lock, flags); | |
4839 | ||
4840 | /* wait for receive complete */ | |
4841 | for (timeout = 100; timeout; --timeout) { | |
4842 | msleep_interruptible(10); | |
4843 | if (loopback_test_rx(info)) { | |
4844 | rc = 0; | |
4845 | break; | |
4846 | } | |
4847 | } | |
4848 | ||
4849 | /* verify received frame length and contents */ | |
4850 | if (!rc && (info->tmp_rbuf_count != count || | |
4851 | memcmp(buf, info->tmp_rbuf, count))) { | |
4852 | rc = -ENODEV; | |
4853 | } | |
4854 | ||
4855 | spin_lock_irqsave(&info->lock,flags); | |
4856 | reset_adapter(info); | |
4857 | spin_unlock_irqrestore(&info->lock,flags); | |
4858 | ||
4859 | memcpy(&info->params, ¶ms, sizeof(info->params)); | |
4860 | info->tty = oldtty; | |
4861 | ||
4862 | info->init_error = rc ? DiagStatus_DmaFailure : 0; | |
4863 | return rc; | |
4864 | } | |
4865 | ||
4866 | static int adapter_test(struct slgt_info *info) | |
4867 | { | |
4868 | DBGINFO(("testing %s\n", info->device_name)); | |
294dad05 | 4869 | if (register_test(info) < 0) { |
705b6c7b PF |
4870 | printk("register test failure %s addr=%08X\n", |
4871 | info->device_name, info->phys_reg_addr); | |
294dad05 | 4872 | } else if (irq_test(info) < 0) { |
705b6c7b PF |
4873 | printk("IRQ test failure %s IRQ=%d\n", |
4874 | info->device_name, info->irq_level); | |
294dad05 | 4875 | } else if (loopback_test(info) < 0) { |
705b6c7b PF |
4876 | printk("loopback test failure %s\n", info->device_name); |
4877 | } | |
4878 | return info->init_error; | |
4879 | } | |
4880 | ||
4881 | /* | |
4882 | * transmit timeout handler | |
4883 | */ | |
4884 | static void tx_timeout(unsigned long context) | |
4885 | { | |
4886 | struct slgt_info *info = (struct slgt_info*)context; | |
4887 | unsigned long flags; | |
4888 | ||
4889 | DBGINFO(("%s tx_timeout\n", info->device_name)); | |
4890 | if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { | |
4891 | info->icount.txtimeout++; | |
4892 | } | |
4893 | spin_lock_irqsave(&info->lock,flags); | |
4894 | info->tx_active = 0; | |
4895 | info->tx_count = 0; | |
4896 | spin_unlock_irqrestore(&info->lock,flags); | |
4897 | ||
af69c7f9 | 4898 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
4899 | if (info->netcount) |
4900 | hdlcdev_tx_done(info); | |
4901 | else | |
4902 | #endif | |
4903 | bh_transmit(info); | |
4904 | } | |
4905 | ||
4906 | /* | |
4907 | * receive buffer polling timer | |
4908 | */ | |
4909 | static void rx_timeout(unsigned long context) | |
4910 | { | |
4911 | struct slgt_info *info = (struct slgt_info*)context; | |
4912 | unsigned long flags; | |
4913 | ||
4914 | DBGINFO(("%s rx_timeout\n", info->device_name)); | |
4915 | spin_lock_irqsave(&info->lock, flags); | |
4916 | info->pending_bh |= BH_RECEIVE; | |
4917 | spin_unlock_irqrestore(&info->lock, flags); | |
c4028958 | 4918 | bh_handler(&info->task); |
705b6c7b PF |
4919 | } |
4920 |