Commit | Line | Data |
---|---|---|
705b6c7b | 1 | /* |
705b6c7b PF |
2 | * Device driver for Microgate SyncLink GT serial adapters. |
3 | * | |
4 | * written by Paul Fulghum for Microgate Corporation | |
5 | * paulkf@microgate.com | |
6 | * | |
7 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
8 | * | |
9 | * This code is released under the GNU General Public License (GPL) | |
10 | * | |
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
13 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
14 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
15 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
16 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
17 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
18 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
19 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
20 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
21 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
22 | */ | |
23 | ||
24 | /* | |
25 | * DEBUG OUTPUT DEFINITIONS | |
26 | * | |
27 | * uncomment lines below to enable specific types of debug output | |
28 | * | |
29 | * DBGINFO information - most verbose output | |
30 | * DBGERR serious errors | |
31 | * DBGBH bottom half service routine debugging | |
32 | * DBGISR interrupt service routine debugging | |
33 | * DBGDATA output receive and transmit data | |
34 | * DBGTBUF output transmit DMA buffers and registers | |
35 | * DBGRBUF output receive DMA buffers and registers | |
36 | */ | |
37 | ||
38 | #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt | |
39 | #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt | |
40 | #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt | |
41 | #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt | |
42 | #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) | |
43 | //#define DBGTBUF(info) dump_tbufs(info) | |
44 | //#define DBGRBUF(info) dump_rbufs(info) | |
45 | ||
46 | ||
705b6c7b | 47 | #include <linux/module.h> |
705b6c7b PF |
48 | #include <linux/errno.h> |
49 | #include <linux/signal.h> | |
50 | #include <linux/sched.h> | |
51 | #include <linux/timer.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/tty.h> | |
55 | #include <linux/tty_flip.h> | |
56 | #include <linux/serial.h> | |
57 | #include <linux/major.h> | |
58 | #include <linux/string.h> | |
59 | #include <linux/fcntl.h> | |
60 | #include <linux/ptrace.h> | |
61 | #include <linux/ioport.h> | |
62 | #include <linux/mm.h> | |
a18c56e5 | 63 | #include <linux/seq_file.h> |
705b6c7b PF |
64 | #include <linux/slab.h> |
65 | #include <linux/netdevice.h> | |
66 | #include <linux/vmalloc.h> | |
67 | #include <linux/init.h> | |
68 | #include <linux/delay.h> | |
69 | #include <linux/ioctl.h> | |
70 | #include <linux/termios.h> | |
71 | #include <linux/bitops.h> | |
72 | #include <linux/workqueue.h> | |
73 | #include <linux/hdlc.h> | |
3dd1247f | 74 | #include <linux/synclink.h> |
705b6c7b | 75 | |
705b6c7b PF |
76 | #include <asm/system.h> |
77 | #include <asm/io.h> | |
78 | #include <asm/irq.h> | |
79 | #include <asm/dma.h> | |
80 | #include <asm/types.h> | |
81 | #include <asm/uaccess.h> | |
82 | ||
af69c7f9 PF |
83 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) |
84 | #define SYNCLINK_GENERIC_HDLC 1 | |
85 | #else | |
86 | #define SYNCLINK_GENERIC_HDLC 0 | |
705b6c7b PF |
87 | #endif |
88 | ||
89 | /* | |
90 | * module identification | |
91 | */ | |
92 | static char *driver_name = "SyncLink GT"; | |
705b6c7b PF |
93 | static char *tty_driver_name = "synclink_gt"; |
94 | static char *tty_dev_prefix = "ttySLG"; | |
95 | MODULE_LICENSE("GPL"); | |
96 | #define MGSL_MAGIC 0x5401 | |
a077c1a0 | 97 | #define MAX_DEVICES 32 |
705b6c7b PF |
98 | |
99 | static struct pci_device_id pci_table[] = { | |
100 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
6f84be84 | 101 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
705b6c7b PF |
102 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
103 | {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, | |
104 | {0,}, /* terminate list */ | |
105 | }; | |
106 | MODULE_DEVICE_TABLE(pci, pci_table); | |
107 | ||
108 | static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); | |
109 | static void remove_one(struct pci_dev *dev); | |
110 | static struct pci_driver pci_driver = { | |
111 | .name = "synclink_gt", | |
112 | .id_table = pci_table, | |
113 | .probe = init_one, | |
114 | .remove = __devexit_p(remove_one), | |
115 | }; | |
116 | ||
0fab6de0 | 117 | static bool pci_registered; |
705b6c7b PF |
118 | |
119 | /* | |
120 | * module configuration and status | |
121 | */ | |
122 | static struct slgt_info *slgt_device_list; | |
123 | static int slgt_device_count; | |
124 | ||
125 | static int ttymajor; | |
126 | static int debug_level; | |
127 | static int maxframe[MAX_DEVICES]; | |
705b6c7b PF |
128 | |
129 | module_param(ttymajor, int, 0); | |
130 | module_param(debug_level, int, 0); | |
131 | module_param_array(maxframe, int, NULL, 0); | |
705b6c7b PF |
132 | |
133 | MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); | |
134 | MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); | |
135 | MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); | |
705b6c7b PF |
136 | |
137 | /* | |
138 | * tty support and callbacks | |
139 | */ | |
705b6c7b PF |
140 | static struct tty_driver *serial_driver; |
141 | ||
142 | static int open(struct tty_struct *tty, struct file * filp); | |
143 | static void close(struct tty_struct *tty, struct file * filp); | |
144 | static void hangup(struct tty_struct *tty); | |
606d099c | 145 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); |
705b6c7b PF |
146 | |
147 | static int write(struct tty_struct *tty, const unsigned char *buf, int count); | |
55da7789 | 148 | static int put_char(struct tty_struct *tty, unsigned char ch); |
705b6c7b PF |
149 | static void send_xchar(struct tty_struct *tty, char ch); |
150 | static void wait_until_sent(struct tty_struct *tty, int timeout); | |
151 | static int write_room(struct tty_struct *tty); | |
152 | static void flush_chars(struct tty_struct *tty); | |
153 | static void flush_buffer(struct tty_struct *tty); | |
154 | static void tx_hold(struct tty_struct *tty); | |
155 | static void tx_release(struct tty_struct *tty); | |
156 | ||
157 | static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg); | |
705b6c7b PF |
158 | static int chars_in_buffer(struct tty_struct *tty); |
159 | static void throttle(struct tty_struct * tty); | |
160 | static void unthrottle(struct tty_struct * tty); | |
9e98966c | 161 | static int set_break(struct tty_struct *tty, int break_state); |
705b6c7b PF |
162 | |
163 | /* | |
164 | * generic HDLC support and callbacks | |
165 | */ | |
af69c7f9 | 166 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
167 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
168 | static void hdlcdev_tx_done(struct slgt_info *info); | |
169 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); | |
170 | static int hdlcdev_init(struct slgt_info *info); | |
171 | static void hdlcdev_exit(struct slgt_info *info); | |
172 | #endif | |
173 | ||
174 | ||
175 | /* | |
176 | * device specific structures, macros and functions | |
177 | */ | |
178 | ||
179 | #define SLGT_MAX_PORTS 4 | |
180 | #define SLGT_REG_SIZE 256 | |
181 | ||
0080b7aa PF |
182 | /* |
183 | * conditional wait facility | |
184 | */ | |
185 | struct cond_wait { | |
186 | struct cond_wait *next; | |
187 | wait_queue_head_t q; | |
188 | wait_queue_t wait; | |
189 | unsigned int data; | |
190 | }; | |
191 | static void init_cond_wait(struct cond_wait *w, unsigned int data); | |
192 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
193 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); | |
194 | static void flush_cond_wait(struct cond_wait **head); | |
195 | ||
705b6c7b PF |
196 | /* |
197 | * DMA buffer descriptor and access macros | |
198 | */ | |
199 | struct slgt_desc | |
200 | { | |
51ef9c57 AV |
201 | __le16 count; |
202 | __le16 status; | |
203 | __le32 pbuf; /* physical address of data buffer */ | |
204 | __le32 next; /* physical address of next descriptor */ | |
705b6c7b PF |
205 | |
206 | /* driver book keeping */ | |
207 | char *buf; /* virtual address of data buffer */ | |
208 | unsigned int pdesc; /* physical address of this descriptor */ | |
209 | dma_addr_t buf_dma_addr; | |
403214d0 | 210 | unsigned short buf_count; |
705b6c7b PF |
211 | }; |
212 | ||
213 | #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) | |
214 | #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) | |
215 | #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) | |
216 | #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) | |
217 | #define desc_count(a) (le16_to_cpu((a).count)) | |
218 | #define desc_status(a) (le16_to_cpu((a).status)) | |
219 | #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) | |
220 | #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) | |
221 | #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) | |
222 | #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) | |
223 | #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) | |
224 | ||
225 | struct _input_signal_events { | |
226 | int ri_up; | |
227 | int ri_down; | |
228 | int dsr_up; | |
229 | int dsr_down; | |
230 | int dcd_up; | |
231 | int dcd_down; | |
232 | int cts_up; | |
233 | int cts_down; | |
234 | }; | |
235 | ||
236 | /* | |
237 | * device instance data structure | |
238 | */ | |
239 | struct slgt_info { | |
240 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | |
8fb06c77 | 241 | struct tty_port port; |
705b6c7b PF |
242 | |
243 | struct slgt_info *next_device; /* device list link */ | |
244 | ||
245 | int magic; | |
705b6c7b PF |
246 | |
247 | char device_name[25]; | |
248 | struct pci_dev *pdev; | |
249 | ||
250 | int port_count; /* count of ports on adapter */ | |
251 | int adapter_num; /* adapter instance number */ | |
252 | int port_num; /* port instance number */ | |
253 | ||
254 | /* array of pointers to port contexts on this adapter */ | |
255 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
256 | ||
705b6c7b | 257 | int line; /* tty line instance number */ |
705b6c7b PF |
258 | |
259 | struct mgsl_icount icount; | |
260 | ||
705b6c7b PF |
261 | int timeout; |
262 | int x_char; /* xon/xoff character */ | |
705b6c7b PF |
263 | unsigned int read_status_mask; |
264 | unsigned int ignore_status_mask; | |
265 | ||
705b6c7b PF |
266 | wait_queue_head_t status_event_wait_q; |
267 | wait_queue_head_t event_wait_q; | |
268 | struct timer_list tx_timer; | |
269 | struct timer_list rx_timer; | |
270 | ||
0080b7aa PF |
271 | unsigned int gpio_present; |
272 | struct cond_wait *gpio_wait_q; | |
273 | ||
705b6c7b PF |
274 | spinlock_t lock; /* spinlock for synchronizing with ISR */ |
275 | ||
276 | struct work_struct task; | |
277 | u32 pending_bh; | |
0fab6de0 JP |
278 | bool bh_requested; |
279 | bool bh_running; | |
705b6c7b PF |
280 | |
281 | int isr_overflow; | |
0fab6de0 JP |
282 | bool irq_requested; /* true if IRQ requested */ |
283 | bool irq_occurred; /* for diagnostics use */ | |
705b6c7b PF |
284 | |
285 | /* device configuration */ | |
286 | ||
287 | unsigned int bus_type; | |
288 | unsigned int irq_level; | |
289 | unsigned long irq_flags; | |
290 | ||
291 | unsigned char __iomem * reg_addr; /* memory mapped registers address */ | |
292 | u32 phys_reg_addr; | |
0fab6de0 | 293 | bool reg_addr_requested; |
705b6c7b PF |
294 | |
295 | MGSL_PARAMS params; /* communications parameters */ | |
296 | u32 idle_mode; | |
297 | u32 max_frame_size; /* as set by device config */ | |
298 | ||
814dae03 | 299 | unsigned int rbuf_fill_level; |
705b6c7b | 300 | unsigned int if_mode; |
1f80769f | 301 | unsigned int base_clock; |
705b6c7b PF |
302 | |
303 | /* device status */ | |
304 | ||
0fab6de0 JP |
305 | bool rx_enabled; |
306 | bool rx_restart; | |
705b6c7b | 307 | |
0fab6de0 JP |
308 | bool tx_enabled; |
309 | bool tx_active; | |
705b6c7b PF |
310 | |
311 | unsigned char signals; /* serial signal states */ | |
2641dfd9 | 312 | int init_error; /* initialization error */ |
705b6c7b PF |
313 | |
314 | unsigned char *tx_buf; | |
315 | int tx_count; | |
316 | ||
317 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | |
318 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; | |
0fab6de0 | 319 | bool drop_rts_on_tx_done; |
705b6c7b PF |
320 | struct _input_signal_events input_signal_events; |
321 | ||
322 | int dcd_chkcount; /* check counts to prevent */ | |
323 | int cts_chkcount; /* too many IRQs if a signal */ | |
324 | int dsr_chkcount; /* is floating */ | |
325 | int ri_chkcount; | |
326 | ||
327 | char *bufs; /* virtual address of DMA buffer lists */ | |
328 | dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ | |
329 | ||
330 | unsigned int rbuf_count; | |
331 | struct slgt_desc *rbufs; | |
332 | unsigned int rbuf_current; | |
333 | unsigned int rbuf_index; | |
334 | ||
335 | unsigned int tbuf_count; | |
336 | struct slgt_desc *tbufs; | |
337 | unsigned int tbuf_current; | |
338 | unsigned int tbuf_start; | |
339 | ||
340 | unsigned char *tmp_rbuf; | |
341 | unsigned int tmp_rbuf_count; | |
342 | ||
343 | /* SPPP/Cisco HDLC device parts */ | |
344 | ||
345 | int netcount; | |
705b6c7b | 346 | spinlock_t netlock; |
af69c7f9 | 347 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
348 | struct net_device *netdev; |
349 | #endif | |
350 | ||
351 | }; | |
352 | ||
353 | static MGSL_PARAMS default_params = { | |
354 | .mode = MGSL_MODE_HDLC, | |
355 | .loopback = 0, | |
356 | .flags = HDLC_FLAG_UNDERRUN_ABORT15, | |
357 | .encoding = HDLC_ENCODING_NRZI_SPACE, | |
358 | .clock_speed = 0, | |
359 | .addr_filter = 0xff, | |
360 | .crc_type = HDLC_CRC_16_CCITT, | |
361 | .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, | |
362 | .preamble = HDLC_PREAMBLE_PATTERN_NONE, | |
363 | .data_rate = 9600, | |
364 | .data_bits = 8, | |
365 | .stop_bits = 1, | |
366 | .parity = ASYNC_PARITY_NONE | |
367 | }; | |
368 | ||
369 | ||
370 | #define BH_RECEIVE 1 | |
371 | #define BH_TRANSMIT 2 | |
372 | #define BH_STATUS 4 | |
373 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
374 | ||
375 | #define DMABUFSIZE 256 | |
376 | #define DESC_LIST_SIZE 4096 | |
377 | ||
378 | #define MASK_PARITY BIT1 | |
202af6d5 PF |
379 | #define MASK_FRAMING BIT0 |
380 | #define MASK_BREAK BIT14 | |
705b6c7b PF |
381 | #define MASK_OVERRUN BIT4 |
382 | ||
383 | #define GSR 0x00 /* global status */ | |
0080b7aa PF |
384 | #define JCR 0x04 /* JTAG control */ |
385 | #define IODR 0x08 /* GPIO direction */ | |
386 | #define IOER 0x0c /* GPIO interrupt enable */ | |
387 | #define IOVR 0x10 /* GPIO value */ | |
388 | #define IOSR 0x14 /* GPIO interrupt status */ | |
705b6c7b PF |
389 | #define TDR 0x80 /* tx data */ |
390 | #define RDR 0x80 /* rx data */ | |
391 | #define TCR 0x82 /* tx control */ | |
392 | #define TIR 0x84 /* tx idle */ | |
393 | #define TPR 0x85 /* tx preamble */ | |
394 | #define RCR 0x86 /* rx control */ | |
395 | #define VCR 0x88 /* V.24 control */ | |
396 | #define CCR 0x89 /* clock control */ | |
397 | #define BDR 0x8a /* baud divisor */ | |
398 | #define SCR 0x8c /* serial control */ | |
399 | #define SSR 0x8e /* serial status */ | |
400 | #define RDCSR 0x90 /* rx DMA control/status */ | |
401 | #define TDCSR 0x94 /* tx DMA control/status */ | |
402 | #define RDDAR 0x98 /* rx DMA descriptor address */ | |
403 | #define TDDAR 0x9c /* tx DMA descriptor address */ | |
404 | ||
405 | #define RXIDLE BIT14 | |
406 | #define RXBREAK BIT14 | |
407 | #define IRQ_TXDATA BIT13 | |
408 | #define IRQ_TXIDLE BIT12 | |
409 | #define IRQ_TXUNDER BIT11 /* HDLC */ | |
410 | #define IRQ_RXDATA BIT10 | |
411 | #define IRQ_RXIDLE BIT9 /* HDLC */ | |
412 | #define IRQ_RXBREAK BIT9 /* async */ | |
413 | #define IRQ_RXOVER BIT8 | |
414 | #define IRQ_DSR BIT7 | |
415 | #define IRQ_CTS BIT6 | |
416 | #define IRQ_DCD BIT5 | |
417 | #define IRQ_RI BIT4 | |
418 | #define IRQ_ALL 0x3ff0 | |
419 | #define IRQ_MASTER BIT0 | |
420 | ||
421 | #define slgt_irq_on(info, mask) \ | |
422 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) | |
423 | #define slgt_irq_off(info, mask) \ | |
424 | wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) | |
425 | ||
426 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); | |
427 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); | |
428 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); | |
429 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); | |
430 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); | |
431 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); | |
432 | ||
433 | static void msc_set_vcr(struct slgt_info *info); | |
434 | ||
435 | static int startup(struct slgt_info *info); | |
436 | static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); | |
437 | static void shutdown(struct slgt_info *info); | |
438 | static void program_hw(struct slgt_info *info); | |
439 | static void change_params(struct slgt_info *info); | |
440 | ||
441 | static int register_test(struct slgt_info *info); | |
442 | static int irq_test(struct slgt_info *info); | |
443 | static int loopback_test(struct slgt_info *info); | |
444 | static int adapter_test(struct slgt_info *info); | |
445 | ||
446 | static void reset_adapter(struct slgt_info *info); | |
447 | static void reset_port(struct slgt_info *info); | |
448 | static void async_mode(struct slgt_info *info); | |
cb10dc9a | 449 | static void sync_mode(struct slgt_info *info); |
705b6c7b PF |
450 | |
451 | static void rx_stop(struct slgt_info *info); | |
452 | static void rx_start(struct slgt_info *info); | |
453 | static void reset_rbufs(struct slgt_info *info); | |
454 | static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); | |
455 | static void rdma_reset(struct slgt_info *info); | |
0fab6de0 JP |
456 | static bool rx_get_frame(struct slgt_info *info); |
457 | static bool rx_get_buf(struct slgt_info *info); | |
705b6c7b PF |
458 | |
459 | static void tx_start(struct slgt_info *info); | |
460 | static void tx_stop(struct slgt_info *info); | |
461 | static void tx_set_idle(struct slgt_info *info); | |
462 | static unsigned int free_tbuf_count(struct slgt_info *info); | |
403214d0 | 463 | static unsigned int tbuf_bytes(struct slgt_info *info); |
705b6c7b PF |
464 | static void reset_tbufs(struct slgt_info *info); |
465 | static void tdma_reset(struct slgt_info *info); | |
bb029c67 | 466 | static void tdma_start(struct slgt_info *info); |
705b6c7b PF |
467 | static void tx_load(struct slgt_info *info, const char *buf, unsigned int count); |
468 | ||
469 | static void get_signals(struct slgt_info *info); | |
470 | static void set_signals(struct slgt_info *info); | |
471 | static void enable_loopback(struct slgt_info *info); | |
472 | static void set_rate(struct slgt_info *info, u32 data_rate); | |
473 | ||
474 | static int bh_action(struct slgt_info *info); | |
c4028958 | 475 | static void bh_handler(struct work_struct *work); |
705b6c7b PF |
476 | static void bh_transmit(struct slgt_info *info); |
477 | static void isr_serial(struct slgt_info *info); | |
478 | static void isr_rdma(struct slgt_info *info); | |
479 | static void isr_txeom(struct slgt_info *info, unsigned short status); | |
480 | static void isr_tdma(struct slgt_info *info); | |
705b6c7b PF |
481 | |
482 | static int alloc_dma_bufs(struct slgt_info *info); | |
483 | static void free_dma_bufs(struct slgt_info *info); | |
484 | static int alloc_desc(struct slgt_info *info); | |
485 | static void free_desc(struct slgt_info *info); | |
486 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
487 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); | |
488 | ||
489 | static int alloc_tmp_rbuf(struct slgt_info *info); | |
490 | static void free_tmp_rbuf(struct slgt_info *info); | |
491 | ||
492 | static void tx_timeout(unsigned long context); | |
493 | static void rx_timeout(unsigned long context); | |
494 | ||
495 | /* | |
496 | * ioctl handlers | |
497 | */ | |
498 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); | |
499 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
500 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); | |
501 | static int get_txidle(struct slgt_info *info, int __user *idle_mode); | |
502 | static int set_txidle(struct slgt_info *info, int idle_mode); | |
503 | static int tx_enable(struct slgt_info *info, int enable); | |
504 | static int tx_abort(struct slgt_info *info); | |
505 | static int rx_enable(struct slgt_info *info, int enable); | |
506 | static int modem_input_wait(struct slgt_info *info,int arg); | |
507 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); | |
508 | static int tiocmget(struct tty_struct *tty, struct file *file); | |
509 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
510 | unsigned int set, unsigned int clear); | |
9e98966c | 511 | static int set_break(struct tty_struct *tty, int break_state); |
705b6c7b PF |
512 | static int get_interface(struct slgt_info *info, int __user *if_mode); |
513 | static int set_interface(struct slgt_info *info, int if_mode); | |
0080b7aa PF |
514 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); |
515 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
516 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); | |
705b6c7b PF |
517 | |
518 | /* | |
519 | * driver functions | |
520 | */ | |
521 | static void add_device(struct slgt_info *info); | |
522 | static void device_init(int adapter_num, struct pci_dev *pdev); | |
523 | static int claim_resources(struct slgt_info *info); | |
524 | static void release_resources(struct slgt_info *info); | |
525 | ||
526 | /* | |
527 | * DEBUG OUTPUT CODE | |
528 | */ | |
529 | #ifndef DBGINFO | |
530 | #define DBGINFO(fmt) | |
531 | #endif | |
532 | #ifndef DBGERR | |
533 | #define DBGERR(fmt) | |
534 | #endif | |
535 | #ifndef DBGBH | |
536 | #define DBGBH(fmt) | |
537 | #endif | |
538 | #ifndef DBGISR | |
539 | #define DBGISR(fmt) | |
540 | #endif | |
541 | ||
542 | #ifdef DBGDATA | |
543 | static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) | |
544 | { | |
545 | int i; | |
546 | int linecount; | |
547 | printk("%s %s data:\n",info->device_name, label); | |
548 | while(count) { | |
549 | linecount = (count > 16) ? 16 : count; | |
550 | for(i=0; i < linecount; i++) | |
551 | printk("%02X ",(unsigned char)data[i]); | |
552 | for(;i<17;i++) | |
553 | printk(" "); | |
554 | for(i=0;i<linecount;i++) { | |
555 | if (data[i]>=040 && data[i]<=0176) | |
556 | printk("%c",data[i]); | |
557 | else | |
558 | printk("."); | |
559 | } | |
560 | printk("\n"); | |
561 | data += linecount; | |
562 | count -= linecount; | |
563 | } | |
564 | } | |
565 | #else | |
566 | #define DBGDATA(info, buf, size, label) | |
567 | #endif | |
568 | ||
569 | #ifdef DBGTBUF | |
570 | static void dump_tbufs(struct slgt_info *info) | |
571 | { | |
572 | int i; | |
573 | printk("tbuf_current=%d\n", info->tbuf_current); | |
574 | for (i=0 ; i < info->tbuf_count ; i++) { | |
575 | printk("%d: count=%04X status=%04X\n", | |
576 | i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); | |
577 | } | |
578 | } | |
579 | #else | |
580 | #define DBGTBUF(info) | |
581 | #endif | |
582 | ||
583 | #ifdef DBGRBUF | |
584 | static void dump_rbufs(struct slgt_info *info) | |
585 | { | |
586 | int i; | |
587 | printk("rbuf_current=%d\n", info->rbuf_current); | |
588 | for (i=0 ; i < info->rbuf_count ; i++) { | |
589 | printk("%d: count=%04X status=%04X\n", | |
590 | i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); | |
591 | } | |
592 | } | |
593 | #else | |
594 | #define DBGRBUF(info) | |
595 | #endif | |
596 | ||
597 | static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) | |
598 | { | |
599 | #ifdef SANITY_CHECK | |
600 | if (!info) { | |
601 | printk("null struct slgt_info for (%s) in %s\n", devname, name); | |
602 | return 1; | |
603 | } | |
604 | if (info->magic != MGSL_MAGIC) { | |
605 | printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); | |
606 | return 1; | |
607 | } | |
608 | #else | |
609 | if (!info) | |
610 | return 1; | |
611 | #endif | |
612 | return 0; | |
613 | } | |
614 | ||
615 | /** | |
616 | * line discipline callback wrappers | |
617 | * | |
618 | * The wrappers maintain line discipline references | |
619 | * while calling into the line discipline. | |
620 | * | |
621 | * ldisc_receive_buf - pass receive data to line discipline | |
622 | */ | |
623 | static void ldisc_receive_buf(struct tty_struct *tty, | |
624 | const __u8 *data, char *flags, int count) | |
625 | { | |
626 | struct tty_ldisc *ld; | |
627 | if (!tty) | |
628 | return; | |
629 | ld = tty_ldisc_ref(tty); | |
630 | if (ld) { | |
a352def2 AC |
631 | if (ld->ops->receive_buf) |
632 | ld->ops->receive_buf(tty, data, flags, count); | |
705b6c7b PF |
633 | tty_ldisc_deref(ld); |
634 | } | |
635 | } | |
636 | ||
637 | /* tty callbacks */ | |
638 | ||
639 | static int open(struct tty_struct *tty, struct file *filp) | |
640 | { | |
641 | struct slgt_info *info; | |
642 | int retval, line; | |
643 | unsigned long flags; | |
644 | ||
645 | line = tty->index; | |
646 | if ((line < 0) || (line >= slgt_device_count)) { | |
647 | DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); | |
648 | return -ENODEV; | |
649 | } | |
650 | ||
651 | info = slgt_device_list; | |
652 | while(info && info->line != line) | |
653 | info = info->next_device; | |
654 | if (sanity_check(info, tty->name, "open")) | |
655 | return -ENODEV; | |
656 | if (info->init_error) { | |
657 | DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); | |
658 | return -ENODEV; | |
659 | } | |
660 | ||
661 | tty->driver_data = info; | |
8fb06c77 | 662 | info->port.tty = tty; |
705b6c7b | 663 | |
8fb06c77 | 664 | DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); |
705b6c7b PF |
665 | |
666 | /* If port is closing, signal caller to try again */ | |
8fb06c77 AC |
667 | if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){ |
668 | if (info->port.flags & ASYNC_CLOSING) | |
669 | interruptible_sleep_on(&info->port.close_wait); | |
670 | retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ? | |
705b6c7b PF |
671 | -EAGAIN : -ERESTARTSYS); |
672 | goto cleanup; | |
673 | } | |
674 | ||
8fb06c77 | 675 | info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
705b6c7b PF |
676 | |
677 | spin_lock_irqsave(&info->netlock, flags); | |
678 | if (info->netcount) { | |
679 | retval = -EBUSY; | |
680 | spin_unlock_irqrestore(&info->netlock, flags); | |
681 | goto cleanup; | |
682 | } | |
8fb06c77 | 683 | info->port.count++; |
705b6c7b PF |
684 | spin_unlock_irqrestore(&info->netlock, flags); |
685 | ||
8fb06c77 | 686 | if (info->port.count == 1) { |
705b6c7b PF |
687 | /* 1st open on this device, init hardware */ |
688 | retval = startup(info); | |
689 | if (retval < 0) | |
690 | goto cleanup; | |
691 | } | |
692 | ||
693 | retval = block_til_ready(tty, filp, info); | |
694 | if (retval) { | |
695 | DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); | |
696 | goto cleanup; | |
697 | } | |
698 | ||
699 | retval = 0; | |
700 | ||
701 | cleanup: | |
702 | if (retval) { | |
703 | if (tty->count == 1) | |
8fb06c77 AC |
704 | info->port.tty = NULL; /* tty layer will release tty struct */ |
705 | if(info->port.count) | |
706 | info->port.count--; | |
705b6c7b PF |
707 | } |
708 | ||
709 | DBGINFO(("%s open rc=%d\n", info->device_name, retval)); | |
710 | return retval; | |
711 | } | |
712 | ||
713 | static void close(struct tty_struct *tty, struct file *filp) | |
714 | { | |
715 | struct slgt_info *info = tty->driver_data; | |
716 | ||
717 | if (sanity_check(info, tty->name, "close")) | |
718 | return; | |
8fb06c77 | 719 | DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); |
705b6c7b | 720 | |
a6614999 | 721 | if (tty_port_close_start(&info->port, tty, filp) == 0) |
705b6c7b PF |
722 | goto cleanup; |
723 | ||
8fb06c77 | 724 | if (info->port.flags & ASYNC_INITIALIZED) |
705b6c7b | 725 | wait_until_sent(tty, info->timeout); |
978e595f | 726 | flush_buffer(tty); |
705b6c7b PF |
727 | tty_ldisc_flush(tty); |
728 | ||
729 | shutdown(info); | |
730 | ||
a6614999 | 731 | tty_port_close_end(&info->port, tty); |
8fb06c77 | 732 | info->port.tty = NULL; |
705b6c7b | 733 | cleanup: |
8fb06c77 | 734 | DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); |
705b6c7b PF |
735 | } |
736 | ||
737 | static void hangup(struct tty_struct *tty) | |
738 | { | |
739 | struct slgt_info *info = tty->driver_data; | |
740 | ||
741 | if (sanity_check(info, tty->name, "hangup")) | |
742 | return; | |
743 | DBGINFO(("%s hangup\n", info->device_name)); | |
744 | ||
745 | flush_buffer(tty); | |
746 | shutdown(info); | |
747 | ||
8fb06c77 AC |
748 | info->port.count = 0; |
749 | info->port.flags &= ~ASYNC_NORMAL_ACTIVE; | |
750 | info->port.tty = NULL; | |
705b6c7b | 751 | |
8fb06c77 | 752 | wake_up_interruptible(&info->port.open_wait); |
705b6c7b PF |
753 | } |
754 | ||
606d099c | 755 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
705b6c7b PF |
756 | { |
757 | struct slgt_info *info = tty->driver_data; | |
758 | unsigned long flags; | |
759 | ||
760 | DBGINFO(("%s set_termios\n", tty->driver->name)); | |
761 | ||
705b6c7b PF |
762 | change_params(info); |
763 | ||
764 | /* Handle transition to B0 status */ | |
765 | if (old_termios->c_cflag & CBAUD && | |
766 | !(tty->termios->c_cflag & CBAUD)) { | |
767 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
768 | spin_lock_irqsave(&info->lock,flags); | |
769 | set_signals(info); | |
770 | spin_unlock_irqrestore(&info->lock,flags); | |
771 | } | |
772 | ||
773 | /* Handle transition away from B0 status */ | |
774 | if (!(old_termios->c_cflag & CBAUD) && | |
775 | tty->termios->c_cflag & CBAUD) { | |
776 | info->signals |= SerialSignal_DTR; | |
777 | if (!(tty->termios->c_cflag & CRTSCTS) || | |
778 | !test_bit(TTY_THROTTLED, &tty->flags)) { | |
779 | info->signals |= SerialSignal_RTS; | |
780 | } | |
781 | spin_lock_irqsave(&info->lock,flags); | |
782 | set_signals(info); | |
783 | spin_unlock_irqrestore(&info->lock,flags); | |
784 | } | |
785 | ||
786 | /* Handle turning off CRTSCTS */ | |
787 | if (old_termios->c_cflag & CRTSCTS && | |
788 | !(tty->termios->c_cflag & CRTSCTS)) { | |
789 | tty->hw_stopped = 0; | |
790 | tx_release(tty); | |
791 | } | |
792 | } | |
793 | ||
794 | static int write(struct tty_struct *tty, | |
795 | const unsigned char *buf, int count) | |
796 | { | |
797 | int ret = 0; | |
798 | struct slgt_info *info = tty->driver_data; | |
799 | unsigned long flags; | |
8a38c285 | 800 | unsigned int bufs_needed; |
705b6c7b PF |
801 | |
802 | if (sanity_check(info, tty->name, "write")) | |
803 | goto cleanup; | |
804 | DBGINFO(("%s write count=%d\n", info->device_name, count)); | |
805 | ||
326f28e9 | 806 | if (!info->tx_buf) |
705b6c7b PF |
807 | goto cleanup; |
808 | ||
809 | if (count > info->max_frame_size) { | |
810 | ret = -EIO; | |
811 | goto cleanup; | |
812 | } | |
813 | ||
814 | if (!count) | |
815 | goto cleanup; | |
816 | ||
8a38c285 PF |
817 | if (!info->tx_active && info->tx_count) { |
818 | /* send accumulated data from send_char() */ | |
819 | tx_load(info, info->tx_buf, info->tx_count); | |
820 | goto start; | |
705b6c7b | 821 | } |
8a38c285 PF |
822 | bufs_needed = (count/DMABUFSIZE); |
823 | if (count % DMABUFSIZE) | |
824 | ++bufs_needed; | |
825 | if (bufs_needed > free_tbuf_count(info)) | |
826 | goto cleanup; | |
705b6c7b PF |
827 | |
828 | ret = info->tx_count = count; | |
829 | tx_load(info, buf, count); | |
830 | goto start; | |
831 | ||
832 | start: | |
833 | if (info->tx_count && !tty->stopped && !tty->hw_stopped) { | |
834 | spin_lock_irqsave(&info->lock,flags); | |
835 | if (!info->tx_active) | |
836 | tx_start(info); | |
bb029c67 PF |
837 | else |
838 | tdma_start(info); | |
705b6c7b PF |
839 | spin_unlock_irqrestore(&info->lock,flags); |
840 | } | |
841 | ||
842 | cleanup: | |
843 | DBGINFO(("%s write rc=%d\n", info->device_name, ret)); | |
844 | return ret; | |
845 | } | |
846 | ||
55da7789 | 847 | static int put_char(struct tty_struct *tty, unsigned char ch) |
705b6c7b PF |
848 | { |
849 | struct slgt_info *info = tty->driver_data; | |
850 | unsigned long flags; | |
6c82c415 | 851 | int ret = 0; |
705b6c7b PF |
852 | |
853 | if (sanity_check(info, tty->name, "put_char")) | |
55da7789 | 854 | return 0; |
705b6c7b | 855 | DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); |
326f28e9 | 856 | if (!info->tx_buf) |
55da7789 | 857 | return 0; |
705b6c7b | 858 | spin_lock_irqsave(&info->lock,flags); |
55da7789 | 859 | if (!info->tx_active && (info->tx_count < info->max_frame_size)) { |
705b6c7b | 860 | info->tx_buf[info->tx_count++] = ch; |
55da7789 AC |
861 | ret = 1; |
862 | } | |
705b6c7b | 863 | spin_unlock_irqrestore(&info->lock,flags); |
55da7789 | 864 | return ret; |
705b6c7b PF |
865 | } |
866 | ||
867 | static void send_xchar(struct tty_struct *tty, char ch) | |
868 | { | |
869 | struct slgt_info *info = tty->driver_data; | |
870 | unsigned long flags; | |
871 | ||
872 | if (sanity_check(info, tty->name, "send_xchar")) | |
873 | return; | |
874 | DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); | |
875 | info->x_char = ch; | |
876 | if (ch) { | |
877 | spin_lock_irqsave(&info->lock,flags); | |
878 | if (!info->tx_enabled) | |
879 | tx_start(info); | |
880 | spin_unlock_irqrestore(&info->lock,flags); | |
881 | } | |
882 | } | |
883 | ||
884 | static void wait_until_sent(struct tty_struct *tty, int timeout) | |
885 | { | |
886 | struct slgt_info *info = tty->driver_data; | |
887 | unsigned long orig_jiffies, char_time; | |
888 | ||
889 | if (!info ) | |
890 | return; | |
891 | if (sanity_check(info, tty->name, "wait_until_sent")) | |
892 | return; | |
893 | DBGINFO(("%s wait_until_sent entry\n", info->device_name)); | |
8fb06c77 | 894 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
705b6c7b PF |
895 | goto exit; |
896 | ||
897 | orig_jiffies = jiffies; | |
898 | ||
899 | /* Set check interval to 1/5 of estimated time to | |
900 | * send a character, and make it at least 1. The check | |
901 | * interval should also be less than the timeout. | |
902 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
903 | */ | |
904 | ||
978e595f AC |
905 | lock_kernel(); |
906 | ||
705b6c7b PF |
907 | if (info->params.data_rate) { |
908 | char_time = info->timeout/(32 * 5); | |
909 | if (!char_time) | |
910 | char_time++; | |
911 | } else | |
912 | char_time = 1; | |
913 | ||
914 | if (timeout) | |
915 | char_time = min_t(unsigned long, char_time, timeout); | |
916 | ||
917 | while (info->tx_active) { | |
918 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
919 | if (signal_pending(current)) | |
920 | break; | |
921 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
922 | break; | |
923 | } | |
978e595f | 924 | unlock_kernel(); |
705b6c7b PF |
925 | |
926 | exit: | |
927 | DBGINFO(("%s wait_until_sent exit\n", info->device_name)); | |
928 | } | |
929 | ||
930 | static int write_room(struct tty_struct *tty) | |
931 | { | |
932 | struct slgt_info *info = tty->driver_data; | |
933 | int ret; | |
934 | ||
935 | if (sanity_check(info, tty->name, "write_room")) | |
936 | return 0; | |
937 | ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; | |
938 | DBGINFO(("%s write_room=%d\n", info->device_name, ret)); | |
939 | return ret; | |
940 | } | |
941 | ||
942 | static void flush_chars(struct tty_struct *tty) | |
943 | { | |
944 | struct slgt_info *info = tty->driver_data; | |
945 | unsigned long flags; | |
946 | ||
947 | if (sanity_check(info, tty->name, "flush_chars")) | |
948 | return; | |
949 | DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); | |
950 | ||
951 | if (info->tx_count <= 0 || tty->stopped || | |
952 | tty->hw_stopped || !info->tx_buf) | |
953 | return; | |
954 | ||
955 | DBGINFO(("%s flush_chars start transmit\n", info->device_name)); | |
956 | ||
957 | spin_lock_irqsave(&info->lock,flags); | |
958 | if (!info->tx_active && info->tx_count) { | |
959 | tx_load(info, info->tx_buf,info->tx_count); | |
960 | tx_start(info); | |
961 | } | |
962 | spin_unlock_irqrestore(&info->lock,flags); | |
963 | } | |
964 | ||
965 | static void flush_buffer(struct tty_struct *tty) | |
966 | { | |
967 | struct slgt_info *info = tty->driver_data; | |
968 | unsigned long flags; | |
969 | ||
970 | if (sanity_check(info, tty->name, "flush_buffer")) | |
971 | return; | |
972 | DBGINFO(("%s flush_buffer\n", info->device_name)); | |
973 | ||
974 | spin_lock_irqsave(&info->lock,flags); | |
975 | if (!info->tx_active) | |
976 | info->tx_count = 0; | |
977 | spin_unlock_irqrestore(&info->lock,flags); | |
978 | ||
705b6c7b PF |
979 | tty_wakeup(tty); |
980 | } | |
981 | ||
982 | /* | |
983 | * throttle (stop) transmitter | |
984 | */ | |
985 | static void tx_hold(struct tty_struct *tty) | |
986 | { | |
987 | struct slgt_info *info = tty->driver_data; | |
988 | unsigned long flags; | |
989 | ||
990 | if (sanity_check(info, tty->name, "tx_hold")) | |
991 | return; | |
992 | DBGINFO(("%s tx_hold\n", info->device_name)); | |
993 | spin_lock_irqsave(&info->lock,flags); | |
994 | if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) | |
995 | tx_stop(info); | |
996 | spin_unlock_irqrestore(&info->lock,flags); | |
997 | } | |
998 | ||
999 | /* | |
1000 | * release (start) transmitter | |
1001 | */ | |
1002 | static void tx_release(struct tty_struct *tty) | |
1003 | { | |
1004 | struct slgt_info *info = tty->driver_data; | |
1005 | unsigned long flags; | |
1006 | ||
1007 | if (sanity_check(info, tty->name, "tx_release")) | |
1008 | return; | |
1009 | DBGINFO(("%s tx_release\n", info->device_name)); | |
1010 | spin_lock_irqsave(&info->lock,flags); | |
1011 | if (!info->tx_active && info->tx_count) { | |
1012 | tx_load(info, info->tx_buf, info->tx_count); | |
1013 | tx_start(info); | |
1014 | } | |
1015 | spin_unlock_irqrestore(&info->lock,flags); | |
1016 | } | |
1017 | ||
1018 | /* | |
1019 | * Service an IOCTL request | |
1020 | * | |
1021 | * Arguments | |
1022 | * | |
1023 | * tty pointer to tty instance data | |
1024 | * file pointer to associated file object for device | |
1025 | * cmd IOCTL command code | |
1026 | * arg command argument/context | |
1027 | * | |
1028 | * Return 0 if success, otherwise error code | |
1029 | */ | |
1030 | static int ioctl(struct tty_struct *tty, struct file *file, | |
1031 | unsigned int cmd, unsigned long arg) | |
1032 | { | |
1033 | struct slgt_info *info = tty->driver_data; | |
1034 | struct mgsl_icount cnow; /* kernel counter temps */ | |
1035 | struct serial_icounter_struct __user *p_cuser; /* user space */ | |
1036 | unsigned long flags; | |
1037 | void __user *argp = (void __user *)arg; | |
1f8cabb7 | 1038 | int ret; |
705b6c7b PF |
1039 | |
1040 | if (sanity_check(info, tty->name, "ioctl")) | |
1041 | return -ENODEV; | |
1042 | DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1043 | ||
1044 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
1045 | (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { | |
1046 | if (tty->flags & (1 << TTY_IO_ERROR)) | |
1047 | return -EIO; | |
1048 | } | |
1049 | ||
1f8cabb7 AC |
1050 | lock_kernel(); |
1051 | ||
705b6c7b PF |
1052 | switch (cmd) { |
1053 | case MGSL_IOCGPARAMS: | |
1f8cabb7 AC |
1054 | ret = get_params(info, argp); |
1055 | break; | |
705b6c7b | 1056 | case MGSL_IOCSPARAMS: |
1f8cabb7 AC |
1057 | ret = set_params(info, argp); |
1058 | break; | |
705b6c7b | 1059 | case MGSL_IOCGTXIDLE: |
1f8cabb7 AC |
1060 | ret = get_txidle(info, argp); |
1061 | break; | |
705b6c7b | 1062 | case MGSL_IOCSTXIDLE: |
1f8cabb7 AC |
1063 | ret = set_txidle(info, (int)arg); |
1064 | break; | |
705b6c7b | 1065 | case MGSL_IOCTXENABLE: |
1f8cabb7 AC |
1066 | ret = tx_enable(info, (int)arg); |
1067 | break; | |
705b6c7b | 1068 | case MGSL_IOCRXENABLE: |
1f8cabb7 AC |
1069 | ret = rx_enable(info, (int)arg); |
1070 | break; | |
705b6c7b | 1071 | case MGSL_IOCTXABORT: |
1f8cabb7 AC |
1072 | ret = tx_abort(info); |
1073 | break; | |
705b6c7b | 1074 | case MGSL_IOCGSTATS: |
1f8cabb7 AC |
1075 | ret = get_stats(info, argp); |
1076 | break; | |
705b6c7b | 1077 | case MGSL_IOCWAITEVENT: |
1f8cabb7 AC |
1078 | ret = wait_mgsl_event(info, argp); |
1079 | break; | |
705b6c7b | 1080 | case TIOCMIWAIT: |
1f8cabb7 AC |
1081 | ret = modem_input_wait(info,(int)arg); |
1082 | break; | |
705b6c7b | 1083 | case MGSL_IOCGIF: |
1f8cabb7 AC |
1084 | ret = get_interface(info, argp); |
1085 | break; | |
705b6c7b | 1086 | case MGSL_IOCSIF: |
1f8cabb7 AC |
1087 | ret = set_interface(info,(int)arg); |
1088 | break; | |
0080b7aa | 1089 | case MGSL_IOCSGPIO: |
1f8cabb7 AC |
1090 | ret = set_gpio(info, argp); |
1091 | break; | |
0080b7aa | 1092 | case MGSL_IOCGGPIO: |
1f8cabb7 AC |
1093 | ret = get_gpio(info, argp); |
1094 | break; | |
0080b7aa | 1095 | case MGSL_IOCWAITGPIO: |
1f8cabb7 AC |
1096 | ret = wait_gpio(info, argp); |
1097 | break; | |
705b6c7b PF |
1098 | case TIOCGICOUNT: |
1099 | spin_lock_irqsave(&info->lock,flags); | |
1100 | cnow = info->icount; | |
1101 | spin_unlock_irqrestore(&info->lock,flags); | |
1102 | p_cuser = argp; | |
1103 | if (put_user(cnow.cts, &p_cuser->cts) || | |
1104 | put_user(cnow.dsr, &p_cuser->dsr) || | |
1105 | put_user(cnow.rng, &p_cuser->rng) || | |
1106 | put_user(cnow.dcd, &p_cuser->dcd) || | |
1107 | put_user(cnow.rx, &p_cuser->rx) || | |
1108 | put_user(cnow.tx, &p_cuser->tx) || | |
1109 | put_user(cnow.frame, &p_cuser->frame) || | |
1110 | put_user(cnow.overrun, &p_cuser->overrun) || | |
1111 | put_user(cnow.parity, &p_cuser->parity) || | |
1112 | put_user(cnow.brk, &p_cuser->brk) || | |
1113 | put_user(cnow.buf_overrun, &p_cuser->buf_overrun)) | |
1f8cabb7 AC |
1114 | ret = -EFAULT; |
1115 | ret = 0; | |
1116 | break; | |
705b6c7b | 1117 | default: |
1f8cabb7 | 1118 | ret = -ENOIOCTLCMD; |
705b6c7b | 1119 | } |
1f8cabb7 AC |
1120 | unlock_kernel(); |
1121 | return ret; | |
705b6c7b PF |
1122 | } |
1123 | ||
2acdb169 PF |
1124 | /* |
1125 | * support for 32 bit ioctl calls on 64 bit systems | |
1126 | */ | |
1127 | #ifdef CONFIG_COMPAT | |
1128 | static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) | |
1129 | { | |
1130 | struct MGSL_PARAMS32 tmp_params; | |
1131 | ||
1132 | DBGINFO(("%s get_params32\n", info->device_name)); | |
1133 | tmp_params.mode = (compat_ulong_t)info->params.mode; | |
1134 | tmp_params.loopback = info->params.loopback; | |
1135 | tmp_params.flags = info->params.flags; | |
1136 | tmp_params.encoding = info->params.encoding; | |
1137 | tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; | |
1138 | tmp_params.addr_filter = info->params.addr_filter; | |
1139 | tmp_params.crc_type = info->params.crc_type; | |
1140 | tmp_params.preamble_length = info->params.preamble_length; | |
1141 | tmp_params.preamble = info->params.preamble; | |
1142 | tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; | |
1143 | tmp_params.data_bits = info->params.data_bits; | |
1144 | tmp_params.stop_bits = info->params.stop_bits; | |
1145 | tmp_params.parity = info->params.parity; | |
1146 | if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) | |
1147 | return -EFAULT; | |
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) | |
1152 | { | |
1153 | struct MGSL_PARAMS32 tmp_params; | |
1154 | ||
1155 | DBGINFO(("%s set_params32\n", info->device_name)); | |
1156 | if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) | |
1157 | return -EFAULT; | |
1158 | ||
1159 | spin_lock(&info->lock); | |
1f80769f PF |
1160 | if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { |
1161 | info->base_clock = tmp_params.clock_speed; | |
1162 | } else { | |
1163 | info->params.mode = tmp_params.mode; | |
1164 | info->params.loopback = tmp_params.loopback; | |
1165 | info->params.flags = tmp_params.flags; | |
1166 | info->params.encoding = tmp_params.encoding; | |
1167 | info->params.clock_speed = tmp_params.clock_speed; | |
1168 | info->params.addr_filter = tmp_params.addr_filter; | |
1169 | info->params.crc_type = tmp_params.crc_type; | |
1170 | info->params.preamble_length = tmp_params.preamble_length; | |
1171 | info->params.preamble = tmp_params.preamble; | |
1172 | info->params.data_rate = tmp_params.data_rate; | |
1173 | info->params.data_bits = tmp_params.data_bits; | |
1174 | info->params.stop_bits = tmp_params.stop_bits; | |
1175 | info->params.parity = tmp_params.parity; | |
1176 | } | |
2acdb169 PF |
1177 | spin_unlock(&info->lock); |
1178 | ||
1f80769f | 1179 | program_hw(info); |
2acdb169 PF |
1180 | |
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file, | |
1185 | unsigned int cmd, unsigned long arg) | |
1186 | { | |
1187 | struct slgt_info *info = tty->driver_data; | |
1188 | int rc = -ENOIOCTLCMD; | |
1189 | ||
1190 | if (sanity_check(info, tty->name, "compat_ioctl")) | |
1191 | return -ENODEV; | |
1192 | DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); | |
1193 | ||
1194 | switch (cmd) { | |
1195 | ||
1196 | case MGSL_IOCSPARAMS32: | |
1197 | rc = set_params32(info, compat_ptr(arg)); | |
1198 | break; | |
1199 | ||
1200 | case MGSL_IOCGPARAMS32: | |
1201 | rc = get_params32(info, compat_ptr(arg)); | |
1202 | break; | |
1203 | ||
1204 | case MGSL_IOCGPARAMS: | |
1205 | case MGSL_IOCSPARAMS: | |
1206 | case MGSL_IOCGTXIDLE: | |
1207 | case MGSL_IOCGSTATS: | |
1208 | case MGSL_IOCWAITEVENT: | |
1209 | case MGSL_IOCGIF: | |
1210 | case MGSL_IOCSGPIO: | |
1211 | case MGSL_IOCGGPIO: | |
1212 | case MGSL_IOCWAITGPIO: | |
1213 | case TIOCGICOUNT: | |
1214 | rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg))); | |
1215 | break; | |
1216 | ||
1217 | case MGSL_IOCSTXIDLE: | |
1218 | case MGSL_IOCTXENABLE: | |
1219 | case MGSL_IOCRXENABLE: | |
1220 | case MGSL_IOCTXABORT: | |
1221 | case TIOCMIWAIT: | |
1222 | case MGSL_IOCSIF: | |
1223 | rc = ioctl(tty, file, cmd, arg); | |
1224 | break; | |
1225 | } | |
1226 | ||
1227 | DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); | |
1228 | return rc; | |
1229 | } | |
1230 | #else | |
1231 | #define slgt_compat_ioctl NULL | |
1232 | #endif /* ifdef CONFIG_COMPAT */ | |
1233 | ||
705b6c7b PF |
1234 | /* |
1235 | * proc fs support | |
1236 | */ | |
a18c56e5 | 1237 | static inline void line_info(struct seq_file *m, struct slgt_info *info) |
705b6c7b PF |
1238 | { |
1239 | char stat_buf[30]; | |
705b6c7b PF |
1240 | unsigned long flags; |
1241 | ||
a18c56e5 | 1242 | seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", |
705b6c7b PF |
1243 | info->device_name, info->phys_reg_addr, |
1244 | info->irq_level, info->max_frame_size); | |
1245 | ||
1246 | /* output current serial signal states */ | |
1247 | spin_lock_irqsave(&info->lock,flags); | |
1248 | get_signals(info); | |
1249 | spin_unlock_irqrestore(&info->lock,flags); | |
1250 | ||
1251 | stat_buf[0] = 0; | |
1252 | stat_buf[1] = 0; | |
1253 | if (info->signals & SerialSignal_RTS) | |
1254 | strcat(stat_buf, "|RTS"); | |
1255 | if (info->signals & SerialSignal_CTS) | |
1256 | strcat(stat_buf, "|CTS"); | |
1257 | if (info->signals & SerialSignal_DTR) | |
1258 | strcat(stat_buf, "|DTR"); | |
1259 | if (info->signals & SerialSignal_DSR) | |
1260 | strcat(stat_buf, "|DSR"); | |
1261 | if (info->signals & SerialSignal_DCD) | |
1262 | strcat(stat_buf, "|CD"); | |
1263 | if (info->signals & SerialSignal_RI) | |
1264 | strcat(stat_buf, "|RI"); | |
1265 | ||
1266 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
a18c56e5 | 1267 | seq_printf(m, "\tHDLC txok:%d rxok:%d", |
705b6c7b PF |
1268 | info->icount.txok, info->icount.rxok); |
1269 | if (info->icount.txunder) | |
a18c56e5 | 1270 | seq_printf(m, " txunder:%d", info->icount.txunder); |
705b6c7b | 1271 | if (info->icount.txabort) |
a18c56e5 | 1272 | seq_printf(m, " txabort:%d", info->icount.txabort); |
705b6c7b | 1273 | if (info->icount.rxshort) |
a18c56e5 | 1274 | seq_printf(m, " rxshort:%d", info->icount.rxshort); |
705b6c7b | 1275 | if (info->icount.rxlong) |
a18c56e5 | 1276 | seq_printf(m, " rxlong:%d", info->icount.rxlong); |
705b6c7b | 1277 | if (info->icount.rxover) |
a18c56e5 | 1278 | seq_printf(m, " rxover:%d", info->icount.rxover); |
705b6c7b | 1279 | if (info->icount.rxcrc) |
a18c56e5 | 1280 | seq_printf(m, " rxcrc:%d", info->icount.rxcrc); |
705b6c7b | 1281 | } else { |
a18c56e5 | 1282 | seq_printf(m, "\tASYNC tx:%d rx:%d", |
705b6c7b PF |
1283 | info->icount.tx, info->icount.rx); |
1284 | if (info->icount.frame) | |
a18c56e5 | 1285 | seq_printf(m, " fe:%d", info->icount.frame); |
705b6c7b | 1286 | if (info->icount.parity) |
a18c56e5 | 1287 | seq_printf(m, " pe:%d", info->icount.parity); |
705b6c7b | 1288 | if (info->icount.brk) |
a18c56e5 | 1289 | seq_printf(m, " brk:%d", info->icount.brk); |
705b6c7b | 1290 | if (info->icount.overrun) |
a18c56e5 | 1291 | seq_printf(m, " oe:%d", info->icount.overrun); |
705b6c7b PF |
1292 | } |
1293 | ||
1294 | /* Append serial signal status to end */ | |
a18c56e5 | 1295 | seq_printf(m, " %s\n", stat_buf+1); |
705b6c7b | 1296 | |
a18c56e5 | 1297 | seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", |
705b6c7b PF |
1298 | info->tx_active,info->bh_requested,info->bh_running, |
1299 | info->pending_bh); | |
705b6c7b PF |
1300 | } |
1301 | ||
1302 | /* Called to print information about devices | |
1303 | */ | |
a18c56e5 | 1304 | static int synclink_gt_proc_show(struct seq_file *m, void *v) |
705b6c7b | 1305 | { |
705b6c7b PF |
1306 | struct slgt_info *info; |
1307 | ||
a18c56e5 | 1308 | seq_puts(m, "synclink_gt driver\n"); |
705b6c7b PF |
1309 | |
1310 | info = slgt_device_list; | |
1311 | while( info ) { | |
a18c56e5 | 1312 | line_info(m, info); |
705b6c7b PF |
1313 | info = info->next_device; |
1314 | } | |
a18c56e5 AD |
1315 | return 0; |
1316 | } | |
705b6c7b | 1317 | |
a18c56e5 AD |
1318 | static int synclink_gt_proc_open(struct inode *inode, struct file *file) |
1319 | { | |
1320 | return single_open(file, synclink_gt_proc_show, NULL); | |
705b6c7b PF |
1321 | } |
1322 | ||
a18c56e5 AD |
1323 | static const struct file_operations synclink_gt_proc_fops = { |
1324 | .owner = THIS_MODULE, | |
1325 | .open = synclink_gt_proc_open, | |
1326 | .read = seq_read, | |
1327 | .llseek = seq_lseek, | |
1328 | .release = single_release, | |
1329 | }; | |
1330 | ||
705b6c7b PF |
1331 | /* |
1332 | * return count of bytes in transmit buffer | |
1333 | */ | |
1334 | static int chars_in_buffer(struct tty_struct *tty) | |
1335 | { | |
1336 | struct slgt_info *info = tty->driver_data; | |
403214d0 | 1337 | int count; |
705b6c7b PF |
1338 | if (sanity_check(info, tty->name, "chars_in_buffer")) |
1339 | return 0; | |
403214d0 PF |
1340 | count = tbuf_bytes(info); |
1341 | DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count)); | |
1342 | return count; | |
705b6c7b PF |
1343 | } |
1344 | ||
1345 | /* | |
1346 | * signal remote device to throttle send data (our receive data) | |
1347 | */ | |
1348 | static void throttle(struct tty_struct * tty) | |
1349 | { | |
1350 | struct slgt_info *info = tty->driver_data; | |
1351 | unsigned long flags; | |
1352 | ||
1353 | if (sanity_check(info, tty->name, "throttle")) | |
1354 | return; | |
1355 | DBGINFO(("%s throttle\n", info->device_name)); | |
1356 | if (I_IXOFF(tty)) | |
1357 | send_xchar(tty, STOP_CHAR(tty)); | |
1358 | if (tty->termios->c_cflag & CRTSCTS) { | |
1359 | spin_lock_irqsave(&info->lock,flags); | |
1360 | info->signals &= ~SerialSignal_RTS; | |
1361 | set_signals(info); | |
1362 | spin_unlock_irqrestore(&info->lock,flags); | |
1363 | } | |
1364 | } | |
1365 | ||
1366 | /* | |
1367 | * signal remote device to stop throttling send data (our receive data) | |
1368 | */ | |
1369 | static void unthrottle(struct tty_struct * tty) | |
1370 | { | |
1371 | struct slgt_info *info = tty->driver_data; | |
1372 | unsigned long flags; | |
1373 | ||
1374 | if (sanity_check(info, tty->name, "unthrottle")) | |
1375 | return; | |
1376 | DBGINFO(("%s unthrottle\n", info->device_name)); | |
1377 | if (I_IXOFF(tty)) { | |
1378 | if (info->x_char) | |
1379 | info->x_char = 0; | |
1380 | else | |
1381 | send_xchar(tty, START_CHAR(tty)); | |
1382 | } | |
1383 | if (tty->termios->c_cflag & CRTSCTS) { | |
1384 | spin_lock_irqsave(&info->lock,flags); | |
1385 | info->signals |= SerialSignal_RTS; | |
1386 | set_signals(info); | |
1387 | spin_unlock_irqrestore(&info->lock,flags); | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | /* | |
1392 | * set or clear transmit break condition | |
1393 | * break_state -1=set break condition, 0=clear | |
1394 | */ | |
9e98966c | 1395 | static int set_break(struct tty_struct *tty, int break_state) |
705b6c7b PF |
1396 | { |
1397 | struct slgt_info *info = tty->driver_data; | |
1398 | unsigned short value; | |
1399 | unsigned long flags; | |
1400 | ||
1401 | if (sanity_check(info, tty->name, "set_break")) | |
9e98966c | 1402 | return -EINVAL; |
705b6c7b PF |
1403 | DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); |
1404 | ||
1405 | spin_lock_irqsave(&info->lock,flags); | |
1406 | value = rd_reg16(info, TCR); | |
1407 | if (break_state == -1) | |
1408 | value |= BIT6; | |
1409 | else | |
1410 | value &= ~BIT6; | |
1411 | wr_reg16(info, TCR, value); | |
1412 | spin_unlock_irqrestore(&info->lock,flags); | |
9e98966c | 1413 | return 0; |
705b6c7b PF |
1414 | } |
1415 | ||
af69c7f9 | 1416 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
1417 | |
1418 | /** | |
1419 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
1420 | * set encoding and frame check sequence (FCS) options | |
1421 | * | |
1422 | * dev pointer to network device structure | |
1423 | * encoding serial encoding setting | |
1424 | * parity FCS setting | |
1425 | * | |
1426 | * returns 0 if success, otherwise error code | |
1427 | */ | |
1428 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
1429 | unsigned short parity) | |
1430 | { | |
1431 | struct slgt_info *info = dev_to_port(dev); | |
1432 | unsigned char new_encoding; | |
1433 | unsigned short new_crctype; | |
1434 | ||
1435 | /* return error if TTY interface open */ | |
8fb06c77 | 1436 | if (info->port.count) |
705b6c7b PF |
1437 | return -EBUSY; |
1438 | ||
1439 | DBGINFO(("%s hdlcdev_attach\n", info->device_name)); | |
1440 | ||
1441 | switch (encoding) | |
1442 | { | |
1443 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
1444 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
1445 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
1446 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
1447 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
1448 | default: return -EINVAL; | |
1449 | } | |
1450 | ||
1451 | switch (parity) | |
1452 | { | |
1453 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
1454 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
1455 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
1456 | default: return -EINVAL; | |
1457 | } | |
1458 | ||
1459 | info->params.encoding = new_encoding; | |
53b3531b | 1460 | info->params.crc_type = new_crctype; |
705b6c7b PF |
1461 | |
1462 | /* if network interface up, reprogram hardware */ | |
1463 | if (info->netcount) | |
1464 | program_hw(info); | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | /** | |
1470 | * called by generic HDLC layer to send frame | |
1471 | * | |
1472 | * skb socket buffer containing HDLC frame | |
1473 | * dev pointer to network device structure | |
1474 | * | |
1475 | * returns 0 if success, otherwise error code | |
1476 | */ | |
1477 | static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev) | |
1478 | { | |
1479 | struct slgt_info *info = dev_to_port(dev); | |
705b6c7b PF |
1480 | unsigned long flags; |
1481 | ||
1482 | DBGINFO(("%s hdlc_xmit\n", dev->name)); | |
1483 | ||
1484 | /* stop sending until this frame completes */ | |
1485 | netif_stop_queue(dev); | |
1486 | ||
1487 | /* copy data to device buffers */ | |
1488 | info->tx_count = skb->len; | |
1489 | tx_load(info, skb->data, skb->len); | |
1490 | ||
1491 | /* update network statistics */ | |
198191c4 KH |
1492 | dev->stats.tx_packets++; |
1493 | dev->stats.tx_bytes += skb->len; | |
705b6c7b PF |
1494 | |
1495 | /* done with socket buffer, so free it */ | |
1496 | dev_kfree_skb(skb); | |
1497 | ||
1498 | /* save start time for transmit timeout detection */ | |
1499 | dev->trans_start = jiffies; | |
1500 | ||
1501 | /* start hardware transmitter if necessary */ | |
1502 | spin_lock_irqsave(&info->lock,flags); | |
1503 | if (!info->tx_active) | |
1504 | tx_start(info); | |
1505 | spin_unlock_irqrestore(&info->lock,flags); | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | /** | |
1511 | * called by network layer when interface enabled | |
1512 | * claim resources and initialize hardware | |
1513 | * | |
1514 | * dev pointer to network device structure | |
1515 | * | |
1516 | * returns 0 if success, otherwise error code | |
1517 | */ | |
1518 | static int hdlcdev_open(struct net_device *dev) | |
1519 | { | |
1520 | struct slgt_info *info = dev_to_port(dev); | |
1521 | int rc; | |
1522 | unsigned long flags; | |
1523 | ||
d4c63b7c PF |
1524 | if (!try_module_get(THIS_MODULE)) |
1525 | return -EBUSY; | |
1526 | ||
705b6c7b PF |
1527 | DBGINFO(("%s hdlcdev_open\n", dev->name)); |
1528 | ||
1529 | /* generic HDLC layer open processing */ | |
1530 | if ((rc = hdlc_open(dev))) | |
1531 | return rc; | |
1532 | ||
1533 | /* arbitrate between network and tty opens */ | |
1534 | spin_lock_irqsave(&info->netlock, flags); | |
8fb06c77 | 1535 | if (info->port.count != 0 || info->netcount != 0) { |
705b6c7b PF |
1536 | DBGINFO(("%s hdlc_open busy\n", dev->name)); |
1537 | spin_unlock_irqrestore(&info->netlock, flags); | |
1538 | return -EBUSY; | |
1539 | } | |
1540 | info->netcount=1; | |
1541 | spin_unlock_irqrestore(&info->netlock, flags); | |
1542 | ||
1543 | /* claim resources and init adapter */ | |
1544 | if ((rc = startup(info)) != 0) { | |
1545 | spin_lock_irqsave(&info->netlock, flags); | |
1546 | info->netcount=0; | |
1547 | spin_unlock_irqrestore(&info->netlock, flags); | |
1548 | return rc; | |
1549 | } | |
1550 | ||
1551 | /* assert DTR and RTS, apply hardware settings */ | |
1552 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
1553 | program_hw(info); | |
1554 | ||
1555 | /* enable network layer transmit */ | |
1556 | dev->trans_start = jiffies; | |
1557 | netif_start_queue(dev); | |
1558 | ||
1559 | /* inform generic HDLC layer of current DCD status */ | |
1560 | spin_lock_irqsave(&info->lock, flags); | |
1561 | get_signals(info); | |
1562 | spin_unlock_irqrestore(&info->lock, flags); | |
fbeff3c1 KH |
1563 | if (info->signals & SerialSignal_DCD) |
1564 | netif_carrier_on(dev); | |
1565 | else | |
1566 | netif_carrier_off(dev); | |
705b6c7b PF |
1567 | return 0; |
1568 | } | |
1569 | ||
1570 | /** | |
1571 | * called by network layer when interface is disabled | |
1572 | * shutdown hardware and release resources | |
1573 | * | |
1574 | * dev pointer to network device structure | |
1575 | * | |
1576 | * returns 0 if success, otherwise error code | |
1577 | */ | |
1578 | static int hdlcdev_close(struct net_device *dev) | |
1579 | { | |
1580 | struct slgt_info *info = dev_to_port(dev); | |
1581 | unsigned long flags; | |
1582 | ||
1583 | DBGINFO(("%s hdlcdev_close\n", dev->name)); | |
1584 | ||
1585 | netif_stop_queue(dev); | |
1586 | ||
1587 | /* shutdown adapter and release resources */ | |
1588 | shutdown(info); | |
1589 | ||
1590 | hdlc_close(dev); | |
1591 | ||
1592 | spin_lock_irqsave(&info->netlock, flags); | |
1593 | info->netcount=0; | |
1594 | spin_unlock_irqrestore(&info->netlock, flags); | |
1595 | ||
d4c63b7c | 1596 | module_put(THIS_MODULE); |
705b6c7b PF |
1597 | return 0; |
1598 | } | |
1599 | ||
1600 | /** | |
1601 | * called by network layer to process IOCTL call to network device | |
1602 | * | |
1603 | * dev pointer to network device structure | |
1604 | * ifr pointer to network interface request structure | |
1605 | * cmd IOCTL command code | |
1606 | * | |
1607 | * returns 0 if success, otherwise error code | |
1608 | */ | |
1609 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1610 | { | |
1611 | const size_t size = sizeof(sync_serial_settings); | |
1612 | sync_serial_settings new_line; | |
1613 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1614 | struct slgt_info *info = dev_to_port(dev); | |
1615 | unsigned int flags; | |
1616 | ||
1617 | DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); | |
1618 | ||
1619 | /* return error if TTY interface open */ | |
8fb06c77 | 1620 | if (info->port.count) |
705b6c7b PF |
1621 | return -EBUSY; |
1622 | ||
1623 | if (cmd != SIOCWANDEV) | |
1624 | return hdlc_ioctl(dev, ifr, cmd); | |
1625 | ||
1626 | switch(ifr->ifr_settings.type) { | |
1627 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
1628 | ||
1629 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1630 | if (ifr->ifr_settings.size < size) { | |
1631 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1632 | return -ENOBUFS; | |
1633 | } | |
1634 | ||
1635 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1636 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1637 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1638 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1639 | ||
1640 | switch (flags){ | |
1641 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
1642 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
1643 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
1644 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
1645 | default: new_line.clock_type = CLOCK_DEFAULT; | |
1646 | } | |
1647 | ||
1648 | new_line.clock_rate = info->params.clock_speed; | |
1649 | new_line.loopback = info->params.loopback ? 1:0; | |
1650 | ||
1651 | if (copy_to_user(line, &new_line, size)) | |
1652 | return -EFAULT; | |
1653 | return 0; | |
1654 | ||
1655 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
1656 | ||
1657 | if(!capable(CAP_NET_ADMIN)) | |
1658 | return -EPERM; | |
1659 | if (copy_from_user(&new_line, line, size)) | |
1660 | return -EFAULT; | |
1661 | ||
1662 | switch (new_line.clock_type) | |
1663 | { | |
1664 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
1665 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
1666 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
1667 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
1668 | case CLOCK_DEFAULT: flags = info->params.flags & | |
1669 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1670 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1671 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1672 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
1673 | default: return -EINVAL; | |
1674 | } | |
1675 | ||
1676 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
1677 | return -EINVAL; | |
1678 | ||
1679 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1680 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1681 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1682 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1683 | info->params.flags |= flags; | |
1684 | ||
1685 | info->params.loopback = new_line.loopback; | |
1686 | ||
1687 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
1688 | info->params.clock_speed = new_line.clock_rate; | |
1689 | else | |
1690 | info->params.clock_speed = 0; | |
1691 | ||
1692 | /* if network interface up, reprogram hardware */ | |
1693 | if (info->netcount) | |
1694 | program_hw(info); | |
1695 | return 0; | |
1696 | ||
1697 | default: | |
1698 | return hdlc_ioctl(dev, ifr, cmd); | |
1699 | } | |
1700 | } | |
1701 | ||
1702 | /** | |
1703 | * called by network layer when transmit timeout is detected | |
1704 | * | |
1705 | * dev pointer to network device structure | |
1706 | */ | |
1707 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
1708 | { | |
1709 | struct slgt_info *info = dev_to_port(dev); | |
705b6c7b PF |
1710 | unsigned long flags; |
1711 | ||
1712 | DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); | |
1713 | ||
198191c4 KH |
1714 | dev->stats.tx_errors++; |
1715 | dev->stats.tx_aborted_errors++; | |
705b6c7b PF |
1716 | |
1717 | spin_lock_irqsave(&info->lock,flags); | |
1718 | tx_stop(info); | |
1719 | spin_unlock_irqrestore(&info->lock,flags); | |
1720 | ||
1721 | netif_wake_queue(dev); | |
1722 | } | |
1723 | ||
1724 | /** | |
1725 | * called by device driver when transmit completes | |
1726 | * reenable network layer transmit if stopped | |
1727 | * | |
1728 | * info pointer to device instance information | |
1729 | */ | |
1730 | static void hdlcdev_tx_done(struct slgt_info *info) | |
1731 | { | |
1732 | if (netif_queue_stopped(info->netdev)) | |
1733 | netif_wake_queue(info->netdev); | |
1734 | } | |
1735 | ||
1736 | /** | |
1737 | * called by device driver when frame received | |
1738 | * pass frame to network layer | |
1739 | * | |
1740 | * info pointer to device instance information | |
1741 | * buf pointer to buffer contianing frame data | |
1742 | * size count of data bytes in buf | |
1743 | */ | |
1744 | static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) | |
1745 | { | |
1746 | struct sk_buff *skb = dev_alloc_skb(size); | |
1747 | struct net_device *dev = info->netdev; | |
705b6c7b PF |
1748 | |
1749 | DBGINFO(("%s hdlcdev_rx\n", dev->name)); | |
1750 | ||
1751 | if (skb == NULL) { | |
1752 | DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); | |
198191c4 | 1753 | dev->stats.rx_dropped++; |
705b6c7b PF |
1754 | return; |
1755 | } | |
1756 | ||
198191c4 | 1757 | memcpy(skb_put(skb, size), buf, size); |
705b6c7b | 1758 | |
198191c4 | 1759 | skb->protocol = hdlc_type_trans(skb, dev); |
705b6c7b | 1760 | |
198191c4 KH |
1761 | dev->stats.rx_packets++; |
1762 | dev->stats.rx_bytes += size; | |
705b6c7b PF |
1763 | |
1764 | netif_rx(skb); | |
705b6c7b PF |
1765 | } |
1766 | ||
991990a1 KH |
1767 | static const struct net_device_ops hdlcdev_ops = { |
1768 | .ndo_open = hdlcdev_open, | |
1769 | .ndo_stop = hdlcdev_close, | |
1770 | .ndo_change_mtu = hdlc_change_mtu, | |
1771 | .ndo_start_xmit = hdlc_start_xmit, | |
1772 | .ndo_do_ioctl = hdlcdev_ioctl, | |
1773 | .ndo_tx_timeout = hdlcdev_tx_timeout, | |
1774 | }; | |
1775 | ||
705b6c7b PF |
1776 | /** |
1777 | * called by device driver when adding device instance | |
1778 | * do generic HDLC initialization | |
1779 | * | |
1780 | * info pointer to device instance information | |
1781 | * | |
1782 | * returns 0 if success, otherwise error code | |
1783 | */ | |
1784 | static int hdlcdev_init(struct slgt_info *info) | |
1785 | { | |
1786 | int rc; | |
1787 | struct net_device *dev; | |
1788 | hdlc_device *hdlc; | |
1789 | ||
1790 | /* allocate and initialize network and HDLC layer objects */ | |
1791 | ||
1792 | if (!(dev = alloc_hdlcdev(info))) { | |
1793 | printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); | |
1794 | return -ENOMEM; | |
1795 | } | |
1796 | ||
1797 | /* for network layer reporting purposes only */ | |
1798 | dev->mem_start = info->phys_reg_addr; | |
1799 | dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; | |
1800 | dev->irq = info->irq_level; | |
1801 | ||
1802 | /* network layer callbacks and settings */ | |
991990a1 KH |
1803 | dev->netdev_ops = &hdlcdev_ops; |
1804 | dev->watchdog_timeo = 10 * HZ; | |
705b6c7b PF |
1805 | dev->tx_queue_len = 50; |
1806 | ||
1807 | /* generic HDLC layer callbacks and settings */ | |
1808 | hdlc = dev_to_hdlc(dev); | |
1809 | hdlc->attach = hdlcdev_attach; | |
1810 | hdlc->xmit = hdlcdev_xmit; | |
1811 | ||
1812 | /* register objects with HDLC layer */ | |
1813 | if ((rc = register_hdlc_device(dev))) { | |
1814 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); | |
1815 | free_netdev(dev); | |
1816 | return rc; | |
1817 | } | |
1818 | ||
1819 | info->netdev = dev; | |
1820 | return 0; | |
1821 | } | |
1822 | ||
1823 | /** | |
1824 | * called by device driver when removing device instance | |
1825 | * do generic HDLC cleanup | |
1826 | * | |
1827 | * info pointer to device instance information | |
1828 | */ | |
1829 | static void hdlcdev_exit(struct slgt_info *info) | |
1830 | { | |
1831 | unregister_hdlc_device(info->netdev); | |
1832 | free_netdev(info->netdev); | |
1833 | info->netdev = NULL; | |
1834 | } | |
1835 | ||
1836 | #endif /* ifdef CONFIG_HDLC */ | |
1837 | ||
1838 | /* | |
1839 | * get async data from rx DMA buffers | |
1840 | */ | |
1841 | static void rx_async(struct slgt_info *info) | |
1842 | { | |
8fb06c77 | 1843 | struct tty_struct *tty = info->port.tty; |
705b6c7b PF |
1844 | struct mgsl_icount *icount = &info->icount; |
1845 | unsigned int start, end; | |
1846 | unsigned char *p; | |
1847 | unsigned char status; | |
1848 | struct slgt_desc *bufs = info->rbufs; | |
1849 | int i, count; | |
33f0f88f AC |
1850 | int chars = 0; |
1851 | int stat; | |
1852 | unsigned char ch; | |
705b6c7b PF |
1853 | |
1854 | start = end = info->rbuf_current; | |
1855 | ||
1856 | while(desc_complete(bufs[end])) { | |
1857 | count = desc_count(bufs[end]) - info->rbuf_index; | |
1858 | p = bufs[end].buf + info->rbuf_index; | |
1859 | ||
1860 | DBGISR(("%s rx_async count=%d\n", info->device_name, count)); | |
1861 | DBGDATA(info, p, count, "rx"); | |
1862 | ||
1863 | for(i=0 ; i < count; i+=2, p+=2) { | |
33f0f88f | 1864 | ch = *p; |
705b6c7b PF |
1865 | icount->rx++; |
1866 | ||
33f0f88f AC |
1867 | stat = 0; |
1868 | ||
202af6d5 PF |
1869 | if ((status = *(p+1) & (BIT1 + BIT0))) { |
1870 | if (status & BIT1) | |
705b6c7b | 1871 | icount->parity++; |
202af6d5 | 1872 | else if (status & BIT0) |
705b6c7b PF |
1873 | icount->frame++; |
1874 | /* discard char if tty control flags say so */ | |
1875 | if (status & info->ignore_status_mask) | |
1876 | continue; | |
202af6d5 | 1877 | if (status & BIT1) |
33f0f88f | 1878 | stat = TTY_PARITY; |
202af6d5 | 1879 | else if (status & BIT0) |
33f0f88f | 1880 | stat = TTY_FRAME; |
705b6c7b PF |
1881 | } |
1882 | if (tty) { | |
33f0f88f AC |
1883 | tty_insert_flip_char(tty, ch, stat); |
1884 | chars++; | |
705b6c7b PF |
1885 | } |
1886 | } | |
1887 | ||
1888 | if (i < count) { | |
1889 | /* receive buffer not completed */ | |
1890 | info->rbuf_index += i; | |
40565f19 | 1891 | mod_timer(&info->rx_timer, jiffies + 1); |
705b6c7b PF |
1892 | break; |
1893 | } | |
1894 | ||
1895 | info->rbuf_index = 0; | |
1896 | free_rbufs(info, end, end); | |
1897 | ||
1898 | if (++end == info->rbuf_count) | |
1899 | end = 0; | |
1900 | ||
1901 | /* if entire list searched then no frame available */ | |
1902 | if (end == start) | |
1903 | break; | |
1904 | } | |
1905 | ||
33f0f88f | 1906 | if (tty && chars) |
705b6c7b PF |
1907 | tty_flip_buffer_push(tty); |
1908 | } | |
1909 | ||
1910 | /* | |
1911 | * return next bottom half action to perform | |
1912 | */ | |
1913 | static int bh_action(struct slgt_info *info) | |
1914 | { | |
1915 | unsigned long flags; | |
1916 | int rc; | |
1917 | ||
1918 | spin_lock_irqsave(&info->lock,flags); | |
1919 | ||
1920 | if (info->pending_bh & BH_RECEIVE) { | |
1921 | info->pending_bh &= ~BH_RECEIVE; | |
1922 | rc = BH_RECEIVE; | |
1923 | } else if (info->pending_bh & BH_TRANSMIT) { | |
1924 | info->pending_bh &= ~BH_TRANSMIT; | |
1925 | rc = BH_TRANSMIT; | |
1926 | } else if (info->pending_bh & BH_STATUS) { | |
1927 | info->pending_bh &= ~BH_STATUS; | |
1928 | rc = BH_STATUS; | |
1929 | } else { | |
1930 | /* Mark BH routine as complete */ | |
0fab6de0 JP |
1931 | info->bh_running = false; |
1932 | info->bh_requested = false; | |
705b6c7b PF |
1933 | rc = 0; |
1934 | } | |
1935 | ||
1936 | spin_unlock_irqrestore(&info->lock,flags); | |
1937 | ||
1938 | return rc; | |
1939 | } | |
1940 | ||
1941 | /* | |
1942 | * perform bottom half processing | |
1943 | */ | |
c4028958 | 1944 | static void bh_handler(struct work_struct *work) |
705b6c7b | 1945 | { |
c4028958 | 1946 | struct slgt_info *info = container_of(work, struct slgt_info, task); |
705b6c7b PF |
1947 | int action; |
1948 | ||
1949 | if (!info) | |
1950 | return; | |
0fab6de0 | 1951 | info->bh_running = true; |
705b6c7b PF |
1952 | |
1953 | while((action = bh_action(info))) { | |
1954 | switch (action) { | |
1955 | case BH_RECEIVE: | |
1956 | DBGBH(("%s bh receive\n", info->device_name)); | |
1957 | switch(info->params.mode) { | |
1958 | case MGSL_MODE_ASYNC: | |
1959 | rx_async(info); | |
1960 | break; | |
1961 | case MGSL_MODE_HDLC: | |
1962 | while(rx_get_frame(info)); | |
1963 | break; | |
1964 | case MGSL_MODE_RAW: | |
cb10dc9a PF |
1965 | case MGSL_MODE_MONOSYNC: |
1966 | case MGSL_MODE_BISYNC: | |
705b6c7b PF |
1967 | while(rx_get_buf(info)); |
1968 | break; | |
1969 | } | |
1970 | /* restart receiver if rx DMA buffers exhausted */ | |
1971 | if (info->rx_restart) | |
1972 | rx_start(info); | |
1973 | break; | |
1974 | case BH_TRANSMIT: | |
1975 | bh_transmit(info); | |
1976 | break; | |
1977 | case BH_STATUS: | |
1978 | DBGBH(("%s bh status\n", info->device_name)); | |
1979 | info->ri_chkcount = 0; | |
1980 | info->dsr_chkcount = 0; | |
1981 | info->dcd_chkcount = 0; | |
1982 | info->cts_chkcount = 0; | |
1983 | break; | |
1984 | default: | |
1985 | DBGBH(("%s unknown action\n", info->device_name)); | |
1986 | break; | |
1987 | } | |
1988 | } | |
1989 | DBGBH(("%s bh_handler exit\n", info->device_name)); | |
1990 | } | |
1991 | ||
1992 | static void bh_transmit(struct slgt_info *info) | |
1993 | { | |
8fb06c77 | 1994 | struct tty_struct *tty = info->port.tty; |
705b6c7b PF |
1995 | |
1996 | DBGBH(("%s bh_transmit\n", info->device_name)); | |
b963a844 | 1997 | if (tty) |
705b6c7b | 1998 | tty_wakeup(tty); |
705b6c7b PF |
1999 | } |
2000 | ||
ed8485fb | 2001 | static void dsr_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2002 | { |
ed8485fb PF |
2003 | if (status & BIT3) { |
2004 | info->signals |= SerialSignal_DSR; | |
2005 | info->input_signal_events.dsr_up++; | |
2006 | } else { | |
2007 | info->signals &= ~SerialSignal_DSR; | |
2008 | info->input_signal_events.dsr_down++; | |
2009 | } | |
705b6c7b PF |
2010 | DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); |
2011 | if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2012 | slgt_irq_off(info, IRQ_DSR); | |
2013 | return; | |
2014 | } | |
2015 | info->icount.dsr++; | |
705b6c7b PF |
2016 | wake_up_interruptible(&info->status_event_wait_q); |
2017 | wake_up_interruptible(&info->event_wait_q); | |
2018 | info->pending_bh |= BH_STATUS; | |
2019 | } | |
2020 | ||
ed8485fb | 2021 | static void cts_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2022 | { |
ed8485fb PF |
2023 | if (status & BIT2) { |
2024 | info->signals |= SerialSignal_CTS; | |
2025 | info->input_signal_events.cts_up++; | |
2026 | } else { | |
2027 | info->signals &= ~SerialSignal_CTS; | |
2028 | info->input_signal_events.cts_down++; | |
2029 | } | |
705b6c7b PF |
2030 | DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); |
2031 | if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2032 | slgt_irq_off(info, IRQ_CTS); | |
2033 | return; | |
2034 | } | |
2035 | info->icount.cts++; | |
705b6c7b PF |
2036 | wake_up_interruptible(&info->status_event_wait_q); |
2037 | wake_up_interruptible(&info->event_wait_q); | |
2038 | info->pending_bh |= BH_STATUS; | |
2039 | ||
8fb06c77 AC |
2040 | if (info->port.flags & ASYNC_CTS_FLOW) { |
2041 | if (info->port.tty) { | |
2042 | if (info->port.tty->hw_stopped) { | |
705b6c7b | 2043 | if (info->signals & SerialSignal_CTS) { |
8fb06c77 | 2044 | info->port.tty->hw_stopped = 0; |
705b6c7b PF |
2045 | info->pending_bh |= BH_TRANSMIT; |
2046 | return; | |
2047 | } | |
2048 | } else { | |
2049 | if (!(info->signals & SerialSignal_CTS)) | |
8fb06c77 | 2050 | info->port.tty->hw_stopped = 1; |
705b6c7b PF |
2051 | } |
2052 | } | |
2053 | } | |
2054 | } | |
2055 | ||
ed8485fb | 2056 | static void dcd_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2057 | { |
ed8485fb PF |
2058 | if (status & BIT1) { |
2059 | info->signals |= SerialSignal_DCD; | |
2060 | info->input_signal_events.dcd_up++; | |
2061 | } else { | |
2062 | info->signals &= ~SerialSignal_DCD; | |
2063 | info->input_signal_events.dcd_down++; | |
2064 | } | |
705b6c7b PF |
2065 | DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); |
2066 | if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2067 | slgt_irq_off(info, IRQ_DCD); | |
2068 | return; | |
2069 | } | |
2070 | info->icount.dcd++; | |
af69c7f9 | 2071 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
2072 | if (info->netcount) { |
2073 | if (info->signals & SerialSignal_DCD) | |
2074 | netif_carrier_on(info->netdev); | |
2075 | else | |
2076 | netif_carrier_off(info->netdev); | |
2077 | } | |
705b6c7b PF |
2078 | #endif |
2079 | wake_up_interruptible(&info->status_event_wait_q); | |
2080 | wake_up_interruptible(&info->event_wait_q); | |
2081 | info->pending_bh |= BH_STATUS; | |
2082 | ||
8fb06c77 | 2083 | if (info->port.flags & ASYNC_CHECK_CD) { |
705b6c7b | 2084 | if (info->signals & SerialSignal_DCD) |
8fb06c77 | 2085 | wake_up_interruptible(&info->port.open_wait); |
705b6c7b | 2086 | else { |
8fb06c77 AC |
2087 | if (info->port.tty) |
2088 | tty_hangup(info->port.tty); | |
705b6c7b PF |
2089 | } |
2090 | } | |
2091 | } | |
2092 | ||
ed8485fb | 2093 | static void ri_change(struct slgt_info *info, unsigned short status) |
705b6c7b | 2094 | { |
ed8485fb PF |
2095 | if (status & BIT0) { |
2096 | info->signals |= SerialSignal_RI; | |
2097 | info->input_signal_events.ri_up++; | |
2098 | } else { | |
2099 | info->signals &= ~SerialSignal_RI; | |
2100 | info->input_signal_events.ri_down++; | |
2101 | } | |
705b6c7b PF |
2102 | DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); |
2103 | if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { | |
2104 | slgt_irq_off(info, IRQ_RI); | |
2105 | return; | |
2106 | } | |
ed8485fb | 2107 | info->icount.rng++; |
705b6c7b PF |
2108 | wake_up_interruptible(&info->status_event_wait_q); |
2109 | wake_up_interruptible(&info->event_wait_q); | |
2110 | info->pending_bh |= BH_STATUS; | |
2111 | } | |
2112 | ||
2113 | static void isr_serial(struct slgt_info *info) | |
2114 | { | |
2115 | unsigned short status = rd_reg16(info, SSR); | |
2116 | ||
2117 | DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); | |
2118 | ||
2119 | wr_reg16(info, SSR, status); /* clear pending */ | |
2120 | ||
0fab6de0 | 2121 | info->irq_occurred = true; |
705b6c7b PF |
2122 | |
2123 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
2124 | if (status & IRQ_TXIDLE) { | |
2125 | if (info->tx_count) | |
2126 | isr_txeom(info, status); | |
2127 | } | |
2128 | if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { | |
2129 | info->icount.brk++; | |
2130 | /* process break detection if tty control allows */ | |
8fb06c77 | 2131 | if (info->port.tty) { |
705b6c7b PF |
2132 | if (!(status & info->ignore_status_mask)) { |
2133 | if (info->read_status_mask & MASK_BREAK) { | |
8fb06c77 AC |
2134 | tty_insert_flip_char(info->port.tty, 0, TTY_BREAK); |
2135 | if (info->port.flags & ASYNC_SAK) | |
2136 | do_SAK(info->port.tty); | |
705b6c7b PF |
2137 | } |
2138 | } | |
2139 | } | |
2140 | } | |
2141 | } else { | |
2142 | if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) | |
2143 | isr_txeom(info, status); | |
2144 | ||
2145 | if (status & IRQ_RXIDLE) { | |
2146 | if (status & RXIDLE) | |
2147 | info->icount.rxidle++; | |
2148 | else | |
2149 | info->icount.exithunt++; | |
2150 | wake_up_interruptible(&info->event_wait_q); | |
2151 | } | |
2152 | ||
2153 | if (status & IRQ_RXOVER) | |
2154 | rx_start(info); | |
2155 | } | |
2156 | ||
2157 | if (status & IRQ_DSR) | |
ed8485fb | 2158 | dsr_change(info, status); |
705b6c7b | 2159 | if (status & IRQ_CTS) |
ed8485fb | 2160 | cts_change(info, status); |
705b6c7b | 2161 | if (status & IRQ_DCD) |
ed8485fb | 2162 | dcd_change(info, status); |
705b6c7b | 2163 | if (status & IRQ_RI) |
ed8485fb | 2164 | ri_change(info, status); |
705b6c7b PF |
2165 | } |
2166 | ||
2167 | static void isr_rdma(struct slgt_info *info) | |
2168 | { | |
2169 | unsigned int status = rd_reg32(info, RDCSR); | |
2170 | ||
2171 | DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); | |
2172 | ||
2173 | /* RDCSR (rx DMA control/status) | |
2174 | * | |
2175 | * 31..07 reserved | |
2176 | * 06 save status byte to DMA buffer | |
2177 | * 05 error | |
2178 | * 04 eol (end of list) | |
2179 | * 03 eob (end of buffer) | |
2180 | * 02 IRQ enable | |
2181 | * 01 reset | |
2182 | * 00 enable | |
2183 | */ | |
2184 | wr_reg32(info, RDCSR, status); /* clear pending */ | |
2185 | ||
2186 | if (status & (BIT5 + BIT4)) { | |
2187 | DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); | |
0fab6de0 | 2188 | info->rx_restart = true; |
705b6c7b PF |
2189 | } |
2190 | info->pending_bh |= BH_RECEIVE; | |
2191 | } | |
2192 | ||
2193 | static void isr_tdma(struct slgt_info *info) | |
2194 | { | |
2195 | unsigned int status = rd_reg32(info, TDCSR); | |
2196 | ||
2197 | DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); | |
2198 | ||
2199 | /* TDCSR (tx DMA control/status) | |
2200 | * | |
2201 | * 31..06 reserved | |
2202 | * 05 error | |
2203 | * 04 eol (end of list) | |
2204 | * 03 eob (end of buffer) | |
2205 | * 02 IRQ enable | |
2206 | * 01 reset | |
2207 | * 00 enable | |
2208 | */ | |
2209 | wr_reg32(info, TDCSR, status); /* clear pending */ | |
2210 | ||
2211 | if (status & (BIT5 + BIT4 + BIT3)) { | |
2212 | // another transmit buffer has completed | |
2213 | // run bottom half to get more send data from user | |
2214 | info->pending_bh |= BH_TRANSMIT; | |
2215 | } | |
2216 | } | |
2217 | ||
2218 | static void isr_txeom(struct slgt_info *info, unsigned short status) | |
2219 | { | |
2220 | DBGISR(("%s txeom status=%04x\n", info->device_name, status)); | |
2221 | ||
2222 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
2223 | tdma_reset(info); | |
2224 | reset_tbufs(info); | |
2225 | if (status & IRQ_TXUNDER) { | |
2226 | unsigned short val = rd_reg16(info, TCR); | |
2227 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
2228 | wr_reg16(info, TCR, val); /* clear reset bit */ | |
2229 | } | |
2230 | ||
2231 | if (info->tx_active) { | |
2232 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2233 | if (status & IRQ_TXUNDER) | |
2234 | info->icount.txunder++; | |
2235 | else if (status & IRQ_TXIDLE) | |
2236 | info->icount.txok++; | |
2237 | } | |
2238 | ||
0fab6de0 | 2239 | info->tx_active = false; |
705b6c7b PF |
2240 | info->tx_count = 0; |
2241 | ||
2242 | del_timer(&info->tx_timer); | |
2243 | ||
2244 | if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { | |
2245 | info->signals &= ~SerialSignal_RTS; | |
0fab6de0 | 2246 | info->drop_rts_on_tx_done = false; |
705b6c7b PF |
2247 | set_signals(info); |
2248 | } | |
2249 | ||
af69c7f9 | 2250 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
2251 | if (info->netcount) |
2252 | hdlcdev_tx_done(info); | |
2253 | else | |
2254 | #endif | |
2255 | { | |
8fb06c77 | 2256 | if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { |
705b6c7b PF |
2257 | tx_stop(info); |
2258 | return; | |
2259 | } | |
2260 | info->pending_bh |= BH_TRANSMIT; | |
2261 | } | |
2262 | } | |
2263 | } | |
2264 | ||
0080b7aa PF |
2265 | static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) |
2266 | { | |
2267 | struct cond_wait *w, *prev; | |
2268 | ||
2269 | /* wake processes waiting for specific transitions */ | |
2270 | for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { | |
2271 | if (w->data & changed) { | |
2272 | w->data = state; | |
2273 | wake_up_interruptible(&w->q); | |
2274 | if (prev != NULL) | |
2275 | prev->next = w->next; | |
2276 | else | |
2277 | info->gpio_wait_q = w->next; | |
2278 | } else | |
2279 | prev = w; | |
2280 | } | |
2281 | } | |
2282 | ||
705b6c7b PF |
2283 | /* interrupt service routine |
2284 | * | |
2285 | * irq interrupt number | |
2286 | * dev_id device ID supplied during interrupt registration | |
705b6c7b | 2287 | */ |
a6f97b29 | 2288 | static irqreturn_t slgt_interrupt(int dummy, void *dev_id) |
705b6c7b | 2289 | { |
a6f97b29 | 2290 | struct slgt_info *info = dev_id; |
705b6c7b PF |
2291 | unsigned int gsr; |
2292 | unsigned int i; | |
2293 | ||
a6f97b29 | 2294 | DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); |
705b6c7b PF |
2295 | |
2296 | spin_lock(&info->lock); | |
2297 | ||
2298 | while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { | |
2299 | DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); | |
0fab6de0 | 2300 | info->irq_occurred = true; |
705b6c7b PF |
2301 | for(i=0; i < info->port_count ; i++) { |
2302 | if (info->port_array[i] == NULL) | |
2303 | continue; | |
2304 | if (gsr & (BIT8 << i)) | |
2305 | isr_serial(info->port_array[i]); | |
2306 | if (gsr & (BIT16 << (i*2))) | |
2307 | isr_rdma(info->port_array[i]); | |
2308 | if (gsr & (BIT17 << (i*2))) | |
2309 | isr_tdma(info->port_array[i]); | |
2310 | } | |
2311 | } | |
2312 | ||
0080b7aa PF |
2313 | if (info->gpio_present) { |
2314 | unsigned int state; | |
2315 | unsigned int changed; | |
2316 | while ((changed = rd_reg32(info, IOSR)) != 0) { | |
2317 | DBGISR(("%s iosr=%08x\n", info->device_name, changed)); | |
2318 | /* read latched state of GPIO signals */ | |
2319 | state = rd_reg32(info, IOVR); | |
2320 | /* clear pending GPIO interrupt bits */ | |
2321 | wr_reg32(info, IOSR, changed); | |
2322 | for (i=0 ; i < info->port_count ; i++) { | |
2323 | if (info->port_array[i] != NULL) | |
2324 | isr_gpio(info->port_array[i], changed, state); | |
2325 | } | |
2326 | } | |
2327 | } | |
2328 | ||
705b6c7b PF |
2329 | for(i=0; i < info->port_count ; i++) { |
2330 | struct slgt_info *port = info->port_array[i]; | |
2331 | ||
8fb06c77 | 2332 | if (port && (port->port.count || port->netcount) && |
705b6c7b PF |
2333 | port->pending_bh && !port->bh_running && |
2334 | !port->bh_requested) { | |
2335 | DBGISR(("%s bh queued\n", port->device_name)); | |
2336 | schedule_work(&port->task); | |
0fab6de0 | 2337 | port->bh_requested = true; |
705b6c7b PF |
2338 | } |
2339 | } | |
2340 | ||
2341 | spin_unlock(&info->lock); | |
2342 | ||
a6f97b29 | 2343 | DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); |
705b6c7b PF |
2344 | return IRQ_HANDLED; |
2345 | } | |
2346 | ||
2347 | static int startup(struct slgt_info *info) | |
2348 | { | |
2349 | DBGINFO(("%s startup\n", info->device_name)); | |
2350 | ||
8fb06c77 | 2351 | if (info->port.flags & ASYNC_INITIALIZED) |
705b6c7b PF |
2352 | return 0; |
2353 | ||
2354 | if (!info->tx_buf) { | |
2355 | info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
2356 | if (!info->tx_buf) { | |
2357 | DBGERR(("%s can't allocate tx buffer\n", info->device_name)); | |
2358 | return -ENOMEM; | |
2359 | } | |
2360 | } | |
2361 | ||
2362 | info->pending_bh = 0; | |
2363 | ||
2364 | memset(&info->icount, 0, sizeof(info->icount)); | |
2365 | ||
2366 | /* program hardware for current parameters */ | |
2367 | change_params(info); | |
2368 | ||
8fb06c77 AC |
2369 | if (info->port.tty) |
2370 | clear_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
705b6c7b | 2371 | |
8fb06c77 | 2372 | info->port.flags |= ASYNC_INITIALIZED; |
705b6c7b PF |
2373 | |
2374 | return 0; | |
2375 | } | |
2376 | ||
2377 | /* | |
2378 | * called by close() and hangup() to shutdown hardware | |
2379 | */ | |
2380 | static void shutdown(struct slgt_info *info) | |
2381 | { | |
2382 | unsigned long flags; | |
2383 | ||
8fb06c77 | 2384 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
705b6c7b PF |
2385 | return; |
2386 | ||
2387 | DBGINFO(("%s shutdown\n", info->device_name)); | |
2388 | ||
2389 | /* clear status wait queue because status changes */ | |
2390 | /* can't happen after shutting down the hardware */ | |
2391 | wake_up_interruptible(&info->status_event_wait_q); | |
2392 | wake_up_interruptible(&info->event_wait_q); | |
2393 | ||
2394 | del_timer_sync(&info->tx_timer); | |
2395 | del_timer_sync(&info->rx_timer); | |
2396 | ||
2397 | kfree(info->tx_buf); | |
2398 | info->tx_buf = NULL; | |
2399 | ||
2400 | spin_lock_irqsave(&info->lock,flags); | |
2401 | ||
2402 | tx_stop(info); | |
2403 | rx_stop(info); | |
2404 | ||
2405 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
2406 | ||
8fb06c77 | 2407 | if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) { |
705b6c7b PF |
2408 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); |
2409 | set_signals(info); | |
2410 | } | |
2411 | ||
0080b7aa PF |
2412 | flush_cond_wait(&info->gpio_wait_q); |
2413 | ||
705b6c7b PF |
2414 | spin_unlock_irqrestore(&info->lock,flags); |
2415 | ||
8fb06c77 AC |
2416 | if (info->port.tty) |
2417 | set_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
705b6c7b | 2418 | |
8fb06c77 | 2419 | info->port.flags &= ~ASYNC_INITIALIZED; |
705b6c7b PF |
2420 | } |
2421 | ||
2422 | static void program_hw(struct slgt_info *info) | |
2423 | { | |
2424 | unsigned long flags; | |
2425 | ||
2426 | spin_lock_irqsave(&info->lock,flags); | |
2427 | ||
2428 | rx_stop(info); | |
2429 | tx_stop(info); | |
2430 | ||
cb10dc9a | 2431 | if (info->params.mode != MGSL_MODE_ASYNC || |
705b6c7b | 2432 | info->netcount) |
cb10dc9a | 2433 | sync_mode(info); |
705b6c7b PF |
2434 | else |
2435 | async_mode(info); | |
2436 | ||
2437 | set_signals(info); | |
2438 | ||
2439 | info->dcd_chkcount = 0; | |
2440 | info->cts_chkcount = 0; | |
2441 | info->ri_chkcount = 0; | |
2442 | info->dsr_chkcount = 0; | |
2443 | ||
a6b2f87b | 2444 | slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); |
705b6c7b PF |
2445 | get_signals(info); |
2446 | ||
2447 | if (info->netcount || | |
8fb06c77 | 2448 | (info->port.tty && info->port.tty->termios->c_cflag & CREAD)) |
705b6c7b PF |
2449 | rx_start(info); |
2450 | ||
2451 | spin_unlock_irqrestore(&info->lock,flags); | |
2452 | } | |
2453 | ||
2454 | /* | |
2455 | * reconfigure adapter based on new parameters | |
2456 | */ | |
2457 | static void change_params(struct slgt_info *info) | |
2458 | { | |
2459 | unsigned cflag; | |
2460 | int bits_per_char; | |
2461 | ||
8fb06c77 | 2462 | if (!info->port.tty || !info->port.tty->termios) |
705b6c7b PF |
2463 | return; |
2464 | DBGINFO(("%s change_params\n", info->device_name)); | |
2465 | ||
8fb06c77 | 2466 | cflag = info->port.tty->termios->c_cflag; |
705b6c7b PF |
2467 | |
2468 | /* if B0 rate (hangup) specified then negate DTR and RTS */ | |
2469 | /* otherwise assert DTR and RTS */ | |
2470 | if (cflag & CBAUD) | |
2471 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
2472 | else | |
2473 | info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR); | |
2474 | ||
2475 | /* byte size and parity */ | |
2476 | ||
2477 | switch (cflag & CSIZE) { | |
2478 | case CS5: info->params.data_bits = 5; break; | |
2479 | case CS6: info->params.data_bits = 6; break; | |
2480 | case CS7: info->params.data_bits = 7; break; | |
2481 | case CS8: info->params.data_bits = 8; break; | |
2482 | default: info->params.data_bits = 7; break; | |
2483 | } | |
2484 | ||
2485 | info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; | |
2486 | ||
2487 | if (cflag & PARENB) | |
2488 | info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; | |
2489 | else | |
2490 | info->params.parity = ASYNC_PARITY_NONE; | |
2491 | ||
2492 | /* calculate number of jiffies to transmit a full | |
2493 | * FIFO (32 bytes) at specified data rate | |
2494 | */ | |
2495 | bits_per_char = info->params.data_bits + | |
2496 | info->params.stop_bits + 1; | |
2497 | ||
8fb06c77 | 2498 | info->params.data_rate = tty_get_baud_rate(info->port.tty); |
705b6c7b PF |
2499 | |
2500 | if (info->params.data_rate) { | |
2501 | info->timeout = (32*HZ*bits_per_char) / | |
2502 | info->params.data_rate; | |
2503 | } | |
2504 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
2505 | ||
2506 | if (cflag & CRTSCTS) | |
8fb06c77 | 2507 | info->port.flags |= ASYNC_CTS_FLOW; |
705b6c7b | 2508 | else |
8fb06c77 | 2509 | info->port.flags &= ~ASYNC_CTS_FLOW; |
705b6c7b PF |
2510 | |
2511 | if (cflag & CLOCAL) | |
8fb06c77 | 2512 | info->port.flags &= ~ASYNC_CHECK_CD; |
705b6c7b | 2513 | else |
8fb06c77 | 2514 | info->port.flags |= ASYNC_CHECK_CD; |
705b6c7b PF |
2515 | |
2516 | /* process tty input control flags */ | |
2517 | ||
2518 | info->read_status_mask = IRQ_RXOVER; | |
8fb06c77 | 2519 | if (I_INPCK(info->port.tty)) |
705b6c7b | 2520 | info->read_status_mask |= MASK_PARITY | MASK_FRAMING; |
8fb06c77 | 2521 | if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) |
705b6c7b | 2522 | info->read_status_mask |= MASK_BREAK; |
8fb06c77 | 2523 | if (I_IGNPAR(info->port.tty)) |
705b6c7b | 2524 | info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; |
8fb06c77 | 2525 | if (I_IGNBRK(info->port.tty)) { |
705b6c7b PF |
2526 | info->ignore_status_mask |= MASK_BREAK; |
2527 | /* If ignoring parity and break indicators, ignore | |
2528 | * overruns too. (For real raw support). | |
2529 | */ | |
8fb06c77 | 2530 | if (I_IGNPAR(info->port.tty)) |
705b6c7b PF |
2531 | info->ignore_status_mask |= MASK_OVERRUN; |
2532 | } | |
2533 | ||
2534 | program_hw(info); | |
2535 | } | |
2536 | ||
2537 | static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) | |
2538 | { | |
2539 | DBGINFO(("%s get_stats\n", info->device_name)); | |
2540 | if (!user_icount) { | |
2541 | memset(&info->icount, 0, sizeof(info->icount)); | |
2542 | } else { | |
2543 | if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) | |
2544 | return -EFAULT; | |
2545 | } | |
2546 | return 0; | |
2547 | } | |
2548 | ||
2549 | static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) | |
2550 | { | |
2551 | DBGINFO(("%s get_params\n", info->device_name)); | |
2552 | if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) | |
2553 | return -EFAULT; | |
2554 | return 0; | |
2555 | } | |
2556 | ||
2557 | static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) | |
2558 | { | |
2559 | unsigned long flags; | |
2560 | MGSL_PARAMS tmp_params; | |
2561 | ||
2562 | DBGINFO(("%s set_params\n", info->device_name)); | |
2563 | if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) | |
2564 | return -EFAULT; | |
2565 | ||
2566 | spin_lock_irqsave(&info->lock, flags); | |
1f80769f PF |
2567 | if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) |
2568 | info->base_clock = tmp_params.clock_speed; | |
2569 | else | |
2570 | memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); | |
705b6c7b PF |
2571 | spin_unlock_irqrestore(&info->lock, flags); |
2572 | ||
1f80769f | 2573 | program_hw(info); |
705b6c7b PF |
2574 | |
2575 | return 0; | |
2576 | } | |
2577 | ||
2578 | static int get_txidle(struct slgt_info *info, int __user *idle_mode) | |
2579 | { | |
2580 | DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); | |
2581 | if (put_user(info->idle_mode, idle_mode)) | |
2582 | return -EFAULT; | |
2583 | return 0; | |
2584 | } | |
2585 | ||
2586 | static int set_txidle(struct slgt_info *info, int idle_mode) | |
2587 | { | |
2588 | unsigned long flags; | |
2589 | DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); | |
2590 | spin_lock_irqsave(&info->lock,flags); | |
2591 | info->idle_mode = idle_mode; | |
643f3319 PF |
2592 | if (info->params.mode != MGSL_MODE_ASYNC) |
2593 | tx_set_idle(info); | |
705b6c7b PF |
2594 | spin_unlock_irqrestore(&info->lock,flags); |
2595 | return 0; | |
2596 | } | |
2597 | ||
2598 | static int tx_enable(struct slgt_info *info, int enable) | |
2599 | { | |
2600 | unsigned long flags; | |
2601 | DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); | |
2602 | spin_lock_irqsave(&info->lock,flags); | |
2603 | if (enable) { | |
2604 | if (!info->tx_enabled) | |
2605 | tx_start(info); | |
2606 | } else { | |
2607 | if (info->tx_enabled) | |
2608 | tx_stop(info); | |
2609 | } | |
2610 | spin_unlock_irqrestore(&info->lock,flags); | |
2611 | return 0; | |
2612 | } | |
2613 | ||
2614 | /* | |
2615 | * abort transmit HDLC frame | |
2616 | */ | |
2617 | static int tx_abort(struct slgt_info *info) | |
2618 | { | |
2619 | unsigned long flags; | |
2620 | DBGINFO(("%s tx_abort\n", info->device_name)); | |
2621 | spin_lock_irqsave(&info->lock,flags); | |
2622 | tdma_reset(info); | |
2623 | spin_unlock_irqrestore(&info->lock,flags); | |
2624 | return 0; | |
2625 | } | |
2626 | ||
2627 | static int rx_enable(struct slgt_info *info, int enable) | |
2628 | { | |
2629 | unsigned long flags; | |
814dae03 PF |
2630 | unsigned int rbuf_fill_level; |
2631 | DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); | |
705b6c7b | 2632 | spin_lock_irqsave(&info->lock,flags); |
814dae03 PF |
2633 | /* |
2634 | * enable[31..16] = receive DMA buffer fill level | |
2635 | * 0 = noop (leave fill level unchanged) | |
2636 | * fill level must be multiple of 4 and <= buffer size | |
2637 | */ | |
2638 | rbuf_fill_level = ((unsigned int)enable) >> 16; | |
2639 | if (rbuf_fill_level) { | |
c68a99cd PF |
2640 | if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { |
2641 | spin_unlock_irqrestore(&info->lock, flags); | |
814dae03 | 2642 | return -EINVAL; |
c68a99cd | 2643 | } |
814dae03 PF |
2644 | info->rbuf_fill_level = rbuf_fill_level; |
2645 | rx_stop(info); /* restart receiver to use new fill level */ | |
2646 | } | |
2647 | ||
2648 | /* | |
2649 | * enable[1..0] = receiver enable command | |
2650 | * 0 = disable | |
2651 | * 1 = enable | |
2652 | * 2 = enable or force hunt mode if already enabled | |
2653 | */ | |
2654 | enable &= 3; | |
705b6c7b PF |
2655 | if (enable) { |
2656 | if (!info->rx_enabled) | |
2657 | rx_start(info); | |
cb10dc9a PF |
2658 | else if (enable == 2) { |
2659 | /* force hunt mode (write 1 to RCR[3]) */ | |
2660 | wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); | |
2661 | } | |
705b6c7b PF |
2662 | } else { |
2663 | if (info->rx_enabled) | |
2664 | rx_stop(info); | |
2665 | } | |
2666 | spin_unlock_irqrestore(&info->lock,flags); | |
2667 | return 0; | |
2668 | } | |
2669 | ||
2670 | /* | |
2671 | * wait for specified event to occur | |
2672 | */ | |
2673 | static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) | |
2674 | { | |
2675 | unsigned long flags; | |
2676 | int s; | |
2677 | int rc=0; | |
2678 | struct mgsl_icount cprev, cnow; | |
2679 | int events; | |
2680 | int mask; | |
2681 | struct _input_signal_events oldsigs, newsigs; | |
2682 | DECLARE_WAITQUEUE(wait, current); | |
2683 | ||
2684 | if (get_user(mask, mask_ptr)) | |
2685 | return -EFAULT; | |
2686 | ||
2687 | DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); | |
2688 | ||
2689 | spin_lock_irqsave(&info->lock,flags); | |
2690 | ||
2691 | /* return immediately if state matches requested events */ | |
2692 | get_signals(info); | |
2693 | s = info->signals; | |
2694 | ||
2695 | events = mask & | |
2696 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
2697 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
2698 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
2699 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
2700 | if (events) { | |
2701 | spin_unlock_irqrestore(&info->lock,flags); | |
2702 | goto exit; | |
2703 | } | |
2704 | ||
2705 | /* save current irq counts */ | |
2706 | cprev = info->icount; | |
2707 | oldsigs = info->input_signal_events; | |
2708 | ||
2709 | /* enable hunt and idle irqs if needed */ | |
2710 | if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { | |
2711 | unsigned short val = rd_reg16(info, SCR); | |
2712 | if (!(val & IRQ_RXIDLE)) | |
2713 | wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); | |
2714 | } | |
2715 | ||
2716 | set_current_state(TASK_INTERRUPTIBLE); | |
2717 | add_wait_queue(&info->event_wait_q, &wait); | |
2718 | ||
2719 | spin_unlock_irqrestore(&info->lock,flags); | |
2720 | ||
2721 | for(;;) { | |
2722 | schedule(); | |
2723 | if (signal_pending(current)) { | |
2724 | rc = -ERESTARTSYS; | |
2725 | break; | |
2726 | } | |
2727 | ||
2728 | /* get current irq counts */ | |
2729 | spin_lock_irqsave(&info->lock,flags); | |
2730 | cnow = info->icount; | |
2731 | newsigs = info->input_signal_events; | |
2732 | set_current_state(TASK_INTERRUPTIBLE); | |
2733 | spin_unlock_irqrestore(&info->lock,flags); | |
2734 | ||
2735 | /* if no change, wait aborted for some reason */ | |
2736 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
2737 | newsigs.dsr_down == oldsigs.dsr_down && | |
2738 | newsigs.dcd_up == oldsigs.dcd_up && | |
2739 | newsigs.dcd_down == oldsigs.dcd_down && | |
2740 | newsigs.cts_up == oldsigs.cts_up && | |
2741 | newsigs.cts_down == oldsigs.cts_down && | |
2742 | newsigs.ri_up == oldsigs.ri_up && | |
2743 | newsigs.ri_down == oldsigs.ri_down && | |
2744 | cnow.exithunt == cprev.exithunt && | |
2745 | cnow.rxidle == cprev.rxidle) { | |
2746 | rc = -EIO; | |
2747 | break; | |
2748 | } | |
2749 | ||
2750 | events = mask & | |
2751 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
2752 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
2753 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
2754 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
2755 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
2756 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
2757 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
2758 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
2759 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
2760 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
2761 | if (events) | |
2762 | break; | |
2763 | ||
2764 | cprev = cnow; | |
2765 | oldsigs = newsigs; | |
2766 | } | |
2767 | ||
2768 | remove_wait_queue(&info->event_wait_q, &wait); | |
2769 | set_current_state(TASK_RUNNING); | |
2770 | ||
2771 | ||
2772 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
2773 | spin_lock_irqsave(&info->lock,flags); | |
2774 | if (!waitqueue_active(&info->event_wait_q)) { | |
2775 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
2776 | wr_reg16(info, SCR, | |
2777 | (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); | |
2778 | } | |
2779 | spin_unlock_irqrestore(&info->lock,flags); | |
2780 | } | |
2781 | exit: | |
2782 | if (rc == 0) | |
2783 | rc = put_user(events, mask_ptr); | |
2784 | return rc; | |
2785 | } | |
2786 | ||
2787 | static int get_interface(struct slgt_info *info, int __user *if_mode) | |
2788 | { | |
2789 | DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); | |
2790 | if (put_user(info->if_mode, if_mode)) | |
2791 | return -EFAULT; | |
2792 | return 0; | |
2793 | } | |
2794 | ||
2795 | static int set_interface(struct slgt_info *info, int if_mode) | |
2796 | { | |
2797 | unsigned long flags; | |
35fbd397 | 2798 | unsigned short val; |
705b6c7b PF |
2799 | |
2800 | DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); | |
2801 | spin_lock_irqsave(&info->lock,flags); | |
2802 | info->if_mode = if_mode; | |
2803 | ||
2804 | msc_set_vcr(info); | |
2805 | ||
2806 | /* TCR (tx control) 07 1=RTS driver control */ | |
2807 | val = rd_reg16(info, TCR); | |
2808 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
2809 | val |= BIT7; | |
2810 | else | |
2811 | val &= ~BIT7; | |
2812 | wr_reg16(info, TCR, val); | |
2813 | ||
2814 | spin_unlock_irqrestore(&info->lock,flags); | |
2815 | return 0; | |
2816 | } | |
2817 | ||
0080b7aa PF |
2818 | /* |
2819 | * set general purpose IO pin state and direction | |
2820 | * | |
2821 | * user_gpio fields: | |
2822 | * state each bit indicates a pin state | |
2823 | * smask set bit indicates pin state to set | |
2824 | * dir each bit indicates a pin direction (0=input, 1=output) | |
2825 | * dmask set bit indicates pin direction to set | |
2826 | */ | |
2827 | static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2828 | { | |
2829 | unsigned long flags; | |
2830 | struct gpio_desc gpio; | |
2831 | __u32 data; | |
2832 | ||
2833 | if (!info->gpio_present) | |
2834 | return -EINVAL; | |
2835 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
2836 | return -EFAULT; | |
2837 | DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", | |
2838 | info->device_name, gpio.state, gpio.smask, | |
2839 | gpio.dir, gpio.dmask)); | |
2840 | ||
2841 | spin_lock_irqsave(&info->lock,flags); | |
2842 | if (gpio.dmask) { | |
2843 | data = rd_reg32(info, IODR); | |
2844 | data |= gpio.dmask & gpio.dir; | |
2845 | data &= ~(gpio.dmask & ~gpio.dir); | |
2846 | wr_reg32(info, IODR, data); | |
2847 | } | |
2848 | if (gpio.smask) { | |
2849 | data = rd_reg32(info, IOVR); | |
2850 | data |= gpio.smask & gpio.state; | |
2851 | data &= ~(gpio.smask & ~gpio.state); | |
2852 | wr_reg32(info, IOVR, data); | |
2853 | } | |
2854 | spin_unlock_irqrestore(&info->lock,flags); | |
2855 | ||
2856 | return 0; | |
2857 | } | |
2858 | ||
2859 | /* | |
2860 | * get general purpose IO pin state and direction | |
2861 | */ | |
2862 | static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2863 | { | |
2864 | struct gpio_desc gpio; | |
2865 | if (!info->gpio_present) | |
2866 | return -EINVAL; | |
2867 | gpio.state = rd_reg32(info, IOVR); | |
2868 | gpio.smask = 0xffffffff; | |
2869 | gpio.dir = rd_reg32(info, IODR); | |
2870 | gpio.dmask = 0xffffffff; | |
2871 | if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
2872 | return -EFAULT; | |
2873 | DBGINFO(("%s get_gpio state=%08x dir=%08x\n", | |
2874 | info->device_name, gpio.state, gpio.dir)); | |
2875 | return 0; | |
2876 | } | |
2877 | ||
2878 | /* | |
2879 | * conditional wait facility | |
2880 | */ | |
2881 | static void init_cond_wait(struct cond_wait *w, unsigned int data) | |
2882 | { | |
2883 | init_waitqueue_head(&w->q); | |
2884 | init_waitqueue_entry(&w->wait, current); | |
2885 | w->data = data; | |
2886 | } | |
2887 | ||
2888 | static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) | |
2889 | { | |
2890 | set_current_state(TASK_INTERRUPTIBLE); | |
2891 | add_wait_queue(&w->q, &w->wait); | |
2892 | w->next = *head; | |
2893 | *head = w; | |
2894 | } | |
2895 | ||
2896 | static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) | |
2897 | { | |
2898 | struct cond_wait *w, *prev; | |
2899 | remove_wait_queue(&cw->q, &cw->wait); | |
2900 | set_current_state(TASK_RUNNING); | |
2901 | for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { | |
2902 | if (w == cw) { | |
2903 | if (prev != NULL) | |
2904 | prev->next = w->next; | |
2905 | else | |
2906 | *head = w->next; | |
2907 | break; | |
2908 | } | |
2909 | } | |
2910 | } | |
2911 | ||
2912 | static void flush_cond_wait(struct cond_wait **head) | |
2913 | { | |
2914 | while (*head != NULL) { | |
2915 | wake_up_interruptible(&(*head)->q); | |
2916 | *head = (*head)->next; | |
2917 | } | |
2918 | } | |
2919 | ||
2920 | /* | |
2921 | * wait for general purpose I/O pin(s) to enter specified state | |
2922 | * | |
2923 | * user_gpio fields: | |
2924 | * state - bit indicates target pin state | |
2925 | * smask - set bit indicates watched pin | |
2926 | * | |
2927 | * The wait ends when at least one watched pin enters the specified | |
2928 | * state. When 0 (no error) is returned, user_gpio->state is set to the | |
2929 | * state of all GPIO pins when the wait ends. | |
2930 | * | |
2931 | * Note: Each pin may be a dedicated input, dedicated output, or | |
2932 | * configurable input/output. The number and configuration of pins | |
2933 | * varies with the specific adapter model. Only input pins (dedicated | |
2934 | * or configured) can be monitored with this function. | |
2935 | */ | |
2936 | static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) | |
2937 | { | |
2938 | unsigned long flags; | |
2939 | int rc = 0; | |
2940 | struct gpio_desc gpio; | |
2941 | struct cond_wait wait; | |
2942 | u32 state; | |
2943 | ||
2944 | if (!info->gpio_present) | |
2945 | return -EINVAL; | |
2946 | if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) | |
2947 | return -EFAULT; | |
2948 | DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", | |
2949 | info->device_name, gpio.state, gpio.smask)); | |
2950 | /* ignore output pins identified by set IODR bit */ | |
2951 | if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) | |
2952 | return -EINVAL; | |
2953 | init_cond_wait(&wait, gpio.smask); | |
2954 | ||
2955 | spin_lock_irqsave(&info->lock, flags); | |
2956 | /* enable interrupts for watched pins */ | |
2957 | wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); | |
2958 | /* get current pin states */ | |
2959 | state = rd_reg32(info, IOVR); | |
2960 | ||
2961 | if (gpio.smask & ~(state ^ gpio.state)) { | |
2962 | /* already in target state */ | |
2963 | gpio.state = state; | |
2964 | } else { | |
2965 | /* wait for target state */ | |
2966 | add_cond_wait(&info->gpio_wait_q, &wait); | |
2967 | spin_unlock_irqrestore(&info->lock, flags); | |
2968 | schedule(); | |
2969 | if (signal_pending(current)) | |
2970 | rc = -ERESTARTSYS; | |
2971 | else | |
2972 | gpio.state = wait.data; | |
2973 | spin_lock_irqsave(&info->lock, flags); | |
2974 | remove_cond_wait(&info->gpio_wait_q, &wait); | |
2975 | } | |
2976 | ||
2977 | /* disable all GPIO interrupts if no waiting processes */ | |
2978 | if (info->gpio_wait_q == NULL) | |
2979 | wr_reg32(info, IOER, 0); | |
2980 | spin_unlock_irqrestore(&info->lock,flags); | |
2981 | ||
2982 | if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) | |
2983 | rc = -EFAULT; | |
2984 | return rc; | |
2985 | } | |
2986 | ||
705b6c7b PF |
2987 | static int modem_input_wait(struct slgt_info *info,int arg) |
2988 | { | |
2989 | unsigned long flags; | |
2990 | int rc; | |
2991 | struct mgsl_icount cprev, cnow; | |
2992 | DECLARE_WAITQUEUE(wait, current); | |
2993 | ||
2994 | /* save current irq counts */ | |
2995 | spin_lock_irqsave(&info->lock,flags); | |
2996 | cprev = info->icount; | |
2997 | add_wait_queue(&info->status_event_wait_q, &wait); | |
2998 | set_current_state(TASK_INTERRUPTIBLE); | |
2999 | spin_unlock_irqrestore(&info->lock,flags); | |
3000 | ||
3001 | for(;;) { | |
3002 | schedule(); | |
3003 | if (signal_pending(current)) { | |
3004 | rc = -ERESTARTSYS; | |
3005 | break; | |
3006 | } | |
3007 | ||
3008 | /* get new irq counts */ | |
3009 | spin_lock_irqsave(&info->lock,flags); | |
3010 | cnow = info->icount; | |
3011 | set_current_state(TASK_INTERRUPTIBLE); | |
3012 | spin_unlock_irqrestore(&info->lock,flags); | |
3013 | ||
3014 | /* if no change, wait aborted for some reason */ | |
3015 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
3016 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
3017 | rc = -EIO; | |
3018 | break; | |
3019 | } | |
3020 | ||
3021 | /* check for change in caller specified modem input */ | |
3022 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
3023 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
3024 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
3025 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
3026 | rc = 0; | |
3027 | break; | |
3028 | } | |
3029 | ||
3030 | cprev = cnow; | |
3031 | } | |
3032 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
3033 | set_current_state(TASK_RUNNING); | |
3034 | return rc; | |
3035 | } | |
3036 | ||
3037 | /* | |
3038 | * return state of serial control and status signals | |
3039 | */ | |
3040 | static int tiocmget(struct tty_struct *tty, struct file *file) | |
3041 | { | |
3042 | struct slgt_info *info = tty->driver_data; | |
3043 | unsigned int result; | |
3044 | unsigned long flags; | |
3045 | ||
3046 | spin_lock_irqsave(&info->lock,flags); | |
3047 | get_signals(info); | |
3048 | spin_unlock_irqrestore(&info->lock,flags); | |
3049 | ||
3050 | result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
3051 | ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
3052 | ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
3053 | ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
3054 | ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
3055 | ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
3056 | ||
3057 | DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); | |
3058 | return result; | |
3059 | } | |
3060 | ||
3061 | /* | |
3062 | * set modem control signals (DTR/RTS) | |
3063 | * | |
3064 | * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit | |
3065 | * TIOCMSET = set/clear signal values | |
3066 | * value bit mask for command | |
3067 | */ | |
3068 | static int tiocmset(struct tty_struct *tty, struct file *file, | |
3069 | unsigned int set, unsigned int clear) | |
3070 | { | |
3071 | struct slgt_info *info = tty->driver_data; | |
3072 | unsigned long flags; | |
3073 | ||
3074 | DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); | |
3075 | ||
3076 | if (set & TIOCM_RTS) | |
3077 | info->signals |= SerialSignal_RTS; | |
3078 | if (set & TIOCM_DTR) | |
3079 | info->signals |= SerialSignal_DTR; | |
3080 | if (clear & TIOCM_RTS) | |
3081 | info->signals &= ~SerialSignal_RTS; | |
3082 | if (clear & TIOCM_DTR) | |
3083 | info->signals &= ~SerialSignal_DTR; | |
3084 | ||
3085 | spin_lock_irqsave(&info->lock,flags); | |
3086 | set_signals(info); | |
3087 | spin_unlock_irqrestore(&info->lock,flags); | |
3088 | return 0; | |
3089 | } | |
3090 | ||
31f35939 AC |
3091 | static int carrier_raised(struct tty_port *port) |
3092 | { | |
3093 | unsigned long flags; | |
3094 | struct slgt_info *info = container_of(port, struct slgt_info, port); | |
3095 | ||
3096 | spin_lock_irqsave(&info->lock,flags); | |
3097 | get_signals(info); | |
3098 | spin_unlock_irqrestore(&info->lock,flags); | |
3099 | return (info->signals & SerialSignal_DCD) ? 1 : 0; | |
3100 | } | |
3101 | ||
5d951fb4 AC |
3102 | static void raise_dtr_rts(struct tty_port *port) |
3103 | { | |
3104 | unsigned long flags; | |
3105 | struct slgt_info *info = container_of(port, struct slgt_info, port); | |
3106 | ||
3107 | spin_lock_irqsave(&info->lock,flags); | |
3108 | info->signals |= SerialSignal_RTS + SerialSignal_DTR; | |
3109 | set_signals(info); | |
3110 | spin_unlock_irqrestore(&info->lock,flags); | |
3111 | } | |
3112 | ||
3113 | ||
705b6c7b PF |
3114 | /* |
3115 | * block current process until the device is ready to open | |
3116 | */ | |
3117 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
3118 | struct slgt_info *info) | |
3119 | { | |
3120 | DECLARE_WAITQUEUE(wait, current); | |
3121 | int retval; | |
0fab6de0 JP |
3122 | bool do_clocal = false; |
3123 | bool extra_count = false; | |
705b6c7b | 3124 | unsigned long flags; |
31f35939 AC |
3125 | int cd; |
3126 | struct tty_port *port = &info->port; | |
705b6c7b PF |
3127 | |
3128 | DBGINFO(("%s block_til_ready\n", tty->driver->name)); | |
3129 | ||
3130 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
3131 | /* nonblock mode is set or port is not enabled */ | |
31f35939 | 3132 | port->flags |= ASYNC_NORMAL_ACTIVE; |
705b6c7b PF |
3133 | return 0; |
3134 | } | |
3135 | ||
3136 | if (tty->termios->c_cflag & CLOCAL) | |
0fab6de0 | 3137 | do_clocal = true; |
705b6c7b PF |
3138 | |
3139 | /* Wait for carrier detect and the line to become | |
3140 | * free (i.e., not in use by the callout). While we are in | |
31f35939 | 3141 | * this loop, port->count is dropped by one, so that |
705b6c7b PF |
3142 | * close() knows when to free things. We restore it upon |
3143 | * exit, either normal or abnormal. | |
3144 | */ | |
3145 | ||
3146 | retval = 0; | |
31f35939 | 3147 | add_wait_queue(&port->open_wait, &wait); |
705b6c7b PF |
3148 | |
3149 | spin_lock_irqsave(&info->lock, flags); | |
3150 | if (!tty_hung_up_p(filp)) { | |
0fab6de0 | 3151 | extra_count = true; |
31f35939 | 3152 | port->count--; |
705b6c7b PF |
3153 | } |
3154 | spin_unlock_irqrestore(&info->lock, flags); | |
31f35939 | 3155 | port->blocked_open++; |
705b6c7b PF |
3156 | |
3157 | while (1) { | |
5d951fb4 AC |
3158 | if ((tty->termios->c_cflag & CBAUD)) |
3159 | tty_port_raise_dtr_rts(port); | |
705b6c7b PF |
3160 | |
3161 | set_current_state(TASK_INTERRUPTIBLE); | |
3162 | ||
31f35939 AC |
3163 | if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ |
3164 | retval = (port->flags & ASYNC_HUP_NOTIFY) ? | |
705b6c7b PF |
3165 | -EAGAIN : -ERESTARTSYS; |
3166 | break; | |
3167 | } | |
3168 | ||
31f35939 | 3169 | cd = tty_port_carrier_raised(port); |
705b6c7b | 3170 | |
31f35939 | 3171 | if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd )) |
705b6c7b | 3172 | break; |
705b6c7b PF |
3173 | |
3174 | if (signal_pending(current)) { | |
3175 | retval = -ERESTARTSYS; | |
3176 | break; | |
3177 | } | |
3178 | ||
3179 | DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); | |
3180 | schedule(); | |
3181 | } | |
3182 | ||
3183 | set_current_state(TASK_RUNNING); | |
31f35939 | 3184 | remove_wait_queue(&port->open_wait, &wait); |
705b6c7b PF |
3185 | |
3186 | if (extra_count) | |
31f35939 AC |
3187 | port->count++; |
3188 | port->blocked_open--; | |
705b6c7b PF |
3189 | |
3190 | if (!retval) | |
31f35939 | 3191 | port->flags |= ASYNC_NORMAL_ACTIVE; |
705b6c7b PF |
3192 | |
3193 | DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); | |
3194 | return retval; | |
3195 | } | |
3196 | ||
3197 | static int alloc_tmp_rbuf(struct slgt_info *info) | |
3198 | { | |
04b374d0 | 3199 | info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); |
705b6c7b PF |
3200 | if (info->tmp_rbuf == NULL) |
3201 | return -ENOMEM; | |
3202 | return 0; | |
3203 | } | |
3204 | ||
3205 | static void free_tmp_rbuf(struct slgt_info *info) | |
3206 | { | |
3207 | kfree(info->tmp_rbuf); | |
3208 | info->tmp_rbuf = NULL; | |
3209 | } | |
3210 | ||
3211 | /* | |
3212 | * allocate DMA descriptor lists. | |
3213 | */ | |
3214 | static int alloc_desc(struct slgt_info *info) | |
3215 | { | |
3216 | unsigned int i; | |
3217 | unsigned int pbufs; | |
3218 | ||
3219 | /* allocate memory to hold descriptor lists */ | |
3220 | info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr); | |
3221 | if (info->bufs == NULL) | |
3222 | return -ENOMEM; | |
3223 | ||
3224 | memset(info->bufs, 0, DESC_LIST_SIZE); | |
3225 | ||
3226 | info->rbufs = (struct slgt_desc*)info->bufs; | |
3227 | info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; | |
3228 | ||
3229 | pbufs = (unsigned int)info->bufs_dma_addr; | |
3230 | ||
3231 | /* | |
3232 | * Build circular lists of descriptors | |
3233 | */ | |
3234 | ||
3235 | for (i=0; i < info->rbuf_count; i++) { | |
3236 | /* physical address of this descriptor */ | |
3237 | info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); | |
3238 | ||
3239 | /* physical address of next descriptor */ | |
3240 | if (i == info->rbuf_count - 1) | |
3241 | info->rbufs[i].next = cpu_to_le32(pbufs); | |
3242 | else | |
3243 | info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); | |
3244 | set_desc_count(info->rbufs[i], DMABUFSIZE); | |
3245 | } | |
3246 | ||
3247 | for (i=0; i < info->tbuf_count; i++) { | |
3248 | /* physical address of this descriptor */ | |
3249 | info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); | |
3250 | ||
3251 | /* physical address of next descriptor */ | |
3252 | if (i == info->tbuf_count - 1) | |
3253 | info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); | |
3254 | else | |
3255 | info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); | |
3256 | } | |
3257 | ||
3258 | return 0; | |
3259 | } | |
3260 | ||
3261 | static void free_desc(struct slgt_info *info) | |
3262 | { | |
3263 | if (info->bufs != NULL) { | |
3264 | pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr); | |
3265 | info->bufs = NULL; | |
3266 | info->rbufs = NULL; | |
3267 | info->tbufs = NULL; | |
3268 | } | |
3269 | } | |
3270 | ||
3271 | static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3272 | { | |
3273 | int i; | |
3274 | for (i=0; i < count; i++) { | |
3275 | if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL) | |
3276 | return -ENOMEM; | |
3277 | bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); | |
3278 | } | |
3279 | return 0; | |
3280 | } | |
3281 | ||
3282 | static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) | |
3283 | { | |
3284 | int i; | |
3285 | for (i=0; i < count; i++) { | |
3286 | if (bufs[i].buf == NULL) | |
3287 | continue; | |
3288 | pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr); | |
3289 | bufs[i].buf = NULL; | |
3290 | } | |
3291 | } | |
3292 | ||
3293 | static int alloc_dma_bufs(struct slgt_info *info) | |
3294 | { | |
3295 | info->rbuf_count = 32; | |
3296 | info->tbuf_count = 32; | |
3297 | ||
3298 | if (alloc_desc(info) < 0 || | |
3299 | alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || | |
3300 | alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || | |
3301 | alloc_tmp_rbuf(info) < 0) { | |
3302 | DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); | |
3303 | return -ENOMEM; | |
3304 | } | |
3305 | reset_rbufs(info); | |
3306 | return 0; | |
3307 | } | |
3308 | ||
3309 | static void free_dma_bufs(struct slgt_info *info) | |
3310 | { | |
3311 | if (info->bufs) { | |
3312 | free_bufs(info, info->rbufs, info->rbuf_count); | |
3313 | free_bufs(info, info->tbufs, info->tbuf_count); | |
3314 | free_desc(info); | |
3315 | } | |
3316 | free_tmp_rbuf(info); | |
3317 | } | |
3318 | ||
3319 | static int claim_resources(struct slgt_info *info) | |
3320 | { | |
3321 | if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { | |
3322 | DBGERR(("%s reg addr conflict, addr=%08X\n", | |
3323 | info->device_name, info->phys_reg_addr)); | |
3324 | info->init_error = DiagStatus_AddressConflict; | |
3325 | goto errout; | |
3326 | } | |
3327 | else | |
0fab6de0 | 3328 | info->reg_addr_requested = true; |
705b6c7b | 3329 | |
24cb2335 | 3330 | info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE); |
705b6c7b PF |
3331 | if (!info->reg_addr) { |
3332 | DBGERR(("%s cant map device registers, addr=%08X\n", | |
3333 | info->device_name, info->phys_reg_addr)); | |
3334 | info->init_error = DiagStatus_CantAssignPciResources; | |
3335 | goto errout; | |
3336 | } | |
705b6c7b PF |
3337 | return 0; |
3338 | ||
3339 | errout: | |
3340 | release_resources(info); | |
3341 | return -ENODEV; | |
3342 | } | |
3343 | ||
3344 | static void release_resources(struct slgt_info *info) | |
3345 | { | |
3346 | if (info->irq_requested) { | |
3347 | free_irq(info->irq_level, info); | |
0fab6de0 | 3348 | info->irq_requested = false; |
705b6c7b PF |
3349 | } |
3350 | ||
3351 | if (info->reg_addr_requested) { | |
3352 | release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); | |
0fab6de0 | 3353 | info->reg_addr_requested = false; |
705b6c7b PF |
3354 | } |
3355 | ||
3356 | if (info->reg_addr) { | |
0c8365ec | 3357 | iounmap(info->reg_addr); |
705b6c7b PF |
3358 | info->reg_addr = NULL; |
3359 | } | |
3360 | } | |
3361 | ||
3362 | /* Add the specified device instance data structure to the | |
3363 | * global linked list of devices and increment the device count. | |
3364 | */ | |
3365 | static void add_device(struct slgt_info *info) | |
3366 | { | |
3367 | char *devstr; | |
3368 | ||
3369 | info->next_device = NULL; | |
3370 | info->line = slgt_device_count; | |
3371 | sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); | |
3372 | ||
3373 | if (info->line < MAX_DEVICES) { | |
3374 | if (maxframe[info->line]) | |
3375 | info->max_frame_size = maxframe[info->line]; | |
705b6c7b PF |
3376 | } |
3377 | ||
3378 | slgt_device_count++; | |
3379 | ||
3380 | if (!slgt_device_list) | |
3381 | slgt_device_list = info; | |
3382 | else { | |
3383 | struct slgt_info *current_dev = slgt_device_list; | |
3384 | while(current_dev->next_device) | |
3385 | current_dev = current_dev->next_device; | |
3386 | current_dev->next_device = info; | |
3387 | } | |
3388 | ||
3389 | if (info->max_frame_size < 4096) | |
3390 | info->max_frame_size = 4096; | |
3391 | else if (info->max_frame_size > 65535) | |
3392 | info->max_frame_size = 65535; | |
3393 | ||
3394 | switch(info->pdev->device) { | |
3395 | case SYNCLINK_GT_DEVICE_ID: | |
3396 | devstr = "GT"; | |
3397 | break; | |
6f84be84 PF |
3398 | case SYNCLINK_GT2_DEVICE_ID: |
3399 | devstr = "GT2"; | |
3400 | break; | |
705b6c7b PF |
3401 | case SYNCLINK_GT4_DEVICE_ID: |
3402 | devstr = "GT4"; | |
3403 | break; | |
3404 | case SYNCLINK_AC_DEVICE_ID: | |
3405 | devstr = "AC"; | |
3406 | info->params.mode = MGSL_MODE_ASYNC; | |
3407 | break; | |
3408 | default: | |
3409 | devstr = "(unknown model)"; | |
3410 | } | |
3411 | printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", | |
3412 | devstr, info->device_name, info->phys_reg_addr, | |
3413 | info->irq_level, info->max_frame_size); | |
3414 | ||
af69c7f9 | 3415 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3416 | hdlcdev_init(info); |
3417 | #endif | |
3418 | } | |
3419 | ||
31f35939 AC |
3420 | static const struct tty_port_operations slgt_port_ops = { |
3421 | .carrier_raised = carrier_raised, | |
5d951fb4 | 3422 | .raise_dtr_rts = raise_dtr_rts, |
31f35939 AC |
3423 | }; |
3424 | ||
705b6c7b PF |
3425 | /* |
3426 | * allocate device instance structure, return NULL on failure | |
3427 | */ | |
3428 | static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) | |
3429 | { | |
3430 | struct slgt_info *info; | |
3431 | ||
dd00cc48 | 3432 | info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); |
705b6c7b PF |
3433 | |
3434 | if (!info) { | |
3435 | DBGERR(("%s device alloc failed adapter=%d port=%d\n", | |
3436 | driver_name, adapter_num, port_num)); | |
3437 | } else { | |
44b7d1b3 | 3438 | tty_port_init(&info->port); |
31f35939 | 3439 | info->port.ops = &slgt_port_ops; |
705b6c7b | 3440 | info->magic = MGSL_MAGIC; |
c4028958 | 3441 | INIT_WORK(&info->task, bh_handler); |
705b6c7b | 3442 | info->max_frame_size = 4096; |
1f80769f | 3443 | info->base_clock = 14745600; |
814dae03 | 3444 | info->rbuf_fill_level = DMABUFSIZE; |
44b7d1b3 AC |
3445 | info->port.close_delay = 5*HZ/10; |
3446 | info->port.closing_wait = 30*HZ; | |
705b6c7b PF |
3447 | init_waitqueue_head(&info->status_event_wait_q); |
3448 | init_waitqueue_head(&info->event_wait_q); | |
3449 | spin_lock_init(&info->netlock); | |
3450 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
3451 | info->idle_mode = HDLC_TXIDLE_FLAGS; | |
3452 | info->adapter_num = adapter_num; | |
3453 | info->port_num = port_num; | |
3454 | ||
40565f19 JS |
3455 | setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); |
3456 | setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info); | |
705b6c7b PF |
3457 | |
3458 | /* Copy configuration info to device instance data */ | |
3459 | info->pdev = pdev; | |
3460 | info->irq_level = pdev->irq; | |
3461 | info->phys_reg_addr = pci_resource_start(pdev,0); | |
3462 | ||
705b6c7b | 3463 | info->bus_type = MGSL_BUS_TYPE_PCI; |
0f2ed4c6 | 3464 | info->irq_flags = IRQF_SHARED; |
705b6c7b PF |
3465 | |
3466 | info->init_error = -1; /* assume error, set to 0 on successful init */ | |
3467 | } | |
3468 | ||
3469 | return info; | |
3470 | } | |
3471 | ||
3472 | static void device_init(int adapter_num, struct pci_dev *pdev) | |
3473 | { | |
3474 | struct slgt_info *port_array[SLGT_MAX_PORTS]; | |
3475 | int i; | |
3476 | int port_count = 1; | |
3477 | ||
6f84be84 PF |
3478 | if (pdev->device == SYNCLINK_GT2_DEVICE_ID) |
3479 | port_count = 2; | |
3480 | else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) | |
705b6c7b PF |
3481 | port_count = 4; |
3482 | ||
3483 | /* allocate device instances for all ports */ | |
3484 | for (i=0; i < port_count; ++i) { | |
3485 | port_array[i] = alloc_dev(adapter_num, i, pdev); | |
3486 | if (port_array[i] == NULL) { | |
3487 | for (--i; i >= 0; --i) | |
3488 | kfree(port_array[i]); | |
3489 | return; | |
3490 | } | |
3491 | } | |
3492 | ||
3493 | /* give copy of port_array to all ports and add to device list */ | |
3494 | for (i=0; i < port_count; ++i) { | |
3495 | memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); | |
3496 | add_device(port_array[i]); | |
3497 | port_array[i]->port_count = port_count; | |
3498 | spin_lock_init(&port_array[i]->lock); | |
3499 | } | |
3500 | ||
3501 | /* Allocate and claim adapter resources */ | |
3502 | if (!claim_resources(port_array[0])) { | |
3503 | ||
3504 | alloc_dma_bufs(port_array[0]); | |
3505 | ||
3506 | /* copy resource information from first port to others */ | |
3507 | for (i = 1; i < port_count; ++i) { | |
3508 | port_array[i]->lock = port_array[0]->lock; | |
3509 | port_array[i]->irq_level = port_array[0]->irq_level; | |
3510 | port_array[i]->reg_addr = port_array[0]->reg_addr; | |
3511 | alloc_dma_bufs(port_array[i]); | |
3512 | } | |
3513 | ||
3514 | if (request_irq(port_array[0]->irq_level, | |
3515 | slgt_interrupt, | |
3516 | port_array[0]->irq_flags, | |
3517 | port_array[0]->device_name, | |
3518 | port_array[0]) < 0) { | |
3519 | DBGERR(("%s request_irq failed IRQ=%d\n", | |
3520 | port_array[0]->device_name, | |
3521 | port_array[0]->irq_level)); | |
3522 | } else { | |
0fab6de0 | 3523 | port_array[0]->irq_requested = true; |
705b6c7b | 3524 | adapter_test(port_array[0]); |
0080b7aa | 3525 | for (i=1 ; i < port_count ; i++) { |
705b6c7b | 3526 | port_array[i]->init_error = port_array[0]->init_error; |
0080b7aa PF |
3527 | port_array[i]->gpio_present = port_array[0]->gpio_present; |
3528 | } | |
705b6c7b PF |
3529 | } |
3530 | } | |
62eb5b1f PF |
3531 | |
3532 | for (i=0; i < port_count; ++i) | |
3533 | tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev)); | |
705b6c7b PF |
3534 | } |
3535 | ||
3536 | static int __devinit init_one(struct pci_dev *dev, | |
3537 | const struct pci_device_id *ent) | |
3538 | { | |
3539 | if (pci_enable_device(dev)) { | |
3540 | printk("error enabling pci device %p\n", dev); | |
3541 | return -EIO; | |
3542 | } | |
3543 | pci_set_master(dev); | |
3544 | device_init(slgt_device_count, dev); | |
3545 | return 0; | |
3546 | } | |
3547 | ||
3548 | static void __devexit remove_one(struct pci_dev *dev) | |
3549 | { | |
3550 | } | |
3551 | ||
b68e31d0 | 3552 | static const struct tty_operations ops = { |
705b6c7b PF |
3553 | .open = open, |
3554 | .close = close, | |
3555 | .write = write, | |
3556 | .put_char = put_char, | |
3557 | .flush_chars = flush_chars, | |
3558 | .write_room = write_room, | |
3559 | .chars_in_buffer = chars_in_buffer, | |
3560 | .flush_buffer = flush_buffer, | |
3561 | .ioctl = ioctl, | |
2acdb169 | 3562 | .compat_ioctl = slgt_compat_ioctl, |
705b6c7b PF |
3563 | .throttle = throttle, |
3564 | .unthrottle = unthrottle, | |
3565 | .send_xchar = send_xchar, | |
3566 | .break_ctl = set_break, | |
3567 | .wait_until_sent = wait_until_sent, | |
705b6c7b PF |
3568 | .set_termios = set_termios, |
3569 | .stop = tx_hold, | |
3570 | .start = tx_release, | |
3571 | .hangup = hangup, | |
3572 | .tiocmget = tiocmget, | |
3573 | .tiocmset = tiocmset, | |
a18c56e5 | 3574 | .proc_fops = &synclink_gt_proc_fops, |
705b6c7b PF |
3575 | }; |
3576 | ||
3577 | static void slgt_cleanup(void) | |
3578 | { | |
3579 | int rc; | |
3580 | struct slgt_info *info; | |
3581 | struct slgt_info *tmp; | |
3582 | ||
a6b2f87b | 3583 | printk(KERN_INFO "unload %s\n", driver_name); |
705b6c7b PF |
3584 | |
3585 | if (serial_driver) { | |
62eb5b1f PF |
3586 | for (info=slgt_device_list ; info != NULL ; info=info->next_device) |
3587 | tty_unregister_device(serial_driver, info->line); | |
705b6c7b PF |
3588 | if ((rc = tty_unregister_driver(serial_driver))) |
3589 | DBGERR(("tty_unregister_driver error=%d\n", rc)); | |
3590 | put_tty_driver(serial_driver); | |
3591 | } | |
3592 | ||
3593 | /* reset devices */ | |
3594 | info = slgt_device_list; | |
3595 | while(info) { | |
3596 | reset_port(info); | |
3597 | info = info->next_device; | |
3598 | } | |
3599 | ||
3600 | /* release devices */ | |
3601 | info = slgt_device_list; | |
3602 | while(info) { | |
af69c7f9 | 3603 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
3604 | hdlcdev_exit(info); |
3605 | #endif | |
3606 | free_dma_bufs(info); | |
3607 | free_tmp_rbuf(info); | |
3608 | if (info->port_num == 0) | |
3609 | release_resources(info); | |
3610 | tmp = info; | |
3611 | info = info->next_device; | |
3612 | kfree(tmp); | |
3613 | } | |
3614 | ||
3615 | if (pci_registered) | |
3616 | pci_unregister_driver(&pci_driver); | |
3617 | } | |
3618 | ||
3619 | /* | |
3620 | * Driver initialization entry point. | |
3621 | */ | |
3622 | static int __init slgt_init(void) | |
3623 | { | |
3624 | int rc; | |
3625 | ||
a6b2f87b | 3626 | printk(KERN_INFO "%s\n", driver_name); |
705b6c7b | 3627 | |
705b6c7b PF |
3628 | serial_driver = alloc_tty_driver(MAX_DEVICES); |
3629 | if (!serial_driver) { | |
62eb5b1f PF |
3630 | printk("%s can't allocate tty driver\n", driver_name); |
3631 | return -ENOMEM; | |
705b6c7b PF |
3632 | } |
3633 | ||
3634 | /* Initialize the tty_driver structure */ | |
3635 | ||
3636 | serial_driver->owner = THIS_MODULE; | |
3637 | serial_driver->driver_name = tty_driver_name; | |
3638 | serial_driver->name = tty_dev_prefix; | |
3639 | serial_driver->major = ttymajor; | |
3640 | serial_driver->minor_start = 64; | |
3641 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
3642 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
3643 | serial_driver->init_termios = tty_std_termios; | |
3644 | serial_driver->init_termios.c_cflag = | |
3645 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
606d099c AC |
3646 | serial_driver->init_termios.c_ispeed = 9600; |
3647 | serial_driver->init_termios.c_ospeed = 9600; | |
62eb5b1f | 3648 | serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; |
705b6c7b PF |
3649 | tty_set_operations(serial_driver, &ops); |
3650 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
3651 | DBGERR(("%s can't register serial driver\n", driver_name)); | |
3652 | put_tty_driver(serial_driver); | |
3653 | serial_driver = NULL; | |
3654 | goto error; | |
3655 | } | |
3656 | ||
a6b2f87b PF |
3657 | printk(KERN_INFO "%s, tty major#%d\n", |
3658 | driver_name, serial_driver->major); | |
705b6c7b | 3659 | |
62eb5b1f PF |
3660 | slgt_device_count = 0; |
3661 | if ((rc = pci_register_driver(&pci_driver)) < 0) { | |
3662 | printk("%s pci_register_driver error=%d\n", driver_name, rc); | |
3663 | goto error; | |
3664 | } | |
0fab6de0 | 3665 | pci_registered = true; |
62eb5b1f PF |
3666 | |
3667 | if (!slgt_device_list) | |
3668 | printk("%s no devices found\n",driver_name); | |
3669 | ||
705b6c7b PF |
3670 | return 0; |
3671 | ||
3672 | error: | |
3673 | slgt_cleanup(); | |
3674 | return rc; | |
3675 | } | |
3676 | ||
3677 | static void __exit slgt_exit(void) | |
3678 | { | |
3679 | slgt_cleanup(); | |
3680 | } | |
3681 | ||
3682 | module_init(slgt_init); | |
3683 | module_exit(slgt_exit); | |
3684 | ||
3685 | /* | |
3686 | * register access routines | |
3687 | */ | |
3688 | ||
3689 | #define CALC_REGADDR() \ | |
3690 | unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ | |
3691 | if (addr >= 0x80) \ | |
3692 | reg_addr += (info->port_num) * 32; | |
3693 | ||
3694 | static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) | |
3695 | { | |
3696 | CALC_REGADDR(); | |
3697 | return readb((void __iomem *)reg_addr); | |
3698 | } | |
3699 | ||
3700 | static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) | |
3701 | { | |
3702 | CALC_REGADDR(); | |
3703 | writeb(value, (void __iomem *)reg_addr); | |
3704 | } | |
3705 | ||
3706 | static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) | |
3707 | { | |
3708 | CALC_REGADDR(); | |
3709 | return readw((void __iomem *)reg_addr); | |
3710 | } | |
3711 | ||
3712 | static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) | |
3713 | { | |
3714 | CALC_REGADDR(); | |
3715 | writew(value, (void __iomem *)reg_addr); | |
3716 | } | |
3717 | ||
3718 | static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) | |
3719 | { | |
3720 | CALC_REGADDR(); | |
3721 | return readl((void __iomem *)reg_addr); | |
3722 | } | |
3723 | ||
3724 | static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) | |
3725 | { | |
3726 | CALC_REGADDR(); | |
3727 | writel(value, (void __iomem *)reg_addr); | |
3728 | } | |
3729 | ||
3730 | static void rdma_reset(struct slgt_info *info) | |
3731 | { | |
3732 | unsigned int i; | |
3733 | ||
3734 | /* set reset bit */ | |
3735 | wr_reg32(info, RDCSR, BIT1); | |
3736 | ||
3737 | /* wait for enable bit cleared */ | |
3738 | for(i=0 ; i < 1000 ; i++) | |
3739 | if (!(rd_reg32(info, RDCSR) & BIT0)) | |
3740 | break; | |
3741 | } | |
3742 | ||
3743 | static void tdma_reset(struct slgt_info *info) | |
3744 | { | |
3745 | unsigned int i; | |
3746 | ||
3747 | /* set reset bit */ | |
3748 | wr_reg32(info, TDCSR, BIT1); | |
3749 | ||
3750 | /* wait for enable bit cleared */ | |
3751 | for(i=0 ; i < 1000 ; i++) | |
3752 | if (!(rd_reg32(info, TDCSR) & BIT0)) | |
3753 | break; | |
3754 | } | |
3755 | ||
3756 | /* | |
3757 | * enable internal loopback | |
3758 | * TxCLK and RxCLK are generated from BRG | |
3759 | * and TxD is looped back to RxD internally. | |
3760 | */ | |
3761 | static void enable_loopback(struct slgt_info *info) | |
3762 | { | |
3763 | /* SCR (serial control) BIT2=looopback enable */ | |
3764 | wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); | |
3765 | ||
3766 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3767 | /* CCR (clock control) | |
3768 | * 07..05 tx clock source (010 = BRG) | |
3769 | * 04..02 rx clock source (010 = BRG) | |
3770 | * 01 auxclk enable (0 = disable) | |
3771 | * 00 BRG enable (1 = enable) | |
3772 | * | |
3773 | * 0100 1001 | |
3774 | */ | |
3775 | wr_reg8(info, CCR, 0x49); | |
3776 | ||
3777 | /* set speed if available, otherwise use default */ | |
3778 | if (info->params.clock_speed) | |
3779 | set_rate(info, info->params.clock_speed); | |
3780 | else | |
3781 | set_rate(info, 3686400); | |
3782 | } | |
3783 | } | |
3784 | ||
3785 | /* | |
3786 | * set baud rate generator to specified rate | |
3787 | */ | |
3788 | static void set_rate(struct slgt_info *info, u32 rate) | |
3789 | { | |
3790 | unsigned int div; | |
1f80769f | 3791 | unsigned int osc = info->base_clock; |
705b6c7b PF |
3792 | |
3793 | /* div = osc/rate - 1 | |
3794 | * | |
3795 | * Round div up if osc/rate is not integer to | |
3796 | * force to next slowest rate. | |
3797 | */ | |
3798 | ||
3799 | if (rate) { | |
3800 | div = osc/rate; | |
3801 | if (!(osc % rate) && div) | |
3802 | div--; | |
3803 | wr_reg16(info, BDR, (unsigned short)div); | |
3804 | } | |
3805 | } | |
3806 | ||
3807 | static void rx_stop(struct slgt_info *info) | |
3808 | { | |
3809 | unsigned short val; | |
3810 | ||
3811 | /* disable and reset receiver */ | |
3812 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3813 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3814 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3815 | ||
3816 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); | |
3817 | ||
3818 | /* clear pending rx interrupts */ | |
3819 | wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); | |
3820 | ||
3821 | rdma_reset(info); | |
3822 | ||
0fab6de0 JP |
3823 | info->rx_enabled = false; |
3824 | info->rx_restart = false; | |
705b6c7b PF |
3825 | } |
3826 | ||
3827 | static void rx_start(struct slgt_info *info) | |
3828 | { | |
3829 | unsigned short val; | |
3830 | ||
3831 | slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); | |
3832 | ||
3833 | /* clear pending rx overrun IRQ */ | |
3834 | wr_reg16(info, SSR, IRQ_RXOVER); | |
3835 | ||
3836 | /* reset and disable receiver */ | |
3837 | val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ | |
3838 | wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
3839 | wr_reg16(info, RCR, val); /* clear reset bit */ | |
3840 | ||
3841 | rdma_reset(info); | |
3842 | reset_rbufs(info); | |
3843 | ||
3844 | /* set 1st descriptor address */ | |
3845 | wr_reg32(info, RDDAR, info->rbufs[0].pdesc); | |
3846 | ||
3847 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3848 | /* enable rx DMA and DMA interrupt */ | |
3849 | wr_reg32(info, RDCSR, (BIT2 + BIT0)); | |
3850 | } else { | |
3851 | /* enable saving of rx status, rx DMA and DMA interrupt */ | |
3852 | wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); | |
3853 | } | |
3854 | ||
3855 | slgt_irq_on(info, IRQ_RXOVER); | |
3856 | ||
3857 | /* enable receiver */ | |
3858 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); | |
3859 | ||
0fab6de0 JP |
3860 | info->rx_restart = false; |
3861 | info->rx_enabled = true; | |
705b6c7b PF |
3862 | } |
3863 | ||
3864 | static void tx_start(struct slgt_info *info) | |
3865 | { | |
3866 | if (!info->tx_enabled) { | |
3867 | wr_reg16(info, TCR, | |
cb10dc9a | 3868 | (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); |
0fab6de0 | 3869 | info->tx_enabled = true; |
705b6c7b PF |
3870 | } |
3871 | ||
3872 | if (info->tx_count) { | |
0fab6de0 | 3873 | info->drop_rts_on_tx_done = false; |
705b6c7b PF |
3874 | |
3875 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
3876 | if (info->params.flags & HDLC_FLAG_AUTO_RTS) { | |
3877 | get_signals(info); | |
3878 | if (!(info->signals & SerialSignal_RTS)) { | |
3879 | info->signals |= SerialSignal_RTS; | |
3880 | set_signals(info); | |
0fab6de0 | 3881 | info->drop_rts_on_tx_done = true; |
705b6c7b PF |
3882 | } |
3883 | } | |
3884 | ||
3885 | slgt_irq_off(info, IRQ_TXDATA); | |
3886 | slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); | |
3887 | /* clear tx idle and underrun status bits */ | |
3888 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
40565f19 JS |
3889 | if (info->params.mode == MGSL_MODE_HDLC) |
3890 | mod_timer(&info->tx_timer, jiffies + | |
3891 | msecs_to_jiffies(5000)); | |
705b6c7b | 3892 | } else { |
705b6c7b PF |
3893 | slgt_irq_off(info, IRQ_TXDATA); |
3894 | slgt_irq_on(info, IRQ_TXIDLE); | |
3895 | /* clear tx idle status bit */ | |
3896 | wr_reg16(info, SSR, IRQ_TXIDLE); | |
705b6c7b | 3897 | } |
bb029c67 | 3898 | tdma_start(info); |
0fab6de0 | 3899 | info->tx_active = true; |
705b6c7b PF |
3900 | } |
3901 | } | |
3902 | ||
bb029c67 PF |
3903 | /* |
3904 | * start transmit DMA if inactive and there are unsent buffers | |
3905 | */ | |
3906 | static void tdma_start(struct slgt_info *info) | |
3907 | { | |
3908 | unsigned int i; | |
3909 | ||
3910 | if (rd_reg32(info, TDCSR) & BIT0) | |
3911 | return; | |
3912 | ||
3913 | /* transmit DMA inactive, check for unsent buffers */ | |
3914 | i = info->tbuf_start; | |
3915 | while (!desc_count(info->tbufs[i])) { | |
3916 | if (++i == info->tbuf_count) | |
3917 | i = 0; | |
3918 | if (i == info->tbuf_current) | |
3919 | return; | |
3920 | } | |
3921 | info->tbuf_start = i; | |
3922 | ||
3923 | /* there are unsent buffers, start transmit DMA */ | |
3924 | ||
3925 | /* reset needed if previous error condition */ | |
3926 | tdma_reset(info); | |
3927 | ||
3928 | /* set 1st descriptor address */ | |
3929 | wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); | |
8a38c285 | 3930 | wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */ |
bb029c67 PF |
3931 | } |
3932 | ||
705b6c7b PF |
3933 | static void tx_stop(struct slgt_info *info) |
3934 | { | |
3935 | unsigned short val; | |
3936 | ||
3937 | del_timer(&info->tx_timer); | |
3938 | ||
3939 | tdma_reset(info); | |
3940 | ||
3941 | /* reset and disable transmitter */ | |
3942 | val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ | |
3943 | wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ | |
705b6c7b PF |
3944 | |
3945 | slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); | |
3946 | ||
3947 | /* clear tx idle and underrun status bit */ | |
3948 | wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); | |
3949 | ||
3950 | reset_tbufs(info); | |
3951 | ||
0fab6de0 JP |
3952 | info->tx_enabled = false; |
3953 | info->tx_active = false; | |
705b6c7b PF |
3954 | } |
3955 | ||
3956 | static void reset_port(struct slgt_info *info) | |
3957 | { | |
3958 | if (!info->reg_addr) | |
3959 | return; | |
3960 | ||
3961 | tx_stop(info); | |
3962 | rx_stop(info); | |
3963 | ||
3964 | info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS); | |
3965 | set_signals(info); | |
3966 | ||
3967 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
3968 | } | |
3969 | ||
3970 | static void reset_adapter(struct slgt_info *info) | |
3971 | { | |
3972 | int i; | |
3973 | for (i=0; i < info->port_count; ++i) { | |
3974 | if (info->port_array[i]) | |
3975 | reset_port(info->port_array[i]); | |
3976 | } | |
3977 | } | |
3978 | ||
3979 | static void async_mode(struct slgt_info *info) | |
3980 | { | |
3981 | unsigned short val; | |
3982 | ||
3983 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
3984 | tx_stop(info); | |
3985 | rx_stop(info); | |
3986 | ||
3987 | /* TCR (tx control) | |
3988 | * | |
3989 | * 15..13 mode, 010=async | |
3990 | * 12..10 encoding, 000=NRZ | |
3991 | * 09 parity enable | |
3992 | * 08 1=odd parity, 0=even parity | |
3993 | * 07 1=RTS driver control | |
3994 | * 06 1=break enable | |
3995 | * 05..04 character length | |
3996 | * 00=5 bits | |
3997 | * 01=6 bits | |
3998 | * 10=7 bits | |
3999 | * 11=8 bits | |
4000 | * 03 0=1 stop bit, 1=2 stop bits | |
4001 | * 02 reset | |
4002 | * 01 enable | |
4003 | * 00 auto-CTS enable | |
4004 | */ | |
4005 | val = 0x4000; | |
4006 | ||
4007 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) | |
4008 | val |= BIT7; | |
4009 | ||
4010 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4011 | val |= BIT9; | |
4012 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4013 | val |= BIT8; | |
4014 | } | |
4015 | ||
4016 | switch (info->params.data_bits) | |
4017 | { | |
4018 | case 6: val |= BIT4; break; | |
4019 | case 7: val |= BIT5; break; | |
4020 | case 8: val |= BIT5 + BIT4; break; | |
4021 | } | |
4022 | ||
4023 | if (info->params.stop_bits != 1) | |
4024 | val |= BIT3; | |
4025 | ||
4026 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4027 | val |= BIT0; | |
4028 | ||
4029 | wr_reg16(info, TCR, val); | |
4030 | ||
4031 | /* RCR (rx control) | |
4032 | * | |
4033 | * 15..13 mode, 010=async | |
4034 | * 12..10 encoding, 000=NRZ | |
4035 | * 09 parity enable | |
4036 | * 08 1=odd parity, 0=even parity | |
4037 | * 07..06 reserved, must be 0 | |
4038 | * 05..04 character length | |
4039 | * 00=5 bits | |
4040 | * 01=6 bits | |
4041 | * 10=7 bits | |
4042 | * 11=8 bits | |
4043 | * 03 reserved, must be zero | |
4044 | * 02 reset | |
4045 | * 01 enable | |
4046 | * 00 auto-DCD enable | |
4047 | */ | |
4048 | val = 0x4000; | |
4049 | ||
4050 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4051 | val |= BIT9; | |
4052 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4053 | val |= BIT8; | |
4054 | } | |
4055 | ||
4056 | switch (info->params.data_bits) | |
4057 | { | |
4058 | case 6: val |= BIT4; break; | |
4059 | case 7: val |= BIT5; break; | |
4060 | case 8: val |= BIT5 + BIT4; break; | |
4061 | } | |
4062 | ||
4063 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4064 | val |= BIT0; | |
4065 | ||
4066 | wr_reg16(info, RCR, val); | |
4067 | ||
4068 | /* CCR (clock control) | |
4069 | * | |
4070 | * 07..05 011 = tx clock source is BRG/16 | |
4071 | * 04..02 010 = rx clock source is BRG | |
4072 | * 01 0 = auxclk disabled | |
4073 | * 00 1 = BRG enabled | |
4074 | * | |
4075 | * 0110 1001 | |
4076 | */ | |
4077 | wr_reg8(info, CCR, 0x69); | |
4078 | ||
4079 | msc_set_vcr(info); | |
4080 | ||
705b6c7b PF |
4081 | /* SCR (serial control) |
4082 | * | |
4083 | * 15 1=tx req on FIFO half empty | |
4084 | * 14 1=rx req on FIFO half full | |
4085 | * 13 tx data IRQ enable | |
4086 | * 12 tx idle IRQ enable | |
4087 | * 11 rx break on IRQ enable | |
4088 | * 10 rx data IRQ enable | |
4089 | * 09 rx break off IRQ enable | |
4090 | * 08 overrun IRQ enable | |
4091 | * 07 DSR IRQ enable | |
4092 | * 06 CTS IRQ enable | |
4093 | * 05 DCD IRQ enable | |
4094 | * 04 RI IRQ enable | |
1f80769f | 4095 | * 03 0=16x sampling, 1=8x sampling |
705b6c7b PF |
4096 | * 02 1=txd->rxd internal loopback enable |
4097 | * 01 reserved, must be zero | |
4098 | * 00 1=master IRQ enable | |
4099 | */ | |
4100 | val = BIT15 + BIT14 + BIT0; | |
1f80769f PF |
4101 | /* JCR[8] : 1 = x8 async mode feature available */ |
4102 | if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && | |
4103 | ((info->base_clock < (info->params.data_rate * 16)) || | |
4104 | (info->base_clock % (info->params.data_rate * 16)))) { | |
4105 | /* use 8x sampling */ | |
4106 | val |= BIT3; | |
4107 | set_rate(info, info->params.data_rate * 8); | |
4108 | } else { | |
4109 | /* use 16x sampling */ | |
4110 | set_rate(info, info->params.data_rate * 16); | |
4111 | } | |
705b6c7b PF |
4112 | wr_reg16(info, SCR, val); |
4113 | ||
4114 | slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); | |
4115 | ||
705b6c7b PF |
4116 | if (info->params.loopback) |
4117 | enable_loopback(info); | |
4118 | } | |
4119 | ||
cb10dc9a | 4120 | static void sync_mode(struct slgt_info *info) |
705b6c7b PF |
4121 | { |
4122 | unsigned short val; | |
4123 | ||
4124 | slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); | |
4125 | tx_stop(info); | |
4126 | rx_stop(info); | |
4127 | ||
4128 | /* TCR (tx control) | |
4129 | * | |
cb10dc9a | 4130 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4131 | * 12..10 encoding |
4132 | * 09 CRC enable | |
4133 | * 08 CRC32 | |
4134 | * 07 1=RTS driver control | |
4135 | * 06 preamble enable | |
4136 | * 05..04 preamble length | |
4137 | * 03 share open/close flag | |
4138 | * 02 reset | |
4139 | * 01 enable | |
4140 | * 00 auto-CTS enable | |
4141 | */ | |
993456cd | 4142 | val = BIT2; |
705b6c7b | 4143 | |
cb10dc9a PF |
4144 | switch(info->params.mode) { |
4145 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4146 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4147 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4148 | } | |
705b6c7b PF |
4149 | if (info->if_mode & MGSL_INTERFACE_RTS_EN) |
4150 | val |= BIT7; | |
4151 | ||
4152 | switch(info->params.encoding) | |
4153 | { | |
4154 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4155 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4156 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4157 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4158 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4159 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4160 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4161 | } | |
4162 | ||
04b374d0 | 4163 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4164 | { |
4165 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4166 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4167 | } | |
4168 | ||
4169 | if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) | |
4170 | val |= BIT6; | |
4171 | ||
4172 | switch (info->params.preamble_length) | |
4173 | { | |
4174 | case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; | |
4175 | case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; | |
4176 | case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; | |
4177 | } | |
4178 | ||
4179 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4180 | val |= BIT0; | |
4181 | ||
4182 | wr_reg16(info, TCR, val); | |
4183 | ||
4184 | /* TPR (transmit preamble) */ | |
4185 | ||
4186 | switch (info->params.preamble) | |
4187 | { | |
4188 | case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; | |
4189 | case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; | |
4190 | case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; | |
4191 | case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; | |
4192 | case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; | |
4193 | default: val = 0x7e; break; | |
4194 | } | |
4195 | wr_reg8(info, TPR, (unsigned char)val); | |
4196 | ||
4197 | /* RCR (rx control) | |
4198 | * | |
cb10dc9a | 4199 | * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync |
705b6c7b PF |
4200 | * 12..10 encoding |
4201 | * 09 CRC enable | |
4202 | * 08 CRC32 | |
4203 | * 07..03 reserved, must be 0 | |
4204 | * 02 reset | |
4205 | * 01 enable | |
4206 | * 00 auto-DCD enable | |
4207 | */ | |
4208 | val = 0; | |
4209 | ||
cb10dc9a PF |
4210 | switch(info->params.mode) { |
4211 | case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; | |
4212 | case MGSL_MODE_BISYNC: val |= BIT15; break; | |
4213 | case MGSL_MODE_RAW: val |= BIT13; break; | |
4214 | } | |
705b6c7b PF |
4215 | |
4216 | switch(info->params.encoding) | |
4217 | { | |
4218 | case HDLC_ENCODING_NRZB: val |= BIT10; break; | |
4219 | case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; | |
4220 | case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; | |
4221 | case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; | |
4222 | case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; | |
4223 | case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; | |
4224 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; | |
4225 | } | |
4226 | ||
04b374d0 | 4227 | switch (info->params.crc_type & HDLC_CRC_MASK) |
705b6c7b PF |
4228 | { |
4229 | case HDLC_CRC_16_CCITT: val |= BIT9; break; | |
4230 | case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; | |
4231 | } | |
4232 | ||
4233 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4234 | val |= BIT0; | |
4235 | ||
4236 | wr_reg16(info, RCR, val); | |
4237 | ||
4238 | /* CCR (clock control) | |
4239 | * | |
4240 | * 07..05 tx clock source | |
4241 | * 04..02 rx clock source | |
4242 | * 01 auxclk enable | |
4243 | * 00 BRG enable | |
4244 | */ | |
4245 | val = 0; | |
4246 | ||
4247 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4248 | { | |
4249 | // when RxC source is DPLL, BRG generates 16X DPLL | |
4250 | // reference clock, so take TxC from BRG/16 to get | |
4251 | // transmit clock at actual data rate | |
4252 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4253 | val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ | |
4254 | else | |
4255 | val |= BIT6; /* 010, txclk = BRG */ | |
4256 | } | |
4257 | else if (info->params.flags & HDLC_FLAG_TXC_DPLL) | |
4258 | val |= BIT7; /* 100, txclk = DPLL Input */ | |
4259 | else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) | |
4260 | val |= BIT5; /* 001, txclk = RXC Input */ | |
4261 | ||
4262 | if (info->params.flags & HDLC_FLAG_RXC_BRG) | |
4263 | val |= BIT3; /* 010, rxclk = BRG */ | |
4264 | else if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4265 | val |= BIT4; /* 100, rxclk = DPLL */ | |
4266 | else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) | |
4267 | val |= BIT2; /* 001, rxclk = TXC Input */ | |
4268 | ||
4269 | if (info->params.clock_speed) | |
4270 | val |= BIT1 + BIT0; | |
4271 | ||
4272 | wr_reg8(info, CCR, (unsigned char)val); | |
4273 | ||
4274 | if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) | |
4275 | { | |
4276 | // program DPLL mode | |
4277 | switch(info->params.encoding) | |
4278 | { | |
4279 | case HDLC_ENCODING_BIPHASE_MARK: | |
4280 | case HDLC_ENCODING_BIPHASE_SPACE: | |
4281 | val = BIT7; break; | |
4282 | case HDLC_ENCODING_BIPHASE_LEVEL: | |
4283 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: | |
4284 | val = BIT7 + BIT6; break; | |
4285 | default: val = BIT6; // NRZ encodings | |
4286 | } | |
4287 | wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); | |
4288 | ||
4289 | // DPLL requires a 16X reference clock from BRG | |
4290 | set_rate(info, info->params.clock_speed * 16); | |
4291 | } | |
4292 | else | |
4293 | set_rate(info, info->params.clock_speed); | |
4294 | ||
4295 | tx_set_idle(info); | |
4296 | ||
4297 | msc_set_vcr(info); | |
4298 | ||
4299 | /* SCR (serial control) | |
4300 | * | |
4301 | * 15 1=tx req on FIFO half empty | |
4302 | * 14 1=rx req on FIFO half full | |
4303 | * 13 tx data IRQ enable | |
4304 | * 12 tx idle IRQ enable | |
4305 | * 11 underrun IRQ enable | |
4306 | * 10 rx data IRQ enable | |
4307 | * 09 rx idle IRQ enable | |
4308 | * 08 overrun IRQ enable | |
4309 | * 07 DSR IRQ enable | |
4310 | * 06 CTS IRQ enable | |
4311 | * 05 DCD IRQ enable | |
4312 | * 04 RI IRQ enable | |
4313 | * 03 reserved, must be zero | |
4314 | * 02 1=txd->rxd internal loopback enable | |
4315 | * 01 reserved, must be zero | |
4316 | * 00 1=master IRQ enable | |
4317 | */ | |
4318 | wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); | |
4319 | ||
4320 | if (info->params.loopback) | |
4321 | enable_loopback(info); | |
4322 | } | |
4323 | ||
4324 | /* | |
4325 | * set transmit idle mode | |
4326 | */ | |
4327 | static void tx_set_idle(struct slgt_info *info) | |
4328 | { | |
643f3319 PF |
4329 | unsigned char val; |
4330 | unsigned short tcr; | |
705b6c7b | 4331 | |
643f3319 PF |
4332 | /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits |
4333 | * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits | |
4334 | */ | |
4335 | tcr = rd_reg16(info, TCR); | |
4336 | if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { | |
4337 | /* disable preamble, set idle size to 16 bits */ | |
4338 | tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; | |
4339 | /* MSB of 16 bit idle specified in tx preamble register (TPR) */ | |
4340 | wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); | |
4341 | } else if (!(tcr & BIT6)) { | |
4342 | /* preamble is disabled, set idle size to 8 bits */ | |
4343 | tcr &= ~(BIT5 + BIT4); | |
4344 | } | |
4345 | wr_reg16(info, TCR, tcr); | |
4346 | ||
4347 | if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { | |
4348 | /* LSB of custom tx idle specified in tx idle register */ | |
4349 | val = (unsigned char)(info->idle_mode & 0xff); | |
4350 | } else { | |
4351 | /* standard 8 bit idle patterns */ | |
4352 | switch(info->idle_mode) | |
4353 | { | |
4354 | case HDLC_TXIDLE_FLAGS: val = 0x7e; break; | |
4355 | case HDLC_TXIDLE_ALT_ZEROS_ONES: | |
4356 | case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; | |
4357 | case HDLC_TXIDLE_ZEROS: | |
4358 | case HDLC_TXIDLE_SPACE: val = 0x00; break; | |
4359 | default: val = 0xff; | |
4360 | } | |
705b6c7b PF |
4361 | } |
4362 | ||
4363 | wr_reg8(info, TIR, val); | |
4364 | } | |
4365 | ||
4366 | /* | |
4367 | * get state of V24 status (input) signals | |
4368 | */ | |
4369 | static void get_signals(struct slgt_info *info) | |
4370 | { | |
4371 | unsigned short status = rd_reg16(info, SSR); | |
4372 | ||
4373 | /* clear all serial signals except DTR and RTS */ | |
4374 | info->signals &= SerialSignal_DTR + SerialSignal_RTS; | |
4375 | ||
4376 | if (status & BIT3) | |
4377 | info->signals |= SerialSignal_DSR; | |
4378 | if (status & BIT2) | |
4379 | info->signals |= SerialSignal_CTS; | |
4380 | if (status & BIT1) | |
4381 | info->signals |= SerialSignal_DCD; | |
4382 | if (status & BIT0) | |
4383 | info->signals |= SerialSignal_RI; | |
4384 | } | |
4385 | ||
4386 | /* | |
4387 | * set V.24 Control Register based on current configuration | |
4388 | */ | |
4389 | static void msc_set_vcr(struct slgt_info *info) | |
4390 | { | |
4391 | unsigned char val = 0; | |
4392 | ||
4393 | /* VCR (V.24 control) | |
4394 | * | |
4395 | * 07..04 serial IF select | |
4396 | * 03 DTR | |
4397 | * 02 RTS | |
4398 | * 01 LL | |
4399 | * 00 RL | |
4400 | */ | |
4401 | ||
4402 | switch(info->if_mode & MGSL_INTERFACE_MASK) | |
4403 | { | |
4404 | case MGSL_INTERFACE_RS232: | |
4405 | val |= BIT5; /* 0010 */ | |
4406 | break; | |
4407 | case MGSL_INTERFACE_V35: | |
4408 | val |= BIT7 + BIT6 + BIT5; /* 1110 */ | |
4409 | break; | |
4410 | case MGSL_INTERFACE_RS422: | |
4411 | val |= BIT6; /* 0100 */ | |
4412 | break; | |
4413 | } | |
4414 | ||
e5590717 PF |
4415 | if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) |
4416 | val |= BIT4; | |
705b6c7b PF |
4417 | if (info->signals & SerialSignal_DTR) |
4418 | val |= BIT3; | |
4419 | if (info->signals & SerialSignal_RTS) | |
4420 | val |= BIT2; | |
4421 | if (info->if_mode & MGSL_INTERFACE_LL) | |
4422 | val |= BIT1; | |
4423 | if (info->if_mode & MGSL_INTERFACE_RL) | |
4424 | val |= BIT0; | |
4425 | wr_reg8(info, VCR, val); | |
4426 | } | |
4427 | ||
4428 | /* | |
4429 | * set state of V24 control (output) signals | |
4430 | */ | |
4431 | static void set_signals(struct slgt_info *info) | |
4432 | { | |
4433 | unsigned char val = rd_reg8(info, VCR); | |
4434 | if (info->signals & SerialSignal_DTR) | |
4435 | val |= BIT3; | |
4436 | else | |
4437 | val &= ~BIT3; | |
4438 | if (info->signals & SerialSignal_RTS) | |
4439 | val |= BIT2; | |
4440 | else | |
4441 | val &= ~BIT2; | |
4442 | wr_reg8(info, VCR, val); | |
4443 | } | |
4444 | ||
4445 | /* | |
4446 | * free range of receive DMA buffers (i to last) | |
4447 | */ | |
4448 | static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) | |
4449 | { | |
4450 | int done = 0; | |
4451 | ||
4452 | while(!done) { | |
4453 | /* reset current buffer for reuse */ | |
4454 | info->rbufs[i].status = 0; | |
814dae03 | 4455 | set_desc_count(info->rbufs[i], info->rbuf_fill_level); |
705b6c7b PF |
4456 | if (i == last) |
4457 | done = 1; | |
4458 | if (++i == info->rbuf_count) | |
4459 | i = 0; | |
4460 | } | |
4461 | info->rbuf_current = i; | |
4462 | } | |
4463 | ||
4464 | /* | |
4465 | * mark all receive DMA buffers as free | |
4466 | */ | |
4467 | static void reset_rbufs(struct slgt_info *info) | |
4468 | { | |
4469 | free_rbufs(info, 0, info->rbuf_count - 1); | |
4470 | } | |
4471 | ||
4472 | /* | |
4473 | * pass receive HDLC frame to upper layer | |
4474 | * | |
0fab6de0 | 4475 | * return true if frame available, otherwise false |
705b6c7b | 4476 | */ |
0fab6de0 | 4477 | static bool rx_get_frame(struct slgt_info *info) |
705b6c7b PF |
4478 | { |
4479 | unsigned int start, end; | |
4480 | unsigned short status; | |
4481 | unsigned int framesize = 0; | |
705b6c7b | 4482 | unsigned long flags; |
8fb06c77 | 4483 | struct tty_struct *tty = info->port.tty; |
705b6c7b | 4484 | unsigned char addr_field = 0xff; |
04b374d0 PF |
4485 | unsigned int crc_size = 0; |
4486 | ||
4487 | switch (info->params.crc_type & HDLC_CRC_MASK) { | |
4488 | case HDLC_CRC_16_CCITT: crc_size = 2; break; | |
4489 | case HDLC_CRC_32_CCITT: crc_size = 4; break; | |
4490 | } | |
705b6c7b PF |
4491 | |
4492 | check_again: | |
4493 | ||
4494 | framesize = 0; | |
4495 | addr_field = 0xff; | |
4496 | start = end = info->rbuf_current; | |
4497 | ||
4498 | for (;;) { | |
4499 | if (!desc_complete(info->rbufs[end])) | |
4500 | goto cleanup; | |
4501 | ||
4502 | if (framesize == 0 && info->params.addr_filter != 0xff) | |
4503 | addr_field = info->rbufs[end].buf[0]; | |
4504 | ||
4505 | framesize += desc_count(info->rbufs[end]); | |
4506 | ||
4507 | if (desc_eof(info->rbufs[end])) | |
4508 | break; | |
4509 | ||
4510 | if (++end == info->rbuf_count) | |
4511 | end = 0; | |
4512 | ||
4513 | if (end == info->rbuf_current) { | |
4514 | if (info->rx_enabled){ | |
4515 | spin_lock_irqsave(&info->lock,flags); | |
4516 | rx_start(info); | |
4517 | spin_unlock_irqrestore(&info->lock,flags); | |
4518 | } | |
4519 | goto cleanup; | |
4520 | } | |
4521 | } | |
4522 | ||
4523 | /* status | |
4524 | * | |
4525 | * 15 buffer complete | |
4526 | * 14..06 reserved | |
4527 | * 05..04 residue | |
4528 | * 02 eof (end of frame) | |
4529 | * 01 CRC error | |
4530 | * 00 abort | |
4531 | */ | |
4532 | status = desc_status(info->rbufs[end]); | |
4533 | ||
4534 | /* ignore CRC bit if not using CRC (bit is undefined) */ | |
04b374d0 | 4535 | if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) |
705b6c7b PF |
4536 | status &= ~BIT1; |
4537 | ||
4538 | if (framesize == 0 || | |
4539 | (addr_field != 0xff && addr_field != info->params.addr_filter)) { | |
4540 | free_rbufs(info, start, end); | |
4541 | goto check_again; | |
4542 | } | |
4543 | ||
04b374d0 PF |
4544 | if (framesize < (2 + crc_size) || status & BIT0) { |
4545 | info->icount.rxshort++; | |
705b6c7b | 4546 | framesize = 0; |
04b374d0 PF |
4547 | } else if (status & BIT1) { |
4548 | info->icount.rxcrc++; | |
4549 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) | |
4550 | framesize = 0; | |
4551 | } | |
705b6c7b | 4552 | |
af69c7f9 | 4553 | #if SYNCLINK_GENERIC_HDLC |
04b374d0 | 4554 | if (framesize == 0) { |
198191c4 KH |
4555 | info->netdev->stats.rx_errors++; |
4556 | info->netdev->stats.rx_frame_errors++; | |
705b6c7b | 4557 | } |
04b374d0 | 4558 | #endif |
705b6c7b PF |
4559 | |
4560 | DBGBH(("%s rx frame status=%04X size=%d\n", | |
4561 | info->device_name, status, framesize)); | |
814dae03 | 4562 | DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); |
705b6c7b PF |
4563 | |
4564 | if (framesize) { | |
04b374d0 PF |
4565 | if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { |
4566 | framesize -= crc_size; | |
4567 | crc_size = 0; | |
4568 | } | |
4569 | ||
4570 | if (framesize > info->max_frame_size + crc_size) | |
705b6c7b PF |
4571 | info->icount.rxlong++; |
4572 | else { | |
4573 | /* copy dma buffer(s) to contiguous temp buffer */ | |
4574 | int copy_count = framesize; | |
4575 | int i = start; | |
4576 | unsigned char *p = info->tmp_rbuf; | |
4577 | info->tmp_rbuf_count = framesize; | |
4578 | ||
4579 | info->icount.rxok++; | |
4580 | ||
4581 | while(copy_count) { | |
814dae03 | 4582 | int partial_count = min_t(int, copy_count, info->rbuf_fill_level); |
705b6c7b PF |
4583 | memcpy(p, info->rbufs[i].buf, partial_count); |
4584 | p += partial_count; | |
4585 | copy_count -= partial_count; | |
4586 | if (++i == info->rbuf_count) | |
4587 | i = 0; | |
4588 | } | |
4589 | ||
04b374d0 PF |
4590 | if (info->params.crc_type & HDLC_CRC_RETURN_EX) { |
4591 | *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; | |
4592 | framesize++; | |
4593 | } | |
4594 | ||
af69c7f9 | 4595 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
4596 | if (info->netcount) |
4597 | hdlcdev_rx(info,info->tmp_rbuf, framesize); | |
4598 | else | |
4599 | #endif | |
4600 | ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); | |
4601 | } | |
4602 | } | |
4603 | free_rbufs(info, start, end); | |
0fab6de0 | 4604 | return true; |
705b6c7b PF |
4605 | |
4606 | cleanup: | |
0fab6de0 | 4607 | return false; |
705b6c7b PF |
4608 | } |
4609 | ||
4610 | /* | |
4611 | * pass receive buffer (RAW synchronous mode) to tty layer | |
0fab6de0 | 4612 | * return true if buffer available, otherwise false |
705b6c7b | 4613 | */ |
0fab6de0 | 4614 | static bool rx_get_buf(struct slgt_info *info) |
705b6c7b PF |
4615 | { |
4616 | unsigned int i = info->rbuf_current; | |
cb10dc9a | 4617 | unsigned int count; |
705b6c7b PF |
4618 | |
4619 | if (!desc_complete(info->rbufs[i])) | |
0fab6de0 | 4620 | return false; |
cb10dc9a PF |
4621 | count = desc_count(info->rbufs[i]); |
4622 | switch(info->params.mode) { | |
4623 | case MGSL_MODE_MONOSYNC: | |
4624 | case MGSL_MODE_BISYNC: | |
4625 | /* ignore residue in byte synchronous modes */ | |
4626 | if (desc_residue(info->rbufs[i])) | |
4627 | count--; | |
4628 | break; | |
4629 | } | |
4630 | DBGDATA(info, info->rbufs[i].buf, count, "rx"); | |
4631 | DBGINFO(("rx_get_buf size=%d\n", count)); | |
4632 | if (count) | |
8fb06c77 | 4633 | ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, |
cb10dc9a | 4634 | info->flag_buf, count); |
705b6c7b | 4635 | free_rbufs(info, i, i); |
0fab6de0 | 4636 | return true; |
705b6c7b PF |
4637 | } |
4638 | ||
4639 | static void reset_tbufs(struct slgt_info *info) | |
4640 | { | |
4641 | unsigned int i; | |
4642 | info->tbuf_current = 0; | |
4643 | for (i=0 ; i < info->tbuf_count ; i++) { | |
4644 | info->tbufs[i].status = 0; | |
4645 | info->tbufs[i].count = 0; | |
4646 | } | |
4647 | } | |
4648 | ||
4649 | /* | |
4650 | * return number of free transmit DMA buffers | |
4651 | */ | |
4652 | static unsigned int free_tbuf_count(struct slgt_info *info) | |
4653 | { | |
4654 | unsigned int count = 0; | |
4655 | unsigned int i = info->tbuf_current; | |
4656 | ||
4657 | do | |
4658 | { | |
4659 | if (desc_count(info->tbufs[i])) | |
4660 | break; /* buffer in use */ | |
4661 | ++count; | |
4662 | if (++i == info->tbuf_count) | |
4663 | i=0; | |
4664 | } while (i != info->tbuf_current); | |
4665 | ||
bb029c67 PF |
4666 | /* if tx DMA active, last zero count buffer is in use */ |
4667 | if (count && (rd_reg32(info, TDCSR) & BIT0)) | |
705b6c7b PF |
4668 | --count; |
4669 | ||
4670 | return count; | |
4671 | } | |
4672 | ||
403214d0 PF |
4673 | /* |
4674 | * return number of bytes in unsent transmit DMA buffers | |
4675 | * and the serial controller tx FIFO | |
4676 | */ | |
4677 | static unsigned int tbuf_bytes(struct slgt_info *info) | |
4678 | { | |
4679 | unsigned int total_count = 0; | |
4680 | unsigned int i = info->tbuf_current; | |
4681 | unsigned int reg_value; | |
4682 | unsigned int count; | |
4683 | unsigned int active_buf_count = 0; | |
4684 | ||
4685 | /* | |
4686 | * Add descriptor counts for all tx DMA buffers. | |
4687 | * If count is zero (cleared by DMA controller after read), | |
4688 | * the buffer is complete or is actively being read from. | |
4689 | * | |
4690 | * Record buf_count of last buffer with zero count starting | |
4691 | * from current ring position. buf_count is mirror | |
4692 | * copy of count and is not cleared by serial controller. | |
4693 | * If DMA controller is active, that buffer is actively | |
4694 | * being read so add to total. | |
4695 | */ | |
4696 | do { | |
4697 | count = desc_count(info->tbufs[i]); | |
4698 | if (count) | |
4699 | total_count += count; | |
4700 | else if (!total_count) | |
4701 | active_buf_count = info->tbufs[i].buf_count; | |
4702 | if (++i == info->tbuf_count) | |
4703 | i = 0; | |
4704 | } while (i != info->tbuf_current); | |
4705 | ||
4706 | /* read tx DMA status register */ | |
4707 | reg_value = rd_reg32(info, TDCSR); | |
4708 | ||
4709 | /* if tx DMA active, last zero count buffer is in use */ | |
4710 | if (reg_value & BIT0) | |
4711 | total_count += active_buf_count; | |
4712 | ||
4713 | /* add tx FIFO count = reg_value[15..8] */ | |
4714 | total_count += (reg_value >> 8) & 0xff; | |
4715 | ||
4716 | /* if transmitter active add one byte for shift register */ | |
4717 | if (info->tx_active) | |
4718 | total_count++; | |
4719 | ||
4720 | return total_count; | |
4721 | } | |
4722 | ||
705b6c7b PF |
4723 | /* |
4724 | * load transmit DMA buffer(s) with data | |
4725 | */ | |
4726 | static void tx_load(struct slgt_info *info, const char *buf, unsigned int size) | |
4727 | { | |
4728 | unsigned short count; | |
4729 | unsigned int i; | |
4730 | struct slgt_desc *d; | |
4731 | ||
4732 | if (size == 0) | |
4733 | return; | |
4734 | ||
4735 | DBGDATA(info, buf, size, "tx"); | |
4736 | ||
4737 | info->tbuf_start = i = info->tbuf_current; | |
4738 | ||
4739 | while (size) { | |
4740 | d = &info->tbufs[i]; | |
4741 | if (++i == info->tbuf_count) | |
4742 | i = 0; | |
4743 | ||
4744 | count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); | |
4745 | memcpy(d->buf, buf, count); | |
4746 | ||
4747 | size -= count; | |
4748 | buf += count; | |
4749 | ||
cb10dc9a PF |
4750 | /* |
4751 | * set EOF bit for last buffer of HDLC frame or | |
4752 | * for every buffer in raw mode | |
4753 | */ | |
4754 | if ((!size && info->params.mode == MGSL_MODE_HDLC) || | |
4755 | info->params.mode == MGSL_MODE_RAW) | |
4756 | set_desc_eof(*d, 1); | |
705b6c7b PF |
4757 | else |
4758 | set_desc_eof(*d, 0); | |
4759 | ||
4760 | set_desc_count(*d, count); | |
403214d0 | 4761 | d->buf_count = count; |
705b6c7b PF |
4762 | } |
4763 | ||
4764 | info->tbuf_current = i; | |
4765 | } | |
4766 | ||
4767 | static int register_test(struct slgt_info *info) | |
4768 | { | |
4769 | static unsigned short patterns[] = | |
4770 | {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; | |
4771 | static unsigned int count = sizeof(patterns)/sizeof(patterns[0]); | |
4772 | unsigned int i; | |
4773 | int rc = 0; | |
4774 | ||
4775 | for (i=0 ; i < count ; i++) { | |
4776 | wr_reg16(info, TIR, patterns[i]); | |
4777 | wr_reg16(info, BDR, patterns[(i+1)%count]); | |
4778 | if ((rd_reg16(info, TIR) != patterns[i]) || | |
4779 | (rd_reg16(info, BDR) != patterns[(i+1)%count])) { | |
4780 | rc = -ENODEV; | |
4781 | break; | |
4782 | } | |
4783 | } | |
0080b7aa | 4784 | info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; |
705b6c7b PF |
4785 | info->init_error = rc ? 0 : DiagStatus_AddressFailure; |
4786 | return rc; | |
4787 | } | |
4788 | ||
4789 | static int irq_test(struct slgt_info *info) | |
4790 | { | |
4791 | unsigned long timeout; | |
4792 | unsigned long flags; | |
8fb06c77 | 4793 | struct tty_struct *oldtty = info->port.tty; |
705b6c7b PF |
4794 | u32 speed = info->params.data_rate; |
4795 | ||
4796 | info->params.data_rate = 921600; | |
8fb06c77 | 4797 | info->port.tty = NULL; |
705b6c7b PF |
4798 | |
4799 | spin_lock_irqsave(&info->lock, flags); | |
4800 | async_mode(info); | |
4801 | slgt_irq_on(info, IRQ_TXIDLE); | |
4802 | ||
4803 | /* enable transmitter */ | |
4804 | wr_reg16(info, TCR, | |
4805 | (unsigned short)(rd_reg16(info, TCR) | BIT1)); | |
4806 | ||
4807 | /* write one byte and wait for tx idle */ | |
4808 | wr_reg16(info, TDR, 0); | |
4809 | ||
4810 | /* assume failure */ | |
4811 | info->init_error = DiagStatus_IrqFailure; | |
0fab6de0 | 4812 | info->irq_occurred = false; |
705b6c7b PF |
4813 | |
4814 | spin_unlock_irqrestore(&info->lock, flags); | |
4815 | ||
4816 | timeout=100; | |
4817 | while(timeout-- && !info->irq_occurred) | |
4818 | msleep_interruptible(10); | |
4819 | ||
4820 | spin_lock_irqsave(&info->lock,flags); | |
4821 | reset_port(info); | |
4822 | spin_unlock_irqrestore(&info->lock,flags); | |
4823 | ||
4824 | info->params.data_rate = speed; | |
8fb06c77 | 4825 | info->port.tty = oldtty; |
705b6c7b PF |
4826 | |
4827 | info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; | |
4828 | return info->irq_occurred ? 0 : -ENODEV; | |
4829 | } | |
4830 | ||
4831 | static int loopback_test_rx(struct slgt_info *info) | |
4832 | { | |
4833 | unsigned char *src, *dest; | |
4834 | int count; | |
4835 | ||
4836 | if (desc_complete(info->rbufs[0])) { | |
4837 | count = desc_count(info->rbufs[0]); | |
4838 | src = info->rbufs[0].buf; | |
4839 | dest = info->tmp_rbuf; | |
4840 | ||
4841 | for( ; count ; count-=2, src+=2) { | |
4842 | /* src=data byte (src+1)=status byte */ | |
4843 | if (!(*(src+1) & (BIT9 + BIT8))) { | |
4844 | *dest = *src; | |
4845 | dest++; | |
4846 | info->tmp_rbuf_count++; | |
4847 | } | |
4848 | } | |
4849 | DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); | |
4850 | return 1; | |
4851 | } | |
4852 | return 0; | |
4853 | } | |
4854 | ||
4855 | static int loopback_test(struct slgt_info *info) | |
4856 | { | |
4857 | #define TESTFRAMESIZE 20 | |
4858 | ||
4859 | unsigned long timeout; | |
4860 | u16 count = TESTFRAMESIZE; | |
4861 | unsigned char buf[TESTFRAMESIZE]; | |
4862 | int rc = -ENODEV; | |
4863 | unsigned long flags; | |
4864 | ||
8fb06c77 | 4865 | struct tty_struct *oldtty = info->port.tty; |
705b6c7b PF |
4866 | MGSL_PARAMS params; |
4867 | ||
4868 | memcpy(¶ms, &info->params, sizeof(params)); | |
4869 | ||
4870 | info->params.mode = MGSL_MODE_ASYNC; | |
4871 | info->params.data_rate = 921600; | |
4872 | info->params.loopback = 1; | |
8fb06c77 | 4873 | info->port.tty = NULL; |
705b6c7b PF |
4874 | |
4875 | /* build and send transmit frame */ | |
4876 | for (count = 0; count < TESTFRAMESIZE; ++count) | |
4877 | buf[count] = (unsigned char)count; | |
4878 | ||
4879 | info->tmp_rbuf_count = 0; | |
4880 | memset(info->tmp_rbuf, 0, TESTFRAMESIZE); | |
4881 | ||
4882 | /* program hardware for HDLC and enabled receiver */ | |
4883 | spin_lock_irqsave(&info->lock,flags); | |
4884 | async_mode(info); | |
4885 | rx_start(info); | |
4886 | info->tx_count = count; | |
4887 | tx_load(info, buf, count); | |
4888 | tx_start(info); | |
4889 | spin_unlock_irqrestore(&info->lock, flags); | |
4890 | ||
4891 | /* wait for receive complete */ | |
4892 | for (timeout = 100; timeout; --timeout) { | |
4893 | msleep_interruptible(10); | |
4894 | if (loopback_test_rx(info)) { | |
4895 | rc = 0; | |
4896 | break; | |
4897 | } | |
4898 | } | |
4899 | ||
4900 | /* verify received frame length and contents */ | |
4901 | if (!rc && (info->tmp_rbuf_count != count || | |
4902 | memcmp(buf, info->tmp_rbuf, count))) { | |
4903 | rc = -ENODEV; | |
4904 | } | |
4905 | ||
4906 | spin_lock_irqsave(&info->lock,flags); | |
4907 | reset_adapter(info); | |
4908 | spin_unlock_irqrestore(&info->lock,flags); | |
4909 | ||
4910 | memcpy(&info->params, ¶ms, sizeof(info->params)); | |
8fb06c77 | 4911 | info->port.tty = oldtty; |
705b6c7b PF |
4912 | |
4913 | info->init_error = rc ? DiagStatus_DmaFailure : 0; | |
4914 | return rc; | |
4915 | } | |
4916 | ||
4917 | static int adapter_test(struct slgt_info *info) | |
4918 | { | |
4919 | DBGINFO(("testing %s\n", info->device_name)); | |
294dad05 | 4920 | if (register_test(info) < 0) { |
705b6c7b PF |
4921 | printk("register test failure %s addr=%08X\n", |
4922 | info->device_name, info->phys_reg_addr); | |
294dad05 | 4923 | } else if (irq_test(info) < 0) { |
705b6c7b PF |
4924 | printk("IRQ test failure %s IRQ=%d\n", |
4925 | info->device_name, info->irq_level); | |
294dad05 | 4926 | } else if (loopback_test(info) < 0) { |
705b6c7b PF |
4927 | printk("loopback test failure %s\n", info->device_name); |
4928 | } | |
4929 | return info->init_error; | |
4930 | } | |
4931 | ||
4932 | /* | |
4933 | * transmit timeout handler | |
4934 | */ | |
4935 | static void tx_timeout(unsigned long context) | |
4936 | { | |
4937 | struct slgt_info *info = (struct slgt_info*)context; | |
4938 | unsigned long flags; | |
4939 | ||
4940 | DBGINFO(("%s tx_timeout\n", info->device_name)); | |
4941 | if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { | |
4942 | info->icount.txtimeout++; | |
4943 | } | |
4944 | spin_lock_irqsave(&info->lock,flags); | |
0fab6de0 | 4945 | info->tx_active = false; |
705b6c7b PF |
4946 | info->tx_count = 0; |
4947 | spin_unlock_irqrestore(&info->lock,flags); | |
4948 | ||
af69c7f9 | 4949 | #if SYNCLINK_GENERIC_HDLC |
705b6c7b PF |
4950 | if (info->netcount) |
4951 | hdlcdev_tx_done(info); | |
4952 | else | |
4953 | #endif | |
4954 | bh_transmit(info); | |
4955 | } | |
4956 | ||
4957 | /* | |
4958 | * receive buffer polling timer | |
4959 | */ | |
4960 | static void rx_timeout(unsigned long context) | |
4961 | { | |
4962 | struct slgt_info *info = (struct slgt_info*)context; | |
4963 | unsigned long flags; | |
4964 | ||
4965 | DBGINFO(("%s rx_timeout\n", info->device_name)); | |
4966 | spin_lock_irqsave(&info->lock, flags); | |
4967 | info->pending_bh |= BH_RECEIVE; | |
4968 | spin_unlock_irqrestore(&info->lock, flags); | |
c4028958 | 4969 | bh_handler(&info->task); |
705b6c7b PF |
4970 | } |
4971 |