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[PATCH] tty-layer-buffering-revamp: jsm is broken
[deliverable/linux.git] / drivers / char / synclink_gt.c
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705b6c7b
PF		 1/*
2 * $Id: synclink_gt.c,v 4.20 2005/11/08 19:51:55 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26/*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45//#define DBGTBUF(info) dump_tbufs(info)
46//#define DBGRBUF(info) dump_rbufs(info)
47
48
49#include <linux/config.h>
50#include <linux/module.h>
51#include <linux/version.h>
52#include <linux/errno.h>
53#include <linux/signal.h>
54#include <linux/sched.h>
55#include <linux/timer.h>
56#include <linux/interrupt.h>
57#include <linux/pci.h>
58#include <linux/tty.h>
59#include <linux/tty_flip.h>
60#include <linux/serial.h>
61#include <linux/major.h>
62#include <linux/string.h>
63#include <linux/fcntl.h>
64#include <linux/ptrace.h>
65#include <linux/ioport.h>
66#include <linux/mm.h>
67#include <linux/slab.h>
68#include <linux/netdevice.h>
69#include <linux/vmalloc.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/ioctl.h>
73#include <linux/termios.h>
74#include <linux/bitops.h>
75#include <linux/workqueue.h>
76#include <linux/hdlc.h>
77
705b6c7b
PF		 78#include <asm/system.h>
79#include <asm/io.h>
80#include <asm/irq.h>
81#include <asm/dma.h>
82#include <asm/types.h>
83#include <asm/uaccess.h>
84
85#include "linux/synclink.h"
86
87#ifdef CONFIG_HDLC_MODULE
88#define CONFIG_HDLC 1
89#endif
90
91/*
92 * module identification
93 */
94static char *driver_name = "SyncLink GT";
95static char *driver_version = "$Revision: 4.20 $";
96static char *tty_driver_name = "synclink_gt";
97static char *tty_dev_prefix = "ttySLG";
98MODULE_LICENSE("GPL");
99#define MGSL_MAGIC 0x5401
100#define MAX_DEVICES 12
101
102static struct pci_device_id pci_table[] = {
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {0,}, /* terminate list */
107};
108MODULE_DEVICE_TABLE(pci, pci_table);
109
110static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
111static void remove_one(struct pci_dev *dev);
112static struct pci_driver pci_driver = {
113 .name = "synclink_gt",
114 .id_table = pci_table,
115 .probe = init_one,
116 .remove = __devexit_p(remove_one),
117};
118
119static int pci_registered;
120
121/*
122 * module configuration and status
123 */
124static struct slgt_info *slgt_device_list;
125static int slgt_device_count;
126
127static int ttymajor;
128static int debug_level;
129static int maxframe[MAX_DEVICES];
130static int dosyncppp[MAX_DEVICES];
131
132module_param(ttymajor, int, 0);
133module_param(debug_level, int, 0);
134module_param_array(maxframe, int, NULL, 0);
135module_param_array(dosyncppp, int, NULL, 0);
136
137MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
138MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
139MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
140MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
141
142/*
143 * tty support and callbacks
144 */
145#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
146
147static struct tty_driver *serial_driver;
148
149static int open(struct tty_struct *tty, struct file * filp);
150static void close(struct tty_struct *tty, struct file * filp);
151static void hangup(struct tty_struct *tty);
152static void set_termios(struct tty_struct *tty, struct termios *old_termios);
153
154static int write(struct tty_struct *tty, const unsigned char *buf, int count);
155static void put_char(struct tty_struct *tty, unsigned char ch);
156static void send_xchar(struct tty_struct *tty, char ch);
157static void wait_until_sent(struct tty_struct *tty, int timeout);
158static int write_room(struct tty_struct *tty);
159static void flush_chars(struct tty_struct *tty);
160static void flush_buffer(struct tty_struct *tty);
161static void tx_hold(struct tty_struct *tty);
162static void tx_release(struct tty_struct *tty);
163
164static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
165static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
166static int chars_in_buffer(struct tty_struct *tty);
167static void throttle(struct tty_struct * tty);
168static void unthrottle(struct tty_struct * tty);
169static void set_break(struct tty_struct *tty, int break_state);
170
171/*
172 * generic HDLC support and callbacks
173 */
174#ifdef CONFIG_HDLC
175#define dev_to_port(D) (dev_to_hdlc(D)->priv)
176static void hdlcdev_tx_done(struct slgt_info *info);
177static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
178static int hdlcdev_init(struct slgt_info *info);
179static void hdlcdev_exit(struct slgt_info *info);
180#endif
181
182
183/*
184 * device specific structures, macros and functions
185 */
186
187#define SLGT_MAX_PORTS 4
188#define SLGT_REG_SIZE 256
189
190/*
191 * DMA buffer descriptor and access macros
192 */
193struct slgt_desc
194{
195 unsigned short count;
196 unsigned short status;
197 unsigned int pbuf; /* physical address of data buffer */
198 unsigned int next; /* physical address of next descriptor */
199
200 /* driver book keeping */
201 char *buf; /* virtual address of data buffer */
202 unsigned int pdesc; /* physical address of this descriptor */
203 dma_addr_t buf_dma_addr;
204};
205
206#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
207#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
208#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
209#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
210#define desc_count(a) (le16_to_cpu((a).count))
211#define desc_status(a) (le16_to_cpu((a).status))
212#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
213#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
214#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
215#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
216#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
217
218struct _input_signal_events {
219 int ri_up;
220 int ri_down;
221 int dsr_up;
222 int dsr_down;
223 int dcd_up;
224 int dcd_down;
225 int cts_up;
226 int cts_down;
227};
228
229/*
230 * device instance data structure
231 */
232struct slgt_info {
233 void *if_ptr; /* General purpose pointer (used by SPPP) */
234
235 struct slgt_info *next_device; /* device list link */
236
237 int magic;
238 int flags;
239
240 char device_name[25];
241 struct pci_dev *pdev;
242
243 int port_count; /* count of ports on adapter */
244 int adapter_num; /* adapter instance number */
245 int port_num; /* port instance number */
246
247 /* array of pointers to port contexts on this adapter */
248 struct slgt_info *port_array[SLGT_MAX_PORTS];
249
250 int count; /* count of opens */
251 int line; /* tty line instance number */
252 unsigned short close_delay;
253 unsigned short closing_wait; /* time to wait before closing */
254
255 struct mgsl_icount icount;
256
257 struct tty_struct *tty;
258 int timeout;
259 int x_char; /* xon/xoff character */
260 int blocked_open; /* # of blocked opens */
261 unsigned int read_status_mask;
262 unsigned int ignore_status_mask;
263
264 wait_queue_head_t open_wait;
265 wait_queue_head_t close_wait;
266
267 wait_queue_head_t status_event_wait_q;
268 wait_queue_head_t event_wait_q;
269 struct timer_list tx_timer;
270 struct timer_list rx_timer;
271
272 spinlock_t lock; /* spinlock for synchronizing with ISR */
273
274 struct work_struct task;
275 u32 pending_bh;
276 int bh_requested;
277 int bh_running;
278
279 int isr_overflow;
280 int irq_requested; /* nonzero if IRQ requested */
281 int irq_occurred; /* for diagnostics use */
282
283 /* device configuration */
284
285 unsigned int bus_type;
286 unsigned int irq_level;
287 unsigned long irq_flags;
288
289 unsigned char __iomem * reg_addr; /* memory mapped registers address */
290 u32 phys_reg_addr;
291 u32 reg_offset;
292 int reg_addr_requested;
293
294 MGSL_PARAMS params; /* communications parameters */
295 u32 idle_mode;
296 u32 max_frame_size; /* as set by device config */
297
298 unsigned int raw_rx_size;
299 unsigned int if_mode;
300
301 /* device status */
302
303 int rx_enabled;
304 int rx_restart;
305
306 int tx_enabled;
307 int tx_active;
308
309 unsigned char signals; /* serial signal states */
310 unsigned int init_error; /* initialization error */
311
312 unsigned char *tx_buf;
313 int tx_count;
314
315 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
316 char char_buf[MAX_ASYNC_BUFFER_SIZE];
317 BOOLEAN drop_rts_on_tx_done;
318 struct _input_signal_events input_signal_events;
319
320 int dcd_chkcount; /* check counts to prevent */
321 int cts_chkcount; /* too many IRQs if a signal */
322 int dsr_chkcount; /* is floating */
323 int ri_chkcount;
324
325 char *bufs; /* virtual address of DMA buffer lists */
326 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
327
328 unsigned int rbuf_count;
329 struct slgt_desc *rbufs;
330 unsigned int rbuf_current;
331 unsigned int rbuf_index;
332
333 unsigned int tbuf_count;
334 struct slgt_desc *tbufs;
335 unsigned int tbuf_current;
336 unsigned int tbuf_start;
337
338 unsigned char *tmp_rbuf;
339 unsigned int tmp_rbuf_count;
340
341 /* SPPP/Cisco HDLC device parts */
342
343 int netcount;
344 int dosyncppp;
345 spinlock_t netlock;
346#ifdef CONFIG_HDLC
347 struct net_device *netdev;
348#endif
349
350};
351
352static MGSL_PARAMS default_params = {
353 .mode = MGSL_MODE_HDLC,
354 .loopback = 0,
355 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
356 .encoding = HDLC_ENCODING_NRZI_SPACE,
357 .clock_speed = 0,
358 .addr_filter = 0xff,
359 .crc_type = HDLC_CRC_16_CCITT,
360 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
361 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
362 .data_rate = 9600,
363 .data_bits = 8,
364 .stop_bits = 1,
365 .parity = ASYNC_PARITY_NONE
366};
367
368
369#define BH_RECEIVE 1
370#define BH_TRANSMIT 2
371#define BH_STATUS 4
372#define IO_PIN_SHUTDOWN_LIMIT 100
373
374#define DMABUFSIZE 256
375#define DESC_LIST_SIZE 4096
376
377#define MASK_PARITY BIT1
378#define MASK_FRAMING BIT2
379#define MASK_BREAK BIT3
380#define MASK_OVERRUN BIT4
381
382#define GSR 0x00 /* global status */
383#define TDR 0x80 /* tx data */
384#define RDR 0x80 /* rx data */
385#define TCR 0x82 /* tx control */
386#define TIR 0x84 /* tx idle */
387#define TPR 0x85 /* tx preamble */
388#define RCR 0x86 /* rx control */
389#define VCR 0x88 /* V.24 control */
390#define CCR 0x89 /* clock control */
391#define BDR 0x8a /* baud divisor */
392#define SCR 0x8c /* serial control */
393#define SSR 0x8e /* serial status */
394#define RDCSR 0x90 /* rx DMA control/status */
395#define TDCSR 0x94 /* tx DMA control/status */
396#define RDDAR 0x98 /* rx DMA descriptor address */
397#define TDDAR 0x9c /* tx DMA descriptor address */
398
399#define RXIDLE BIT14
400#define RXBREAK BIT14
401#define IRQ_TXDATA BIT13
402#define IRQ_TXIDLE BIT12
403#define IRQ_TXUNDER BIT11 /* HDLC */
404#define IRQ_RXDATA BIT10
405#define IRQ_RXIDLE BIT9 /* HDLC */
406#define IRQ_RXBREAK BIT9 /* async */
407#define IRQ_RXOVER BIT8
408#define IRQ_DSR BIT7
409#define IRQ_CTS BIT6
410#define IRQ_DCD BIT5
411#define IRQ_RI BIT4
412#define IRQ_ALL 0x3ff0
413#define IRQ_MASTER BIT0
414
415#define slgt_irq_on(info, mask) \
416 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
417#define slgt_irq_off(info, mask) \
418 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
419
420static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
421static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
422static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
423static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
424static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
425static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
426
427static void msc_set_vcr(struct slgt_info *info);
428
429static int startup(struct slgt_info *info);
430static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
431static void shutdown(struct slgt_info *info);
432static void program_hw(struct slgt_info *info);
433static void change_params(struct slgt_info *info);
434
435static int register_test(struct slgt_info *info);
436static int irq_test(struct slgt_info *info);
437static int loopback_test(struct slgt_info *info);
438static int adapter_test(struct slgt_info *info);
439
440static void reset_adapter(struct slgt_info *info);
441static void reset_port(struct slgt_info *info);
442static void async_mode(struct slgt_info *info);
443static void hdlc_mode(struct slgt_info *info);
444
445static void rx_stop(struct slgt_info *info);
446static void rx_start(struct slgt_info *info);
447static void reset_rbufs(struct slgt_info *info);
448static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
449static void rdma_reset(struct slgt_info *info);
450static int rx_get_frame(struct slgt_info *info);
451static int rx_get_buf(struct slgt_info *info);
452
453static void tx_start(struct slgt_info *info);
454static void tx_stop(struct slgt_info *info);
455static void tx_set_idle(struct slgt_info *info);
456static unsigned int free_tbuf_count(struct slgt_info *info);
457static void reset_tbufs(struct slgt_info *info);
458static void tdma_reset(struct slgt_info *info);
459static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
460
461static void get_signals(struct slgt_info *info);
462static void set_signals(struct slgt_info *info);
463static void enable_loopback(struct slgt_info *info);
464static void set_rate(struct slgt_info *info, u32 data_rate);
465
466static int bh_action(struct slgt_info *info);
467static void bh_handler(void* context);
468static void bh_transmit(struct slgt_info *info);
469static void isr_serial(struct slgt_info *info);
470static void isr_rdma(struct slgt_info *info);
471static void isr_txeom(struct slgt_info *info, unsigned short status);
472static void isr_tdma(struct slgt_info *info);
473static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs);
474
475static int alloc_dma_bufs(struct slgt_info *info);
476static void free_dma_bufs(struct slgt_info *info);
477static int alloc_desc(struct slgt_info *info);
478static void free_desc(struct slgt_info *info);
479static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
480static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
481
482static int alloc_tmp_rbuf(struct slgt_info *info);
483static void free_tmp_rbuf(struct slgt_info *info);
484
485static void tx_timeout(unsigned long context);
486static void rx_timeout(unsigned long context);
487
488/*
489 * ioctl handlers
490 */
491static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
492static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
493static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
494static int get_txidle(struct slgt_info *info, int __user *idle_mode);
495static int set_txidle(struct slgt_info *info, int idle_mode);
496static int tx_enable(struct slgt_info *info, int enable);
497static int tx_abort(struct slgt_info *info);
498static int rx_enable(struct slgt_info *info, int enable);
499static int modem_input_wait(struct slgt_info *info,int arg);
500static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
501static int tiocmget(struct tty_struct *tty, struct file *file);
502static int tiocmset(struct tty_struct *tty, struct file *file,
503 unsigned int set, unsigned int clear);
504static void set_break(struct tty_struct *tty, int break_state);
505static int get_interface(struct slgt_info *info, int __user *if_mode);
506static int set_interface(struct slgt_info *info, int if_mode);
507
508/*
509 * driver functions
510 */
511static void add_device(struct slgt_info *info);
512static void device_init(int adapter_num, struct pci_dev *pdev);
513static int claim_resources(struct slgt_info *info);
514static void release_resources(struct slgt_info *info);
515
516/*
517 * DEBUG OUTPUT CODE
518 */
519#ifndef DBGINFO
520#define DBGINFO(fmt)
521#endif
522#ifndef DBGERR
523#define DBGERR(fmt)
524#endif
525#ifndef DBGBH
526#define DBGBH(fmt)
527#endif
528#ifndef DBGISR
529#define DBGISR(fmt)
530#endif
531
532#ifdef DBGDATA
533static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
534{
535 int i;
536 int linecount;
537 printk("%s %s data:\n",info->device_name, label);
538 while(count) {
539 linecount = (count > 16) ? 16 : count;
540 for(i=0; i < linecount; i++)
541 printk("%02X ",(unsigned char)data[i]);
542 for(;i<17;i++)
543 printk(" ");
544 for(i=0;i<linecount;i++) {
545 if (data[i]>=040 && data[i]<=0176)
546 printk("%c",data[i]);
547 else
548 printk(".");
549 }
550 printk("\n");
551 data += linecount;
552 count -= linecount;
553 }
554}
555#else
556#define DBGDATA(info, buf, size, label)
557#endif
558
559#ifdef DBGTBUF
560static void dump_tbufs(struct slgt_info *info)
561{
562 int i;
563 printk("tbuf_current=%d\n", info->tbuf_current);
564 for (i=0 ; i < info->tbuf_count ; i++) {
565 printk("%d: count=%04X status=%04X\n",
566 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
567 }
568}
569#else
570#define DBGTBUF(info)
571#endif
572
573#ifdef DBGRBUF
574static void dump_rbufs(struct slgt_info *info)
575{
576 int i;
577 printk("rbuf_current=%d\n", info->rbuf_current);
578 for (i=0 ; i < info->rbuf_count ; i++) {
579 printk("%d: count=%04X status=%04X\n",
580 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
581 }
582}
583#else
584#define DBGRBUF(info)
585#endif
586
587static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
588{
589#ifdef SANITY_CHECK
590 if (!info) {
591 printk("null struct slgt_info for (%s) in %s\n", devname, name);
592 return 1;
593 }
594 if (info->magic != MGSL_MAGIC) {
595 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
596 return 1;
597 }
598#else
599 if (!info)
600 return 1;
601#endif
602 return 0;
603}
604
605/**
606 * line discipline callback wrappers
607 *
608 * The wrappers maintain line discipline references
609 * while calling into the line discipline.
610 *
611 * ldisc_receive_buf - pass receive data to line discipline
612 */
613static void ldisc_receive_buf(struct tty_struct *tty,
614 const __u8 *data, char *flags, int count)
615{
616 struct tty_ldisc *ld;
617 if (!tty)
618 return;
619 ld = tty_ldisc_ref(tty);
620 if (ld) {
621 if (ld->receive_buf)
622 ld->receive_buf(tty, data, flags, count);
623 tty_ldisc_deref(ld);
624 }
625}
626
627/* tty callbacks */
628
629static int open(struct tty_struct *tty, struct file *filp)
630{
631 struct slgt_info *info;
632 int retval, line;
633 unsigned long flags;
634
635 line = tty->index;
636 if ((line < 0) || (line >= slgt_device_count)) {
637 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
638 return -ENODEV;
639 }
640
641 info = slgt_device_list;
642 while(info && info->line != line)
643 info = info->next_device;
644 if (sanity_check(info, tty->name, "open"))
645 return -ENODEV;
646 if (info->init_error) {
647 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
648 return -ENODEV;
649 }
650
651 tty->driver_data = info;
652 info->tty = tty;
653
654 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
655
656 /* If port is closing, signal caller to try again */
657 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
658 if (info->flags & ASYNC_CLOSING)
659 interruptible_sleep_on(&info->close_wait);
660 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
661 -EAGAIN : -ERESTARTSYS);
662 goto cleanup;
663 }
664
665 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
666
667 spin_lock_irqsave(&info->netlock, flags);
668 if (info->netcount) {
669 retval = -EBUSY;
670 spin_unlock_irqrestore(&info->netlock, flags);
671 goto cleanup;
672 }
673 info->count++;
674 spin_unlock_irqrestore(&info->netlock, flags);
675
676 if (info->count == 1) {
677 /* 1st open on this device, init hardware */
678 retval = startup(info);
679 if (retval < 0)
680 goto cleanup;
681 }
682
683 retval = block_til_ready(tty, filp, info);
684 if (retval) {
685 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
686 goto cleanup;
687 }
688
689 retval = 0;
690
691cleanup:
692 if (retval) {
693 if (tty->count == 1)
694 info->tty = NULL; /* tty layer will release tty struct */
695 if(info->count)
696 info->count--;
697 }
698
699 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
700 return retval;
701}
702
703static void close(struct tty_struct *tty, struct file *filp)
704{
705 struct slgt_info *info = tty->driver_data;
706
707 if (sanity_check(info, tty->name, "close"))
708 return;
709 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
710
711 if (!info->count)
712 return;
713
714 if (tty_hung_up_p(filp))
715 goto cleanup;
716
717 if ((tty->count == 1) && (info->count != 1)) {
718 /*
719 * tty->count is 1 and the tty structure will be freed.
720 * info->count should be one in this case.
721 * if it's not, correct it so that the port is shutdown.
722 */
723 DBGERR(("%s close: bad refcount; tty->count=1, "
724 "info->count=%d\n", info->device_name, info->count));
725 info->count = 1;
726 }
727
728 info->count--;
729
730 /* if at least one open remaining, leave hardware active */
731 if (info->count)
732 goto cleanup;
733
734 info->flags |= ASYNC_CLOSING;
735
736 /* set tty->closing to notify line discipline to
737 * only process XON/XOFF characters. Only the N_TTY
738 * discipline appears to use this (ppp does not).
739 */
740 tty->closing = 1;
741
742 /* wait for transmit data to clear all layers */
743
744 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
745 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
746 tty_wait_until_sent(tty, info->closing_wait);
747 }
748
749 if (info->flags & ASYNC_INITIALIZED)
750 wait_until_sent(tty, info->timeout);
751 if (tty->driver->flush_buffer)
752 tty->driver->flush_buffer(tty);
753 tty_ldisc_flush(tty);
754
755 shutdown(info);
756
757 tty->closing = 0;
758 info->tty = NULL;
759
760 if (info->blocked_open) {
761 if (info->close_delay) {
762 msleep_interruptible(jiffies_to_msecs(info->close_delay));
763 }
764 wake_up_interruptible(&info->open_wait);
765 }
766
767 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
768
769 wake_up_interruptible(&info->close_wait);
770
771cleanup:
772 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
773}
774
775static void hangup(struct tty_struct *tty)
776{
777 struct slgt_info *info = tty->driver_data;
778
779 if (sanity_check(info, tty->name, "hangup"))
780 return;
781 DBGINFO(("%s hangup\n", info->device_name));
782
783 flush_buffer(tty);
784 shutdown(info);
785
786 info->count = 0;
787 info->flags &= ~ASYNC_NORMAL_ACTIVE;
788 info->tty = NULL;
789
790 wake_up_interruptible(&info->open_wait);
791}
792
793static void set_termios(struct tty_struct *tty, struct termios *old_termios)
794{
795 struct slgt_info *info = tty->driver_data;
796 unsigned long flags;
797
798 DBGINFO(("%s set_termios\n", tty->driver->name));
799
800 /* just return if nothing has changed */
801 if ((tty->termios->c_cflag == old_termios->c_cflag)
802 && (RELEVANT_IFLAG(tty->termios->c_iflag)
803 == RELEVANT_IFLAG(old_termios->c_iflag)))
804 return;
805
806 change_params(info);
807
808 /* Handle transition to B0 status */
809 if (old_termios->c_cflag & CBAUD &&
810 !(tty->termios->c_cflag & CBAUD)) {
811 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
812 spin_lock_irqsave(&info->lock,flags);
813 set_signals(info);
814 spin_unlock_irqrestore(&info->lock,flags);
815 }
816
817 /* Handle transition away from B0 status */
818 if (!(old_termios->c_cflag & CBAUD) &&
819 tty->termios->c_cflag & CBAUD) {
820 info->signals |= SerialSignal_DTR;
821 if (!(tty->termios->c_cflag & CRTSCTS) ||
822 !test_bit(TTY_THROTTLED, &tty->flags)) {
823 info->signals |= SerialSignal_RTS;
824 }
825 spin_lock_irqsave(&info->lock,flags);
826 set_signals(info);
827 spin_unlock_irqrestore(&info->lock,flags);
828 }
829
830 /* Handle turning off CRTSCTS */
831 if (old_termios->c_cflag & CRTSCTS &&
832 !(tty->termios->c_cflag & CRTSCTS)) {
833 tty->hw_stopped = 0;
834 tx_release(tty);
835 }
836}
837
838static int write(struct tty_struct *tty,
839 const unsigned char *buf, int count)
840{
841 int ret = 0;
842 struct slgt_info *info = tty->driver_data;
843 unsigned long flags;
844
845 if (sanity_check(info, tty->name, "write"))
846 goto cleanup;
847 DBGINFO(("%s write count=%d\n", info->device_name, count));
848
849 if (!tty || !info->tx_buf)
850 goto cleanup;
851
852 if (count > info->max_frame_size) {
853 ret = -EIO;
854 goto cleanup;
855 }
856
857 if (!count)
858 goto cleanup;
859
860 if (info->params.mode == MGSL_MODE_RAW) {
861 unsigned int bufs_needed = (count/DMABUFSIZE);
862 unsigned int bufs_free = free_tbuf_count(info);
863 if (count % DMABUFSIZE)
864 ++bufs_needed;
865 if (bufs_needed > bufs_free)
866 goto cleanup;
867 } else {
868 if (info->tx_active)
869 goto cleanup;
870 if (info->tx_count) {
871 /* send accumulated data from send_char() calls */
872 /* as frame and wait before accepting more data. */
873 tx_load(info, info->tx_buf, info->tx_count);
874 goto start;
875 }
876 }
877
878 ret = info->tx_count = count;
879 tx_load(info, buf, count);
880 goto start;
881
882start:
883 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
884 spin_lock_irqsave(&info->lock,flags);
885 if (!info->tx_active)
886 tx_start(info);
887 spin_unlock_irqrestore(&info->lock,flags);
888 }
889
890cleanup:
891 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
892 return ret;
893}
894
895static void put_char(struct tty_struct *tty, unsigned char ch)
896{
897 struct slgt_info *info = tty->driver_data;
898 unsigned long flags;
899
900 if (sanity_check(info, tty->name, "put_char"))
901 return;
902 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
903 if (!tty || !info->tx_buf)
904 return;
905 spin_lock_irqsave(&info->lock,flags);
906 if (!info->tx_active && (info->tx_count < info->max_frame_size))
907 info->tx_buf[info->tx_count++] = ch;
908 spin_unlock_irqrestore(&info->lock,flags);
909}
910
911static void send_xchar(struct tty_struct *tty, char ch)
912{
913 struct slgt_info *info = tty->driver_data;
914 unsigned long flags;
915
916 if (sanity_check(info, tty->name, "send_xchar"))
917 return;
918 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
919 info->x_char = ch;
920 if (ch) {
921 spin_lock_irqsave(&info->lock,flags);
922 if (!info->tx_enabled)
923 tx_start(info);
924 spin_unlock_irqrestore(&info->lock,flags);
925 }
926}
927
928static void wait_until_sent(struct tty_struct *tty, int timeout)
929{
930 struct slgt_info *info = tty->driver_data;
931 unsigned long orig_jiffies, char_time;
932
933 if (!info )
934 return;
935 if (sanity_check(info, tty->name, "wait_until_sent"))
936 return;
937 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
938 if (!(info->flags & ASYNC_INITIALIZED))
939 goto exit;
940
941 orig_jiffies = jiffies;
942
943 /* Set check interval to 1/5 of estimated time to
944 * send a character, and make it at least 1. The check
945 * interval should also be less than the timeout.
946 * Note: use tight timings here to satisfy the NIST-PCTS.
947 */
948
949 if (info->params.data_rate) {
950 char_time = info->timeout/(32 * 5);
951 if (!char_time)
952 char_time++;
953 } else
954 char_time = 1;
955
956 if (timeout)
957 char_time = min_t(unsigned long, char_time, timeout);
958
959 while (info->tx_active) {
960 msleep_interruptible(jiffies_to_msecs(char_time));
961 if (signal_pending(current))
962 break;
963 if (timeout && time_after(jiffies, orig_jiffies + timeout))
964 break;
965 }
966
967exit:
968 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
969}
970
971static int write_room(struct tty_struct *tty)
972{
973 struct slgt_info *info = tty->driver_data;
974 int ret;
975
976 if (sanity_check(info, tty->name, "write_room"))
977 return 0;
978 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
979 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
980 return ret;
981}
982
983static void flush_chars(struct tty_struct *tty)
984{
985 struct slgt_info *info = tty->driver_data;
986 unsigned long flags;
987
988 if (sanity_check(info, tty->name, "flush_chars"))
989 return;
990 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
991
992 if (info->tx_count <= 0 || tty->stopped ||
993 tty->hw_stopped || !info->tx_buf)
994 return;
995
996 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
997
998 spin_lock_irqsave(&info->lock,flags);
999 if (!info->tx_active && info->tx_count) {
1000 tx_load(info, info->tx_buf,info->tx_count);
1001 tx_start(info);
1002 }
1003 spin_unlock_irqrestore(&info->lock,flags);
1004}
1005
1006static void flush_buffer(struct tty_struct *tty)
1007{
1008 struct slgt_info *info = tty->driver_data;
1009 unsigned long flags;
1010
1011 if (sanity_check(info, tty->name, "flush_buffer"))
1012 return;
1013 DBGINFO(("%s flush_buffer\n", info->device_name));
1014
1015 spin_lock_irqsave(&info->lock,flags);
1016 if (!info->tx_active)
1017 info->tx_count = 0;
1018 spin_unlock_irqrestore(&info->lock,flags);
1019
1020 wake_up_interruptible(&tty->write_wait);
1021 tty_wakeup(tty);
1022}
1023
1024/*
1025 * throttle (stop) transmitter
1026 */
1027static void tx_hold(struct tty_struct *tty)
1028{
1029 struct slgt_info *info = tty->driver_data;
1030 unsigned long flags;
1031
1032 if (sanity_check(info, tty->name, "tx_hold"))
1033 return;
1034 DBGINFO(("%s tx_hold\n", info->device_name));
1035 spin_lock_irqsave(&info->lock,flags);
1036 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1037 tx_stop(info);
1038 spin_unlock_irqrestore(&info->lock,flags);
1039}
1040
1041/*
1042 * release (start) transmitter
1043 */
1044static void tx_release(struct tty_struct *tty)
1045{
1046 struct slgt_info *info = tty->driver_data;
1047 unsigned long flags;
1048
1049 if (sanity_check(info, tty->name, "tx_release"))
1050 return;
1051 DBGINFO(("%s tx_release\n", info->device_name));
1052 spin_lock_irqsave(&info->lock,flags);
1053 if (!info->tx_active && info->tx_count) {
1054 tx_load(info, info->tx_buf, info->tx_count);
1055 tx_start(info);
1056 }
1057 spin_unlock_irqrestore(&info->lock,flags);
1058}
1059
1060/*
1061 * Service an IOCTL request
1062 *
1063 * Arguments
1064 *
1065 * tty pointer to tty instance data
1066 * file pointer to associated file object for device
1067 * cmd IOCTL command code
1068 * arg command argument/context
1069 *
1070 * Return 0 if success, otherwise error code
1071 */
1072static int ioctl(struct tty_struct *tty, struct file *file,
1073 unsigned int cmd, unsigned long arg)
1074{
1075 struct slgt_info *info = tty->driver_data;
1076 struct mgsl_icount cnow; /* kernel counter temps */
1077 struct serial_icounter_struct __user *p_cuser; /* user space */
1078 unsigned long flags;
1079 void __user *argp = (void __user *)arg;
1080
1081 if (sanity_check(info, tty->name, "ioctl"))
1082 return -ENODEV;
1083 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1084
1085 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1086 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1087 if (tty->flags & (1 << TTY_IO_ERROR))
1088 return -EIO;
1089 }
1090
1091 switch (cmd) {
1092 case MGSL_IOCGPARAMS:
1093 return get_params(info, argp);
1094 case MGSL_IOCSPARAMS:
1095 return set_params(info, argp);
1096 case MGSL_IOCGTXIDLE:
1097 return get_txidle(info, argp);
1098 case MGSL_IOCSTXIDLE:
1099 return set_txidle(info, (int)arg);
1100 case MGSL_IOCTXENABLE:
1101 return tx_enable(info, (int)arg);
1102 case MGSL_IOCRXENABLE:
1103 return rx_enable(info, (int)arg);
1104 case MGSL_IOCTXABORT:
1105 return tx_abort(info);
1106 case MGSL_IOCGSTATS:
1107 return get_stats(info, argp);
1108 case MGSL_IOCWAITEVENT:
1109 return wait_mgsl_event(info, argp);
1110 case TIOCMIWAIT:
1111 return modem_input_wait(info,(int)arg);
1112 case MGSL_IOCGIF:
1113 return get_interface(info, argp);
1114 case MGSL_IOCSIF:
1115 return set_interface(info,(int)arg);
1116 case TIOCGICOUNT:
1117 spin_lock_irqsave(&info->lock,flags);
1118 cnow = info->icount;
1119 spin_unlock_irqrestore(&info->lock,flags);
1120 p_cuser = argp;
1121 if (put_user(cnow.cts, &p_cuser->cts) ||
1122 put_user(cnow.dsr, &p_cuser->dsr) ||
1123 put_user(cnow.rng, &p_cuser->rng) ||
1124 put_user(cnow.dcd, &p_cuser->dcd) ||
1125 put_user(cnow.rx, &p_cuser->rx) ||
1126 put_user(cnow.tx, &p_cuser->tx) ||
1127 put_user(cnow.frame, &p_cuser->frame) ||
1128 put_user(cnow.overrun, &p_cuser->overrun) ||
1129 put_user(cnow.parity, &p_cuser->parity) ||
1130 put_user(cnow.brk, &p_cuser->brk) ||
1131 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1132 return -EFAULT;
1133 return 0;
1134 default:
1135 return -ENOIOCTLCMD;
1136 }
1137 return 0;
1138}
1139
1140/*
1141 * proc fs support
1142 */
1143static inline int line_info(char *buf, struct slgt_info *info)
1144{
1145 char stat_buf[30];
1146 int ret;
1147 unsigned long flags;
1148
1149 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1150 info->device_name, info->phys_reg_addr,
1151 info->irq_level, info->max_frame_size);
1152
1153 /* output current serial signal states */
1154 spin_lock_irqsave(&info->lock,flags);
1155 get_signals(info);
1156 spin_unlock_irqrestore(&info->lock,flags);
1157
1158 stat_buf[0] = 0;
1159 stat_buf[1] = 0;
1160 if (info->signals & SerialSignal_RTS)
1161 strcat(stat_buf, "|RTS");
1162 if (info->signals & SerialSignal_CTS)
1163 strcat(stat_buf, "|CTS");
1164 if (info->signals & SerialSignal_DTR)
1165 strcat(stat_buf, "|DTR");
1166 if (info->signals & SerialSignal_DSR)
1167 strcat(stat_buf, "|DSR");
1168 if (info->signals & SerialSignal_DCD)
1169 strcat(stat_buf, "|CD");
1170 if (info->signals & SerialSignal_RI)
1171 strcat(stat_buf, "|RI");
1172
1173 if (info->params.mode != MGSL_MODE_ASYNC) {
1174 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1175 info->icount.txok, info->icount.rxok);
1176 if (info->icount.txunder)
1177 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1178 if (info->icount.txabort)
1179 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1180 if (info->icount.rxshort)
1181 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1182 if (info->icount.rxlong)
1183 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1184 if (info->icount.rxover)
1185 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1186 if (info->icount.rxcrc)
1187 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1188 } else {
1189 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1190 info->icount.tx, info->icount.rx);
1191 if (info->icount.frame)
1192 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1193 if (info->icount.parity)
1194 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1195 if (info->icount.brk)
1196 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1197 if (info->icount.overrun)
1198 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1199 }
1200
1201 /* Append serial signal status to end */
1202 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1203
1204 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1205 info->tx_active,info->bh_requested,info->bh_running,
1206 info->pending_bh);
1207
1208 return ret;
1209}
1210
1211/* Called to print information about devices
1212 */
1213static int read_proc(char *page, char **start, off_t off, int count,
1214 int *eof, void *data)
1215{
1216 int len = 0, l;
1217 off_t begin = 0;
1218 struct slgt_info *info;
1219
1220 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1221
1222 info = slgt_device_list;
1223 while( info ) {
1224 l = line_info(page + len, info);
1225 len += l;
1226 if (len+begin > off+count)
1227 goto done;
1228 if (len+begin < off) {
1229 begin += len;
1230 len = 0;
1231 }
1232 info = info->next_device;
1233 }
1234
1235 *eof = 1;
1236done:
1237 if (off >= len+begin)
1238 return 0;
1239 *start = page + (off-begin);
1240 return ((count < begin+len-off) ? count : begin+len-off);
1241}
1242
1243/*
1244 * return count of bytes in transmit buffer
1245 */
1246static int chars_in_buffer(struct tty_struct *tty)
1247{
1248 struct slgt_info *info = tty->driver_data;
1249 if (sanity_check(info, tty->name, "chars_in_buffer"))
1250 return 0;
1251 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1252 return info->tx_count;
1253}
1254
1255/*
1256 * signal remote device to throttle send data (our receive data)
1257 */
1258static void throttle(struct tty_struct * tty)
1259{
1260 struct slgt_info *info = tty->driver_data;
1261 unsigned long flags;
1262
1263 if (sanity_check(info, tty->name, "throttle"))
1264 return;
1265 DBGINFO(("%s throttle\n", info->device_name));
1266 if (I_IXOFF(tty))
1267 send_xchar(tty, STOP_CHAR(tty));
1268 if (tty->termios->c_cflag & CRTSCTS) {
1269 spin_lock_irqsave(&info->lock,flags);
1270 info->signals &= ~SerialSignal_RTS;
1271 set_signals(info);
1272 spin_unlock_irqrestore(&info->lock,flags);
1273 }
1274}
1275
1276/*
1277 * signal remote device to stop throttling send data (our receive data)
1278 */
1279static void unthrottle(struct tty_struct * tty)
1280{
1281 struct slgt_info *info = tty->driver_data;
1282 unsigned long flags;
1283
1284 if (sanity_check(info, tty->name, "unthrottle"))
1285 return;
1286 DBGINFO(("%s unthrottle\n", info->device_name));
1287 if (I_IXOFF(tty)) {
1288 if (info->x_char)
1289 info->x_char = 0;
1290 else
1291 send_xchar(tty, START_CHAR(tty));
1292 }
1293 if (tty->termios->c_cflag & CRTSCTS) {
1294 spin_lock_irqsave(&info->lock,flags);
1295 info->signals |= SerialSignal_RTS;
1296 set_signals(info);
1297 spin_unlock_irqrestore(&info->lock,flags);
1298 }
1299}
1300
1301/*
1302 * set or clear transmit break condition
1303 * break_state -1=set break condition, 0=clear
1304 */
1305static void set_break(struct tty_struct *tty, int break_state)
1306{
1307 struct slgt_info *info = tty->driver_data;
1308 unsigned short value;
1309 unsigned long flags;
1310
1311 if (sanity_check(info, tty->name, "set_break"))
1312 return;
1313 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1314
1315 spin_lock_irqsave(&info->lock,flags);
1316 value = rd_reg16(info, TCR);
1317 if (break_state == -1)
1318 value |= BIT6;
1319 else
1320 value &= ~BIT6;
1321 wr_reg16(info, TCR, value);
1322 spin_unlock_irqrestore(&info->lock,flags);
1323}
1324
1325#ifdef CONFIG_HDLC
1326
1327/**
1328 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1329 * set encoding and frame check sequence (FCS) options
1330 *
1331 * dev pointer to network device structure
1332 * encoding serial encoding setting
1333 * parity FCS setting
1334 *
1335 * returns 0 if success, otherwise error code
1336 */
1337static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1338 unsigned short parity)
1339{
1340 struct slgt_info *info = dev_to_port(dev);
1341 unsigned char new_encoding;
1342 unsigned short new_crctype;
1343
1344 /* return error if TTY interface open */
1345 if (info->count)
1346 return -EBUSY;
1347
1348 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1349
1350 switch (encoding)
1351 {
1352 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1353 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1354 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1355 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1356 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1357 default: return -EINVAL;
1358 }
1359
1360 switch (parity)
1361 {
1362 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1363 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1364 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1365 default: return -EINVAL;
1366 }
1367
1368 info->params.encoding = new_encoding;
1369 info->params.crc_type = new_crctype;;
1370
1371 /* if network interface up, reprogram hardware */
1372 if (info->netcount)
1373 program_hw(info);
1374
1375 return 0;
1376}
1377
1378/**
1379 * called by generic HDLC layer to send frame
1380 *
1381 * skb socket buffer containing HDLC frame
1382 * dev pointer to network device structure
1383 *
1384 * returns 0 if success, otherwise error code
1385 */
1386static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1387{
1388 struct slgt_info *info = dev_to_port(dev);
1389 struct net_device_stats *stats = hdlc_stats(dev);
1390 unsigned long flags;
1391
1392 DBGINFO(("%s hdlc_xmit\n", dev->name));
1393
1394 /* stop sending until this frame completes */
1395 netif_stop_queue(dev);
1396
1397 /* copy data to device buffers */
1398 info->tx_count = skb->len;
1399 tx_load(info, skb->data, skb->len);
1400
1401 /* update network statistics */
1402 stats->tx_packets++;
1403 stats->tx_bytes += skb->len;
1404
1405 /* done with socket buffer, so free it */
1406 dev_kfree_skb(skb);
1407
1408 /* save start time for transmit timeout detection */
1409 dev->trans_start = jiffies;
1410
1411 /* start hardware transmitter if necessary */
1412 spin_lock_irqsave(&info->lock,flags);
1413 if (!info->tx_active)
1414 tx_start(info);
1415 spin_unlock_irqrestore(&info->lock,flags);
1416
1417 return 0;
1418}
1419
1420/**
1421 * called by network layer when interface enabled
1422 * claim resources and initialize hardware
1423 *
1424 * dev pointer to network device structure
1425 *
1426 * returns 0 if success, otherwise error code
1427 */
1428static int hdlcdev_open(struct net_device *dev)
1429{
1430 struct slgt_info *info = dev_to_port(dev);
1431 int rc;
1432 unsigned long flags;
1433
1434 DBGINFO(("%s hdlcdev_open\n", dev->name));
1435
1436 /* generic HDLC layer open processing */
1437 if ((rc = hdlc_open(dev)))
1438 return rc;
1439
1440 /* arbitrate between network and tty opens */
1441 spin_lock_irqsave(&info->netlock, flags);
1442 if (info->count != 0 || info->netcount != 0) {
1443 DBGINFO(("%s hdlc_open busy\n", dev->name));
1444 spin_unlock_irqrestore(&info->netlock, flags);
1445 return -EBUSY;
1446 }
1447 info->netcount=1;
1448 spin_unlock_irqrestore(&info->netlock, flags);
1449
1450 /* claim resources and init adapter */
1451 if ((rc = startup(info)) != 0) {
1452 spin_lock_irqsave(&info->netlock, flags);
1453 info->netcount=0;
1454 spin_unlock_irqrestore(&info->netlock, flags);
1455 return rc;
1456 }
1457
1458 /* assert DTR and RTS, apply hardware settings */
1459 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1460 program_hw(info);
1461
1462 /* enable network layer transmit */
1463 dev->trans_start = jiffies;
1464 netif_start_queue(dev);
1465
1466 /* inform generic HDLC layer of current DCD status */
1467 spin_lock_irqsave(&info->lock, flags);
1468 get_signals(info);
1469 spin_unlock_irqrestore(&info->lock, flags);
1470 hdlc_set_carrier(info->signals & SerialSignal_DCD, dev);
1471
1472 return 0;
1473}
1474
1475/**
1476 * called by network layer when interface is disabled
1477 * shutdown hardware and release resources
1478 *
1479 * dev pointer to network device structure
1480 *
1481 * returns 0 if success, otherwise error code
1482 */
1483static int hdlcdev_close(struct net_device *dev)
1484{
1485 struct slgt_info *info = dev_to_port(dev);
1486 unsigned long flags;
1487
1488 DBGINFO(("%s hdlcdev_close\n", dev->name));
1489
1490 netif_stop_queue(dev);
1491
1492 /* shutdown adapter and release resources */
1493 shutdown(info);
1494
1495 hdlc_close(dev);
1496
1497 spin_lock_irqsave(&info->netlock, flags);
1498 info->netcount=0;
1499 spin_unlock_irqrestore(&info->netlock, flags);
1500
1501 return 0;
1502}
1503
1504/**
1505 * called by network layer to process IOCTL call to network device
1506 *
1507 * dev pointer to network device structure
1508 * ifr pointer to network interface request structure
1509 * cmd IOCTL command code
1510 *
1511 * returns 0 if success, otherwise error code
1512 */
1513static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1514{
1515 const size_t size = sizeof(sync_serial_settings);
1516 sync_serial_settings new_line;
1517 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1518 struct slgt_info *info = dev_to_port(dev);
1519 unsigned int flags;
1520
1521 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1522
1523 /* return error if TTY interface open */
1524 if (info->count)
1525 return -EBUSY;
1526
1527 if (cmd != SIOCWANDEV)
1528 return hdlc_ioctl(dev, ifr, cmd);
1529
1530 switch(ifr->ifr_settings.type) {
1531 case IF_GET_IFACE: /* return current sync_serial_settings */
1532
1533 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1534 if (ifr->ifr_settings.size < size) {
1535 ifr->ifr_settings.size = size; /* data size wanted */
1536 return -ENOBUFS;
1537 }
1538
1539 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1540 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1541 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1542 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1543
1544 switch (flags){
1545 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1546 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1547 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1548 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1549 default: new_line.clock_type = CLOCK_DEFAULT;
1550 }
1551
1552 new_line.clock_rate = info->params.clock_speed;
1553 new_line.loopback = info->params.loopback ? 1:0;
1554
1555 if (copy_to_user(line, &new_line, size))
1556 return -EFAULT;
1557 return 0;
1558
1559 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1560
1561 if(!capable(CAP_NET_ADMIN))
1562 return -EPERM;
1563 if (copy_from_user(&new_line, line, size))
1564 return -EFAULT;
1565
1566 switch (new_line.clock_type)
1567 {
1568 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1569 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1570 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1571 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1572 case CLOCK_DEFAULT: flags = info->params.flags &
1573 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1574 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1575 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1576 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1577 default: return -EINVAL;
1578 }
1579
1580 if (new_line.loopback != 0 && new_line.loopback != 1)
1581 return -EINVAL;
1582
1583 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1584 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1585 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1586 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1587 info->params.flags |= flags;
1588
1589 info->params.loopback = new_line.loopback;
1590
1591 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1592 info->params.clock_speed = new_line.clock_rate;
1593 else
1594 info->params.clock_speed = 0;
1595
1596 /* if network interface up, reprogram hardware */
1597 if (info->netcount)
1598 program_hw(info);
1599 return 0;
1600
1601 default:
1602 return hdlc_ioctl(dev, ifr, cmd);
1603 }
1604}
1605
1606/**
1607 * called by network layer when transmit timeout is detected
1608 *
1609 * dev pointer to network device structure
1610 */
1611static void hdlcdev_tx_timeout(struct net_device *dev)
1612{
1613 struct slgt_info *info = dev_to_port(dev);
1614 struct net_device_stats *stats = hdlc_stats(dev);
1615 unsigned long flags;
1616
1617 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1618
1619 stats->tx_errors++;
1620 stats->tx_aborted_errors++;
1621
1622 spin_lock_irqsave(&info->lock,flags);
1623 tx_stop(info);
1624 spin_unlock_irqrestore(&info->lock,flags);
1625
1626 netif_wake_queue(dev);
1627}
1628
1629/**
1630 * called by device driver when transmit completes
1631 * reenable network layer transmit if stopped
1632 *
1633 * info pointer to device instance information
1634 */
1635static void hdlcdev_tx_done(struct slgt_info *info)
1636{
1637 if (netif_queue_stopped(info->netdev))
1638 netif_wake_queue(info->netdev);
1639}
1640
1641/**
1642 * called by device driver when frame received
1643 * pass frame to network layer
1644 *
1645 * info pointer to device instance information
1646 * buf pointer to buffer contianing frame data
1647 * size count of data bytes in buf
1648 */
1649static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1650{
1651 struct sk_buff *skb = dev_alloc_skb(size);
1652 struct net_device *dev = info->netdev;
1653 struct net_device_stats *stats = hdlc_stats(dev);
1654
1655 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1656
1657 if (skb == NULL) {
1658 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1659 stats->rx_dropped++;
1660 return;
1661 }
1662
1663 memcpy(skb_put(skb, size),buf,size);
1664
1665 skb->protocol = hdlc_type_trans(skb, info->netdev);
1666
1667 stats->rx_packets++;
1668 stats->rx_bytes += size;
1669
1670 netif_rx(skb);
1671
1672 info->netdev->last_rx = jiffies;
1673}
1674
1675/**
1676 * called by device driver when adding device instance
1677 * do generic HDLC initialization
1678 *
1679 * info pointer to device instance information
1680 *
1681 * returns 0 if success, otherwise error code
1682 */
1683static int hdlcdev_init(struct slgt_info *info)
1684{
1685 int rc;
1686 struct net_device *dev;
1687 hdlc_device *hdlc;
1688
1689 /* allocate and initialize network and HDLC layer objects */
1690
1691 if (!(dev = alloc_hdlcdev(info))) {
1692 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1693 return -ENOMEM;
1694 }
1695
1696 /* for network layer reporting purposes only */
1697 dev->mem_start = info->phys_reg_addr;
1698 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1699 dev->irq = info->irq_level;
1700
1701 /* network layer callbacks and settings */
1702 dev->do_ioctl = hdlcdev_ioctl;
1703 dev->open = hdlcdev_open;
1704 dev->stop = hdlcdev_close;
1705 dev->tx_timeout = hdlcdev_tx_timeout;
1706 dev->watchdog_timeo = 10*HZ;
1707 dev->tx_queue_len = 50;
1708
1709 /* generic HDLC layer callbacks and settings */
1710 hdlc = dev_to_hdlc(dev);
1711 hdlc->attach = hdlcdev_attach;
1712 hdlc->xmit = hdlcdev_xmit;
1713
1714 /* register objects with HDLC layer */
1715 if ((rc = register_hdlc_device(dev))) {
1716 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1717 free_netdev(dev);
1718 return rc;
1719 }
1720
1721 info->netdev = dev;
1722 return 0;
1723}
1724
1725/**
1726 * called by device driver when removing device instance
1727 * do generic HDLC cleanup
1728 *
1729 * info pointer to device instance information
1730 */
1731static void hdlcdev_exit(struct slgt_info *info)
1732{
1733 unregister_hdlc_device(info->netdev);
1734 free_netdev(info->netdev);
1735 info->netdev = NULL;
1736}
1737
1738#endif /* ifdef CONFIG_HDLC */
1739
1740/*
1741 * get async data from rx DMA buffers
1742 */
1743static void rx_async(struct slgt_info *info)
1744{
1745 struct tty_struct *tty = info->tty;
1746 struct mgsl_icount *icount = &info->icount;
1747 unsigned int start, end;
1748 unsigned char *p;
1749 unsigned char status;
1750 struct slgt_desc *bufs = info->rbufs;
1751 int i, count;
1752
1753 start = end = info->rbuf_current;
1754
1755 while(desc_complete(bufs[end])) {
1756 count = desc_count(bufs[end]) - info->rbuf_index;
1757 p = bufs[end].buf + info->rbuf_index;
1758
1759 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1760 DBGDATA(info, p, count, "rx");
1761
1762 for(i=0 ; i < count; i+=2, p+=2) {
1763 if (tty) {
1764 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1765 tty_flip_buffer_push(tty);
1766 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1767 break;
1768 *tty->flip.char_buf_ptr = *p;
1769 *tty->flip.flag_buf_ptr = 0;
1770 }
1771 icount->rx++;
1772
1773 if ((status = *(p+1) & (BIT9 + BIT8))) {
1774 if (status & BIT9)
1775 icount->parity++;
1776 else if (status & BIT8)
1777 icount->frame++;
1778 /* discard char if tty control flags say so */
1779 if (status & info->ignore_status_mask)
1780 continue;
1781 if (tty) {
1782 if (status & BIT9)
1783 *tty->flip.flag_buf_ptr = TTY_PARITY;
1784 else if (status & BIT8)
1785 *tty->flip.flag_buf_ptr = TTY_FRAME;
1786 }
1787 }
1788 if (tty) {
1789 tty->flip.flag_buf_ptr++;
1790 tty->flip.char_buf_ptr++;
1791 tty->flip.count++;
1792 }
1793 }
1794
1795 if (i < count) {
1796 /* receive buffer not completed */
1797 info->rbuf_index += i;
1798 info->rx_timer.expires = jiffies + 1;
1799 add_timer(&info->rx_timer);
1800 break;
1801 }
1802
1803 info->rbuf_index = 0;
1804 free_rbufs(info, end, end);
1805
1806 if (++end == info->rbuf_count)
1807 end = 0;
1808
1809 /* if entire list searched then no frame available */
1810 if (end == start)
1811 break;
1812 }
1813
1814 if (tty && tty->flip.count)
1815 tty_flip_buffer_push(tty);
1816}
1817
1818/*
1819 * return next bottom half action to perform
1820 */
1821static int bh_action(struct slgt_info *info)
1822{
1823 unsigned long flags;
1824 int rc;
1825
1826 spin_lock_irqsave(&info->lock,flags);
1827
1828 if (info->pending_bh & BH_RECEIVE) {
1829 info->pending_bh &= ~BH_RECEIVE;
1830 rc = BH_RECEIVE;
1831 } else if (info->pending_bh & BH_TRANSMIT) {
1832 info->pending_bh &= ~BH_TRANSMIT;
1833 rc = BH_TRANSMIT;
1834 } else if (info->pending_bh & BH_STATUS) {
1835 info->pending_bh &= ~BH_STATUS;
1836 rc = BH_STATUS;
1837 } else {
1838 /* Mark BH routine as complete */
1839 info->bh_running = 0;
1840 info->bh_requested = 0;
1841 rc = 0;
1842 }
1843
1844 spin_unlock_irqrestore(&info->lock,flags);
1845
1846 return rc;
1847}
1848
1849/*
1850 * perform bottom half processing
1851 */
1852static void bh_handler(void* context)
1853{
1854 struct slgt_info *info = context;
1855 int action;
1856
1857 if (!info)
1858 return;
1859 info->bh_running = 1;
1860
1861 while((action = bh_action(info))) {
1862 switch (action) {
1863 case BH_RECEIVE:
1864 DBGBH(("%s bh receive\n", info->device_name));
1865 switch(info->params.mode) {
1866 case MGSL_MODE_ASYNC:
1867 rx_async(info);
1868 break;
1869 case MGSL_MODE_HDLC:
1870 while(rx_get_frame(info));
1871 break;
1872 case MGSL_MODE_RAW:
1873 while(rx_get_buf(info));
1874 break;
1875 }
1876 /* restart receiver if rx DMA buffers exhausted */
1877 if (info->rx_restart)
1878 rx_start(info);
1879 break;
1880 case BH_TRANSMIT:
1881 bh_transmit(info);
1882 break;
1883 case BH_STATUS:
1884 DBGBH(("%s bh status\n", info->device_name));
1885 info->ri_chkcount = 0;
1886 info->dsr_chkcount = 0;
1887 info->dcd_chkcount = 0;
1888 info->cts_chkcount = 0;
1889 break;
1890 default:
1891 DBGBH(("%s unknown action\n", info->device_name));
1892 break;
1893 }
1894 }
1895 DBGBH(("%s bh_handler exit\n", info->device_name));
1896}
1897
1898static void bh_transmit(struct slgt_info *info)
1899{
1900 struct tty_struct *tty = info->tty;
1901
1902 DBGBH(("%s bh_transmit\n", info->device_name));
1903 if (tty) {
1904 tty_wakeup(tty);
1905 wake_up_interruptible(&tty->write_wait);
1906 }
1907}
1908
1909static void dsr_change(struct slgt_info *info)
1910{
1911 get_signals(info);
1912 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1913 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1914 slgt_irq_off(info, IRQ_DSR);
1915 return;
1916 }
1917 info->icount.dsr++;
1918 if (info->signals & SerialSignal_DSR)
1919 info->input_signal_events.dsr_up++;
1920 else
1921 info->input_signal_events.dsr_down++;
1922 wake_up_interruptible(&info->status_event_wait_q);
1923 wake_up_interruptible(&info->event_wait_q);
1924 info->pending_bh |= BH_STATUS;
1925}
1926
1927static void cts_change(struct slgt_info *info)
1928{
1929 get_signals(info);
1930 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1931 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1932 slgt_irq_off(info, IRQ_CTS);
1933 return;
1934 }
1935 info->icount.cts++;
1936 if (info->signals & SerialSignal_CTS)
1937 info->input_signal_events.cts_up++;
1938 else
1939 info->input_signal_events.cts_down++;
1940 wake_up_interruptible(&info->status_event_wait_q);
1941 wake_up_interruptible(&info->event_wait_q);
1942 info->pending_bh |= BH_STATUS;
1943
1944 if (info->flags & ASYNC_CTS_FLOW) {
1945 if (info->tty) {
1946 if (info->tty->hw_stopped) {
1947 if (info->signals & SerialSignal_CTS) {
1948 info->tty->hw_stopped = 0;
1949 info->pending_bh |= BH_TRANSMIT;
1950 return;
1951 }
1952 } else {
1953 if (!(info->signals & SerialSignal_CTS))
1954 info->tty->hw_stopped = 1;
1955 }
1956 }
1957 }
1958}
1959
1960static void dcd_change(struct slgt_info *info)
1961{
1962 get_signals(info);
1963 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1964 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1965 slgt_irq_off(info, IRQ_DCD);
1966 return;
1967 }
1968 info->icount.dcd++;
1969 if (info->signals & SerialSignal_DCD) {
1970 info->input_signal_events.dcd_up++;
1971 } else {
1972 info->input_signal_events.dcd_down++;
1973 }
1974#ifdef CONFIG_HDLC
1975 if (info->netcount)
1976 hdlc_set_carrier(info->signals & SerialSignal_DCD, info->netdev);
1977#endif
1978 wake_up_interruptible(&info->status_event_wait_q);
1979 wake_up_interruptible(&info->event_wait_q);
1980 info->pending_bh |= BH_STATUS;
1981
1982 if (info->flags & ASYNC_CHECK_CD) {
1983 if (info->signals & SerialSignal_DCD)
1984 wake_up_interruptible(&info->open_wait);
1985 else {
1986 if (info->tty)
1987 tty_hangup(info->tty);
1988 }
1989 }
1990}
1991
1992static void ri_change(struct slgt_info *info)
1993{
1994 get_signals(info);
1995 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
1996 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1997 slgt_irq_off(info, IRQ_RI);
1998 return;
1999 }
2000 info->icount.dcd++;
2001 if (info->signals & SerialSignal_RI) {
2002 info->input_signal_events.ri_up++;
2003 } else {
2004 info->input_signal_events.ri_down++;
2005 }
2006 wake_up_interruptible(&info->status_event_wait_q);
2007 wake_up_interruptible(&info->event_wait_q);
2008 info->pending_bh |= BH_STATUS;
2009}
2010
2011static void isr_serial(struct slgt_info *info)
2012{
2013 unsigned short status = rd_reg16(info, SSR);
2014
2015 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2016
2017 wr_reg16(info, SSR, status); /* clear pending */
2018
2019 info->irq_occurred = 1;
2020
2021 if (info->params.mode == MGSL_MODE_ASYNC) {
2022 if (status & IRQ_TXIDLE) {
2023 if (info->tx_count)
2024 isr_txeom(info, status);
2025 }
2026 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2027 info->icount.brk++;
2028 /* process break detection if tty control allows */
2029 if (info->tty) {
2030 if (!(status & info->ignore_status_mask)) {
2031 if (info->read_status_mask & MASK_BREAK) {
2032 *info->tty->flip.flag_buf_ptr = TTY_BREAK;
2033 if (info->flags & ASYNC_SAK)
2034 do_SAK(info->tty);
2035 }
2036 }
2037 }
2038 }
2039 } else {
2040 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2041 isr_txeom(info, status);
2042
2043 if (status & IRQ_RXIDLE) {
2044 if (status & RXIDLE)
2045 info->icount.rxidle++;
2046 else
2047 info->icount.exithunt++;
2048 wake_up_interruptible(&info->event_wait_q);
2049 }
2050
2051 if (status & IRQ_RXOVER)
2052 rx_start(info);
2053 }
2054
2055 if (status & IRQ_DSR)
2056 dsr_change(info);
2057 if (status & IRQ_CTS)
2058 cts_change(info);
2059 if (status & IRQ_DCD)
2060 dcd_change(info);
2061 if (status & IRQ_RI)
2062 ri_change(info);
2063}
2064
2065static void isr_rdma(struct slgt_info *info)
2066{
2067 unsigned int status = rd_reg32(info, RDCSR);
2068
2069 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2070
2071 /* RDCSR (rx DMA control/status)
2072 *
2073 * 31..07 reserved
2074 * 06 save status byte to DMA buffer
2075 * 05 error
2076 * 04 eol (end of list)
2077 * 03 eob (end of buffer)
2078 * 02 IRQ enable
2079 * 01 reset
2080 * 00 enable
2081 */
2082 wr_reg32(info, RDCSR, status); /* clear pending */
2083
2084 if (status & (BIT5 + BIT4)) {
2085 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2086 info->rx_restart = 1;
2087 }
2088 info->pending_bh |= BH_RECEIVE;
2089}
2090
2091static void isr_tdma(struct slgt_info *info)
2092{
2093 unsigned int status = rd_reg32(info, TDCSR);
2094
2095 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2096
2097 /* TDCSR (tx DMA control/status)
2098 *
2099 * 31..06 reserved
2100 * 05 error
2101 * 04 eol (end of list)
2102 * 03 eob (end of buffer)
2103 * 02 IRQ enable
2104 * 01 reset
2105 * 00 enable
2106 */
2107 wr_reg32(info, TDCSR, status); /* clear pending */
2108
2109 if (status & (BIT5 + BIT4 + BIT3)) {
2110 // another transmit buffer has completed
2111 // run bottom half to get more send data from user
2112 info->pending_bh |= BH_TRANSMIT;
2113 }
2114}
2115
2116static void isr_txeom(struct slgt_info *info, unsigned short status)
2117{
2118 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2119
2120 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2121 tdma_reset(info);
2122 reset_tbufs(info);
2123 if (status & IRQ_TXUNDER) {
2124 unsigned short val = rd_reg16(info, TCR);
2125 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2126 wr_reg16(info, TCR, val); /* clear reset bit */
2127 }
2128
2129 if (info->tx_active) {
2130 if (info->params.mode != MGSL_MODE_ASYNC) {
2131 if (status & IRQ_TXUNDER)
2132 info->icount.txunder++;
2133 else if (status & IRQ_TXIDLE)
2134 info->icount.txok++;
2135 }
2136
2137 info->tx_active = 0;
2138 info->tx_count = 0;
2139
2140 del_timer(&info->tx_timer);
2141
2142 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2143 info->signals &= ~SerialSignal_RTS;
2144 info->drop_rts_on_tx_done = 0;
2145 set_signals(info);
2146 }
2147
2148#ifdef CONFIG_HDLC
2149 if (info->netcount)
2150 hdlcdev_tx_done(info);
2151 else
2152#endif
2153 {
2154 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2155 tx_stop(info);
2156 return;
2157 }
2158 info->pending_bh |= BH_TRANSMIT;
2159 }
2160 }
2161}
2162
2163/* interrupt service routine
2164 *
2165 * irq interrupt number
2166 * dev_id device ID supplied during interrupt registration
2167 * regs interrupted processor context
2168 */
2169static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2170{
2171 struct slgt_info *info;
2172 unsigned int gsr;
2173 unsigned int i;
2174
2175 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2176
2177 info = dev_id;
2178 if (!info)
2179 return IRQ_NONE;
2180
2181 spin_lock(&info->lock);
2182
2183 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2184 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2185 info->irq_occurred = 1;
2186 for(i=0; i < info->port_count ; i++) {
2187 if (info->port_array[i] == NULL)
2188 continue;
2189 if (gsr & (BIT8 << i))
2190 isr_serial(info->port_array[i]);
2191 if (gsr & (BIT16 << (i*2)))
2192 isr_rdma(info->port_array[i]);
2193 if (gsr & (BIT17 << (i*2)))
2194 isr_tdma(info->port_array[i]);
2195 }
2196 }
2197
2198 for(i=0; i < info->port_count ; i++) {
2199 struct slgt_info *port = info->port_array[i];
2200
2201 if (port && (port->count || port->netcount) &&
2202 port->pending_bh && !port->bh_running &&
2203 !port->bh_requested) {
2204 DBGISR(("%s bh queued\n", port->device_name));
2205 schedule_work(&port->task);
2206 port->bh_requested = 1;
2207 }
2208 }
2209
2210 spin_unlock(&info->lock);
2211
2212 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2213 return IRQ_HANDLED;
2214}
2215
2216static int startup(struct slgt_info *info)
2217{
2218 DBGINFO(("%s startup\n", info->device_name));
2219
2220 if (info->flags & ASYNC_INITIALIZED)
2221 return 0;
2222
2223 if (!info->tx_buf) {
2224 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2225 if (!info->tx_buf) {
2226 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2227 return -ENOMEM;
2228 }
2229 }
2230
2231 info->pending_bh = 0;
2232
2233 memset(&info->icount, 0, sizeof(info->icount));
2234
2235 /* program hardware for current parameters */
2236 change_params(info);
2237
2238 if (info->tty)
2239 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2240
2241 info->flags |= ASYNC_INITIALIZED;
2242
2243 return 0;
2244}
2245
2246/*
2247 * called by close() and hangup() to shutdown hardware
2248 */
2249static void shutdown(struct slgt_info *info)
2250{
2251 unsigned long flags;
2252
2253 if (!(info->flags & ASYNC_INITIALIZED))
2254 return;
2255
2256 DBGINFO(("%s shutdown\n", info->device_name));
2257
2258 /* clear status wait queue because status changes */
2259 /* can't happen after shutting down the hardware */
2260 wake_up_interruptible(&info->status_event_wait_q);
2261 wake_up_interruptible(&info->event_wait_q);
2262
2263 del_timer_sync(&info->tx_timer);
2264 del_timer_sync(&info->rx_timer);
2265
2266 kfree(info->tx_buf);
2267 info->tx_buf = NULL;
2268
2269 spin_lock_irqsave(&info->lock,flags);
2270
2271 tx_stop(info);
2272 rx_stop(info);
2273
2274 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2275
2276 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2277 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2278 set_signals(info);
2279 }
2280
2281 spin_unlock_irqrestore(&info->lock,flags);
2282
2283 if (info->tty)
2284 set_bit(TTY_IO_ERROR, &info->tty->flags);
2285
2286 info->flags &= ~ASYNC_INITIALIZED;
2287}
2288
2289static void program_hw(struct slgt_info *info)
2290{
2291 unsigned long flags;
2292
2293 spin_lock_irqsave(&info->lock,flags);
2294
2295 rx_stop(info);
2296 tx_stop(info);
2297
2298 if (info->params.mode == MGSL_MODE_HDLC ||
2299 info->params.mode == MGSL_MODE_RAW ||
2300 info->netcount)
2301 hdlc_mode(info);
2302 else
2303 async_mode(info);
2304
2305 set_signals(info);
2306
2307 info->dcd_chkcount = 0;
2308 info->cts_chkcount = 0;
2309 info->ri_chkcount = 0;
2310 info->dsr_chkcount = 0;
2311
2312 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2313 get_signals(info);
2314
2315 if (info->netcount ||
2316 (info->tty && info->tty->termios->c_cflag & CREAD))
2317 rx_start(info);
2318
2319 spin_unlock_irqrestore(&info->lock,flags);
2320}
2321
2322/*
2323 * reconfigure adapter based on new parameters
2324 */
2325static void change_params(struct slgt_info *info)
2326{
2327 unsigned cflag;
2328 int bits_per_char;
2329
2330 if (!info->tty || !info->tty->termios)
2331 return;
2332 DBGINFO(("%s change_params\n", info->device_name));
2333
2334 cflag = info->tty->termios->c_cflag;
2335
2336 /* if B0 rate (hangup) specified then negate DTR and RTS */
2337 /* otherwise assert DTR and RTS */
2338 if (cflag & CBAUD)
2339 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2340 else
2341 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2342
2343 /* byte size and parity */
2344
2345 switch (cflag & CSIZE) {
2346 case CS5: info->params.data_bits = 5; break;
2347 case CS6: info->params.data_bits = 6; break;
2348 case CS7: info->params.data_bits = 7; break;
2349 case CS8: info->params.data_bits = 8; break;
2350 default: info->params.data_bits = 7; break;
2351 }
2352
2353 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2354
2355 if (cflag & PARENB)
2356 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2357 else
2358 info->params.parity = ASYNC_PARITY_NONE;
2359
2360 /* calculate number of jiffies to transmit a full
2361 * FIFO (32 bytes) at specified data rate
2362 */
2363 bits_per_char = info->params.data_bits +
2364 info->params.stop_bits + 1;
2365
2366 info->params.data_rate = tty_get_baud_rate(info->tty);
2367
2368 if (info->params.data_rate) {
2369 info->timeout = (32*HZ*bits_per_char) /
2370 info->params.data_rate;
2371 }
2372 info->timeout += HZ/50; /* Add .02 seconds of slop */
2373
2374 if (cflag & CRTSCTS)
2375 info->flags |= ASYNC_CTS_FLOW;
2376 else
2377 info->flags &= ~ASYNC_CTS_FLOW;
2378
2379 if (cflag & CLOCAL)
2380 info->flags &= ~ASYNC_CHECK_CD;
2381 else
2382 info->flags |= ASYNC_CHECK_CD;
2383
2384 /* process tty input control flags */
2385
2386 info->read_status_mask = IRQ_RXOVER;
2387 if (I_INPCK(info->tty))
2388 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2389 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2390 info->read_status_mask |= MASK_BREAK;
2391 if (I_IGNPAR(info->tty))
2392 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2393 if (I_IGNBRK(info->tty)) {
2394 info->ignore_status_mask |= MASK_BREAK;
2395 /* If ignoring parity and break indicators, ignore
2396 * overruns too. (For real raw support).
2397 */
2398 if (I_IGNPAR(info->tty))
2399 info->ignore_status_mask |= MASK_OVERRUN;
2400 }
2401
2402 program_hw(info);
2403}
2404
2405static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2406{
2407 DBGINFO(("%s get_stats\n", info->device_name));
2408 if (!user_icount) {
2409 memset(&info->icount, 0, sizeof(info->icount));
2410 } else {
2411 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2412 return -EFAULT;
2413 }
2414 return 0;
2415}
2416
2417static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2418{
2419 DBGINFO(("%s get_params\n", info->device_name));
2420 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2421 return -EFAULT;
2422 return 0;
2423}
2424
2425static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2426{
2427 unsigned long flags;
2428 MGSL_PARAMS tmp_params;
2429
2430 DBGINFO(("%s set_params\n", info->device_name));
2431 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2432 return -EFAULT;
2433
2434 spin_lock_irqsave(&info->lock, flags);
2435 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2436 spin_unlock_irqrestore(&info->lock, flags);
2437
2438 change_params(info);
2439
2440 return 0;
2441}
2442
2443static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2444{
2445 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2446 if (put_user(info->idle_mode, idle_mode))
2447 return -EFAULT;
2448 return 0;
2449}
2450
2451static int set_txidle(struct slgt_info *info, int idle_mode)
2452{
2453 unsigned long flags;
2454 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2455 spin_lock_irqsave(&info->lock,flags);
2456 info->idle_mode = idle_mode;
2457 tx_set_idle(info);
2458 spin_unlock_irqrestore(&info->lock,flags);
2459 return 0;
2460}
2461
2462static int tx_enable(struct slgt_info *info, int enable)
2463{
2464 unsigned long flags;
2465 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2466 spin_lock_irqsave(&info->lock,flags);
2467 if (enable) {
2468 if (!info->tx_enabled)
2469 tx_start(info);
2470 } else {
2471 if (info->tx_enabled)
2472 tx_stop(info);
2473 }
2474 spin_unlock_irqrestore(&info->lock,flags);
2475 return 0;
2476}
2477
2478/*
2479 * abort transmit HDLC frame
2480 */
2481static int tx_abort(struct slgt_info *info)
2482{
2483 unsigned long flags;
2484 DBGINFO(("%s tx_abort\n", info->device_name));
2485 spin_lock_irqsave(&info->lock,flags);
2486 tdma_reset(info);
2487 spin_unlock_irqrestore(&info->lock,flags);
2488 return 0;
2489}
2490
2491static int rx_enable(struct slgt_info *info, int enable)
2492{
2493 unsigned long flags;
2494 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2495 spin_lock_irqsave(&info->lock,flags);
2496 if (enable) {
2497 if (!info->rx_enabled)
2498 rx_start(info);
2499 } else {
2500 if (info->rx_enabled)
2501 rx_stop(info);
2502 }
2503 spin_unlock_irqrestore(&info->lock,flags);
2504 return 0;
2505}
2506
2507/*
2508 * wait for specified event to occur
2509 */
2510static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2511{
2512 unsigned long flags;
2513 int s;
2514 int rc=0;
2515 struct mgsl_icount cprev, cnow;
2516 int events;
2517 int mask;
2518 struct _input_signal_events oldsigs, newsigs;
2519 DECLARE_WAITQUEUE(wait, current);
2520
2521 if (get_user(mask, mask_ptr))
2522 return -EFAULT;
2523
2524 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2525
2526 spin_lock_irqsave(&info->lock,flags);
2527
2528 /* return immediately if state matches requested events */
2529 get_signals(info);
2530 s = info->signals;
2531
2532 events = mask &
2533 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2534 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2535 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2536 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2537 if (events) {
2538 spin_unlock_irqrestore(&info->lock,flags);
2539 goto exit;
2540 }
2541
2542 /* save current irq counts */
2543 cprev = info->icount;
2544 oldsigs = info->input_signal_events;
2545
2546 /* enable hunt and idle irqs if needed */
2547 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2548 unsigned short val = rd_reg16(info, SCR);
2549 if (!(val & IRQ_RXIDLE))
2550 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2551 }
2552
2553 set_current_state(TASK_INTERRUPTIBLE);
2554 add_wait_queue(&info->event_wait_q, &wait);
2555
2556 spin_unlock_irqrestore(&info->lock,flags);
2557
2558 for(;;) {
2559 schedule();
2560 if (signal_pending(current)) {
2561 rc = -ERESTARTSYS;
2562 break;
2563 }
2564
2565 /* get current irq counts */
2566 spin_lock_irqsave(&info->lock,flags);
2567 cnow = info->icount;
2568 newsigs = info->input_signal_events;
2569 set_current_state(TASK_INTERRUPTIBLE);
2570 spin_unlock_irqrestore(&info->lock,flags);
2571
2572 /* if no change, wait aborted for some reason */
2573 if (newsigs.dsr_up == oldsigs.dsr_up &&
2574 newsigs.dsr_down == oldsigs.dsr_down &&
2575 newsigs.dcd_up == oldsigs.dcd_up &&
2576 newsigs.dcd_down == oldsigs.dcd_down &&
2577 newsigs.cts_up == oldsigs.cts_up &&
2578 newsigs.cts_down == oldsigs.cts_down &&
2579 newsigs.ri_up == oldsigs.ri_up &&
2580 newsigs.ri_down == oldsigs.ri_down &&
2581 cnow.exithunt == cprev.exithunt &&
2582 cnow.rxidle == cprev.rxidle) {
2583 rc = -EIO;
2584 break;
2585 }
2586
2587 events = mask &
2588 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2589 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2590 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2591 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2592 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2593 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2594 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2595 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2596 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2597 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2598 if (events)
2599 break;
2600
2601 cprev = cnow;
2602 oldsigs = newsigs;
2603 }
2604
2605 remove_wait_queue(&info->event_wait_q, &wait);
2606 set_current_state(TASK_RUNNING);
2607
2608
2609 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2610 spin_lock_irqsave(&info->lock,flags);
2611 if (!waitqueue_active(&info->event_wait_q)) {
2612 /* disable enable exit hunt mode/idle rcvd IRQs */
2613 wr_reg16(info, SCR,
2614 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2615 }
2616 spin_unlock_irqrestore(&info->lock,flags);
2617 }
2618exit:
2619 if (rc == 0)
2620 rc = put_user(events, mask_ptr);
2621 return rc;
2622}
2623
2624static int get_interface(struct slgt_info *info, int __user *if_mode)
2625{
2626 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2627 if (put_user(info->if_mode, if_mode))
2628 return -EFAULT;
2629 return 0;
2630}
2631
2632static int set_interface(struct slgt_info *info, int if_mode)
2633{
2634 unsigned long flags;
2635 unsigned char val;
2636
2637 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2638 spin_lock_irqsave(&info->lock,flags);
2639 info->if_mode = if_mode;
2640
2641 msc_set_vcr(info);
2642
2643 /* TCR (tx control) 07 1=RTS driver control */
2644 val = rd_reg16(info, TCR);
2645 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2646 val |= BIT7;
2647 else
2648 val &= ~BIT7;
2649 wr_reg16(info, TCR, val);
2650
2651 spin_unlock_irqrestore(&info->lock,flags);
2652 return 0;
2653}
2654
2655static int modem_input_wait(struct slgt_info *info,int arg)
2656{
2657 unsigned long flags;
2658 int rc;
2659 struct mgsl_icount cprev, cnow;
2660 DECLARE_WAITQUEUE(wait, current);
2661
2662 /* save current irq counts */
2663 spin_lock_irqsave(&info->lock,flags);
2664 cprev = info->icount;
2665 add_wait_queue(&info->status_event_wait_q, &wait);
2666 set_current_state(TASK_INTERRUPTIBLE);
2667 spin_unlock_irqrestore(&info->lock,flags);
2668
2669 for(;;) {
2670 schedule();
2671 if (signal_pending(current)) {
2672 rc = -ERESTARTSYS;
2673 break;
2674 }
2675
2676 /* get new irq counts */
2677 spin_lock_irqsave(&info->lock,flags);
2678 cnow = info->icount;
2679 set_current_state(TASK_INTERRUPTIBLE);
2680 spin_unlock_irqrestore(&info->lock,flags);
2681
2682 /* if no change, wait aborted for some reason */
2683 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2684 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2685 rc = -EIO;
2686 break;
2687 }
2688
2689 /* check for change in caller specified modem input */
2690 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2691 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2692 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2693 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2694 rc = 0;
2695 break;
2696 }
2697
2698 cprev = cnow;
2699 }
2700 remove_wait_queue(&info->status_event_wait_q, &wait);
2701 set_current_state(TASK_RUNNING);
2702 return rc;
2703}
2704
2705/*
2706 * return state of serial control and status signals
2707 */
2708static int tiocmget(struct tty_struct *tty, struct file *file)
2709{
2710 struct slgt_info *info = tty->driver_data;
2711 unsigned int result;
2712 unsigned long flags;
2713
2714 spin_lock_irqsave(&info->lock,flags);
2715 get_signals(info);
2716 spin_unlock_irqrestore(&info->lock,flags);
2717
2718 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2719 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2720 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2721 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2722 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2723 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2724
2725 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2726 return result;
2727}
2728
2729/*
2730 * set modem control signals (DTR/RTS)
2731 *
2732 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2733 * TIOCMSET = set/clear signal values
2734 * value bit mask for command
2735 */
2736static int tiocmset(struct tty_struct *tty, struct file *file,
2737 unsigned int set, unsigned int clear)
2738{
2739 struct slgt_info *info = tty->driver_data;
2740 unsigned long flags;
2741
2742 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2743
2744 if (set & TIOCM_RTS)
2745 info->signals |= SerialSignal_RTS;
2746 if (set & TIOCM_DTR)
2747 info->signals |= SerialSignal_DTR;
2748 if (clear & TIOCM_RTS)
2749 info->signals &= ~SerialSignal_RTS;
2750 if (clear & TIOCM_DTR)
2751 info->signals &= ~SerialSignal_DTR;
2752
2753 spin_lock_irqsave(&info->lock,flags);
2754 set_signals(info);
2755 spin_unlock_irqrestore(&info->lock,flags);
2756 return 0;
2757}
2758
2759/*
2760 * block current process until the device is ready to open
2761 */
2762static int block_til_ready(struct tty_struct *tty, struct file *filp,
2763 struct slgt_info *info)
2764{
2765 DECLARE_WAITQUEUE(wait, current);
2766 int retval;
2767 int do_clocal = 0, extra_count = 0;
2768 unsigned long flags;
2769
2770 DBGINFO(("%s block_til_ready\n", tty->driver->name));
2771
2772 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
2773 /* nonblock mode is set or port is not enabled */
2774 info->flags |= ASYNC_NORMAL_ACTIVE;
2775 return 0;
2776 }
2777
2778 if (tty->termios->c_cflag & CLOCAL)
2779 do_clocal = 1;
2780
2781 /* Wait for carrier detect and the line to become
2782 * free (i.e., not in use by the callout). While we are in
2783 * this loop, info->count is dropped by one, so that
2784 * close() knows when to free things. We restore it upon
2785 * exit, either normal or abnormal.
2786 */
2787
2788 retval = 0;
2789 add_wait_queue(&info->open_wait, &wait);
2790
2791 spin_lock_irqsave(&info->lock, flags);
2792 if (!tty_hung_up_p(filp)) {
2793 extra_count = 1;
2794 info->count--;
2795 }
2796 spin_unlock_irqrestore(&info->lock, flags);
2797 info->blocked_open++;
2798
2799 while (1) {
2800 if ((tty->termios->c_cflag & CBAUD)) {
2801 spin_lock_irqsave(&info->lock,flags);
2802 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2803 set_signals(info);
2804 spin_unlock_irqrestore(&info->lock,flags);
2805 }
2806
2807 set_current_state(TASK_INTERRUPTIBLE);
2808
2809 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
2810 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
2811 -EAGAIN : -ERESTARTSYS;
2812 break;
2813 }
2814
2815 spin_lock_irqsave(&info->lock,flags);
2816 get_signals(info);
2817 spin_unlock_irqrestore(&info->lock,flags);
2818
2819 if (!(info->flags & ASYNC_CLOSING) &&
2820 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
2821 break;
2822 }
2823
2824 if (signal_pending(current)) {
2825 retval = -ERESTARTSYS;
2826 break;
2827 }
2828
2829 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
2830 schedule();
2831 }
2832
2833 set_current_state(TASK_RUNNING);
2834 remove_wait_queue(&info->open_wait, &wait);
2835
2836 if (extra_count)
2837 info->count++;
2838 info->blocked_open--;
2839
2840 if (!retval)
2841 info->flags |= ASYNC_NORMAL_ACTIVE;
2842
2843 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
2844 return retval;
2845}
2846
2847static int alloc_tmp_rbuf(struct slgt_info *info)
2848{
2849 info->tmp_rbuf = kmalloc(info->max_frame_size, GFP_KERNEL);
2850 if (info->tmp_rbuf == NULL)
2851 return -ENOMEM;
2852 return 0;
2853}
2854
2855static void free_tmp_rbuf(struct slgt_info *info)
2856{
2857 kfree(info->tmp_rbuf);
2858 info->tmp_rbuf = NULL;
2859}
2860
2861/*
2862 * allocate DMA descriptor lists.
2863 */
2864static int alloc_desc(struct slgt_info *info)
2865{
2866 unsigned int i;
2867 unsigned int pbufs;
2868
2869 /* allocate memory to hold descriptor lists */
2870 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
2871 if (info->bufs == NULL)
2872 return -ENOMEM;
2873
2874 memset(info->bufs, 0, DESC_LIST_SIZE);
2875
2876 info->rbufs = (struct slgt_desc*)info->bufs;
2877 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
2878
2879 pbufs = (unsigned int)info->bufs_dma_addr;
2880
2881 /*
2882 * Build circular lists of descriptors
2883 */
2884
2885 for (i=0; i < info->rbuf_count; i++) {
2886 /* physical address of this descriptor */
2887 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
2888
2889 /* physical address of next descriptor */
2890 if (i == info->rbuf_count - 1)
2891 info->rbufs[i].next = cpu_to_le32(pbufs);
2892 else
2893 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
2894 set_desc_count(info->rbufs[i], DMABUFSIZE);
2895 }
2896
2897 for (i=0; i < info->tbuf_count; i++) {
2898 /* physical address of this descriptor */
2899 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
2900
2901 /* physical address of next descriptor */
2902 if (i == info->tbuf_count - 1)
2903 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
2904 else
2905 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
2906 }
2907
2908 return 0;
2909}
2910
2911static void free_desc(struct slgt_info *info)
2912{
2913 if (info->bufs != NULL) {
2914 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
2915 info->bufs = NULL;
2916 info->rbufs = NULL;
2917 info->tbufs = NULL;
2918 }
2919}
2920
2921static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
2922{
2923 int i;
2924 for (i=0; i < count; i++) {
2925 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
2926 return -ENOMEM;
2927 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
2928 }
2929 return 0;
2930}
2931
2932static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
2933{
2934 int i;
2935 for (i=0; i < count; i++) {
2936 if (bufs[i].buf == NULL)
2937 continue;
2938 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
2939 bufs[i].buf = NULL;
2940 }
2941}
2942
2943static int alloc_dma_bufs(struct slgt_info *info)
2944{
2945 info->rbuf_count = 32;
2946 info->tbuf_count = 32;
2947
2948 if (alloc_desc(info) < 0 ||
2949 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
2950 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
2951 alloc_tmp_rbuf(info) < 0) {
2952 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
2953 return -ENOMEM;
2954 }
2955 reset_rbufs(info);
2956 return 0;
2957}
2958
2959static void free_dma_bufs(struct slgt_info *info)
2960{
2961 if (info->bufs) {
2962 free_bufs(info, info->rbufs, info->rbuf_count);
2963 free_bufs(info, info->tbufs, info->tbuf_count);
2964 free_desc(info);
2965 }
2966 free_tmp_rbuf(info);
2967}
2968
2969static int claim_resources(struct slgt_info *info)
2970{
2971 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
2972 DBGERR(("%s reg addr conflict, addr=%08X\n",
2973 info->device_name, info->phys_reg_addr));
2974 info->init_error = DiagStatus_AddressConflict;
2975 goto errout;
2976 }
2977 else
2978 info->reg_addr_requested = 1;
2979
2980 info->reg_addr = ioremap(info->phys_reg_addr, PAGE_SIZE);
2981 if (!info->reg_addr) {
2982 DBGERR(("%s cant map device registers, addr=%08X\n",
2983 info->device_name, info->phys_reg_addr));
2984 info->init_error = DiagStatus_CantAssignPciResources;
2985 goto errout;
2986 }
2987 info->reg_addr += info->reg_offset;
2988 return 0;
2989
2990errout:
2991 release_resources(info);
2992 return -ENODEV;
2993}
2994
2995static void release_resources(struct slgt_info *info)
2996{
2997 if (info->irq_requested) {
2998 free_irq(info->irq_level, info);
2999 info->irq_requested = 0;
3000 }
3001
3002 if (info->reg_addr_requested) {
3003 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3004 info->reg_addr_requested = 0;
3005 }
3006
3007 if (info->reg_addr) {
3008 iounmap(info->reg_addr - info->reg_offset);
3009 info->reg_addr = NULL;
3010 }
3011}
3012
3013/* Add the specified device instance data structure to the
3014 * global linked list of devices and increment the device count.
3015 */
3016static void add_device(struct slgt_info *info)
3017{
3018 char *devstr;
3019
3020 info->next_device = NULL;
3021 info->line = slgt_device_count;
3022 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3023
3024 if (info->line < MAX_DEVICES) {
3025 if (maxframe[info->line])
3026 info->max_frame_size = maxframe[info->line];
3027 info->dosyncppp = dosyncppp[info->line];
3028 }
3029
3030 slgt_device_count++;
3031
3032 if (!slgt_device_list)
3033 slgt_device_list = info;
3034 else {
3035 struct slgt_info *current_dev = slgt_device_list;
3036 while(current_dev->next_device)
3037 current_dev = current_dev->next_device;
3038 current_dev->next_device = info;
3039 }
3040
3041 if (info->max_frame_size < 4096)
3042 info->max_frame_size = 4096;
3043 else if (info->max_frame_size > 65535)
3044 info->max_frame_size = 65535;
3045
3046 switch(info->pdev->device) {
3047 case SYNCLINK_GT_DEVICE_ID:
3048 devstr = "GT";
3049 break;
3050 case SYNCLINK_GT4_DEVICE_ID:
3051 devstr = "GT4";
3052 break;
3053 case SYNCLINK_AC_DEVICE_ID:
3054 devstr = "AC";
3055 info->params.mode = MGSL_MODE_ASYNC;
3056 break;
3057 default:
3058 devstr = "(unknown model)";
3059 }
3060 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3061 devstr, info->device_name, info->phys_reg_addr,
3062 info->irq_level, info->max_frame_size);
3063
3064#ifdef CONFIG_HDLC
3065 hdlcdev_init(info);
3066#endif
3067}
3068
3069/*
3070 * allocate device instance structure, return NULL on failure
3071 */
3072static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3073{
3074 struct slgt_info *info;
3075
3076 info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3077
3078 if (!info) {
3079 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3080 driver_name, adapter_num, port_num));
3081 } else {
3082 memset(info, 0, sizeof(struct slgt_info));
3083 info->magic = MGSL_MAGIC;
3084 INIT_WORK(&info->task, bh_handler, info);
3085 info->max_frame_size = 4096;
3086 info->raw_rx_size = DMABUFSIZE;
3087 info->close_delay = 5*HZ/10;
3088 info->closing_wait = 30*HZ;
3089 init_waitqueue_head(&info->open_wait);
3090 init_waitqueue_head(&info->close_wait);
3091 init_waitqueue_head(&info->status_event_wait_q);
3092 init_waitqueue_head(&info->event_wait_q);
3093 spin_lock_init(&info->netlock);
3094 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3095 info->idle_mode = HDLC_TXIDLE_FLAGS;
3096 info->adapter_num = adapter_num;
3097 info->port_num = port_num;
3098
3099 init_timer(&info->tx_timer);
3100 info->tx_timer.data = (unsigned long)info;
3101 info->tx_timer.function = tx_timeout;
3102
3103 init_timer(&info->rx_timer);
3104 info->rx_timer.data = (unsigned long)info;
3105 info->rx_timer.function = rx_timeout;
3106
3107 /* Copy configuration info to device instance data */
3108 info->pdev = pdev;
3109 info->irq_level = pdev->irq;
3110 info->phys_reg_addr = pci_resource_start(pdev,0);
3111
3112 /* veremap works on page boundaries
3113 * map full page starting at the page boundary
3114 */
3115 info->reg_offset = info->phys_reg_addr & (PAGE_SIZE-1);
3116 info->phys_reg_addr &= ~(PAGE_SIZE-1);
3117
3118 info->bus_type = MGSL_BUS_TYPE_PCI;
3119 info->irq_flags = SA_SHIRQ;
3120
3121 info->init_error = -1; /* assume error, set to 0 on successful init */
3122 }
3123
3124 return info;
3125}
3126
3127static void device_init(int adapter_num, struct pci_dev *pdev)
3128{
3129 struct slgt_info *port_array[SLGT_MAX_PORTS];
3130 int i;
3131 int port_count = 1;
3132
3133 if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3134 port_count = 4;
3135
3136 /* allocate device instances for all ports */
3137 for (i=0; i < port_count; ++i) {
3138 port_array[i] = alloc_dev(adapter_num, i, pdev);
3139 if (port_array[i] == NULL) {
3140 for (--i; i >= 0; --i)
3141 kfree(port_array[i]);
3142 return;
3143 }
3144 }
3145
3146 /* give copy of port_array to all ports and add to device list */
3147 for (i=0; i < port_count; ++i) {
3148 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3149 add_device(port_array[i]);
3150 port_array[i]->port_count = port_count;
3151 spin_lock_init(&port_array[i]->lock);
3152 }
3153
3154 /* Allocate and claim adapter resources */
3155 if (!claim_resources(port_array[0])) {
3156
3157 alloc_dma_bufs(port_array[0]);
3158
3159 /* copy resource information from first port to others */
3160 for (i = 1; i < port_count; ++i) {
3161 port_array[i]->lock = port_array[0]->lock;
3162 port_array[i]->irq_level = port_array[0]->irq_level;
3163 port_array[i]->reg_addr = port_array[0]->reg_addr;
3164 alloc_dma_bufs(port_array[i]);
3165 }
3166
3167 if (request_irq(port_array[0]->irq_level,
3168 slgt_interrupt,
3169 port_array[0]->irq_flags,
3170 port_array[0]->device_name,
3171 port_array[0]) < 0) {
3172 DBGERR(("%s request_irq failed IRQ=%d\n",
3173 port_array[0]->device_name,
3174 port_array[0]->irq_level));
3175 } else {
3176 port_array[0]->irq_requested = 1;
3177 adapter_test(port_array[0]);
3178 for (i=1 ; i < port_count ; i++)
3179 port_array[i]->init_error = port_array[0]->init_error;
3180 }
3181 }
3182}
3183
3184static int __devinit init_one(struct pci_dev *dev,
3185 const struct pci_device_id *ent)
3186{
3187 if (pci_enable_device(dev)) {
3188 printk("error enabling pci device %p\n", dev);
3189 return -EIO;
3190 }
3191 pci_set_master(dev);
3192 device_init(slgt_device_count, dev);
3193 return 0;
3194}
3195
3196static void __devexit remove_one(struct pci_dev *dev)
3197{
3198}
3199
3200static struct tty_operations ops = {
3201 .open = open,
3202 .close = close,
3203 .write = write,
3204 .put_char = put_char,
3205 .flush_chars = flush_chars,
3206 .write_room = write_room,
3207 .chars_in_buffer = chars_in_buffer,
3208 .flush_buffer = flush_buffer,
3209 .ioctl = ioctl,
3210 .throttle = throttle,
3211 .unthrottle = unthrottle,
3212 .send_xchar = send_xchar,
3213 .break_ctl = set_break,
3214 .wait_until_sent = wait_until_sent,
3215 .read_proc = read_proc,
3216 .set_termios = set_termios,
3217 .stop = tx_hold,
3218 .start = tx_release,
3219 .hangup = hangup,
3220 .tiocmget = tiocmget,
3221 .tiocmset = tiocmset,
3222};
3223
3224static void slgt_cleanup(void)
3225{
3226 int rc;
3227 struct slgt_info *info;
3228 struct slgt_info *tmp;
3229
3230 printk("unload %s %s\n", driver_name, driver_version);
3231
3232 if (serial_driver) {
3233 if ((rc = tty_unregister_driver(serial_driver)))
3234 DBGERR(("tty_unregister_driver error=%d\n", rc));
3235 put_tty_driver(serial_driver);
3236 }
3237
3238 /* reset devices */
3239 info = slgt_device_list;
3240 while(info) {
3241 reset_port(info);
3242 info = info->next_device;
3243 }
3244
3245 /* release devices */
3246 info = slgt_device_list;
3247 while(info) {
3248#ifdef CONFIG_HDLC
3249 hdlcdev_exit(info);
3250#endif
3251 free_dma_bufs(info);
3252 free_tmp_rbuf(info);
3253 if (info->port_num == 0)
3254 release_resources(info);
3255 tmp = info;
3256 info = info->next_device;
3257 kfree(tmp);
3258 }
3259
3260 if (pci_registered)
3261 pci_unregister_driver(&pci_driver);
3262}
3263
3264/*
3265 * Driver initialization entry point.
3266 */
3267static int __init slgt_init(void)
3268{
3269 int rc;
3270
3271 printk("%s %s\n", driver_name, driver_version);
3272
3273 slgt_device_count = 0;
3274 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3275 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3276 return rc;
3277 }
3278 pci_registered = 1;
3279
3280 if (!slgt_device_list) {
3281 printk("%s no devices found\n",driver_name);
3282 return -ENODEV;
3283 }
3284
3285 serial_driver = alloc_tty_driver(MAX_DEVICES);
3286 if (!serial_driver) {
3287 rc = -ENOMEM;
3288 goto error;
3289 }
3290
3291 /* Initialize the tty_driver structure */
3292
3293 serial_driver->owner = THIS_MODULE;
3294 serial_driver->driver_name = tty_driver_name;
3295 serial_driver->name = tty_dev_prefix;
3296 serial_driver->major = ttymajor;
3297 serial_driver->minor_start = 64;
3298 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3299 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3300 serial_driver->init_termios = tty_std_termios;
3301 serial_driver->init_termios.c_cflag =
3302 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3303 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3304 tty_set_operations(serial_driver, &ops);
3305 if ((rc = tty_register_driver(serial_driver)) < 0) {
3306 DBGERR(("%s can't register serial driver\n", driver_name));
3307 put_tty_driver(serial_driver);
3308 serial_driver = NULL;
3309 goto error;
3310 }
3311
3312 printk("%s %s, tty major#%d\n",
3313 driver_name, driver_version,
3314 serial_driver->major);
3315
3316 return 0;
3317
3318error:
3319 slgt_cleanup();
3320 return rc;
3321}
3322
3323static void __exit slgt_exit(void)
3324{
3325 slgt_cleanup();
3326}
3327
3328module_init(slgt_init);
3329module_exit(slgt_exit);
3330
3331/*
3332 * register access routines
3333 */
3334
3335#define CALC_REGADDR() \
3336 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3337 if (addr >= 0x80) \
3338 reg_addr += (info->port_num) * 32;
3339
3340static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3341{
3342 CALC_REGADDR();
3343 return readb((void __iomem *)reg_addr);
3344}
3345
3346static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3347{
3348 CALC_REGADDR();
3349 writeb(value, (void __iomem *)reg_addr);
3350}
3351
3352static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3353{
3354 CALC_REGADDR();
3355 return readw((void __iomem *)reg_addr);
3356}
3357
3358static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3359{
3360 CALC_REGADDR();
3361 writew(value, (void __iomem *)reg_addr);
3362}
3363
3364static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3365{
3366 CALC_REGADDR();
3367 return readl((void __iomem *)reg_addr);
3368}
3369
3370static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3371{
3372 CALC_REGADDR();
3373 writel(value, (void __iomem *)reg_addr);
3374}
3375
3376static void rdma_reset(struct slgt_info *info)
3377{
3378 unsigned int i;
3379
3380 /* set reset bit */
3381 wr_reg32(info, RDCSR, BIT1);
3382
3383 /* wait for enable bit cleared */
3384 for(i=0 ; i < 1000 ; i++)
3385 if (!(rd_reg32(info, RDCSR) & BIT0))
3386 break;
3387}
3388
3389static void tdma_reset(struct slgt_info *info)
3390{
3391 unsigned int i;
3392
3393 /* set reset bit */
3394 wr_reg32(info, TDCSR, BIT1);
3395
3396 /* wait for enable bit cleared */
3397 for(i=0 ; i < 1000 ; i++)
3398 if (!(rd_reg32(info, TDCSR) & BIT0))
3399 break;
3400}
3401
3402/*
3403 * enable internal loopback
3404 * TxCLK and RxCLK are generated from BRG
3405 * and TxD is looped back to RxD internally.
3406 */
3407static void enable_loopback(struct slgt_info *info)
3408{
3409 /* SCR (serial control) BIT2=looopback enable */
3410 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3411
3412 if (info->params.mode != MGSL_MODE_ASYNC) {
3413 /* CCR (clock control)
3414 * 07..05 tx clock source (010 = BRG)
3415 * 04..02 rx clock source (010 = BRG)
3416 * 01 auxclk enable (0 = disable)
3417 * 00 BRG enable (1 = enable)
3418 *
3419 * 0100 1001
3420 */
3421 wr_reg8(info, CCR, 0x49);
3422
3423 /* set speed if available, otherwise use default */
3424 if (info->params.clock_speed)
3425 set_rate(info, info->params.clock_speed);
3426 else
3427 set_rate(info, 3686400);
3428 }
3429}
3430
3431/*
3432 * set baud rate generator to specified rate
3433 */
3434static void set_rate(struct slgt_info *info, u32 rate)
3435{
3436 unsigned int div;
3437 static unsigned int osc = 14745600;
3438
3439 /* div = osc/rate - 1
3440 *
3441 * Round div up if osc/rate is not integer to
3442 * force to next slowest rate.
3443 */
3444
3445 if (rate) {
3446 div = osc/rate;
3447 if (!(osc % rate) && div)
3448 div--;
3449 wr_reg16(info, BDR, (unsigned short)div);
3450 }
3451}
3452
3453static void rx_stop(struct slgt_info *info)
3454{
3455 unsigned short val;
3456
3457 /* disable and reset receiver */
3458 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3459 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3460 wr_reg16(info, RCR, val); /* clear reset bit */
3461
3462 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3463
3464 /* clear pending rx interrupts */
3465 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3466
3467 rdma_reset(info);
3468
3469 info->rx_enabled = 0;
3470 info->rx_restart = 0;
3471}
3472
3473static void rx_start(struct slgt_info *info)
3474{
3475 unsigned short val;
3476
3477 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3478
3479 /* clear pending rx overrun IRQ */
3480 wr_reg16(info, SSR, IRQ_RXOVER);
3481
3482 /* reset and disable receiver */
3483 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3484 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3485 wr_reg16(info, RCR, val); /* clear reset bit */
3486
3487 rdma_reset(info);
3488 reset_rbufs(info);
3489
3490 /* set 1st descriptor address */
3491 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3492
3493 if (info->params.mode != MGSL_MODE_ASYNC) {
3494 /* enable rx DMA and DMA interrupt */
3495 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3496 } else {
3497 /* enable saving of rx status, rx DMA and DMA interrupt */
3498 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3499 }
3500
3501 slgt_irq_on(info, IRQ_RXOVER);
3502
3503 /* enable receiver */
3504 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3505
3506 info->rx_restart = 0;
3507 info->rx_enabled = 1;
3508}
3509
3510static void tx_start(struct slgt_info *info)
3511{
3512 if (!info->tx_enabled) {
3513 wr_reg16(info, TCR,
3514 (unsigned short)(rd_reg16(info, TCR) | BIT1));
3515 info->tx_enabled = TRUE;
3516 }
3517
3518 if (info->tx_count) {
3519 info->drop_rts_on_tx_done = 0;
3520
3521 if (info->params.mode != MGSL_MODE_ASYNC) {
3522 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3523 get_signals(info);
3524 if (!(info->signals & SerialSignal_RTS)) {
3525 info->signals |= SerialSignal_RTS;
3526 set_signals(info);
3527 info->drop_rts_on_tx_done = 1;
3528 }
3529 }
3530
3531 slgt_irq_off(info, IRQ_TXDATA);
3532 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3533 /* clear tx idle and underrun status bits */
3534 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3535
3536 if (!(rd_reg32(info, TDCSR) & BIT0)) {
3537 /* tx DMA stopped, restart tx DMA */
3538 tdma_reset(info);
3539 /* set 1st descriptor address */
3540 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3541 if (info->params.mode == MGSL_MODE_RAW)
3542 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3543 else
3544 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3545 }
3546
3547 if (info->params.mode != MGSL_MODE_RAW) {
3548 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3549 add_timer(&info->tx_timer);
3550 }
3551 } else {
3552 tdma_reset(info);
3553 /* set 1st descriptor address */
3554 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3555
3556 slgt_irq_off(info, IRQ_TXDATA);
3557 slgt_irq_on(info, IRQ_TXIDLE);
3558 /* clear tx idle status bit */
3559 wr_reg16(info, SSR, IRQ_TXIDLE);
3560
3561 /* enable tx DMA */
3562 wr_reg32(info, TDCSR, BIT0);
3563 }
3564
3565 info->tx_active = 1;
3566 }
3567}
3568
3569static void tx_stop(struct slgt_info *info)
3570{
3571 unsigned short val;
3572
3573 del_timer(&info->tx_timer);
3574
3575 tdma_reset(info);
3576
3577 /* reset and disable transmitter */
3578 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3579 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3580 wr_reg16(info, TCR, val); /* clear reset */
3581
3582 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3583
3584 /* clear tx idle and underrun status bit */
3585 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3586
3587 reset_tbufs(info);
3588
3589 info->tx_enabled = 0;
3590 info->tx_active = 0;
3591}
3592
3593static void reset_port(struct slgt_info *info)
3594{
3595 if (!info->reg_addr)
3596 return;
3597
3598 tx_stop(info);
3599 rx_stop(info);
3600
3601 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3602 set_signals(info);
3603
3604 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3605}
3606
3607static void reset_adapter(struct slgt_info *info)
3608{
3609 int i;
3610 for (i=0; i < info->port_count; ++i) {
3611 if (info->port_array[i])
3612 reset_port(info->port_array[i]);
3613 }
3614}
3615
3616static void async_mode(struct slgt_info *info)
3617{
3618 unsigned short val;
3619
3620 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3621 tx_stop(info);
3622 rx_stop(info);
3623
3624 /* TCR (tx control)
3625 *
3626 * 15..13 mode, 010=async
3627 * 12..10 encoding, 000=NRZ
3628 * 09 parity enable
3629 * 08 1=odd parity, 0=even parity
3630 * 07 1=RTS driver control
3631 * 06 1=break enable
3632 * 05..04 character length
3633 * 00=5 bits
3634 * 01=6 bits
3635 * 10=7 bits
3636 * 11=8 bits
3637 * 03 0=1 stop bit, 1=2 stop bits
3638 * 02 reset
3639 * 01 enable
3640 * 00 auto-CTS enable
3641 */
3642 val = 0x4000;
3643
3644 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3645 val |= BIT7;
3646
3647 if (info->params.parity != ASYNC_PARITY_NONE) {
3648 val |= BIT9;
3649 if (info->params.parity == ASYNC_PARITY_ODD)
3650 val |= BIT8;
3651 }
3652
3653 switch (info->params.data_bits)
3654 {
3655 case 6: val |= BIT4; break;
3656 case 7: val |= BIT5; break;
3657 case 8: val |= BIT5 + BIT4; break;
3658 }
3659
3660 if (info->params.stop_bits != 1)
3661 val |= BIT3;
3662
3663 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3664 val |= BIT0;
3665
3666 wr_reg16(info, TCR, val);
3667
3668 /* RCR (rx control)
3669 *
3670 * 15..13 mode, 010=async
3671 * 12..10 encoding, 000=NRZ
3672 * 09 parity enable
3673 * 08 1=odd parity, 0=even parity
3674 * 07..06 reserved, must be 0
3675 * 05..04 character length
3676 * 00=5 bits
3677 * 01=6 bits
3678 * 10=7 bits
3679 * 11=8 bits
3680 * 03 reserved, must be zero
3681 * 02 reset
3682 * 01 enable
3683 * 00 auto-DCD enable
3684 */
3685 val = 0x4000;
3686
3687 if (info->params.parity != ASYNC_PARITY_NONE) {
3688 val |= BIT9;
3689 if (info->params.parity == ASYNC_PARITY_ODD)
3690 val |= BIT8;
3691 }
3692
3693 switch (info->params.data_bits)
3694 {
3695 case 6: val |= BIT4; break;
3696 case 7: val |= BIT5; break;
3697 case 8: val |= BIT5 + BIT4; break;
3698 }
3699
3700 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3701 val |= BIT0;
3702
3703 wr_reg16(info, RCR, val);
3704
3705 /* CCR (clock control)
3706 *
3707 * 07..05 011 = tx clock source is BRG/16
3708 * 04..02 010 = rx clock source is BRG
3709 * 01 0 = auxclk disabled
3710 * 00 1 = BRG enabled
3711 *
3712 * 0110 1001
3713 */
3714 wr_reg8(info, CCR, 0x69);
3715
3716 msc_set_vcr(info);
3717
3718 tx_set_idle(info);
3719
3720 /* SCR (serial control)
3721 *
3722 * 15 1=tx req on FIFO half empty
3723 * 14 1=rx req on FIFO half full
3724 * 13 tx data IRQ enable
3725 * 12 tx idle IRQ enable
3726 * 11 rx break on IRQ enable
3727 * 10 rx data IRQ enable
3728 * 09 rx break off IRQ enable
3729 * 08 overrun IRQ enable
3730 * 07 DSR IRQ enable
3731 * 06 CTS IRQ enable
3732 * 05 DCD IRQ enable
3733 * 04 RI IRQ enable
3734 * 03 reserved, must be zero
3735 * 02 1=txd->rxd internal loopback enable
3736 * 01 reserved, must be zero
3737 * 00 1=master IRQ enable
3738 */
3739 val = BIT15 + BIT14 + BIT0;
3740 wr_reg16(info, SCR, val);
3741
3742 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3743
3744 set_rate(info, info->params.data_rate * 16);
3745
3746 if (info->params.loopback)
3747 enable_loopback(info);
3748}
3749
3750static void hdlc_mode(struct slgt_info *info)
3751{
3752 unsigned short val;
3753
3754 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3755 tx_stop(info);
3756 rx_stop(info);
3757
3758 /* TCR (tx control)
3759 *
3760 * 15..13 mode, 000=HDLC 001=raw sync
3761 * 12..10 encoding
3762 * 09 CRC enable
3763 * 08 CRC32
3764 * 07 1=RTS driver control
3765 * 06 preamble enable
3766 * 05..04 preamble length
3767 * 03 share open/close flag
3768 * 02 reset
3769 * 01 enable
3770 * 00 auto-CTS enable
3771 */
3772 val = 0;
3773
3774 if (info->params.mode == MGSL_MODE_RAW)
3775 val |= BIT13;
3776 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3777 val |= BIT7;
3778
3779 switch(info->params.encoding)
3780 {
3781 case HDLC_ENCODING_NRZB: val |= BIT10; break;
3782 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
3783 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
3784 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
3785 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
3786 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
3787 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
3788 }
3789
3790 switch (info->params.crc_type)
3791 {
3792 case HDLC_CRC_16_CCITT: val |= BIT9; break;
3793 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
3794 }
3795
3796 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3797 val |= BIT6;
3798
3799 switch (info->params.preamble_length)
3800 {
3801 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
3802 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
3803 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
3804 }
3805
3806 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3807 val |= BIT0;
3808
3809 wr_reg16(info, TCR, val);
3810
3811 /* TPR (transmit preamble) */
3812
3813 switch (info->params.preamble)
3814 {
3815 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3816 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3817 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
3818 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
3819 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
3820 default: val = 0x7e; break;
3821 }
3822 wr_reg8(info, TPR, (unsigned char)val);
3823
3824 /* RCR (rx control)
3825 *
3826 * 15..13 mode, 000=HDLC 001=raw sync
3827 * 12..10 encoding
3828 * 09 CRC enable
3829 * 08 CRC32
3830 * 07..03 reserved, must be 0
3831 * 02 reset
3832 * 01 enable
3833 * 00 auto-DCD enable
3834 */
3835 val = 0;
3836
3837 if (info->params.mode == MGSL_MODE_RAW)
3838 val |= BIT13;
3839
3840 switch(info->params.encoding)
3841 {
3842 case HDLC_ENCODING_NRZB: val |= BIT10; break;
3843 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
3844 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
3845 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
3846 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
3847 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
3848 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
3849 }
3850
3851 switch (info->params.crc_type)
3852 {
3853 case HDLC_CRC_16_CCITT: val |= BIT9; break;
3854 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
3855 }
3856
3857 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3858 val |= BIT0;
3859
3860 wr_reg16(info, RCR, val);
3861
3862 /* CCR (clock control)
3863 *
3864 * 07..05 tx clock source
3865 * 04..02 rx clock source
3866 * 01 auxclk enable
3867 * 00 BRG enable
3868 */
3869 val = 0;
3870
3871 if (info->params.flags & HDLC_FLAG_TXC_BRG)
3872 {
3873 // when RxC source is DPLL, BRG generates 16X DPLL
3874 // reference clock, so take TxC from BRG/16 to get
3875 // transmit clock at actual data rate
3876 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3877 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
3878 else
3879 val |= BIT6; /* 010, txclk = BRG */
3880 }
3881 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
3882 val |= BIT7; /* 100, txclk = DPLL Input */
3883 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
3884 val |= BIT5; /* 001, txclk = RXC Input */
3885
3886 if (info->params.flags & HDLC_FLAG_RXC_BRG)
3887 val |= BIT3; /* 010, rxclk = BRG */
3888 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3889 val |= BIT4; /* 100, rxclk = DPLL */
3890 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
3891 val |= BIT2; /* 001, rxclk = TXC Input */
3892
3893 if (info->params.clock_speed)
3894 val |= BIT1 + BIT0;
3895
3896 wr_reg8(info, CCR, (unsigned char)val);
3897
3898 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
3899 {
3900 // program DPLL mode
3901 switch(info->params.encoding)
3902 {
3903 case HDLC_ENCODING_BIPHASE_MARK:
3904 case HDLC_ENCODING_BIPHASE_SPACE:
3905 val = BIT7; break;
3906 case HDLC_ENCODING_BIPHASE_LEVEL:
3907 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
3908 val = BIT7 + BIT6; break;
3909 default: val = BIT6; // NRZ encodings
3910 }
3911 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
3912
3913 // DPLL requires a 16X reference clock from BRG
3914 set_rate(info, info->params.clock_speed * 16);
3915 }
3916 else
3917 set_rate(info, info->params.clock_speed);
3918
3919 tx_set_idle(info);
3920
3921 msc_set_vcr(info);
3922
3923 /* SCR (serial control)
3924 *
3925 * 15 1=tx req on FIFO half empty
3926 * 14 1=rx req on FIFO half full
3927 * 13 tx data IRQ enable
3928 * 12 tx idle IRQ enable
3929 * 11 underrun IRQ enable
3930 * 10 rx data IRQ enable
3931 * 09 rx idle IRQ enable
3932 * 08 overrun IRQ enable
3933 * 07 DSR IRQ enable
3934 * 06 CTS IRQ enable
3935 * 05 DCD IRQ enable
3936 * 04 RI IRQ enable
3937 * 03 reserved, must be zero
3938 * 02 1=txd->rxd internal loopback enable
3939 * 01 reserved, must be zero
3940 * 00 1=master IRQ enable
3941 */
3942 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
3943
3944 if (info->params.loopback)
3945 enable_loopback(info);
3946}
3947
3948/*
3949 * set transmit idle mode
3950 */
3951static void tx_set_idle(struct slgt_info *info)
3952{
3953 unsigned char val = 0xff;
3954
3955 switch(info->idle_mode)
3956 {
3957 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
3958 case HDLC_TXIDLE_ALT_ZEROS_ONES: val = 0xaa; break;
3959 case HDLC_TXIDLE_ZEROS: val = 0x00; break;
3960 case HDLC_TXIDLE_ONES: val = 0xff; break;
3961 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
3962 case HDLC_TXIDLE_SPACE: val = 0x00; break;
3963 case HDLC_TXIDLE_MARK: val = 0xff; break;
3964 }
3965
3966 wr_reg8(info, TIR, val);
3967}
3968
3969/*
3970 * get state of V24 status (input) signals
3971 */
3972static void get_signals(struct slgt_info *info)
3973{
3974 unsigned short status = rd_reg16(info, SSR);
3975
3976 /* clear all serial signals except DTR and RTS */
3977 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
3978
3979 if (status & BIT3)
3980 info->signals |= SerialSignal_DSR;
3981 if (status & BIT2)
3982 info->signals |= SerialSignal_CTS;
3983 if (status & BIT1)
3984 info->signals |= SerialSignal_DCD;
3985 if (status & BIT0)
3986 info->signals |= SerialSignal_RI;
3987}
3988
3989/*
3990 * set V.24 Control Register based on current configuration
3991 */
3992static void msc_set_vcr(struct slgt_info *info)
3993{
3994 unsigned char val = 0;
3995
3996 /* VCR (V.24 control)
3997 *
3998 * 07..04 serial IF select
3999 * 03 DTR
4000 * 02 RTS
4001 * 01 LL
4002 * 00 RL
4003 */
4004
4005 switch(info->if_mode & MGSL_INTERFACE_MASK)
4006 {
4007 case MGSL_INTERFACE_RS232:
4008 val |= BIT5; /* 0010 */
4009 break;
4010 case MGSL_INTERFACE_V35:
4011 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4012 break;
4013 case MGSL_INTERFACE_RS422:
4014 val |= BIT6; /* 0100 */
4015 break;
4016 }
4017
4018 if (info->signals & SerialSignal_DTR)
4019 val |= BIT3;
4020 if (info->signals & SerialSignal_RTS)
4021 val |= BIT2;
4022 if (info->if_mode & MGSL_INTERFACE_LL)
4023 val |= BIT1;
4024 if (info->if_mode & MGSL_INTERFACE_RL)
4025 val |= BIT0;
4026 wr_reg8(info, VCR, val);
4027}
4028
4029/*
4030 * set state of V24 control (output) signals
4031 */
4032static void set_signals(struct slgt_info *info)
4033{
4034 unsigned char val = rd_reg8(info, VCR);
4035 if (info->signals & SerialSignal_DTR)
4036 val |= BIT3;
4037 else
4038 val &= ~BIT3;
4039 if (info->signals & SerialSignal_RTS)
4040 val |= BIT2;
4041 else
4042 val &= ~BIT2;
4043 wr_reg8(info, VCR, val);
4044}
4045
4046/*
4047 * free range of receive DMA buffers (i to last)
4048 */
4049static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4050{
4051 int done = 0;
4052
4053 while(!done) {
4054 /* reset current buffer for reuse */
4055 info->rbufs[i].status = 0;
4056 if (info->params.mode == MGSL_MODE_RAW)
4057 set_desc_count(info->rbufs[i], info->raw_rx_size);
4058 else
4059 set_desc_count(info->rbufs[i], DMABUFSIZE);
4060
4061 if (i == last)
4062 done = 1;
4063 if (++i == info->rbuf_count)
4064 i = 0;
4065 }
4066 info->rbuf_current = i;
4067}
4068
4069/*
4070 * mark all receive DMA buffers as free
4071 */
4072static void reset_rbufs(struct slgt_info *info)
4073{
4074 free_rbufs(info, 0, info->rbuf_count - 1);
4075}
4076
4077/*
4078 * pass receive HDLC frame to upper layer
4079 *
4080 * return 1 if frame available, otherwise 0
4081 */
4082static int rx_get_frame(struct slgt_info *info)
4083{
4084 unsigned int start, end;
4085 unsigned short status;
4086 unsigned int framesize = 0;
4087 int rc = 0;
4088 unsigned long flags;
4089 struct tty_struct *tty = info->tty;
4090 unsigned char addr_field = 0xff;
4091
4092check_again:
4093
4094 framesize = 0;
4095 addr_field = 0xff;
4096 start = end = info->rbuf_current;
4097
4098 for (;;) {
4099 if (!desc_complete(info->rbufs[end]))
4100 goto cleanup;
4101
4102 if (framesize == 0 && info->params.addr_filter != 0xff)
4103 addr_field = info->rbufs[end].buf[0];
4104
4105 framesize += desc_count(info->rbufs[end]);
4106
4107 if (desc_eof(info->rbufs[end]))
4108 break;
4109
4110 if (++end == info->rbuf_count)
4111 end = 0;
4112
4113 if (end == info->rbuf_current) {
4114 if (info->rx_enabled){
4115 spin_lock_irqsave(&info->lock,flags);
4116 rx_start(info);
4117 spin_unlock_irqrestore(&info->lock,flags);
4118 }
4119 goto cleanup;
4120 }
4121 }
4122
4123 /* status
4124 *
4125 * 15 buffer complete
4126 * 14..06 reserved
4127 * 05..04 residue
4128 * 02 eof (end of frame)
4129 * 01 CRC error
4130 * 00 abort
4131 */
4132 status = desc_status(info->rbufs[end]);
4133
4134 /* ignore CRC bit if not using CRC (bit is undefined) */
4135 if (info->params.crc_type == HDLC_CRC_NONE)
4136 status &= ~BIT1;
4137
4138 if (framesize == 0 ||
4139 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4140 free_rbufs(info, start, end);
4141 goto check_again;
4142 }
4143
4144 if (framesize < 2 || status & (BIT1+BIT0)) {
4145 if (framesize < 2 || (status & BIT0))
4146 info->icount.rxshort++;
4147 else
4148 info->icount.rxcrc++;
4149 framesize = 0;
4150
4151#ifdef CONFIG_HDLC
4152 {
4153 struct net_device_stats *stats = hdlc_stats(info->netdev);
4154 stats->rx_errors++;
4155 stats->rx_frame_errors++;
4156 }
4157#endif
4158 } else {
4159 /* adjust frame size for CRC, if any */
4160 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4161 framesize -= 2;
4162 else if (info->params.crc_type == HDLC_CRC_32_CCITT)
4163 framesize -= 4;
4164 }
4165
4166 DBGBH(("%s rx frame status=%04X size=%d\n",
4167 info->device_name, status, framesize));
4168 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4169
4170 if (framesize) {
4171 if (framesize > info->max_frame_size)
4172 info->icount.rxlong++;
4173 else {
4174 /* copy dma buffer(s) to contiguous temp buffer */
4175 int copy_count = framesize;
4176 int i = start;
4177 unsigned char *p = info->tmp_rbuf;
4178 info->tmp_rbuf_count = framesize;
4179
4180 info->icount.rxok++;
4181
4182 while(copy_count) {
4183 int partial_count = min(copy_count, DMABUFSIZE);
4184 memcpy(p, info->rbufs[i].buf, partial_count);
4185 p += partial_count;
4186 copy_count -= partial_count;
4187 if (++i == info->rbuf_count)
4188 i = 0;
4189 }
4190
4191#ifdef CONFIG_HDLC
4192 if (info->netcount)
4193 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4194 else
4195#endif
4196 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4197 }
4198 }
4199 free_rbufs(info, start, end);
4200 rc = 1;
4201
4202cleanup:
4203 return rc;
4204}
4205
4206/*
4207 * pass receive buffer (RAW synchronous mode) to tty layer
4208 * return 1 if buffer available, otherwise 0
4209 */
4210static int rx_get_buf(struct slgt_info *info)
4211{
4212 unsigned int i = info->rbuf_current;
4213
4214 if (!desc_complete(info->rbufs[i]))
4215 return 0;
4216 DBGDATA(info, info->rbufs[i].buf, desc_count(info->rbufs[i]), "rx");
4217 DBGINFO(("rx_get_buf size=%d\n", desc_count(info->rbufs[i])));
4218 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4219 info->flag_buf, desc_count(info->rbufs[i]));
4220 free_rbufs(info, i, i);
4221 return 1;
4222}
4223
4224static void reset_tbufs(struct slgt_info *info)
4225{
4226 unsigned int i;
4227 info->tbuf_current = 0;
4228 for (i=0 ; i < info->tbuf_count ; i++) {
4229 info->tbufs[i].status = 0;
4230 info->tbufs[i].count = 0;
4231 }
4232}
4233
4234/*
4235 * return number of free transmit DMA buffers
4236 */
4237static unsigned int free_tbuf_count(struct slgt_info *info)
4238{
4239 unsigned int count = 0;
4240 unsigned int i = info->tbuf_current;
4241
4242 do
4243 {
4244 if (desc_count(info->tbufs[i]))
4245 break; /* buffer in use */
4246 ++count;
4247 if (++i == info->tbuf_count)
4248 i=0;
4249 } while (i != info->tbuf_current);
4250
4251 /* last buffer with zero count may be in use, assume it is */
4252 if (count)
4253 --count;
4254
4255 return count;
4256}
4257
4258/*
4259 * load transmit DMA buffer(s) with data
4260 */
4261static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4262{
4263 unsigned short count;
4264 unsigned int i;
4265 struct slgt_desc *d;
4266
4267 if (size == 0)
4268 return;
4269
4270 DBGDATA(info, buf, size, "tx");
4271
4272 info->tbuf_start = i = info->tbuf_current;
4273
4274 while (size) {
4275 d = &info->tbufs[i];
4276 if (++i == info->tbuf_count)
4277 i = 0;
4278
4279 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4280 memcpy(d->buf, buf, count);
4281
4282 size -= count;
4283 buf += count;
4284
4285 if (!size && info->params.mode != MGSL_MODE_RAW)
4286 set_desc_eof(*d, 1); /* HDLC: set EOF of last desc */
4287 else
4288 set_desc_eof(*d, 0);
4289
4290 set_desc_count(*d, count);
4291 }
4292
4293 info->tbuf_current = i;
4294}
4295
4296static int register_test(struct slgt_info *info)
4297{
4298 static unsigned short patterns[] =
4299 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4300 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4301 unsigned int i;
4302 int rc = 0;
4303
4304 for (i=0 ; i < count ; i++) {
4305 wr_reg16(info, TIR, patterns[i]);
4306 wr_reg16(info, BDR, patterns[(i+1)%count]);
4307 if ((rd_reg16(info, TIR) != patterns[i]) ||
4308 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4309 rc = -ENODEV;
4310 break;
4311 }
4312 }
4313
4314 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4315 return rc;
4316}
4317
4318static int irq_test(struct slgt_info *info)
4319{
4320 unsigned long timeout;
4321 unsigned long flags;
4322 struct tty_struct *oldtty = info->tty;
4323 u32 speed = info->params.data_rate;
4324
4325 info->params.data_rate = 921600;
4326 info->tty = NULL;
4327
4328 spin_lock_irqsave(&info->lock, flags);
4329 async_mode(info);
4330 slgt_irq_on(info, IRQ_TXIDLE);
4331
4332 /* enable transmitter */
4333 wr_reg16(info, TCR,
4334 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4335
4336 /* write one byte and wait for tx idle */
4337 wr_reg16(info, TDR, 0);
4338
4339 /* assume failure */
4340 info->init_error = DiagStatus_IrqFailure;
4341 info->irq_occurred = FALSE;
4342
4343 spin_unlock_irqrestore(&info->lock, flags);
4344
4345 timeout=100;
4346 while(timeout-- && !info->irq_occurred)
4347 msleep_interruptible(10);
4348
4349 spin_lock_irqsave(&info->lock,flags);
4350 reset_port(info);
4351 spin_unlock_irqrestore(&info->lock,flags);
4352
4353 info->params.data_rate = speed;
4354 info->tty = oldtty;
4355
4356 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4357 return info->irq_occurred ? 0 : -ENODEV;
4358}
4359
4360static int loopback_test_rx(struct slgt_info *info)
4361{
4362 unsigned char *src, *dest;
4363 int count;
4364
4365 if (desc_complete(info->rbufs[0])) {
4366 count = desc_count(info->rbufs[0]);
4367 src = info->rbufs[0].buf;
4368 dest = info->tmp_rbuf;
4369
4370 for( ; count ; count-=2, src+=2) {
4371 /* src=data byte (src+1)=status byte */
4372 if (!(*(src+1) & (BIT9 + BIT8))) {
4373 *dest = *src;
4374 dest++;
4375 info->tmp_rbuf_count++;
4376 }
4377 }
4378 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4379 return 1;
4380 }
4381 return 0;
4382}
4383
4384static int loopback_test(struct slgt_info *info)
4385{
4386#define TESTFRAMESIZE 20
4387
4388 unsigned long timeout;
4389 u16 count = TESTFRAMESIZE;
4390 unsigned char buf[TESTFRAMESIZE];
4391 int rc = -ENODEV;
4392 unsigned long flags;
4393
4394 struct tty_struct *oldtty = info->tty;
4395 MGSL_PARAMS params;
4396
4397 memcpy(&params, &info->params, sizeof(params));
4398
4399 info->params.mode = MGSL_MODE_ASYNC;
4400 info->params.data_rate = 921600;
4401 info->params.loopback = 1;
4402 info->tty = NULL;
4403
4404 /* build and send transmit frame */
4405 for (count = 0; count < TESTFRAMESIZE; ++count)
4406 buf[count] = (unsigned char)count;
4407
4408 info->tmp_rbuf_count = 0;
4409 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4410
4411 /* program hardware for HDLC and enabled receiver */
4412 spin_lock_irqsave(&info->lock,flags);
4413 async_mode(info);
4414 rx_start(info);
4415 info->tx_count = count;
4416 tx_load(info, buf, count);
4417 tx_start(info);
4418 spin_unlock_irqrestore(&info->lock, flags);
4419
4420 /* wait for receive complete */
4421 for (timeout = 100; timeout; --timeout) {
4422 msleep_interruptible(10);
4423 if (loopback_test_rx(info)) {
4424 rc = 0;
4425 break;
4426 }
4427 }
4428
4429 /* verify received frame length and contents */
4430 if (!rc && (info->tmp_rbuf_count != count ||
4431 memcmp(buf, info->tmp_rbuf, count))) {
4432 rc = -ENODEV;
4433 }
4434
4435 spin_lock_irqsave(&info->lock,flags);
4436 reset_adapter(info);
4437 spin_unlock_irqrestore(&info->lock,flags);
4438
4439 memcpy(&info->params, &params, sizeof(info->params));
4440 info->tty = oldtty;
4441
4442 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4443 return rc;
4444}
4445
4446static int adapter_test(struct slgt_info *info)
4447{
4448 DBGINFO(("testing %s\n", info->device_name));
4449 if ((info->init_error = register_test(info)) < 0) {
4450 printk("register test failure %s addr=%08X\n",
4451 info->device_name, info->phys_reg_addr);
4452 } else if ((info->init_error = irq_test(info)) < 0) {
4453 printk("IRQ test failure %s IRQ=%d\n",
4454 info->device_name, info->irq_level);
4455 } else if ((info->init_error = loopback_test(info)) < 0) {
4456 printk("loopback test failure %s\n", info->device_name);
4457 }
4458 return info->init_error;
4459}
4460
4461/*
4462 * transmit timeout handler
4463 */
4464static void tx_timeout(unsigned long context)
4465{
4466 struct slgt_info *info = (struct slgt_info*)context;
4467 unsigned long flags;
4468
4469 DBGINFO(("%s tx_timeout\n", info->device_name));
4470 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4471 info->icount.txtimeout++;
4472 }
4473 spin_lock_irqsave(&info->lock,flags);
4474 info->tx_active = 0;
4475 info->tx_count = 0;
4476 spin_unlock_irqrestore(&info->lock,flags);
4477
4478#ifdef CONFIG_HDLC
4479 if (info->netcount)
4480 hdlcdev_tx_done(info);
4481 else
4482#endif
4483 bh_transmit(info);
4484}
4485
4486/*
4487 * receive buffer polling timer
4488 */
4489static void rx_timeout(unsigned long context)
4490{
4491 struct slgt_info *info = (struct slgt_info*)context;
4492 unsigned long flags;
4493
4494 DBGINFO(("%s rx_timeout\n", info->device_name));
4495 spin_lock_irqsave(&info->lock, flags);
4496 info->pending_bh |= BH_RECEIVE;
4497 spin_unlock_irqrestore(&info->lock, flags);
4498 bh_handler(info);
4499}
4500
Linux kernel - Deliverables
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