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1 | /* |
2 | * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010 | |
3 | * | |
4 | * Copyright (C) 2005 Kontron Canada | |
5 | * | |
6 | * All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or (at | |
11 | * your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
16 | * NON INFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | * | |
23 | * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current | |
24 | * Maintainer <mark.gross@intel.com> | |
25 | * | |
26 | * Description : This is the TELECOM CLOCK module driver for the ATCA | |
27 | * MPCBL0010 ATCA computer. | |
28 | */ | |
29 | ||
30 | #include <linux/config.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/kernel.h> /* printk() */ | |
35 | #include <linux/fs.h> /* everything... */ | |
36 | #include <linux/errno.h> /* error codes */ | |
37 | #include <linux/delay.h> /* udelay */ | |
38 | #include <linux/slab.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/timer.h> | |
43 | #include <linux/sysfs.h> | |
44 | #include <linux/device.h> | |
45 | #include <linux/miscdevice.h> | |
46 | #include <asm/io.h> /* inb/outb */ | |
47 | #include <asm/uaccess.h> | |
48 | ||
49 | MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>"); | |
50 | MODULE_LICENSE("GPL"); | |
51 | ||
52 | /*Hardware Reset of the PLL */ | |
53 | #define RESET_ON 0x00 | |
54 | #define RESET_OFF 0x01 | |
55 | ||
56 | /* MODE SELECT */ | |
57 | #define NORMAL_MODE 0x00 | |
58 | #define HOLDOVER_MODE 0x10 | |
59 | #define FREERUN_MODE 0x20 | |
60 | ||
61 | /* FILTER SELECT */ | |
62 | #define FILTER_6HZ 0x04 | |
63 | #define FILTER_12HZ 0x00 | |
64 | ||
65 | /* SELECT REFERENCE FREQUENCY */ | |
66 | #define REF_CLK1_8kHz 0x00 | |
67 | #define REF_CLK2_19_44MHz 0x02 | |
68 | ||
69 | /* Select primary or secondary redundant clock */ | |
70 | #define PRIMARY_CLOCK 0x00 | |
71 | #define SECONDARY_CLOCK 0x01 | |
72 | ||
73 | /* CLOCK TRANSMISSION DEFINE */ | |
74 | #define CLK_8kHz 0xff | |
75 | #define CLK_16_384MHz 0xfb | |
76 | ||
77 | #define CLK_1_544MHz 0x00 | |
78 | #define CLK_2_048MHz 0x01 | |
79 | #define CLK_4_096MHz 0x02 | |
80 | #define CLK_6_312MHz 0x03 | |
81 | #define CLK_8_192MHz 0x04 | |
82 | #define CLK_19_440MHz 0x06 | |
83 | ||
84 | #define CLK_8_592MHz 0x08 | |
85 | #define CLK_11_184MHz 0x09 | |
86 | #define CLK_34_368MHz 0x0b | |
87 | #define CLK_44_736MHz 0x0a | |
88 | ||
89 | /* RECEIVED REFERENCE */ | |
90 | #define AMC_B1 0 | |
91 | #define AMC_B2 1 | |
92 | ||
93 | /* HARDWARE SWITCHING DEFINE */ | |
94 | #define HW_ENABLE 0x80 | |
95 | #define HW_DISABLE 0x00 | |
96 | ||
97 | /* HARDWARE SWITCHING MODE DEFINE */ | |
98 | #define PLL_HOLDOVER 0x40 | |
99 | #define LOST_CLOCK 0x00 | |
100 | ||
101 | /* ALARMS DEFINE */ | |
102 | #define UNLOCK_MASK 0x10 | |
103 | #define HOLDOVER_MASK 0x20 | |
104 | #define SEC_LOST_MASK 0x40 | |
105 | #define PRI_LOST_MASK 0x80 | |
106 | ||
107 | /* INTERRUPT CAUSE DEFINE */ | |
108 | ||
109 | #define PRI_LOS_01_MASK 0x01 | |
110 | #define PRI_LOS_10_MASK 0x02 | |
111 | ||
112 | #define SEC_LOS_01_MASK 0x04 | |
113 | #define SEC_LOS_10_MASK 0x08 | |
114 | ||
115 | #define HOLDOVER_01_MASK 0x10 | |
116 | #define HOLDOVER_10_MASK 0x20 | |
117 | ||
118 | #define UNLOCK_01_MASK 0x40 | |
119 | #define UNLOCK_10_MASK 0x80 | |
120 | ||
121 | struct tlclk_alarms { | |
122 | __u32 lost_clocks; | |
123 | __u32 lost_primary_clock; | |
124 | __u32 lost_secondary_clock; | |
125 | __u32 primary_clock_back; | |
126 | __u32 secondary_clock_back; | |
127 | __u32 switchover_primary; | |
128 | __u32 switchover_secondary; | |
129 | __u32 pll_holdover; | |
130 | __u32 pll_end_holdover; | |
131 | __u32 pll_lost_sync; | |
132 | __u32 pll_sync; | |
133 | }; | |
134 | /* Telecom clock I/O register definition */ | |
135 | #define TLCLK_BASE 0xa08 | |
136 | #define TLCLK_REG0 TLCLK_BASE | |
137 | #define TLCLK_REG1 (TLCLK_BASE+1) | |
138 | #define TLCLK_REG2 (TLCLK_BASE+2) | |
139 | #define TLCLK_REG3 (TLCLK_BASE+3) | |
140 | #define TLCLK_REG4 (TLCLK_BASE+4) | |
141 | #define TLCLK_REG5 (TLCLK_BASE+5) | |
142 | #define TLCLK_REG6 (TLCLK_BASE+6) | |
143 | #define TLCLK_REG7 (TLCLK_BASE+7) | |
144 | ||
145 | #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port) | |
146 | ||
147 | /* 0 = Dynamic allocation of the major device number */ | |
148 | #define TLCLK_MAJOR 0 | |
149 | ||
150 | /* sysfs interface definition: | |
151 | Upon loading the driver will create a sysfs directory under | |
152 | /sys/devices/platform/telco_clock. | |
153 | ||
154 | This directory exports the following interfaces. There operation is | |
155 | documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4. | |
156 | alarms : | |
157 | current_ref : | |
158 | enable_clk3a_output : | |
159 | enable_clk3b_output : | |
160 | enable_clka0_output : | |
161 | enable_clka1_output : | |
162 | enable_clkb0_output : | |
163 | enable_clkb1_output : | |
164 | filter_select : | |
165 | hardware_switching : | |
166 | hardware_switching_mode : | |
167 | interrupt_switch : | |
168 | mode_select : | |
169 | refalign : | |
170 | reset : | |
171 | select_amcb1_transmit_clock : | |
172 | select_amcb2_transmit_clock : | |
173 | select_redundant_clock : | |
174 | select_ref_frequency : | |
175 | test_mode : | |
176 | ||
177 | All sysfs interfaces are integers in hex format, i.e echo 99 > refalign | |
178 | has the same effect as echo 0x99 > refalign. | |
179 | */ | |
180 | ||
181 | static unsigned int telclk_interrupt; | |
182 | ||
183 | static int int_events; /* Event that generate a interrupt */ | |
184 | static int got_event; /* if events processing have been done */ | |
185 | ||
186 | static void switchover_timeout(unsigned long data); | |
187 | static struct timer_list switchover_timer = | |
188 | TIMER_INITIALIZER(switchover_timeout , 0, 0); | |
189 | ||
190 | static struct tlclk_alarms *alarm_events; | |
191 | ||
192 | static DEFINE_SPINLOCK(event_lock); | |
193 | ||
194 | static int tlclk_major = TLCLK_MAJOR; | |
195 | ||
196 | static irqreturn_t tlclk_interrupt(int irq, void *dev_id, struct pt_regs *regs); | |
197 | ||
198 | static DECLARE_WAIT_QUEUE_HEAD(wq); | |
199 | ||
200 | static int tlclk_open(struct inode *inode, struct file *filp) | |
201 | { | |
202 | int result; | |
203 | ||
204 | /* Make sure there is no interrupt pending while | |
205 | * initialising interrupt handler */ | |
206 | inb(TLCLK_REG6); | |
207 | ||
208 | /* This device is wired through the FPGA IO space of the ATCA blade | |
209 | * we can't share this IRQ */ | |
210 | result = request_irq(telclk_interrupt, &tlclk_interrupt, | |
211 | SA_INTERRUPT, "telco_clock", tlclk_interrupt); | |
212 | if (result == -EBUSY) { | |
213 | printk(KERN_ERR "telco_clock: Interrupt can't be reserved!\n"); | |
214 | return -EBUSY; | |
215 | } | |
216 | inb(TLCLK_REG6); /* Clear interrupt events */ | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | static int tlclk_release(struct inode *inode, struct file *filp) | |
222 | { | |
223 | free_irq(telclk_interrupt, tlclk_interrupt); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count, | |
229 | loff_t *f_pos) | |
230 | { | |
231 | if (count < sizeof(struct tlclk_alarms)) | |
232 | return -EIO; | |
233 | ||
234 | wait_event_interruptible(wq, got_event); | |
235 | if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms))) | |
236 | return -EFAULT; | |
237 | ||
238 | memset(alarm_events, 0, sizeof(struct tlclk_alarms)); | |
239 | got_event = 0; | |
240 | ||
241 | return sizeof(struct tlclk_alarms); | |
242 | } | |
243 | ||
244 | ssize_t tlclk_write(struct file *filp, const char __user *buf, size_t count, | |
245 | loff_t *f_pos) | |
246 | { | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static struct file_operations tlclk_fops = { | |
251 | .read = tlclk_read, | |
252 | .write = tlclk_write, | |
253 | .open = tlclk_open, | |
254 | .release = tlclk_release, | |
255 | ||
256 | }; | |
257 | ||
258 | static struct miscdevice tlclk_miscdev = { | |
259 | .minor = MISC_DYNAMIC_MINOR, | |
260 | .name = "telco_clock", | |
261 | .fops = &tlclk_fops, | |
262 | }; | |
263 | ||
264 | static ssize_t show_current_ref(struct device *d, | |
265 | struct device_attribute *attr, char *buf) | |
266 | { | |
267 | unsigned long ret_val; | |
268 | unsigned long flags; | |
269 | ||
270 | spin_lock_irqsave(&event_lock, flags); | |
271 | ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3); | |
272 | spin_unlock_irqrestore(&event_lock, flags); | |
273 | ||
274 | return sprintf(buf, "0x%lX\n", ret_val); | |
275 | } | |
276 | ||
277 | static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL); | |
278 | ||
279 | ||
280 | static ssize_t show_interrupt_switch(struct device *d, | |
281 | struct device_attribute *attr, char *buf) | |
282 | { | |
283 | unsigned long ret_val; | |
284 | unsigned long flags; | |
285 | ||
286 | spin_lock_irqsave(&event_lock, flags); | |
287 | ret_val = inb(TLCLK_REG6); | |
288 | spin_unlock_irqrestore(&event_lock, flags); | |
289 | ||
290 | return sprintf(buf, "0x%lX\n", ret_val); | |
291 | } | |
292 | ||
293 | static DEVICE_ATTR(interrupt_switch, S_IRUGO, | |
294 | show_interrupt_switch, NULL); | |
295 | ||
296 | static ssize_t show_alarms(struct device *d, | |
297 | struct device_attribute *attr, char *buf) | |
298 | { | |
299 | unsigned long ret_val; | |
300 | unsigned long flags; | |
301 | ||
302 | spin_lock_irqsave(&event_lock, flags); | |
303 | ret_val = (inb(TLCLK_REG2) & 0xf0); | |
304 | spin_unlock_irqrestore(&event_lock, flags); | |
305 | ||
306 | return sprintf(buf, "0x%lX\n", ret_val); | |
307 | } | |
308 | ||
309 | static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL); | |
310 | ||
311 | static ssize_t store_enable_clk3b_output(struct device *d, | |
312 | struct device_attribute *attr, const char *buf, size_t count) | |
313 | { | |
314 | unsigned long tmp; | |
315 | unsigned char val; | |
316 | unsigned long flags; | |
317 | ||
318 | sscanf(buf, "%lX", &tmp); | |
319 | dev_dbg(d, ": tmp = 0x%lX\n", tmp); | |
320 | ||
321 | val = (unsigned char)tmp; | |
322 | spin_lock_irqsave(&event_lock, flags); | |
323 | SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7); | |
324 | spin_unlock_irqrestore(&event_lock, flags); | |
325 | ||
326 | return strnlen(buf, count); | |
327 | } | |
328 | ||
329 | static DEVICE_ATTR(enable_clk3b_output, S_IWUGO, NULL, | |
330 | store_enable_clk3b_output); | |
331 | ||
332 | static ssize_t store_enable_clk3a_output(struct device *d, | |
333 | struct device_attribute *attr, const char *buf, size_t count) | |
334 | { | |
335 | unsigned long flags; | |
336 | unsigned long tmp; | |
337 | unsigned char val; | |
338 | ||
339 | sscanf(buf, "%lX", &tmp); | |
340 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
341 | ||
342 | val = (unsigned char)tmp; | |
343 | spin_lock_irqsave(&event_lock, flags); | |
344 | SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6); | |
345 | spin_unlock_irqrestore(&event_lock, flags); | |
346 | ||
347 | return strnlen(buf, count); | |
348 | } | |
349 | ||
350 | static DEVICE_ATTR(enable_clk3a_output, S_IWUGO, NULL, | |
351 | store_enable_clk3a_output); | |
352 | ||
353 | static ssize_t store_enable_clkb1_output(struct device *d, | |
354 | struct device_attribute *attr, const char *buf, size_t count) | |
355 | { | |
356 | unsigned long flags; | |
357 | unsigned long tmp; | |
358 | unsigned char val; | |
359 | ||
360 | sscanf(buf, "%lX", &tmp); | |
361 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
362 | ||
363 | val = (unsigned char)tmp; | |
364 | spin_lock_irqsave(&event_lock, flags); | |
365 | SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3); | |
366 | spin_unlock_irqrestore(&event_lock, flags); | |
367 | ||
368 | return strnlen(buf, count); | |
369 | } | |
370 | ||
371 | static DEVICE_ATTR(enable_clkb1_output, S_IWUGO, NULL, | |
372 | store_enable_clkb1_output); | |
373 | ||
374 | ||
375 | static ssize_t store_enable_clka1_output(struct device *d, | |
376 | struct device_attribute *attr, const char *buf, size_t count) | |
377 | { | |
378 | unsigned long flags; | |
379 | unsigned long tmp; | |
380 | unsigned char val; | |
381 | ||
382 | sscanf(buf, "%lX", &tmp); | |
383 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
384 | ||
385 | val = (unsigned char)tmp; | |
386 | spin_lock_irqsave(&event_lock, flags); | |
387 | SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2); | |
388 | spin_unlock_irqrestore(&event_lock, flags); | |
389 | ||
390 | return strnlen(buf, count); | |
391 | } | |
392 | ||
393 | static DEVICE_ATTR(enable_clka1_output, S_IWUGO, NULL, | |
394 | store_enable_clka1_output); | |
395 | ||
396 | static ssize_t store_enable_clkb0_output(struct device *d, | |
397 | struct device_attribute *attr, const char *buf, size_t count) | |
398 | { | |
399 | unsigned long flags; | |
400 | unsigned long tmp; | |
401 | unsigned char val; | |
402 | ||
403 | sscanf(buf, "%lX", &tmp); | |
404 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
405 | ||
406 | val = (unsigned char)tmp; | |
407 | spin_lock_irqsave(&event_lock, flags); | |
408 | SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1); | |
409 | spin_unlock_irqrestore(&event_lock, flags); | |
410 | ||
411 | return strnlen(buf, count); | |
412 | } | |
413 | ||
414 | static DEVICE_ATTR(enable_clkb0_output, S_IWUGO, NULL, | |
415 | store_enable_clkb0_output); | |
416 | ||
417 | static ssize_t store_enable_clka0_output(struct device *d, | |
418 | struct device_attribute *attr, const char *buf, size_t count) | |
419 | { | |
420 | unsigned long flags; | |
421 | unsigned long tmp; | |
422 | unsigned char val; | |
423 | ||
424 | sscanf(buf, "%lX", &tmp); | |
425 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
426 | ||
427 | val = (unsigned char)tmp; | |
428 | spin_lock_irqsave(&event_lock, flags); | |
429 | SET_PORT_BITS(TLCLK_REG2, 0xfe, val); | |
430 | spin_unlock_irqrestore(&event_lock, flags); | |
431 | ||
432 | return strnlen(buf, count); | |
433 | } | |
434 | ||
435 | static DEVICE_ATTR(enable_clka0_output, S_IWUGO, NULL, | |
436 | store_enable_clka0_output); | |
437 | ||
438 | static ssize_t store_test_mode(struct device *d, | |
439 | struct device_attribute *attr, const char *buf, size_t count) | |
440 | { | |
441 | unsigned long flags; | |
442 | unsigned long tmp; | |
443 | unsigned char val; | |
444 | ||
445 | sscanf(buf, "%lX", &tmp); | |
446 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
447 | ||
448 | val = (unsigned char)tmp; | |
449 | spin_lock_irqsave(&event_lock, flags); | |
450 | SET_PORT_BITS(TLCLK_REG4, 0xfd, 2); | |
451 | spin_unlock_irqrestore(&event_lock, flags); | |
452 | ||
453 | return strnlen(buf, count); | |
454 | } | |
455 | ||
456 | static DEVICE_ATTR(test_mode, S_IWUGO, NULL, store_test_mode); | |
457 | ||
458 | static ssize_t store_select_amcb2_transmit_clock(struct device *d, | |
459 | struct device_attribute *attr, const char *buf, size_t count) | |
460 | { | |
461 | unsigned long flags; | |
462 | unsigned long tmp; | |
463 | unsigned char val; | |
464 | ||
465 | sscanf(buf, "%lX", &tmp); | |
466 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
467 | ||
468 | val = (unsigned char)tmp; | |
469 | spin_lock_irqsave(&event_lock, flags); | |
470 | if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) { | |
471 | SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28); | |
472 | SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val); | |
473 | } else if (val >= CLK_8_592MHz) { | |
474 | SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38); | |
475 | switch (val) { | |
476 | case CLK_8_592MHz: | |
477 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 1); | |
478 | break; | |
479 | case CLK_11_184MHz: | |
480 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 0); | |
481 | break; | |
482 | case CLK_34_368MHz: | |
483 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 3); | |
484 | break; | |
485 | case CLK_44_736MHz: | |
486 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 2); | |
487 | break; | |
488 | } | |
489 | } else | |
490 | SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3); | |
491 | ||
492 | spin_unlock_irqrestore(&event_lock, flags); | |
493 | ||
494 | return strnlen(buf, count); | |
495 | } | |
496 | ||
497 | static DEVICE_ATTR(select_amcb2_transmit_clock, S_IWUGO, NULL, | |
498 | store_select_amcb2_transmit_clock); | |
499 | ||
500 | static ssize_t store_select_amcb1_transmit_clock(struct device *d, | |
501 | struct device_attribute *attr, const char *buf, size_t count) | |
502 | { | |
503 | unsigned long tmp; | |
504 | unsigned char val; | |
505 | unsigned long flags; | |
506 | ||
507 | sscanf(buf, "%lX", &tmp); | |
508 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
509 | ||
510 | val = (unsigned char)tmp; | |
511 | spin_lock_irqsave(&event_lock, flags); | |
512 | if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) { | |
513 | SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5); | |
514 | SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val); | |
515 | } else if (val >= CLK_8_592MHz) { | |
516 | SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7); | |
517 | switch (val) { | |
518 | case CLK_8_592MHz: | |
519 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 1); | |
520 | break; | |
521 | case CLK_11_184MHz: | |
522 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 0); | |
523 | break; | |
524 | case CLK_34_368MHz: | |
525 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 3); | |
526 | break; | |
527 | case CLK_44_736MHz: | |
528 | SET_PORT_BITS(TLCLK_REG0, 0xfc, 2); | |
529 | break; | |
530 | } | |
531 | } else | |
532 | SET_PORT_BITS(TLCLK_REG3, 0xf8, val); | |
533 | spin_unlock_irqrestore(&event_lock, flags); | |
534 | ||
535 | return strnlen(buf, count); | |
536 | } | |
537 | ||
538 | static DEVICE_ATTR(select_amcb1_transmit_clock, S_IWUGO, NULL, | |
539 | store_select_amcb1_transmit_clock); | |
540 | ||
541 | static ssize_t store_select_redundant_clock(struct device *d, | |
542 | struct device_attribute *attr, const char *buf, size_t count) | |
543 | { | |
544 | unsigned long tmp; | |
545 | unsigned char val; | |
546 | unsigned long flags; | |
547 | ||
548 | sscanf(buf, "%lX", &tmp); | |
549 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
550 | ||
551 | val = (unsigned char)tmp; | |
552 | spin_lock_irqsave(&event_lock, flags); | |
553 | SET_PORT_BITS(TLCLK_REG1, 0xfe, val); | |
554 | spin_unlock_irqrestore(&event_lock, flags); | |
555 | ||
556 | return strnlen(buf, count); | |
557 | } | |
558 | ||
559 | static DEVICE_ATTR(select_redundant_clock, S_IWUGO, NULL, | |
560 | store_select_redundant_clock); | |
561 | ||
562 | static ssize_t store_select_ref_frequency(struct device *d, | |
563 | struct device_attribute *attr, const char *buf, size_t count) | |
564 | { | |
565 | unsigned long tmp; | |
566 | unsigned char val; | |
567 | unsigned long flags; | |
568 | ||
569 | sscanf(buf, "%lX", &tmp); | |
570 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
571 | ||
572 | val = (unsigned char)tmp; | |
573 | spin_lock_irqsave(&event_lock, flags); | |
574 | SET_PORT_BITS(TLCLK_REG1, 0xfd, val); | |
575 | spin_unlock_irqrestore(&event_lock, flags); | |
576 | ||
577 | return strnlen(buf, count); | |
578 | } | |
579 | ||
580 | static DEVICE_ATTR(select_ref_frequency, S_IWUGO, NULL, | |
581 | store_select_ref_frequency); | |
582 | ||
583 | static ssize_t store_filter_select(struct device *d, | |
584 | struct device_attribute *attr, const char *buf, size_t count) | |
585 | { | |
586 | unsigned long tmp; | |
587 | unsigned char val; | |
588 | unsigned long flags; | |
589 | ||
590 | sscanf(buf, "%lX", &tmp); | |
591 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
592 | ||
593 | val = (unsigned char)tmp; | |
594 | spin_lock_irqsave(&event_lock, flags); | |
595 | SET_PORT_BITS(TLCLK_REG0, 0xfb, val); | |
596 | spin_unlock_irqrestore(&event_lock, flags); | |
597 | ||
598 | return strnlen(buf, count); | |
599 | } | |
600 | ||
601 | static DEVICE_ATTR(filter_select, S_IWUGO, NULL, store_filter_select); | |
602 | ||
603 | static ssize_t store_hardware_switching_mode(struct device *d, | |
604 | struct device_attribute *attr, const char *buf, size_t count) | |
605 | { | |
606 | unsigned long tmp; | |
607 | unsigned char val; | |
608 | unsigned long flags; | |
609 | ||
610 | sscanf(buf, "%lX", &tmp); | |
611 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
612 | ||
613 | val = (unsigned char)tmp; | |
614 | spin_lock_irqsave(&event_lock, flags); | |
615 | SET_PORT_BITS(TLCLK_REG0, 0xbf, val); | |
616 | spin_unlock_irqrestore(&event_lock, flags); | |
617 | ||
618 | return strnlen(buf, count); | |
619 | } | |
620 | ||
621 | static DEVICE_ATTR(hardware_switching_mode, S_IWUGO, NULL, | |
622 | store_hardware_switching_mode); | |
623 | ||
624 | static ssize_t store_hardware_switching(struct device *d, | |
625 | struct device_attribute *attr, const char *buf, size_t count) | |
626 | { | |
627 | unsigned long tmp; | |
628 | unsigned char val; | |
629 | unsigned long flags; | |
630 | ||
631 | sscanf(buf, "%lX", &tmp); | |
632 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
633 | ||
634 | val = (unsigned char)tmp; | |
635 | spin_lock_irqsave(&event_lock, flags); | |
636 | SET_PORT_BITS(TLCLK_REG0, 0x7f, val); | |
637 | spin_unlock_irqrestore(&event_lock, flags); | |
638 | ||
639 | return strnlen(buf, count); | |
640 | } | |
641 | ||
642 | static DEVICE_ATTR(hardware_switching, S_IWUGO, NULL, | |
643 | store_hardware_switching); | |
644 | ||
645 | static ssize_t store_refalign (struct device *d, | |
646 | struct device_attribute *attr, const char *buf, size_t count) | |
647 | { | |
648 | unsigned long tmp; | |
649 | unsigned long flags; | |
650 | ||
651 | sscanf(buf, "%lX", &tmp); | |
652 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
653 | spin_lock_irqsave(&event_lock, flags); | |
654 | SET_PORT_BITS(TLCLK_REG0, 0xf7, 0); | |
655 | udelay(2); | |
656 | SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08); | |
657 | udelay(2); | |
658 | SET_PORT_BITS(TLCLK_REG0, 0xf7, 0); | |
659 | spin_unlock_irqrestore(&event_lock, flags); | |
660 | ||
661 | return strnlen(buf, count); | |
662 | } | |
663 | ||
664 | static DEVICE_ATTR(refalign, S_IWUGO, NULL, store_refalign); | |
665 | ||
666 | static ssize_t store_mode_select (struct device *d, | |
667 | struct device_attribute *attr, const char *buf, size_t count) | |
668 | { | |
669 | unsigned long tmp; | |
670 | unsigned char val; | |
671 | unsigned long flags; | |
672 | ||
673 | sscanf(buf, "%lX", &tmp); | |
674 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
675 | ||
676 | val = (unsigned char)tmp; | |
677 | spin_lock_irqsave(&event_lock, flags); | |
678 | SET_PORT_BITS(TLCLK_REG0, 0xcf, val); | |
679 | spin_unlock_irqrestore(&event_lock, flags); | |
680 | ||
681 | return strnlen(buf, count); | |
682 | } | |
683 | ||
684 | static DEVICE_ATTR(mode_select, S_IWUGO, NULL, store_mode_select); | |
685 | ||
686 | static ssize_t store_reset (struct device *d, | |
687 | struct device_attribute *attr, const char *buf, size_t count) | |
688 | { | |
689 | unsigned long tmp; | |
690 | unsigned char val; | |
691 | unsigned long flags; | |
692 | ||
693 | sscanf(buf, "%lX", &tmp); | |
694 | dev_dbg(d, "tmp = 0x%lX\n", tmp); | |
695 | ||
696 | val = (unsigned char)tmp; | |
697 | spin_lock_irqsave(&event_lock, flags); | |
698 | SET_PORT_BITS(TLCLK_REG4, 0xfd, val); | |
699 | spin_unlock_irqrestore(&event_lock, flags); | |
700 | ||
701 | return strnlen(buf, count); | |
702 | } | |
703 | ||
704 | static DEVICE_ATTR(reset, S_IWUGO, NULL, store_reset); | |
705 | ||
706 | static struct attribute *tlclk_sysfs_entries[] = { | |
707 | &dev_attr_current_ref.attr, | |
708 | &dev_attr_interrupt_switch.attr, | |
709 | &dev_attr_alarms.attr, | |
710 | &dev_attr_enable_clk3a_output.attr, | |
711 | &dev_attr_enable_clk3b_output.attr, | |
712 | &dev_attr_enable_clkb1_output.attr, | |
713 | &dev_attr_enable_clka1_output.attr, | |
714 | &dev_attr_enable_clkb0_output.attr, | |
715 | &dev_attr_enable_clka0_output.attr, | |
716 | &dev_attr_test_mode.attr, | |
717 | &dev_attr_select_amcb1_transmit_clock.attr, | |
718 | &dev_attr_select_amcb2_transmit_clock.attr, | |
719 | &dev_attr_select_redundant_clock.attr, | |
720 | &dev_attr_select_ref_frequency.attr, | |
721 | &dev_attr_filter_select.attr, | |
722 | &dev_attr_hardware_switching_mode.attr, | |
723 | &dev_attr_hardware_switching.attr, | |
724 | &dev_attr_refalign.attr, | |
725 | &dev_attr_mode_select.attr, | |
726 | &dev_attr_reset.attr, | |
727 | NULL | |
728 | }; | |
729 | ||
730 | static struct attribute_group tlclk_attribute_group = { | |
731 | .name = NULL, /* put in device directory */ | |
732 | .attrs = tlclk_sysfs_entries, | |
733 | }; | |
734 | ||
735 | static struct platform_device *tlclk_device; | |
736 | ||
737 | static int __init tlclk_init(void) | |
738 | { | |
739 | int ret; | |
740 | ||
741 | ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops); | |
742 | if (ret < 0) { | |
743 | printk(KERN_ERR "telco_clock: can't get major! %d\n", tlclk_major); | |
744 | return ret; | |
745 | } | |
746 | alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL); | |
747 | if (!alarm_events) | |
748 | goto out1; | |
749 | ||
750 | /* Read telecom clock IRQ number (Set by BIOS) */ | |
751 | if (!request_region(TLCLK_BASE, 8, "telco_clock")) { | |
752 | printk(KERN_ERR "tlclk: request_region failed! 0x%X\n", | |
753 | TLCLK_BASE); | |
754 | ret = -EBUSY; | |
755 | goto out2; | |
756 | } | |
757 | telclk_interrupt = (inb(TLCLK_REG7) & 0x0f); | |
758 | ||
759 | if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */ | |
760 | printk(KERN_ERR "telclk_interrup = 0x%x non-mcpbl0010 hw\n", | |
761 | telclk_interrupt); | |
762 | ret = -ENXIO; | |
763 | goto out3; | |
764 | } | |
765 | ||
766 | init_timer(&switchover_timer); | |
767 | ||
768 | ret = misc_register(&tlclk_miscdev); | |
769 | if (ret < 0) { | |
770 | printk(KERN_ERR " misc_register retruns %d\n", ret); | |
771 | ret = -EBUSY; | |
772 | goto out3; | |
773 | } | |
774 | ||
775 | tlclk_device = platform_device_register_simple("telco_clock", | |
776 | -1, NULL, 0); | |
777 | if (!tlclk_device) { | |
778 | printk(KERN_ERR " platform_device_register retruns 0x%X\n", | |
779 | (unsigned int) tlclk_device); | |
780 | ret = -EBUSY; | |
781 | goto out4; | |
782 | } | |
783 | ||
784 | ret = sysfs_create_group(&tlclk_device->dev.kobj, | |
785 | &tlclk_attribute_group); | |
786 | if (ret) { | |
787 | printk(KERN_ERR "failed to create sysfs device attributes\n"); | |
788 | sysfs_remove_group(&tlclk_device->dev.kobj, | |
789 | &tlclk_attribute_group); | |
790 | goto out5; | |
791 | } | |
792 | ||
793 | return 0; | |
794 | out5: | |
795 | platform_device_unregister(tlclk_device); | |
796 | out4: | |
797 | misc_deregister(&tlclk_miscdev); | |
798 | out3: | |
799 | release_region(TLCLK_BASE, 8); | |
800 | out2: | |
801 | kfree(alarm_events); | |
802 | out1: | |
803 | unregister_chrdev(tlclk_major, "telco_clock"); | |
804 | return ret; | |
805 | } | |
806 | ||
807 | static void __exit tlclk_cleanup(void) | |
808 | { | |
809 | sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group); | |
810 | platform_device_unregister(tlclk_device); | |
811 | misc_deregister(&tlclk_miscdev); | |
812 | unregister_chrdev(tlclk_major, "telco_clock"); | |
813 | ||
814 | release_region(TLCLK_BASE, 8); | |
815 | del_timer_sync(&switchover_timer); | |
816 | kfree(alarm_events); | |
817 | ||
818 | } | |
819 | ||
820 | static void switchover_timeout(unsigned long data) | |
821 | { | |
822 | if ((data & 1)) { | |
823 | if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08)) | |
824 | alarm_events->switchover_primary++; | |
825 | } else { | |
826 | if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08)) | |
827 | alarm_events->switchover_secondary++; | |
828 | } | |
829 | ||
830 | /* Alarm processing is done, wake up read task */ | |
831 | del_timer(&switchover_timer); | |
832 | got_event = 1; | |
833 | wake_up(&wq); | |
834 | } | |
835 | ||
836 | static irqreturn_t tlclk_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
837 | { | |
838 | unsigned long flags; | |
839 | ||
840 | spin_lock_irqsave(&event_lock, flags); | |
841 | /* Read and clear interrupt events */ | |
842 | int_events = inb(TLCLK_REG6); | |
843 | ||
844 | /* Primary_Los changed from 0 to 1 ? */ | |
845 | if (int_events & PRI_LOS_01_MASK) { | |
846 | if (inb(TLCLK_REG2) & SEC_LOST_MASK) | |
847 | alarm_events->lost_clocks++; | |
848 | else | |
849 | alarm_events->lost_primary_clock++; | |
850 | } | |
851 | ||
852 | /* Primary_Los changed from 1 to 0 ? */ | |
853 | if (int_events & PRI_LOS_10_MASK) { | |
854 | alarm_events->primary_clock_back++; | |
855 | SET_PORT_BITS(TLCLK_REG1, 0xFE, 1); | |
856 | } | |
857 | /* Secondary_Los changed from 0 to 1 ? */ | |
858 | if (int_events & SEC_LOS_01_MASK) { | |
859 | if (inb(TLCLK_REG2) & PRI_LOST_MASK) | |
860 | alarm_events->lost_clocks++; | |
861 | else | |
862 | alarm_events->lost_secondary_clock++; | |
863 | } | |
864 | /* Secondary_Los changed from 1 to 0 ? */ | |
865 | if (int_events & SEC_LOS_10_MASK) { | |
866 | alarm_events->secondary_clock_back++; | |
867 | SET_PORT_BITS(TLCLK_REG1, 0xFE, 0); | |
868 | } | |
869 | if (int_events & HOLDOVER_10_MASK) | |
870 | alarm_events->pll_end_holdover++; | |
871 | ||
872 | if (int_events & UNLOCK_01_MASK) | |
873 | alarm_events->pll_lost_sync++; | |
874 | ||
875 | if (int_events & UNLOCK_10_MASK) | |
876 | alarm_events->pll_sync++; | |
877 | ||
878 | /* Holdover changed from 0 to 1 ? */ | |
879 | if (int_events & HOLDOVER_01_MASK) { | |
880 | alarm_events->pll_holdover++; | |
881 | ||
882 | /* TIMEOUT in ~10ms */ | |
883 | switchover_timer.expires = jiffies + msecs_to_jiffies(10); | |
884 | switchover_timer.data = inb(TLCLK_REG1); | |
885 | add_timer(&switchover_timer); | |
886 | } else { | |
887 | got_event = 1; | |
888 | wake_up(&wq); | |
889 | } | |
890 | spin_unlock_irqrestore(&event_lock, flags); | |
891 | ||
892 | return IRQ_HANDLED; | |
893 | } | |
894 | ||
895 | module_init(tlclk_init); | |
896 | module_exit(tlclk_cleanup); |