Merge git://git.infradead.org/intel-iommu
[deliverable/linux.git] / drivers / char / tpm / tpm.h
CommitLineData
1da177e4
LT
1/*
2 * Copyright (C) 2004 IBM Corporation
3 *
4 * Authors:
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Dave Safford <safford@watson.ibm.com>
7 * Reiner Sailer <sailer@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
9 *
8e81cc13 10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
1da177e4
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11 *
12 * Device driver for TCG/TCPA TPM (trusted platform module).
3b09825d 13 * Specifications at www.trustedcomputinggroup.org
1da177e4
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14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation, version 2 of the
18 * License.
3b09825d 19 *
1da177e4
LT
20 */
21#include <linux/module.h>
1da177e4
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22#include <linux/delay.h>
23#include <linux/fs.h>
d081d470 24#include <linux/mutex.h>
914e2637 25#include <linux/sched.h>
bbc5b212 26#include <linux/platform_device.h>
276ad0c1 27#include <linux/io.h>
659aaf2b 28#include <linux/tpm.h>
0dc55365 29#include <linux/acpi.h>
313d21ee 30#include <linux/cdev.h>
1da177e4 31
41ab999c
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32enum tpm_const {
33 TPM_MINOR = 224, /* officially assigned */
34 TPM_BUFSIZE = 4096,
35 TPM_NUM_DEVICES = 256,
32d33b29 36 TPM_RETRY = 50, /* 5 seconds */
41ab999c
KY
37};
38
3122a88a
KH
39enum tpm_timeout {
40 TPM_TIMEOUT = 5, /* msecs */
32d33b29 41 TPM_TIMEOUT_RETRY = 100 /* msecs */
3122a88a 42};
1da177e4
LT
43
44/* TPM addresses */
3122a88a 45enum tpm_addr {
daacdfa6 46 TPM_SUPERIO_ADDR = 0x2E,
3122a88a 47 TPM_ADDR = 0x4E,
3122a88a
KH
48};
49
000a07b0
JG
50/* Indexes the duration array */
51enum tpm_duration {
52 TPM_SHORT = 0,
53 TPM_MEDIUM = 1,
54 TPM_LONG = 2,
55 TPM_UNDEFINED,
56};
57
32d33b29 58#define TPM_WARN_RETRY 0x800
68d6e671 59#define TPM_WARN_DOING_SELFTEST 0x802
be405411
SB
60#define TPM_ERR_DEACTIVATED 0x6
61#define TPM_ERR_DISABLED 0x7
c584af19 62#define TPM_ERR_INVALID_POSTINIT 38
be405411 63
b9e3238a 64#define TPM_HEADER_SIZE 10
7a1d7e6d
JS
65
66enum tpm2_const {
67 TPM2_PLATFORM_PCR = 24,
68 TPM2_PCR_SELECT_MIN = ((TPM2_PLATFORM_PCR + 7) / 8),
69 TPM2_TIMEOUT_A = 750,
70 TPM2_TIMEOUT_B = 2000,
71 TPM2_TIMEOUT_C = 200,
72 TPM2_TIMEOUT_D = 30,
73 TPM2_DURATION_SHORT = 20,
74 TPM2_DURATION_MEDIUM = 750,
75 TPM2_DURATION_LONG = 2000,
76};
77
78enum tpm2_structures {
79 TPM2_ST_NO_SESSIONS = 0x8001,
80 TPM2_ST_SESSIONS = 0x8002,
81};
82
83enum tpm2_return_codes {
84 TPM2_RC_INITIALIZE = 0x0100,
85 TPM2_RC_TESTING = 0x090A,
86 TPM2_RC_DISABLED = 0x0120,
87};
88
89enum tpm2_algorithms {
90 TPM2_ALG_SHA1 = 0x0004,
91};
92
93enum tpm2_command_codes {
94 TPM2_CC_FIRST = 0x011F,
95 TPM2_CC_SELF_TEST = 0x0143,
96 TPM2_CC_STARTUP = 0x0144,
97 TPM2_CC_SHUTDOWN = 0x0145,
98 TPM2_CC_GET_CAPABILITY = 0x017A,
99 TPM2_CC_GET_RANDOM = 0x017B,
100 TPM2_CC_PCR_READ = 0x017E,
101 TPM2_CC_PCR_EXTEND = 0x0182,
102 TPM2_CC_LAST = 0x018F,
103};
104
105enum tpm2_permanent_handles {
106 TPM2_RS_PW = 0x40000009,
107};
108
109enum tpm2_capabilities {
110 TPM2_CAP_TPM_PROPERTIES = 6,
111};
112
113enum tpm2_startup_types {
114 TPM2_SU_CLEAR = 0x0000,
115 TPM2_SU_STATE = 0x0001,
116};
117
1da177e4
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118struct tpm_chip;
119
120struct tpm_vendor_specific {
ad5ea3cc
KJH
121 void __iomem *iobase; /* ioremapped address */
122 unsigned long base; /* TPM base address */
123
27084efe 124 int irq;
a7b66822 125 int probed_irq;
27084efe 126
ad5ea3cc
KJH
127 int region_size;
128 int have_region;
1da177e4 129
27084efe
LD
130 struct list_head list;
131 int locality;
36b20020 132 unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* jiffies */
62592101 133 bool timeout_adjusted;
36b20020 134 unsigned long duration[3]; /* jiffies */
04ab2293 135 bool duration_adjusted;
775585e4 136 void *priv;
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LD
137
138 wait_queue_head_t read_queue;
139 wait_queue_head_t int_queue;
3e3a5e90
SB
140
141 u16 manufacturer_id;
1da177e4
LT
142};
143
3b09825d 144#define TPM_VPRIV(c) ((c)->vendor.priv)
775585e4 145
4e401fb0 146#define TPM_VID_INTEL 0x8086
1f866057
SB
147#define TPM_VID_WINBOND 0x1050
148#define TPM_VID_STM 0x104A
4e401fb0 149
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150#define TPM_PPI_VERSION_LEN 3
151
afb5abc2
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152enum tpm_chip_flags {
153 TPM_CHIP_FLAG_REGISTERED = BIT(0),
0dc55365 154 TPM_CHIP_FLAG_PPI = BIT(1),
7a1d7e6d 155 TPM_CHIP_FLAG_TPM2 = BIT(2),
afb5abc2
JS
156};
157
1da177e4 158struct tpm_chip {
71ed848f 159 struct device *pdev; /* Device stuff */
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JS
160 struct device dev;
161 struct cdev cdev;
162
5f82e9f0 163 const struct tpm_class_ops *ops;
afb5abc2 164 unsigned int flags;
1da177e4
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165
166 int dev_num; /* /dev/tpm# */
6aff1fdc 167 char devname[7];
dc36d32c 168 unsigned long is_open; /* only one allowed */
1da177e4
LT
169 int time_expired;
170
d081d470 171 struct mutex tpm_mutex; /* tpm is processing */
1da177e4 172
90dda520 173 struct tpm_vendor_specific vendor;
1da177e4 174
55a82ab3
KJH
175 struct dentry **bios_dir;
176
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177#ifdef CONFIG_ACPI
178 acpi_handle acpi_dev_handle;
179 char ppi_version[TPM_PPI_VERSION_LEN + 1];
180#endif /* CONFIG_ACPI */
181
1da177e4
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182 struct list_head list;
183};
184
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LD
185#define to_tpm_chip(n) container_of(n, struct tpm_chip, vendor)
186
a0e39349
MZ
187static inline void tpm_chip_put(struct tpm_chip *chip)
188{
71ed848f 189 module_put(chip->pdev->driver->owner);
a0e39349
MZ
190}
191
daacdfa6 192static inline int tpm_read_index(int base, int index)
1da177e4 193{
daacdfa6
KJH
194 outb(index, base);
195 return inb(base+1) & 0xFF;
1da177e4
LT
196}
197
daacdfa6 198static inline void tpm_write_index(int base, int index, int value)
1da177e4 199{
daacdfa6
KJH
200 outb(index, base);
201 outb(value & 0xFF, base+1);
1da177e4 202}
08837438
RA
203struct tpm_input_header {
204 __be16 tag;
205 __be32 length;
206 __be32 ordinal;
348df8db 207} __packed;
08837438
RA
208
209struct tpm_output_header {
210 __be16 tag;
211 __be32 length;
212 __be32 return_code;
348df8db 213} __packed;
08837438 214
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215#define TPM_TAG_RQU_COMMAND cpu_to_be16(193)
216
08837438
RA
217struct stclear_flags_t {
218 __be16 tag;
219 u8 deactivated;
220 u8 disableForceClear;
221 u8 physicalPresence;
222 u8 physicalPresenceLock;
223 u8 bGlobalLock;
348df8db 224} __packed;
08837438
RA
225
226struct tpm_version_t {
227 u8 Major;
228 u8 Minor;
229 u8 revMajor;
230 u8 revMinor;
348df8db 231} __packed;
08837438
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232
233struct tpm_version_1_2_t {
234 __be16 tag;
235 u8 Major;
236 u8 Minor;
237 u8 revMajor;
238 u8 revMinor;
348df8db 239} __packed;
08837438
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240
241struct timeout_t {
242 __be32 a;
243 __be32 b;
244 __be32 c;
245 __be32 d;
348df8db 246} __packed;
08837438
RA
247
248struct duration_t {
249 __be32 tpm_short;
250 __be32 tpm_medium;
251 __be32 tpm_long;
348df8db 252} __packed;
08837438
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253
254struct permanent_flags_t {
255 __be16 tag;
256 u8 disable;
257 u8 ownership;
258 u8 deactivated;
259 u8 readPubek;
260 u8 disableOwnerClear;
261 u8 allowMaintenance;
262 u8 physicalPresenceLifetimeLock;
263 u8 physicalPresenceHWEnable;
264 u8 physicalPresenceCMDEnable;
265 u8 CEKPUsed;
266 u8 TPMpost;
267 u8 TPMpostLock;
268 u8 FIPS;
269 u8 operator;
270 u8 enableRevokeEK;
271 u8 nvLocked;
272 u8 readSRKPub;
273 u8 tpmEstablished;
274 u8 maintenanceDone;
275 u8 disableFullDALogicInfo;
348df8db 276} __packed;
08837438
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277
278typedef union {
279 struct permanent_flags_t perm_flags;
280 struct stclear_flags_t stclear_flags;
281 bool owned;
282 __be32 num_pcrs;
283 struct tpm_version_t tpm_version;
284 struct tpm_version_1_2_t tpm_version_1_2;
285 __be32 manufacturer_id;
286 struct timeout_t timeout;
287 struct duration_t duration;
288} cap_t;
289
000a07b0
JG
290enum tpm_capabilities {
291 TPM_CAP_FLAG = cpu_to_be32(4),
292 TPM_CAP_PROP = cpu_to_be32(5),
293 CAP_VERSION_1_1 = cpu_to_be32(0x06),
294 CAP_VERSION_1_2 = cpu_to_be32(0x1A)
295};
296
297enum tpm_sub_capabilities {
298 TPM_CAP_PROP_PCR = cpu_to_be32(0x101),
299 TPM_CAP_PROP_MANUFACTURER = cpu_to_be32(0x103),
300 TPM_CAP_FLAG_PERM = cpu_to_be32(0x108),
301 TPM_CAP_FLAG_VOL = cpu_to_be32(0x109),
302 TPM_CAP_PROP_OWNER = cpu_to_be32(0x111),
303 TPM_CAP_PROP_TIS_TIMEOUT = cpu_to_be32(0x115),
304 TPM_CAP_PROP_TIS_DURATION = cpu_to_be32(0x120),
305
306};
307
08837438
RA
308struct tpm_getcap_params_in {
309 __be32 cap;
310 __be32 subcap_size;
311 __be32 subcap;
348df8db 312} __packed;
08837438
RA
313
314struct tpm_getcap_params_out {
315 __be32 cap_size;
316 cap_t cap;
348df8db 317} __packed;
08837438
RA
318
319struct tpm_readpubek_params_out {
320 u8 algorithm[4];
321 u8 encscheme[2];
322 u8 sigscheme[2];
02a077c5 323 __be32 paramsize;
08837438
RA
324 u8 parameters[12]; /*assuming RSA*/
325 __be32 keysize;
326 u8 modulus[256];
327 u8 checksum[20];
348df8db 328} __packed;
08837438
RA
329
330typedef union {
331 struct tpm_input_header in;
332 struct tpm_output_header out;
333} tpm_cmd_header;
334
659aaf2b
RA
335struct tpm_pcrread_out {
336 u8 pcr_result[TPM_DIGEST_SIZE];
348df8db 337} __packed;
659aaf2b
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338
339struct tpm_pcrread_in {
340 __be32 pcr_idx;
348df8db 341} __packed;
659aaf2b
RA
342
343struct tpm_pcrextend_in {
344 __be32 pcr_idx;
345 u8 hash[TPM_DIGEST_SIZE];
348df8db 346} __packed;
659aaf2b 347
41ab999c
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348/* 128 bytes is an arbitrary cap. This could be as large as TPM_BUFSIZE - 18
349 * bytes, but 128 is still a relatively large number of random bytes and
350 * anything much bigger causes users of struct tpm_cmd_t to start getting
351 * compiler warnings about stack frame size. */
352#define TPM_MAX_RNG_DATA 128
353
354struct tpm_getrandom_out {
355 __be32 rng_data_len;
356 u8 rng_data[TPM_MAX_RNG_DATA];
348df8db 357} __packed;
41ab999c
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358
359struct tpm_getrandom_in {
360 __be32 num_bytes;
348df8db 361} __packed;
41ab999c 362
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363struct tpm_startup_in {
364 __be16 startup_type;
365} __packed;
366
08837438
RA
367typedef union {
368 struct tpm_getcap_params_out getcap_out;
369 struct tpm_readpubek_params_out readpubek_out;
370 u8 readpubek_out_buffer[sizeof(struct tpm_readpubek_params_out)];
371 struct tpm_getcap_params_in getcap_in;
659aaf2b
RA
372 struct tpm_pcrread_in pcrread_in;
373 struct tpm_pcrread_out pcrread_out;
374 struct tpm_pcrextend_in pcrextend_in;
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375 struct tpm_getrandom_in getrandom_in;
376 struct tpm_getrandom_out getrandom_out;
c584af19 377 struct tpm_startup_in startup_in;
08837438
RA
378} tpm_cmd_params;
379
380struct tpm_cmd_t {
381 tpm_cmd_header header;
382 tpm_cmd_params params;
348df8db 383} __packed;
08837438 384
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JS
385extern struct class *tpm_class;
386extern dev_t tpm_devt;
387extern const struct file_operations tpm_fops;
388
08837438 389ssize_t tpm_getcap(struct device *, __be32, cap_t *, const char *);
afdba32e
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390ssize_t tpm_transmit(struct tpm_chip *chip, const char *buf,
391 size_t bufsiz);
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392ssize_t tpm_transmit_cmd(struct tpm_chip *chip, void *cmd, int len,
393 const char *desc);
2b30a90f 394extern int tpm_get_timeouts(struct tpm_chip *);
08e96e48 395extern void tpm_gen_interrupt(struct tpm_chip *);
68d6e671 396extern int tpm_do_selftest(struct tpm_chip *);
9e18ee19 397extern unsigned long tpm_calc_ordinal_duration(struct tpm_chip *, u32);
035e2ce8 398extern int tpm_pm_suspend(struct device *);
ce2c87d4 399extern int tpm_pm_resume(struct device *);
fd048866 400extern int wait_for_tpm_stat(struct tpm_chip *, u8, unsigned long,
78f09cc2 401 wait_queue_head_t *, bool);
f84fdff0 402
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403struct tpm_chip *tpm_chip_find_get(int chip_num);
404extern struct tpm_chip *tpmm_chip_alloc(struct device *dev,
405 const struct tpm_class_ops *ops);
406extern int tpm_chip_register(struct tpm_chip *chip);
407extern void tpm_chip_unregister(struct tpm_chip *chip);
408
1e3b73a9
JG
409int tpm_sysfs_add_device(struct tpm_chip *chip);
410void tpm_sysfs_del_device(struct tpm_chip *chip);
afdba32e 411
000a07b0
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412int tpm_pcr_read_dev(struct tpm_chip *chip, int pcr_idx, u8 *res_buf);
413
f84fdff0 414#ifdef CONFIG_ACPI
0dc55365
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415extern int tpm_add_ppi(struct tpm_chip *chip);
416extern void tpm_remove_ppi(struct tpm_chip *chip);
f84fdff0 417#else
0dc55365 418static inline int tpm_add_ppi(struct tpm_chip *chip)
f84fdff0
XZ
419{
420 return 0;
421}
1631cfb7 422
0dc55365 423static inline void tpm_remove_ppi(struct tpm_chip *chip)
1631cfb7
GW
424{
425}
f84fdff0 426#endif
7a1d7e6d
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427
428int tpm2_pcr_read(struct tpm_chip *chip, int pcr_idx, u8 *res_buf);
429int tpm2_pcr_extend(struct tpm_chip *chip, int pcr_idx, const u8 *hash);
430int tpm2_get_random(struct tpm_chip *chip, u8 *out, size_t max);
431ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id,
432 u32 *value, const char *desc);
433
434extern int tpm2_startup(struct tpm_chip *chip, u16 startup_type);
74d6b3ce 435extern void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type);
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436extern unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *, u32);
437extern int tpm2_do_selftest(struct tpm_chip *chip);
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438extern int tpm2_gen_interrupt(struct tpm_chip *chip);
439extern int tpm2_probe(struct tpm_chip *chip);
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