Commit | Line | Data |
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27084efe LD |
1 | /* |
2 | * Copyright (C) 2005, 2006 IBM Corporation | |
3 | * | |
4 | * Authors: | |
5 | * Leendert van Doorn <leendert@watson.ibm.com> | |
6 | * Kylene Hall <kjhall@us.ibm.com> | |
7 | * | |
8e81cc13 KY |
8 | * Maintained by: <tpmdd-devel@lists.sourceforge.net> |
9 | * | |
27084efe LD |
10 | * Device driver for TCG/TCPA TPM (trusted platform module). |
11 | * Specifications at www.trustedcomputinggroup.org | |
12 | * | |
13 | * This device driver implements the TPM interface as defined in | |
14 | * the TCG TPM Interface Spec version 1.2, revision 1.0. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation, version 2 of the | |
19 | * License. | |
20 | */ | |
57135568 KJH |
21 | #include <linux/init.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
27084efe | 24 | #include <linux/pnp.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
27084efe LD |
26 | #include <linux/interrupt.h> |
27 | #include <linux/wait.h> | |
3f0d3d01 | 28 | #include <linux/acpi.h> |
27084efe LD |
29 | #include "tpm.h" |
30 | ||
31 | #define TPM_HEADER_SIZE 10 | |
32 | ||
33 | enum tis_access { | |
34 | TPM_ACCESS_VALID = 0x80, | |
35 | TPM_ACCESS_ACTIVE_LOCALITY = 0x20, | |
36 | TPM_ACCESS_REQUEST_PENDING = 0x04, | |
37 | TPM_ACCESS_REQUEST_USE = 0x02, | |
38 | }; | |
39 | ||
40 | enum tis_status { | |
41 | TPM_STS_VALID = 0x80, | |
42 | TPM_STS_COMMAND_READY = 0x40, | |
43 | TPM_STS_GO = 0x20, | |
44 | TPM_STS_DATA_AVAIL = 0x10, | |
45 | TPM_STS_DATA_EXPECT = 0x08, | |
46 | }; | |
47 | ||
48 | enum tis_int_flags { | |
49 | TPM_GLOBAL_INT_ENABLE = 0x80000000, | |
50 | TPM_INTF_BURST_COUNT_STATIC = 0x100, | |
51 | TPM_INTF_CMD_READY_INT = 0x080, | |
52 | TPM_INTF_INT_EDGE_FALLING = 0x040, | |
53 | TPM_INTF_INT_EDGE_RISING = 0x020, | |
54 | TPM_INTF_INT_LEVEL_LOW = 0x010, | |
55 | TPM_INTF_INT_LEVEL_HIGH = 0x008, | |
56 | TPM_INTF_LOCALITY_CHANGE_INT = 0x004, | |
57 | TPM_INTF_STS_VALID_INT = 0x002, | |
58 | TPM_INTF_DATA_AVAIL_INT = 0x001, | |
59 | }; | |
60 | ||
36b20020 | 61 | enum tis_defaults { |
2a7362f5 | 62 | TIS_MEM_BASE = 0xFED40000, |
b09d5300 | 63 | TIS_MEM_LEN = 0x5000, |
cb535425 KJH |
64 | TIS_SHORT_TIMEOUT = 750, /* ms */ |
65 | TIS_LONG_TIMEOUT = 2000, /* 2 sec */ | |
36b20020 KJH |
66 | }; |
67 | ||
27084efe LD |
68 | #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) |
69 | #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) | |
70 | #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) | |
71 | #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) | |
72 | #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) | |
73 | #define TPM_STS(l) (0x0018 | ((l) << 12)) | |
74 | #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) | |
75 | ||
76 | #define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) | |
77 | #define TPM_RID(l) (0x0F04 | ((l) << 12)) | |
78 | ||
79 | static LIST_HEAD(tis_chips); | |
80 | static DEFINE_SPINLOCK(tis_lock); | |
81 | ||
3f0d3d01 MG |
82 | #ifdef CONFIG_ACPI |
83 | static int is_itpm(struct pnp_dev *dev) | |
84 | { | |
85 | struct acpi_device *acpi = pnp_acpi_device(dev); | |
86 | struct acpi_hardware_id *id; | |
87 | ||
88 | list_for_each_entry(id, &acpi->pnp.ids, list) { | |
89 | if (!strcmp("INTC0102", id->id)) | |
90 | return 1; | |
91 | } | |
92 | ||
93 | return 0; | |
94 | } | |
95 | #else | |
96 | static int is_itpm(struct pnp_dev *dev) | |
97 | { | |
98 | return 0; | |
99 | } | |
100 | #endif | |
101 | ||
27084efe LD |
102 | static int check_locality(struct tpm_chip *chip, int l) |
103 | { | |
104 | if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
105 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == | |
106 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) | |
107 | return chip->vendor.locality = l; | |
108 | ||
109 | return -1; | |
110 | } | |
111 | ||
112 | static void release_locality(struct tpm_chip *chip, int l, int force) | |
113 | { | |
114 | if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
115 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) == | |
116 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) | |
117 | iowrite8(TPM_ACCESS_ACTIVE_LOCALITY, | |
118 | chip->vendor.iobase + TPM_ACCESS(l)); | |
119 | } | |
120 | ||
121 | static int request_locality(struct tpm_chip *chip, int l) | |
122 | { | |
123 | unsigned long stop; | |
124 | long rc; | |
125 | ||
126 | if (check_locality(chip, l) >= 0) | |
127 | return l; | |
128 | ||
129 | iowrite8(TPM_ACCESS_REQUEST_USE, | |
130 | chip->vendor.iobase + TPM_ACCESS(l)); | |
131 | ||
132 | if (chip->vendor.irq) { | |
36b20020 | 133 | rc = wait_event_interruptible_timeout(chip->vendor.int_queue, |
27084efe LD |
134 | (check_locality |
135 | (chip, l) >= 0), | |
36b20020 | 136 | chip->vendor.timeout_a); |
27084efe LD |
137 | if (rc > 0) |
138 | return l; | |
139 | ||
140 | } else { | |
141 | /* wait for burstcount */ | |
36b20020 | 142 | stop = jiffies + chip->vendor.timeout_a; |
27084efe LD |
143 | do { |
144 | if (check_locality(chip, l) >= 0) | |
145 | return l; | |
146 | msleep(TPM_TIMEOUT); | |
147 | } | |
148 | while (time_before(jiffies, stop)); | |
149 | } | |
150 | return -1; | |
151 | } | |
152 | ||
153 | static u8 tpm_tis_status(struct tpm_chip *chip) | |
154 | { | |
155 | return ioread8(chip->vendor.iobase + | |
156 | TPM_STS(chip->vendor.locality)); | |
157 | } | |
158 | ||
159 | static void tpm_tis_ready(struct tpm_chip *chip) | |
160 | { | |
161 | /* this causes the current command to be aborted */ | |
162 | iowrite8(TPM_STS_COMMAND_READY, | |
163 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
164 | } | |
165 | ||
166 | static int get_burstcount(struct tpm_chip *chip) | |
167 | { | |
168 | unsigned long stop; | |
169 | int burstcnt; | |
170 | ||
171 | /* wait for burstcount */ | |
172 | /* which timeout value, spec has 2 answers (c & d) */ | |
36b20020 | 173 | stop = jiffies + chip->vendor.timeout_d; |
27084efe LD |
174 | do { |
175 | burstcnt = ioread8(chip->vendor.iobase + | |
176 | TPM_STS(chip->vendor.locality) + 1); | |
177 | burstcnt += ioread8(chip->vendor.iobase + | |
178 | TPM_STS(chip->vendor.locality) + | |
179 | 2) << 8; | |
180 | if (burstcnt) | |
181 | return burstcnt; | |
182 | msleep(TPM_TIMEOUT); | |
183 | } while (time_before(jiffies, stop)); | |
184 | return -EBUSY; | |
185 | } | |
186 | ||
36b20020 | 187 | static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout, |
27084efe LD |
188 | wait_queue_head_t *queue) |
189 | { | |
190 | unsigned long stop; | |
191 | long rc; | |
192 | u8 status; | |
193 | ||
194 | /* check current status */ | |
195 | status = tpm_tis_status(chip); | |
196 | if ((status & mask) == mask) | |
197 | return 0; | |
198 | ||
199 | if (chip->vendor.irq) { | |
200 | rc = wait_event_interruptible_timeout(*queue, | |
201 | ((tpm_tis_status | |
202 | (chip) & mask) == | |
36b20020 | 203 | mask), timeout); |
27084efe LD |
204 | if (rc > 0) |
205 | return 0; | |
206 | } else { | |
36b20020 | 207 | stop = jiffies + timeout; |
27084efe LD |
208 | do { |
209 | msleep(TPM_TIMEOUT); | |
210 | status = tpm_tis_status(chip); | |
211 | if ((status & mask) == mask) | |
212 | return 0; | |
213 | } while (time_before(jiffies, stop)); | |
214 | } | |
215 | return -ETIME; | |
216 | } | |
217 | ||
cb535425 | 218 | static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe LD |
219 | { |
220 | int size = 0, burstcnt; | |
221 | while (size < count && | |
222 | wait_for_stat(chip, | |
223 | TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
224 | chip->vendor.timeout_c, | |
225 | &chip->vendor.read_queue) | |
226 | == 0) { | |
227 | burstcnt = get_burstcount(chip); | |
228 | for (; burstcnt > 0 && size < count; burstcnt--) | |
229 | buf[size++] = ioread8(chip->vendor.iobase + | |
230 | TPM_DATA_FIFO(chip->vendor. | |
231 | locality)); | |
232 | } | |
233 | return size; | |
234 | } | |
235 | ||
cb535425 | 236 | static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe LD |
237 | { |
238 | int size = 0; | |
239 | int expected, status; | |
240 | ||
241 | if (count < TPM_HEADER_SIZE) { | |
242 | size = -EIO; | |
243 | goto out; | |
244 | } | |
245 | ||
246 | /* read first 10 bytes, including tag, paramsize, and result */ | |
247 | if ((size = | |
248 | recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) { | |
249 | dev_err(chip->dev, "Unable to read header\n"); | |
250 | goto out; | |
251 | } | |
252 | ||
253 | expected = be32_to_cpu(*(__be32 *) (buf + 2)); | |
254 | if (expected > count) { | |
255 | size = -EIO; | |
256 | goto out; | |
257 | } | |
258 | ||
259 | if ((size += | |
260 | recv_data(chip, &buf[TPM_HEADER_SIZE], | |
261 | expected - TPM_HEADER_SIZE)) < expected) { | |
262 | dev_err(chip->dev, "Unable to read remainder of result\n"); | |
263 | size = -ETIME; | |
264 | goto out; | |
265 | } | |
266 | ||
267 | wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, | |
268 | &chip->vendor.int_queue); | |
269 | status = tpm_tis_status(chip); | |
270 | if (status & TPM_STS_DATA_AVAIL) { /* retry? */ | |
271 | dev_err(chip->dev, "Error left over data\n"); | |
272 | size = -EIO; | |
273 | goto out; | |
274 | } | |
275 | ||
276 | out: | |
277 | tpm_tis_ready(chip); | |
278 | release_locality(chip, chip->vendor.locality, 0); | |
279 | return size; | |
280 | } | |
281 | ||
3507d612 RA |
282 | static int itpm; |
283 | module_param(itpm, bool, 0444); | |
284 | MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)"); | |
285 | ||
27084efe LD |
286 | /* |
287 | * If interrupts are used (signaled by an irq set in the vendor structure) | |
288 | * tpm.c can skip polling for the data to be available as the interrupt is | |
289 | * waited for here | |
290 | */ | |
cb535425 | 291 | static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len) |
27084efe LD |
292 | { |
293 | int rc, status, burstcnt; | |
294 | size_t count = 0; | |
295 | u32 ordinal; | |
296 | ||
297 | if (request_locality(chip, 0) < 0) | |
298 | return -EBUSY; | |
299 | ||
300 | status = tpm_tis_status(chip); | |
301 | if ((status & TPM_STS_COMMAND_READY) == 0) { | |
302 | tpm_tis_ready(chip); | |
303 | if (wait_for_stat | |
304 | (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b, | |
305 | &chip->vendor.int_queue) < 0) { | |
306 | rc = -ETIME; | |
307 | goto out_err; | |
308 | } | |
309 | } | |
310 | ||
311 | while (count < len - 1) { | |
312 | burstcnt = get_burstcount(chip); | |
313 | for (; burstcnt > 0 && count < len - 1; burstcnt--) { | |
314 | iowrite8(buf[count], chip->vendor.iobase + | |
315 | TPM_DATA_FIFO(chip->vendor.locality)); | |
316 | count++; | |
317 | } | |
318 | ||
319 | wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, | |
320 | &chip->vendor.int_queue); | |
321 | status = tpm_tis_status(chip); | |
3507d612 | 322 | if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) { |
27084efe LD |
323 | rc = -EIO; |
324 | goto out_err; | |
325 | } | |
326 | } | |
327 | ||
328 | /* write last byte */ | |
329 | iowrite8(buf[count], | |
330 | chip->vendor.iobase + | |
331 | TPM_DATA_FIFO(chip->vendor.locality)); | |
332 | wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, | |
333 | &chip->vendor.int_queue); | |
334 | status = tpm_tis_status(chip); | |
335 | if ((status & TPM_STS_DATA_EXPECT) != 0) { | |
336 | rc = -EIO; | |
337 | goto out_err; | |
338 | } | |
339 | ||
340 | /* go and do it */ | |
341 | iowrite8(TPM_STS_GO, | |
342 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
343 | ||
344 | if (chip->vendor.irq) { | |
345 | ordinal = be32_to_cpu(*((__be32 *) (buf + 6))); | |
346 | if (wait_for_stat | |
347 | (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
348 | tpm_calc_ordinal_duration(chip, ordinal), | |
349 | &chip->vendor.read_queue) < 0) { | |
350 | rc = -ETIME; | |
351 | goto out_err; | |
352 | } | |
353 | } | |
354 | return len; | |
355 | out_err: | |
356 | tpm_tis_ready(chip); | |
357 | release_locality(chip, chip->vendor.locality, 0); | |
358 | return rc; | |
359 | } | |
360 | ||
62322d25 | 361 | static const struct file_operations tis_ops = { |
27084efe LD |
362 | .owner = THIS_MODULE, |
363 | .llseek = no_llseek, | |
364 | .open = tpm_open, | |
365 | .read = tpm_read, | |
366 | .write = tpm_write, | |
367 | .release = tpm_release, | |
368 | }; | |
369 | ||
370 | static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL); | |
371 | static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL); | |
372 | static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL); | |
373 | static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL); | |
374 | static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL); | |
375 | static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated, | |
376 | NULL); | |
377 | static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL); | |
378 | static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel); | |
9b29050f | 379 | static DEVICE_ATTR(timeouts, S_IRUGO, tpm_show_timeouts, NULL); |
27084efe LD |
380 | |
381 | static struct attribute *tis_attrs[] = { | |
382 | &dev_attr_pubek.attr, | |
383 | &dev_attr_pcrs.attr, | |
384 | &dev_attr_enabled.attr, | |
385 | &dev_attr_active.attr, | |
386 | &dev_attr_owned.attr, | |
387 | &dev_attr_temp_deactivated.attr, | |
388 | &dev_attr_caps.attr, | |
9b29050f SB |
389 | &dev_attr_cancel.attr, |
390 | &dev_attr_timeouts.attr, NULL, | |
27084efe LD |
391 | }; |
392 | ||
393 | static struct attribute_group tis_attr_grp = { | |
394 | .attrs = tis_attrs | |
395 | }; | |
396 | ||
397 | static struct tpm_vendor_specific tpm_tis = { | |
398 | .status = tpm_tis_status, | |
399 | .recv = tpm_tis_recv, | |
400 | .send = tpm_tis_send, | |
401 | .cancel = tpm_tis_ready, | |
402 | .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
403 | .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
404 | .req_canceled = TPM_STS_COMMAND_READY, | |
405 | .attr_group = &tis_attr_grp, | |
406 | .miscdev = { | |
407 | .fops = &tis_ops,}, | |
408 | }; | |
409 | ||
7d12e780 | 410 | static irqreturn_t tis_int_probe(int irq, void *dev_id) |
27084efe | 411 | { |
06efcad0 | 412 | struct tpm_chip *chip = dev_id; |
27084efe LD |
413 | u32 interrupt; |
414 | ||
415 | interrupt = ioread32(chip->vendor.iobase + | |
416 | TPM_INT_STATUS(chip->vendor.locality)); | |
417 | ||
418 | if (interrupt == 0) | |
419 | return IRQ_NONE; | |
420 | ||
421 | chip->vendor.irq = irq; | |
422 | ||
423 | /* Clear interrupts handled with TPM_EOI */ | |
424 | iowrite32(interrupt, | |
425 | chip->vendor.iobase + | |
426 | TPM_INT_STATUS(chip->vendor.locality)); | |
427 | return IRQ_HANDLED; | |
428 | } | |
429 | ||
a6f97b29 | 430 | static irqreturn_t tis_int_handler(int dummy, void *dev_id) |
27084efe | 431 | { |
06efcad0 | 432 | struct tpm_chip *chip = dev_id; |
27084efe LD |
433 | u32 interrupt; |
434 | int i; | |
435 | ||
436 | interrupt = ioread32(chip->vendor.iobase + | |
437 | TPM_INT_STATUS(chip->vendor.locality)); | |
438 | ||
439 | if (interrupt == 0) | |
440 | return IRQ_NONE; | |
441 | ||
442 | if (interrupt & TPM_INTF_DATA_AVAIL_INT) | |
443 | wake_up_interruptible(&chip->vendor.read_queue); | |
444 | if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT) | |
445 | for (i = 0; i < 5; i++) | |
446 | if (check_locality(chip, i) >= 0) | |
447 | break; | |
448 | if (interrupt & | |
449 | (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT | | |
450 | TPM_INTF_CMD_READY_INT)) | |
451 | wake_up_interruptible(&chip->vendor.int_queue); | |
452 | ||
453 | /* Clear interrupts handled with TPM_EOI */ | |
454 | iowrite32(interrupt, | |
455 | chip->vendor.iobase + | |
456 | TPM_INT_STATUS(chip->vendor.locality)); | |
cab091ea | 457 | ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); |
27084efe LD |
458 | return IRQ_HANDLED; |
459 | } | |
460 | ||
57135568 KJH |
461 | static int interrupts = 1; |
462 | module_param(interrupts, bool, 0444); | |
463 | MODULE_PARM_DESC(interrupts, "Enable interrupts"); | |
464 | ||
c3c36aa9 | 465 | static int tpm_tis_init(struct device *dev, resource_size_t start, |
7917ff9a | 466 | resource_size_t len, unsigned int irq) |
27084efe LD |
467 | { |
468 | u32 vendor, intfcaps, intmask; | |
469 | int rc, i; | |
27084efe LD |
470 | struct tpm_chip *chip; |
471 | ||
9e323d3e | 472 | if (!(chip = tpm_register_hardware(dev, &tpm_tis))) |
27084efe LD |
473 | return -ENODEV; |
474 | ||
475 | chip->vendor.iobase = ioremap(start, len); | |
476 | if (!chip->vendor.iobase) { | |
477 | rc = -EIO; | |
478 | goto out_err; | |
479 | } | |
480 | ||
ec579358 JG |
481 | /* Default timeouts */ |
482 | chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT); | |
483 | chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT); | |
484 | chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT); | |
485 | chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT); | |
486 | ||
05a462af MS |
487 | if (request_locality(chip, 0) != 0) { |
488 | rc = -ENODEV; | |
489 | goto out_err; | |
490 | } | |
491 | ||
27084efe | 492 | vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); |
27084efe | 493 | |
9e323d3e | 494 | dev_info(dev, |
27084efe LD |
495 | "1.2 TPM (device-id 0x%X, rev-id %d)\n", |
496 | vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0))); | |
497 | ||
3507d612 RA |
498 | if (itpm) |
499 | dev_info(dev, "Intel iTPM workaround enabled\n"); | |
500 | ||
501 | ||
27084efe LD |
502 | /* Figure out the capabilities */ |
503 | intfcaps = | |
504 | ioread32(chip->vendor.iobase + | |
505 | TPM_INTF_CAPS(chip->vendor.locality)); | |
9e323d3e | 506 | dev_dbg(dev, "TPM interface capabilities (0x%x):\n", |
27084efe LD |
507 | intfcaps); |
508 | if (intfcaps & TPM_INTF_BURST_COUNT_STATIC) | |
9e323d3e | 509 | dev_dbg(dev, "\tBurst Count Static\n"); |
27084efe | 510 | if (intfcaps & TPM_INTF_CMD_READY_INT) |
9e323d3e | 511 | dev_dbg(dev, "\tCommand Ready Int Support\n"); |
27084efe | 512 | if (intfcaps & TPM_INTF_INT_EDGE_FALLING) |
9e323d3e | 513 | dev_dbg(dev, "\tInterrupt Edge Falling\n"); |
27084efe | 514 | if (intfcaps & TPM_INTF_INT_EDGE_RISING) |
9e323d3e | 515 | dev_dbg(dev, "\tInterrupt Edge Rising\n"); |
27084efe | 516 | if (intfcaps & TPM_INTF_INT_LEVEL_LOW) |
9e323d3e | 517 | dev_dbg(dev, "\tInterrupt Level Low\n"); |
27084efe | 518 | if (intfcaps & TPM_INTF_INT_LEVEL_HIGH) |
9e323d3e | 519 | dev_dbg(dev, "\tInterrupt Level High\n"); |
27084efe | 520 | if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT) |
9e323d3e | 521 | dev_dbg(dev, "\tLocality Change Int Support\n"); |
27084efe | 522 | if (intfcaps & TPM_INTF_STS_VALID_INT) |
9e323d3e | 523 | dev_dbg(dev, "\tSts Valid Int Support\n"); |
27084efe | 524 | if (intfcaps & TPM_INTF_DATA_AVAIL_INT) |
9e323d3e | 525 | dev_dbg(dev, "\tData Avail Int Support\n"); |
27084efe | 526 | |
27084efe LD |
527 | /* INTERRUPT Setup */ |
528 | init_waitqueue_head(&chip->vendor.read_queue); | |
529 | init_waitqueue_head(&chip->vendor.int_queue); | |
530 | ||
531 | intmask = | |
532 | ioread32(chip->vendor.iobase + | |
533 | TPM_INT_ENABLE(chip->vendor.locality)); | |
534 | ||
535 | intmask |= TPM_INTF_CMD_READY_INT | |
536 | | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT | |
537 | | TPM_INTF_STS_VALID_INT; | |
538 | ||
539 | iowrite32(intmask, | |
540 | chip->vendor.iobase + | |
541 | TPM_INT_ENABLE(chip->vendor.locality)); | |
7917ff9a BH |
542 | if (interrupts) |
543 | chip->vendor.irq = irq; | |
544 | if (interrupts && !chip->vendor.irq) { | |
57135568 KJH |
545 | chip->vendor.irq = |
546 | ioread8(chip->vendor.iobase + | |
547 | TPM_INT_VECTOR(chip->vendor.locality)); | |
548 | ||
549 | for (i = 3; i < 16 && chip->vendor.irq == 0; i++) { | |
550 | iowrite8(i, chip->vendor.iobase + | |
551 | TPM_INT_VECTOR(chip->vendor.locality)); | |
552 | if (request_irq | |
0f2ed4c6 | 553 | (i, tis_int_probe, IRQF_SHARED, |
57135568 KJH |
554 | chip->vendor.miscdev.name, chip) != 0) { |
555 | dev_info(chip->dev, | |
556 | "Unable to request irq: %d for probe\n", | |
557 | i); | |
558 | continue; | |
559 | } | |
27084efe | 560 | |
57135568 KJH |
561 | /* Clear all existing */ |
562 | iowrite32(ioread32 | |
563 | (chip->vendor.iobase + | |
564 | TPM_INT_STATUS(chip->vendor.locality)), | |
565 | chip->vendor.iobase + | |
566 | TPM_INT_STATUS(chip->vendor.locality)); | |
567 | ||
568 | /* Turn on */ | |
569 | iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, | |
570 | chip->vendor.iobase + | |
571 | TPM_INT_ENABLE(chip->vendor.locality)); | |
572 | ||
573 | /* Generate Interrupts */ | |
574 | tpm_gen_interrupt(chip); | |
575 | ||
576 | /* Turn off */ | |
577 | iowrite32(intmask, | |
578 | chip->vendor.iobase + | |
579 | TPM_INT_ENABLE(chip->vendor.locality)); | |
580 | free_irq(i, chip); | |
27084efe | 581 | } |
27084efe LD |
582 | } |
583 | if (chip->vendor.irq) { | |
584 | iowrite8(chip->vendor.irq, | |
585 | chip->vendor.iobase + | |
586 | TPM_INT_VECTOR(chip->vendor.locality)); | |
587 | if (request_irq | |
0f2ed4c6 | 588 | (chip->vendor.irq, tis_int_handler, IRQF_SHARED, |
27084efe LD |
589 | chip->vendor.miscdev.name, chip) != 0) { |
590 | dev_info(chip->dev, | |
57135568 KJH |
591 | "Unable to request irq: %d for use\n", |
592 | chip->vendor.irq); | |
27084efe LD |
593 | chip->vendor.irq = 0; |
594 | } else { | |
595 | /* Clear all existing */ | |
596 | iowrite32(ioread32 | |
597 | (chip->vendor.iobase + | |
598 | TPM_INT_STATUS(chip->vendor.locality)), | |
599 | chip->vendor.iobase + | |
600 | TPM_INT_STATUS(chip->vendor.locality)); | |
601 | ||
602 | /* Turn on */ | |
603 | iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, | |
604 | chip->vendor.iobase + | |
605 | TPM_INT_ENABLE(chip->vendor.locality)); | |
606 | } | |
607 | } | |
608 | ||
609 | INIT_LIST_HEAD(&chip->vendor.list); | |
610 | spin_lock(&tis_lock); | |
611 | list_add(&chip->vendor.list, &tis_chips); | |
612 | spin_unlock(&tis_lock); | |
613 | ||
614 | tpm_get_timeouts(chip); | |
615 | tpm_continue_selftest(chip); | |
616 | ||
617 | return 0; | |
618 | out_err: | |
619 | if (chip->vendor.iobase) | |
620 | iounmap(chip->vendor.iobase); | |
621 | tpm_remove_hardware(chip->dev); | |
622 | return rc; | |
623 | } | |
7f2ab000 | 624 | #ifdef CONFIG_PNP |
9e323d3e KJH |
625 | static int __devinit tpm_tis_pnp_init(struct pnp_dev *pnp_dev, |
626 | const struct pnp_device_id *pnp_id) | |
627 | { | |
c3c36aa9 | 628 | resource_size_t start, len; |
7917ff9a BH |
629 | unsigned int irq = 0; |
630 | ||
9e323d3e KJH |
631 | start = pnp_mem_start(pnp_dev, 0); |
632 | len = pnp_mem_len(pnp_dev, 0); | |
633 | ||
7917ff9a BH |
634 | if (pnp_irq_valid(pnp_dev, 0)) |
635 | irq = pnp_irq(pnp_dev, 0); | |
636 | else | |
637 | interrupts = 0; | |
638 | ||
e5cce6c1 OJ |
639 | if (is_itpm(pnp_dev)) |
640 | itpm = 1; | |
641 | ||
7917ff9a | 642 | return tpm_tis_init(&pnp_dev->dev, start, len, irq); |
9e323d3e KJH |
643 | } |
644 | ||
27084efe LD |
645 | static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg) |
646 | { | |
647 | return tpm_pm_suspend(&dev->dev, msg); | |
648 | } | |
649 | ||
650 | static int tpm_tis_pnp_resume(struct pnp_dev *dev) | |
651 | { | |
59f6fbe4 RA |
652 | struct tpm_chip *chip = pnp_get_drvdata(dev); |
653 | int ret; | |
654 | ||
655 | ret = tpm_pm_resume(&dev->dev); | |
656 | if (!ret) | |
657 | tpm_continue_selftest(chip); | |
658 | ||
659 | return ret; | |
27084efe LD |
660 | } |
661 | ||
662 | static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = { | |
663 | {"PNP0C31", 0}, /* TPM */ | |
93e1b7d4 KJH |
664 | {"ATM1200", 0}, /* Atmel */ |
665 | {"IFX0102", 0}, /* Infineon */ | |
666 | {"BCM0101", 0}, /* Broadcom */ | |
061991ec | 667 | {"BCM0102", 0}, /* Broadcom */ |
93e1b7d4 | 668 | {"NSC1200", 0}, /* National */ |
fb0e7e11 | 669 | {"ICO0102", 0}, /* Intel */ |
93e1b7d4 KJH |
670 | /* Add new here */ |
671 | {"", 0}, /* User Specified */ | |
672 | {"", 0} /* Terminator */ | |
27084efe | 673 | }; |
31bde71c | 674 | MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl); |
27084efe | 675 | |
253115b7 RA |
676 | static __devexit void tpm_tis_pnp_remove(struct pnp_dev *dev) |
677 | { | |
678 | struct tpm_chip *chip = pnp_get_drvdata(dev); | |
679 | ||
680 | tpm_dev_vendor_release(chip); | |
681 | ||
682 | kfree(chip); | |
683 | } | |
684 | ||
685 | ||
27084efe LD |
686 | static struct pnp_driver tis_pnp_driver = { |
687 | .name = "tpm_tis", | |
688 | .id_table = tpm_pnp_tbl, | |
689 | .probe = tpm_tis_pnp_init, | |
690 | .suspend = tpm_tis_pnp_suspend, | |
691 | .resume = tpm_tis_pnp_resume, | |
253115b7 | 692 | .remove = tpm_tis_pnp_remove, |
27084efe LD |
693 | }; |
694 | ||
93e1b7d4 KJH |
695 | #define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2 |
696 | module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id, | |
697 | sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444); | |
698 | MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe"); | |
7f2ab000 | 699 | #endif |
7a192ec3 ML |
700 | static int tpm_tis_suspend(struct platform_device *dev, pm_message_t msg) |
701 | { | |
702 | return tpm_pm_suspend(&dev->dev, msg); | |
703 | } | |
704 | ||
705 | static int tpm_tis_resume(struct platform_device *dev) | |
706 | { | |
707 | return tpm_pm_resume(&dev->dev); | |
708 | } | |
709 | static struct platform_driver tis_drv = { | |
710 | .driver = { | |
711 | .name = "tpm_tis", | |
712 | .owner = THIS_MODULE, | |
713 | }, | |
714 | .suspend = tpm_tis_suspend, | |
715 | .resume = tpm_tis_resume, | |
9e323d3e KJH |
716 | }; |
717 | ||
718 | static struct platform_device *pdev; | |
719 | ||
720 | static int force; | |
721 | module_param(force, bool, 0444); | |
722 | MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry"); | |
27084efe LD |
723 | static int __init init_tis(void) |
724 | { | |
9e323d3e | 725 | int rc; |
7f2ab000 RA |
726 | #ifdef CONFIG_PNP |
727 | if (!force) | |
728 | return pnp_register_driver(&tis_pnp_driver); | |
729 | #endif | |
9e323d3e | 730 | |
7f2ab000 RA |
731 | rc = platform_driver_register(&tis_drv); |
732 | if (rc < 0) | |
9e323d3e | 733 | return rc; |
7f2ab000 RA |
734 | if (IS_ERR(pdev=platform_device_register_simple("tpm_tis", -1, NULL, 0))) |
735 | return PTR_ERR(pdev); | |
736 | if((rc=tpm_tis_init(&pdev->dev, TIS_MEM_BASE, TIS_MEM_LEN, 0)) != 0) { | |
737 | platform_device_unregister(pdev); | |
738 | platform_driver_unregister(&tis_drv); | |
9e323d3e | 739 | } |
7f2ab000 | 740 | return rc; |
27084efe LD |
741 | } |
742 | ||
743 | static void __exit cleanup_tis(void) | |
744 | { | |
745 | struct tpm_vendor_specific *i, *j; | |
746 | struct tpm_chip *chip; | |
747 | spin_lock(&tis_lock); | |
748 | list_for_each_entry_safe(i, j, &tis_chips, list) { | |
749 | chip = to_tpm_chip(i); | |
253115b7 | 750 | tpm_remove_hardware(chip->dev); |
27084efe LD |
751 | iowrite32(~TPM_GLOBAL_INT_ENABLE & |
752 | ioread32(chip->vendor.iobase + | |
753 | TPM_INT_ENABLE(chip->vendor. | |
754 | locality)), | |
755 | chip->vendor.iobase + | |
756 | TPM_INT_ENABLE(chip->vendor.locality)); | |
757 | release_locality(chip, chip->vendor.locality, 1); | |
758 | if (chip->vendor.irq) | |
759 | free_irq(chip->vendor.irq, chip); | |
760 | iounmap(i->iobase); | |
761 | list_del(&i->list); | |
27084efe LD |
762 | } |
763 | spin_unlock(&tis_lock); | |
7f2ab000 RA |
764 | #ifdef CONFIG_PNP |
765 | if (!force) { | |
9e323d3e | 766 | pnp_unregister_driver(&tis_pnp_driver); |
7f2ab000 RA |
767 | return; |
768 | } | |
769 | #endif | |
770 | platform_device_unregister(pdev); | |
771 | platform_driver_unregister(&tis_drv); | |
27084efe LD |
772 | } |
773 | ||
774 | module_init(init_tis); | |
775 | module_exit(cleanup_tis); | |
776 | MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); | |
777 | MODULE_DESCRIPTION("TPM Driver"); | |
778 | MODULE_VERSION("2.0"); | |
779 | MODULE_LICENSE("GPL"); |