char: tpm: Add missing error check for devm_kzalloc
[deliverable/linux.git] / drivers / char / tpm / tpm_tis.c
CommitLineData
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1/*
2 * Copyright (C) 2005, 2006 IBM Corporation
3 *
4 * Authors:
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Kylene Hall <kjhall@us.ibm.com>
7 *
8e81cc13
KY
8 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
9 *
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10 * Device driver for TCG/TCPA TPM (trusted platform module).
11 * Specifications at www.trustedcomputinggroup.org
12 *
13 * This device driver implements the TPM interface as defined in
14 * the TCG TPM Interface Spec version 1.2, revision 1.0.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation, version 2 of the
19 * License.
20 */
57135568
KJH
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/moduleparam.h>
27084efe 24#include <linux/pnp.h>
5a0e3ad6 25#include <linux/slab.h>
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LD
26#include <linux/interrupt.h>
27#include <linux/wait.h>
3f0d3d01 28#include <linux/acpi.h>
20b87bbf 29#include <linux/freezer.h>
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LD
30#include "tpm.h"
31
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32enum tis_access {
33 TPM_ACCESS_VALID = 0x80,
34 TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
35 TPM_ACCESS_REQUEST_PENDING = 0x04,
36 TPM_ACCESS_REQUEST_USE = 0x02,
37};
38
39enum tis_status {
40 TPM_STS_VALID = 0x80,
41 TPM_STS_COMMAND_READY = 0x40,
42 TPM_STS_GO = 0x20,
43 TPM_STS_DATA_AVAIL = 0x10,
44 TPM_STS_DATA_EXPECT = 0x08,
45};
46
47enum tis_int_flags {
48 TPM_GLOBAL_INT_ENABLE = 0x80000000,
49 TPM_INTF_BURST_COUNT_STATIC = 0x100,
50 TPM_INTF_CMD_READY_INT = 0x080,
51 TPM_INTF_INT_EDGE_FALLING = 0x040,
52 TPM_INTF_INT_EDGE_RISING = 0x020,
53 TPM_INTF_INT_LEVEL_LOW = 0x010,
54 TPM_INTF_INT_LEVEL_HIGH = 0x008,
55 TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
56 TPM_INTF_STS_VALID_INT = 0x002,
57 TPM_INTF_DATA_AVAIL_INT = 0x001,
58};
59
36b20020 60enum tis_defaults {
2a7362f5 61 TIS_MEM_BASE = 0xFED40000,
b09d5300 62 TIS_MEM_LEN = 0x5000,
cb535425
KJH
63 TIS_SHORT_TIMEOUT = 750, /* ms */
64 TIS_LONG_TIMEOUT = 2000, /* 2 sec */
36b20020
KJH
65};
66
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67#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
68#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
69#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
70#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
71#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
72#define TPM_STS(l) (0x0018 | ((l) << 12))
73#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
74
75#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
76#define TPM_RID(l) (0x0F04 | ((l) << 12))
77
78static LIST_HEAD(tis_chips);
4e70daaf 79static DEFINE_MUTEX(tis_lock);
27084efe 80
1560ffe6 81#if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
3f0d3d01
MG
82static int is_itpm(struct pnp_dev *dev)
83{
84 struct acpi_device *acpi = pnp_acpi_device(dev);
85 struct acpi_hardware_id *id;
86
6e38bfaa
KY
87 if (!acpi)
88 return 0;
89
3f0d3d01
MG
90 list_for_each_entry(id, &acpi->pnp.ids, list) {
91 if (!strcmp("INTC0102", id->id))
92 return 1;
93 }
94
95 return 0;
96}
1560ffe6
RD
97#else
98static inline int is_itpm(struct pnp_dev *dev)
99{
100 return 0;
101}
3f0d3d01
MG
102#endif
103
7240b983
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104/* Before we attempt to access the TPM we must see that the valid bit is set.
105 * The specification says that this bit is 0 at reset and remains 0 until the
106 * 'TPM has gone through its self test and initialization and has established
107 * correct values in the other bits.' */
108static int wait_startup(struct tpm_chip *chip, int l)
109{
110 unsigned long stop = jiffies + chip->vendor.timeout_a;
111 do {
112 if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
113 TPM_ACCESS_VALID)
114 return 0;
115 msleep(TPM_TIMEOUT);
116 } while (time_before(jiffies, stop));
117 return -1;
118}
119
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LD
120static int check_locality(struct tpm_chip *chip, int l)
121{
122 if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
123 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
124 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
125 return chip->vendor.locality = l;
126
127 return -1;
128}
129
130static void release_locality(struct tpm_chip *chip, int l, int force)
131{
132 if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
133 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
134 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
135 iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
136 chip->vendor.iobase + TPM_ACCESS(l));
137}
138
139static int request_locality(struct tpm_chip *chip, int l)
140{
20b87bbf 141 unsigned long stop, timeout;
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142 long rc;
143
144 if (check_locality(chip, l) >= 0)
145 return l;
146
147 iowrite8(TPM_ACCESS_REQUEST_USE,
148 chip->vendor.iobase + TPM_ACCESS(l));
149
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SB
150 stop = jiffies + chip->vendor.timeout_a;
151
27084efe 152 if (chip->vendor.irq) {
20b87bbf
SB
153again:
154 timeout = stop - jiffies;
155 if ((long)timeout <= 0)
156 return -1;
36b20020 157 rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
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LD
158 (check_locality
159 (chip, l) >= 0),
20b87bbf 160 timeout);
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161 if (rc > 0)
162 return l;
20b87bbf
SB
163 if (rc == -ERESTARTSYS && freezing(current)) {
164 clear_thread_flag(TIF_SIGPENDING);
165 goto again;
166 }
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LD
167 } else {
168 /* wait for burstcount */
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169 do {
170 if (check_locality(chip, l) >= 0)
171 return l;
172 msleep(TPM_TIMEOUT);
173 }
174 while (time_before(jiffies, stop));
175 }
176 return -1;
177}
178
179static u8 tpm_tis_status(struct tpm_chip *chip)
180{
181 return ioread8(chip->vendor.iobase +
182 TPM_STS(chip->vendor.locality));
183}
184
185static void tpm_tis_ready(struct tpm_chip *chip)
186{
187 /* this causes the current command to be aborted */
188 iowrite8(TPM_STS_COMMAND_READY,
189 chip->vendor.iobase + TPM_STS(chip->vendor.locality));
190}
191
192static int get_burstcount(struct tpm_chip *chip)
193{
194 unsigned long stop;
195 int burstcnt;
196
197 /* wait for burstcount */
198 /* which timeout value, spec has 2 answers (c & d) */
36b20020 199 stop = jiffies + chip->vendor.timeout_d;
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200 do {
201 burstcnt = ioread8(chip->vendor.iobase +
202 TPM_STS(chip->vendor.locality) + 1);
203 burstcnt += ioread8(chip->vendor.iobase +
204 TPM_STS(chip->vendor.locality) +
205 2) << 8;
206 if (burstcnt)
207 return burstcnt;
208 msleep(TPM_TIMEOUT);
209 } while (time_before(jiffies, stop));
210 return -EBUSY;
211}
212
cb535425 213static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
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LD
214{
215 int size = 0, burstcnt;
216 while (size < count &&
fd048866
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217 wait_for_tpm_stat(chip,
218 TPM_STS_DATA_AVAIL | TPM_STS_VALID,
219 chip->vendor.timeout_c,
78f09cc2 220 &chip->vendor.read_queue, true)
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LD
221 == 0) {
222 burstcnt = get_burstcount(chip);
223 for (; burstcnt > 0 && size < count; burstcnt--)
224 buf[size++] = ioread8(chip->vendor.iobase +
225 TPM_DATA_FIFO(chip->vendor.
226 locality));
227 }
228 return size;
229}
230
cb535425 231static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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LD
232{
233 int size = 0;
234 int expected, status;
235
236 if (count < TPM_HEADER_SIZE) {
237 size = -EIO;
238 goto out;
239 }
240
241 /* read first 10 bytes, including tag, paramsize, and result */
242 if ((size =
243 recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
244 dev_err(chip->dev, "Unable to read header\n");
245 goto out;
246 }
247
248 expected = be32_to_cpu(*(__be32 *) (buf + 2));
249 if (expected > count) {
250 size = -EIO;
251 goto out;
252 }
253
254 if ((size +=
255 recv_data(chip, &buf[TPM_HEADER_SIZE],
256 expected - TPM_HEADER_SIZE)) < expected) {
257 dev_err(chip->dev, "Unable to read remainder of result\n");
258 size = -ETIME;
259 goto out;
260 }
261
fd048866 262 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 263 &chip->vendor.int_queue, false);
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LD
264 status = tpm_tis_status(chip);
265 if (status & TPM_STS_DATA_AVAIL) { /* retry? */
266 dev_err(chip->dev, "Error left over data\n");
267 size = -EIO;
268 goto out;
269 }
270
271out:
272 tpm_tis_ready(chip);
273 release_locality(chip, chip->vendor.locality, 0);
274 return size;
275}
276
90ab5ee9 277static bool itpm;
3507d612
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278module_param(itpm, bool, 0444);
279MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)");
280
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281/*
282 * If interrupts are used (signaled by an irq set in the vendor structure)
283 * tpm.c can skip polling for the data to be available as the interrupt is
284 * waited for here
285 */
9519de3f 286static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
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LD
287{
288 int rc, status, burstcnt;
289 size_t count = 0;
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LD
290
291 if (request_locality(chip, 0) < 0)
292 return -EBUSY;
293
294 status = tpm_tis_status(chip);
295 if ((status & TPM_STS_COMMAND_READY) == 0) {
296 tpm_tis_ready(chip);
fd048866 297 if (wait_for_tpm_stat
27084efe 298 (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
78f09cc2 299 &chip->vendor.int_queue, false) < 0) {
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LD
300 rc = -ETIME;
301 goto out_err;
302 }
303 }
304
305 while (count < len - 1) {
306 burstcnt = get_burstcount(chip);
307 for (; burstcnt > 0 && count < len - 1; burstcnt--) {
308 iowrite8(buf[count], chip->vendor.iobase +
309 TPM_DATA_FIFO(chip->vendor.locality));
310 count++;
311 }
312
fd048866 313 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 314 &chip->vendor.int_queue, false);
27084efe 315 status = tpm_tis_status(chip);
3507d612 316 if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
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LD
317 rc = -EIO;
318 goto out_err;
319 }
320 }
321
322 /* write last byte */
323 iowrite8(buf[count],
9519de3f 324 chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
fd048866 325 wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
78f09cc2 326 &chip->vendor.int_queue, false);
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LD
327 status = tpm_tis_status(chip);
328 if ((status & TPM_STS_DATA_EXPECT) != 0) {
329 rc = -EIO;
330 goto out_err;
331 }
332
9519de3f
SB
333 return 0;
334
335out_err:
336 tpm_tis_ready(chip);
337 release_locality(chip, chip->vendor.locality, 0);
338 return rc;
339}
340
341/*
342 * If interrupts are used (signaled by an irq set in the vendor structure)
343 * tpm.c can skip polling for the data to be available as the interrupt is
344 * waited for here
345 */
346static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
347{
348 int rc;
349 u32 ordinal;
350
351 rc = tpm_tis_send_data(chip, buf, len);
352 if (rc < 0)
353 return rc;
354
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355 /* go and do it */
356 iowrite8(TPM_STS_GO,
357 chip->vendor.iobase + TPM_STS(chip->vendor.locality));
358
359 if (chip->vendor.irq) {
360 ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
fd048866 361 if (wait_for_tpm_stat
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LD
362 (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
363 tpm_calc_ordinal_duration(chip, ordinal),
78f09cc2 364 &chip->vendor.read_queue, false) < 0) {
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LD
365 rc = -ETIME;
366 goto out_err;
367 }
368 }
369 return len;
370out_err:
371 tpm_tis_ready(chip);
372 release_locality(chip, chip->vendor.locality, 0);
373 return rc;
374}
375
8e54caf4
JG
376struct tis_vendor_timeout_override {
377 u32 did_vid;
378 unsigned long timeout_us[4];
379};
380
381static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
382 /* Atmel 3204 */
383 { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
384 (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
385};
386
387static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
388 unsigned long *timeout_cap)
389{
390 int i;
391 u32 did_vid;
392
393 did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
394
395 for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
396 if (vendor_timeout_overrides[i].did_vid != did_vid)
397 continue;
398 memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
399 sizeof(vendor_timeout_overrides[i].timeout_us));
400 return true;
401 }
402
403 return false;
404}
405
9519de3f
SB
406/*
407 * Early probing for iTPM with STS_DATA_EXPECT flaw.
408 * Try sending command without itpm flag set and if that
409 * fails, repeat with itpm flag set.
410 */
411static int probe_itpm(struct tpm_chip *chip)
412{
413 int rc = 0;
414 u8 cmd_getticks[] = {
415 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
416 0x00, 0x00, 0x00, 0xf1
417 };
418 size_t len = sizeof(cmd_getticks);
968de8e2 419 bool rem_itpm = itpm;
4e401fb0
SB
420 u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0));
421
422 /* probe only iTPMS */
423 if (vendor != TPM_VID_INTEL)
424 return 0;
9519de3f 425
73249695 426 itpm = false;
9519de3f
SB
427
428 rc = tpm_tis_send_data(chip, cmd_getticks, len);
429 if (rc == 0)
430 goto out;
431
432 tpm_tis_ready(chip);
433 release_locality(chip, chip->vendor.locality, 0);
434
73249695 435 itpm = true;
9519de3f
SB
436
437 rc = tpm_tis_send_data(chip, cmd_getticks, len);
438 if (rc == 0) {
439 dev_info(chip->dev, "Detected an iTPM.\n");
440 rc = 1;
441 } else
442 rc = -EFAULT;
443
444out:
445 itpm = rem_itpm;
446 tpm_tis_ready(chip);
447 release_locality(chip, chip->vendor.locality, 0);
448
449 return rc;
450}
451
1f866057
SB
452static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
453{
454 switch (chip->vendor.manufacturer_id) {
455 case TPM_VID_WINBOND:
456 return ((status == TPM_STS_VALID) ||
457 (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
458 case TPM_VID_STM:
459 return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
460 default:
461 return (status == TPM_STS_COMMAND_READY);
462 }
463}
464
01ad1fa7 465static const struct tpm_class_ops tpm_tis = {
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LD
466 .status = tpm_tis_status,
467 .recv = tpm_tis_recv,
468 .send = tpm_tis_send,
469 .cancel = tpm_tis_ready,
8e54caf4 470 .update_timeouts = tpm_tis_update_timeouts,
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LD
471 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
472 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
1f866057 473 .req_canceled = tpm_tis_req_canceled,
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LD
474};
475
7d12e780 476static irqreturn_t tis_int_probe(int irq, void *dev_id)
27084efe 477{
06efcad0 478 struct tpm_chip *chip = dev_id;
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LD
479 u32 interrupt;
480
481 interrupt = ioread32(chip->vendor.iobase +
482 TPM_INT_STATUS(chip->vendor.locality));
483
484 if (interrupt == 0)
485 return IRQ_NONE;
486
a7b66822 487 chip->vendor.probed_irq = irq;
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LD
488
489 /* Clear interrupts handled with TPM_EOI */
490 iowrite32(interrupt,
491 chip->vendor.iobase +
492 TPM_INT_STATUS(chip->vendor.locality));
493 return IRQ_HANDLED;
494}
495
a6f97b29 496static irqreturn_t tis_int_handler(int dummy, void *dev_id)
27084efe 497{
06efcad0 498 struct tpm_chip *chip = dev_id;
27084efe
LD
499 u32 interrupt;
500 int i;
501
502 interrupt = ioread32(chip->vendor.iobase +
503 TPM_INT_STATUS(chip->vendor.locality));
504
505 if (interrupt == 0)
506 return IRQ_NONE;
507
508 if (interrupt & TPM_INTF_DATA_AVAIL_INT)
509 wake_up_interruptible(&chip->vendor.read_queue);
510 if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
511 for (i = 0; i < 5; i++)
512 if (check_locality(chip, i) >= 0)
513 break;
514 if (interrupt &
515 (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
516 TPM_INTF_CMD_READY_INT))
517 wake_up_interruptible(&chip->vendor.int_queue);
518
519 /* Clear interrupts handled with TPM_EOI */
520 iowrite32(interrupt,
521 chip->vendor.iobase +
522 TPM_INT_STATUS(chip->vendor.locality));
cab091ea 523 ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
27084efe
LD
524 return IRQ_HANDLED;
525}
526
73249695 527static bool interrupts = true;
57135568
KJH
528module_param(interrupts, bool, 0444);
529MODULE_PARM_DESC(interrupts, "Enable interrupts");
530
c3c36aa9 531static int tpm_tis_init(struct device *dev, resource_size_t start,
7917ff9a 532 resource_size_t len, unsigned int irq)
27084efe
LD
533{
534 u32 vendor, intfcaps, intmask;
968de8e2 535 int rc, i, irq_s, irq_e, probe;
27084efe
LD
536 struct tpm_chip *chip;
537
9e323d3e 538 if (!(chip = tpm_register_hardware(dev, &tpm_tis)))
27084efe
LD
539 return -ENODEV;
540
541 chip->vendor.iobase = ioremap(start, len);
542 if (!chip->vendor.iobase) {
543 rc = -EIO;
544 goto out_err;
545 }
546
ec579358
JG
547 /* Default timeouts */
548 chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
549 chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
550 chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
551 chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
552
7240b983
JG
553 if (wait_startup(chip, 0) != 0) {
554 rc = -ENODEV;
555 goto out_err;
556 }
557
05a462af
MS
558 if (request_locality(chip, 0) != 0) {
559 rc = -ENODEV;
560 goto out_err;
561 }
562
27084efe 563 vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
3e3a5e90 564 chip->vendor.manufacturer_id = vendor;
27084efe 565
9e323d3e 566 dev_info(dev,
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LD
567 "1.2 TPM (device-id 0x%X, rev-id %d)\n",
568 vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
569
9519de3f 570 if (!itpm) {
968de8e2
SB
571 probe = probe_itpm(chip);
572 if (probe < 0) {
9519de3f
SB
573 rc = -ENODEV;
574 goto out_err;
575 }
73249695 576 itpm = !!probe;
9519de3f
SB
577 }
578
3507d612
RA
579 if (itpm)
580 dev_info(dev, "Intel iTPM workaround enabled\n");
581
582
27084efe
LD
583 /* Figure out the capabilities */
584 intfcaps =
585 ioread32(chip->vendor.iobase +
586 TPM_INTF_CAPS(chip->vendor.locality));
9e323d3e 587 dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
27084efe
LD
588 intfcaps);
589 if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
9e323d3e 590 dev_dbg(dev, "\tBurst Count Static\n");
27084efe 591 if (intfcaps & TPM_INTF_CMD_READY_INT)
9e323d3e 592 dev_dbg(dev, "\tCommand Ready Int Support\n");
27084efe 593 if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
9e323d3e 594 dev_dbg(dev, "\tInterrupt Edge Falling\n");
27084efe 595 if (intfcaps & TPM_INTF_INT_EDGE_RISING)
9e323d3e 596 dev_dbg(dev, "\tInterrupt Edge Rising\n");
27084efe 597 if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
9e323d3e 598 dev_dbg(dev, "\tInterrupt Level Low\n");
27084efe 599 if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
9e323d3e 600 dev_dbg(dev, "\tInterrupt Level High\n");
27084efe 601 if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
9e323d3e 602 dev_dbg(dev, "\tLocality Change Int Support\n");
27084efe 603 if (intfcaps & TPM_INTF_STS_VALID_INT)
9e323d3e 604 dev_dbg(dev, "\tSts Valid Int Support\n");
27084efe 605 if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
9e323d3e 606 dev_dbg(dev, "\tData Avail Int Support\n");
27084efe 607
a7b66822 608 /* get the timeouts before testing for irqs */
7f326ed7
SB
609 if (tpm_get_timeouts(chip)) {
610 dev_err(dev, "Could not get TPM timeouts and durations\n");
611 rc = -ENODEV;
612 goto out_err;
613 }
a7b66822 614
68d6e671
SB
615 if (tpm_do_selftest(chip)) {
616 dev_err(dev, "TPM self test failed\n");
617 rc = -ENODEV;
618 goto out_err;
619 }
620
27084efe
LD
621 /* INTERRUPT Setup */
622 init_waitqueue_head(&chip->vendor.read_queue);
623 init_waitqueue_head(&chip->vendor.int_queue);
624
625 intmask =
626 ioread32(chip->vendor.iobase +
627 TPM_INT_ENABLE(chip->vendor.locality));
628
629 intmask |= TPM_INTF_CMD_READY_INT
630 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
631 | TPM_INTF_STS_VALID_INT;
632
633 iowrite32(intmask,
634 chip->vendor.iobase +
635 TPM_INT_ENABLE(chip->vendor.locality));
7917ff9a
BH
636 if (interrupts)
637 chip->vendor.irq = irq;
638 if (interrupts && !chip->vendor.irq) {
a7b66822 639 irq_s =
57135568
KJH
640 ioread8(chip->vendor.iobase +
641 TPM_INT_VECTOR(chip->vendor.locality));
a7b66822
SB
642 if (irq_s) {
643 irq_e = irq_s;
644 } else {
645 irq_s = 3;
646 irq_e = 15;
647 }
57135568 648
a7b66822 649 for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) {
57135568 650 iowrite8(i, chip->vendor.iobase +
a7b66822 651 TPM_INT_VECTOR(chip->vendor.locality));
57135568 652 if (request_irq
0f2ed4c6 653 (i, tis_int_probe, IRQF_SHARED,
57135568
KJH
654 chip->vendor.miscdev.name, chip) != 0) {
655 dev_info(chip->dev,
656 "Unable to request irq: %d for probe\n",
657 i);
658 continue;
659 }
27084efe 660
57135568
KJH
661 /* Clear all existing */
662 iowrite32(ioread32
663 (chip->vendor.iobase +
664 TPM_INT_STATUS(chip->vendor.locality)),
665 chip->vendor.iobase +
666 TPM_INT_STATUS(chip->vendor.locality));
667
668 /* Turn on */
669 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
670 chip->vendor.iobase +
671 TPM_INT_ENABLE(chip->vendor.locality));
672
a7b66822
SB
673 chip->vendor.probed_irq = 0;
674
57135568
KJH
675 /* Generate Interrupts */
676 tpm_gen_interrupt(chip);
677
a7b66822
SB
678 chip->vendor.irq = chip->vendor.probed_irq;
679
680 /* free_irq will call into tis_int_probe;
681 clear all irqs we haven't seen while doing
682 tpm_gen_interrupt */
683 iowrite32(ioread32
684 (chip->vendor.iobase +
685 TPM_INT_STATUS(chip->vendor.locality)),
686 chip->vendor.iobase +
687 TPM_INT_STATUS(chip->vendor.locality));
688
57135568
KJH
689 /* Turn off */
690 iowrite32(intmask,
691 chip->vendor.iobase +
692 TPM_INT_ENABLE(chip->vendor.locality));
693 free_irq(i, chip);
27084efe 694 }
27084efe
LD
695 }
696 if (chip->vendor.irq) {
697 iowrite8(chip->vendor.irq,
698 chip->vendor.iobase +
699 TPM_INT_VECTOR(chip->vendor.locality));
700 if (request_irq
0f2ed4c6 701 (chip->vendor.irq, tis_int_handler, IRQF_SHARED,
27084efe
LD
702 chip->vendor.miscdev.name, chip) != 0) {
703 dev_info(chip->dev,
57135568
KJH
704 "Unable to request irq: %d for use\n",
705 chip->vendor.irq);
27084efe
LD
706 chip->vendor.irq = 0;
707 } else {
708 /* Clear all existing */
709 iowrite32(ioread32
710 (chip->vendor.iobase +
711 TPM_INT_STATUS(chip->vendor.locality)),
712 chip->vendor.iobase +
713 TPM_INT_STATUS(chip->vendor.locality));
714
715 /* Turn on */
716 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
717 chip->vendor.iobase +
718 TPM_INT_ENABLE(chip->vendor.locality));
719 }
720 }
721
722 INIT_LIST_HEAD(&chip->vendor.list);
4e70daaf 723 mutex_lock(&tis_lock);
27084efe 724 list_add(&chip->vendor.list, &tis_chips);
4e70daaf 725 mutex_unlock(&tis_lock);
27084efe 726
27084efe
LD
727
728 return 0;
729out_err:
730 if (chip->vendor.iobase)
731 iounmap(chip->vendor.iobase);
732 tpm_remove_hardware(chip->dev);
733 return rc;
734}
96854310 735
19b94d2d 736#ifdef CONFIG_PM_SLEEP
96854310
SB
737static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
738{
739 u32 intmask;
740
741 /* reenable interrupts that device may have lost or
742 BIOS/firmware may have disabled */
743 iowrite8(chip->vendor.irq, chip->vendor.iobase +
744 TPM_INT_VECTOR(chip->vendor.locality));
745
746 intmask =
747 ioread32(chip->vendor.iobase +
748 TPM_INT_ENABLE(chip->vendor.locality));
749
750 intmask |= TPM_INTF_CMD_READY_INT
751 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
752 | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
753
754 iowrite32(intmask,
755 chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
756}
96854310 757
a2fa3fb0
SK
758static int tpm_tis_resume(struct device *dev)
759{
760 struct tpm_chip *chip = dev_get_drvdata(dev);
761 int ret;
762
763 if (chip->vendor.irq)
764 tpm_tis_reenable_interrupts(chip);
765
766 ret = tpm_pm_resume(dev);
767 if (!ret)
768 tpm_do_selftest(chip);
769
770 return ret;
771}
772#endif
773
774static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
775
7f2ab000 776#ifdef CONFIG_PNP
afc6d369 777static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
9e323d3e
KJH
778 const struct pnp_device_id *pnp_id)
779{
c3c36aa9 780 resource_size_t start, len;
7917ff9a
BH
781 unsigned int irq = 0;
782
9e323d3e
KJH
783 start = pnp_mem_start(pnp_dev, 0);
784 len = pnp_mem_len(pnp_dev, 0);
785
7917ff9a
BH
786 if (pnp_irq_valid(pnp_dev, 0))
787 irq = pnp_irq(pnp_dev, 0);
788 else
73249695 789 interrupts = false;
7917ff9a 790
e5cce6c1 791 if (is_itpm(pnp_dev))
73249695 792 itpm = true;
e5cce6c1 793
7917ff9a 794 return tpm_tis_init(&pnp_dev->dev, start, len, irq);
9e323d3e
KJH
795}
796
0bbed20e 797static struct pnp_device_id tpm_pnp_tbl[] = {
27084efe 798 {"PNP0C31", 0}, /* TPM */
93e1b7d4
KJH
799 {"ATM1200", 0}, /* Atmel */
800 {"IFX0102", 0}, /* Infineon */
801 {"BCM0101", 0}, /* Broadcom */
061991ec 802 {"BCM0102", 0}, /* Broadcom */
93e1b7d4 803 {"NSC1200", 0}, /* National */
fb0e7e11 804 {"ICO0102", 0}, /* Intel */
93e1b7d4
KJH
805 /* Add new here */
806 {"", 0}, /* User Specified */
807 {"", 0} /* Terminator */
27084efe 808};
31bde71c 809MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
27084efe 810
39af33fc 811static void tpm_tis_pnp_remove(struct pnp_dev *dev)
253115b7
RA
812{
813 struct tpm_chip *chip = pnp_get_drvdata(dev);
814
815 tpm_dev_vendor_release(chip);
816
817 kfree(chip);
818}
819
820
27084efe
LD
821static struct pnp_driver tis_pnp_driver = {
822 .name = "tpm_tis",
823 .id_table = tpm_pnp_tbl,
824 .probe = tpm_tis_pnp_init,
253115b7 825 .remove = tpm_tis_pnp_remove,
a2fa3fb0
SK
826 .driver = {
827 .pm = &tpm_tis_pm,
828 },
27084efe
LD
829};
830
93e1b7d4
KJH
831#define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
832module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
833 sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
834MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
7f2ab000 835#endif
7a192ec3 836
7a192ec3
ML
837static struct platform_driver tis_drv = {
838 .driver = {
839 .name = "tpm_tis",
b633f050 840 .pm = &tpm_tis_pm,
7a192ec3 841 },
9e323d3e
KJH
842};
843
844static struct platform_device *pdev;
845
90ab5ee9 846static bool force;
9e323d3e
KJH
847module_param(force, bool, 0444);
848MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
27084efe
LD
849static int __init init_tis(void)
850{
9e323d3e 851 int rc;
7f2ab000
RA
852#ifdef CONFIG_PNP
853 if (!force)
854 return pnp_register_driver(&tis_pnp_driver);
855#endif
9e323d3e 856
7f2ab000
RA
857 rc = platform_driver_register(&tis_drv);
858 if (rc < 0)
9e323d3e 859 return rc;
4fba3c3b
WY
860 pdev = platform_device_register_simple("tpm_tis", -1, NULL, 0);
861 if (IS_ERR(pdev)) {
862 rc = PTR_ERR(pdev);
863 goto err_dev;
9e323d3e 864 }
4fba3c3b
WY
865 rc = tpm_tis_init(&pdev->dev, TIS_MEM_BASE, TIS_MEM_LEN, 0);
866 if (rc)
867 goto err_init;
868 return 0;
869err_init:
870 platform_device_unregister(pdev);
871err_dev:
872 platform_driver_unregister(&tis_drv);
7f2ab000 873 return rc;
27084efe
LD
874}
875
876static void __exit cleanup_tis(void)
877{
878 struct tpm_vendor_specific *i, *j;
879 struct tpm_chip *chip;
4e70daaf 880 mutex_lock(&tis_lock);
27084efe
LD
881 list_for_each_entry_safe(i, j, &tis_chips, list) {
882 chip = to_tpm_chip(i);
253115b7 883 tpm_remove_hardware(chip->dev);
27084efe
LD
884 iowrite32(~TPM_GLOBAL_INT_ENABLE &
885 ioread32(chip->vendor.iobase +
886 TPM_INT_ENABLE(chip->vendor.
887 locality)),
888 chip->vendor.iobase +
889 TPM_INT_ENABLE(chip->vendor.locality));
890 release_locality(chip, chip->vendor.locality, 1);
891 if (chip->vendor.irq)
892 free_irq(chip->vendor.irq, chip);
893 iounmap(i->iobase);
894 list_del(&i->list);
27084efe 895 }
4e70daaf 896 mutex_unlock(&tis_lock);
7f2ab000
RA
897#ifdef CONFIG_PNP
898 if (!force) {
9e323d3e 899 pnp_unregister_driver(&tis_pnp_driver);
7f2ab000
RA
900 return;
901 }
902#endif
903 platform_device_unregister(pdev);
904 platform_driver_unregister(&tis_drv);
27084efe
LD
905}
906
907module_init(init_tis);
908module_exit(cleanup_tis);
909MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
910MODULE_DESCRIPTION("TPM Driver");
911MODULE_VERSION("2.0");
912MODULE_LICENSE("GPL");
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