[deliverable/linux.git] / drivers / char / watchdog / pnx4008_wdt.c

/*
 * drivers/char/watchdog/pnx4008_wdt.c
 *
 * Watchdog driver for PNX4008 board
 *
 * Authors: Dmitry Chigirev <source@mvista.com>,
 * 	    Vitaly Wool <vitalywool@gmail.com>
 * Based on sa1100 driver,
 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
 *
 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spinlock.h>

#include <asm/hardware.h>
#include <asm/uaccess.h>
#include <asm/io.h>

#define MODULE_NAME "PNX4008-WDT: "

/* WatchDog Timer - Chapter 23 Page 207 */

#define DEFAULT_HEARTBEAT 19
#define MAX_HEARTBEAT     60

/* Watchdog timer register set definition */
#define WDTIM_INT(p)     ((p) + 0x0)
#define WDTIM_CTRL(p)    ((p) + 0x4)
#define WDTIM_COUNTER(p) ((p) + 0x8)
#define WDTIM_MCTRL(p)   ((p) + 0xC)
#define WDTIM_MATCH0(p)  ((p) + 0x10)
#define WDTIM_EMR(p)     ((p) + 0x14)
#define WDTIM_PULSE(p)   ((p) + 0x18)
#define WDTIM_RES(p)     ((p) + 0x1C)

/* WDTIM_INT bit definitions */
#define MATCH_INT      1

/* WDTIM_CTRL bit definitions */
#define COUNT_ENAB     1
#define RESET_COUNT    (1<<1)
#define DEBUG_EN       (1<<2)

/* WDTIM_MCTRL bit definitions */
#define MR0_INT        1
#undef  RESET_COUNT0
#define RESET_COUNT0   (1<<2)
#define STOP_COUNT0    (1<<2)
#define M_RES1         (1<<3)
#define M_RES2         (1<<4)
#define RESFRC1        (1<<5)
#define RESFRC2        (1<<6)

/* WDTIM_EMR bit definitions */
#define EXT_MATCH0      1
#define MATCH_OUTPUT_HIGH (2<<4)	/*a MATCH_CTRL setting */

/* WDTIM_RES bit definitions */
#define WDOG_RESET      1	/* read only */

#define WDOG_COUNTER_RATE 13000000	/*the counter clock is 13 MHz fixed */

static int nowayout = WATCHDOG_NOWAYOUT;
static int heartbeat = DEFAULT_HEARTBEAT;

static spinlock_t io_lock;
static unsigned long wdt_status;
#define WDT_IN_USE        0
#define WDT_OK_TO_CLOSE   1
#define WDT_REGION_INITED 2
#define WDT_DEVICE_INITED 3

static unsigned long boot_status;

static struct resource	*wdt_mem;
static void __iomem	*wdt_base;
struct clk		*wdt_clk;

static void wdt_enable(void)
{
	spin_lock(&io_lock);

	if (wdt_clk)
		clk_set_rate(wdt_clk, 1);

	/* stop counter, initiate counter reset */
	__raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
	/*wait for reset to complete. 100% guarantee event */
	while (__raw_readl(WDTIM_COUNTER(wdt_base)))
		cpu_relax();
	/* internal and external reset, stop after that */
	__raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0,
		WDTIM_MCTRL(wdt_base));
	/* configure match output */
	__raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
	/* clear interrupt, just in case */
	__raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
	/* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
	__raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
	__raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
	/*enable counter, stop when debugger active */
	__raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));

	spin_unlock(&io_lock);
}

static void wdt_disable(void)
{
	spin_lock(&io_lock);

	__raw_writel(0, WDTIM_CTRL(wdt_base));	/*stop counter */
	if (wdt_clk)
		clk_set_rate(wdt_clk, 0);

	spin_unlock(&io_lock);
}

static int pnx4008_wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
		return -EBUSY;

	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	wdt_enable();

	return nonseekable_open(inode, file);
}

static ssize_t
pnx4008_wdt_write(struct file *file, const char *data, size_t len,
		  loff_t * ppos)
{
	/*  Can't seek (pwrite) on this device  */
	if (ppos != &file->f_pos)
		return -ESPIPE;

	if (len) {
		if (!nowayout) {
			size_t i;

			clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

			for (i = 0; i != len; i++) {
				char c;

				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					set_bit(WDT_OK_TO_CLOSE, &wdt_status);
			}
		}
		wdt_enable();
	}

	return len;
}

static struct watchdog_info ident = {
	.options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
	    WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
	.identity = "PNX4008 Watchdog",
};

static int
pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
		  unsigned long arg)
{
	int ret = -ENOTTY;
	int time;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		ret = copy_to_user((struct watchdog_info *)arg, &ident,
				   sizeof(ident)) ? -EFAULT : 0;
		break;

	case WDIOC_GETSTATUS:
		ret = put_user(0, (int *)arg);
		break;

	case WDIOC_GETBOOTSTATUS:
		ret = put_user(boot_status, (int *)arg);
		break;

	case WDIOC_SETTIMEOUT:
		ret = get_user(time, (int *)arg);
		if (ret)
			break;

		if (time <= 0 || time > MAX_HEARTBEAT) {
			ret = -EINVAL;
			break;
		}

		heartbeat = time;
		wdt_enable();
		/* Fall through */

	case WDIOC_GETTIMEOUT:
		ret = put_user(heartbeat, (int *)arg);
		break;

	case WDIOC_KEEPALIVE:
		wdt_enable();
		ret = 0;
		break;
	}
	return ret;
}

static int pnx4008_wdt_release(struct inode *inode, struct file *file)
{
	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
		printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");

	wdt_disable();
	clear_bit(WDT_IN_USE, &wdt_status);
	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	return 0;
}

static const struct file_operations pnx4008_wdt_fops = {
	.owner = THIS_MODULE,
	.llseek = no_llseek,
	.write = pnx4008_wdt_write,
	.ioctl = pnx4008_wdt_ioctl,
	.open = pnx4008_wdt_open,
	.release = pnx4008_wdt_release,
};

static struct miscdevice pnx4008_wdt_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &pnx4008_wdt_fops,
};

static int pnx4008_wdt_probe(struct platform_device *pdev)
{
	int ret = 0, size;
	struct resource *res;

	spin_lock_init(&io_lock);

	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
		heartbeat = DEFAULT_HEARTBEAT;

	printk(KERN_INFO MODULE_NAME
		"PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		printk(KERN_INFO MODULE_NAME
			"failed to get memory region resouce\n");
		return -ENOENT;
	}

	size = res->end - res->start + 1;
	wdt_mem = request_mem_region(res->start, size, pdev->name);

	if (wdt_mem == NULL) {
		printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
		return -ENOENT;
	}
	wdt_base = (void __iomem *)IO_ADDRESS(res->start);

	wdt_clk = clk_get(&pdev->dev, "wdt_ck");
	if (!wdt_clk) {
		release_resource(wdt_mem);
		kfree(wdt_mem);
		goto out;
	} else
		clk_set_rate(wdt_clk, 1);

	ret = misc_register(&pnx4008_wdt_miscdev);
	if (ret < 0) {
		printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
		release_resource(wdt_mem);
		kfree(wdt_mem);
		clk_set_rate(wdt_clk, 0);
	} else {
		boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
		    WDIOF_CARDRESET : 0;
		wdt_disable();		/*disable for now */
		set_bit(WDT_DEVICE_INITED, &wdt_status);
	}

out:
	return ret;
}

static int pnx4008_wdt_remove(struct platform_device *pdev)
{
	misc_deregister(&pnx4008_wdt_miscdev);
	if (wdt_clk) {
		clk_set_rate(wdt_clk, 0);
		clk_put(wdt_clk);
		wdt_clk = NULL;
	}
	if (wdt_mem) {
		release_resource(wdt_mem);
		kfree(wdt_mem);
		wdt_mem = NULL;
	}
	return 0;
}

static struct platform_driver platform_wdt_driver = {
	.driver = {
		.name = "watchdog",
	},
	.probe = pnx4008_wdt_probe,
	.remove = pnx4008_wdt_remove,
};

static int __init pnx4008_wdt_init(void)
{
	return platform_driver_register(&platform_wdt_driver);
}

static void __exit pnx4008_wdt_exit(void)
{
	return platform_driver_unregister(&platform_wdt_driver);
}

module_init(pnx4008_wdt_init);
module_exit(pnx4008_wdt_exit);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("PNX4008 Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout,
		 "Set to 1 to keep watchdog running after device release");

MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Commit	Line	Data
9325fa36 VW	1	/*
	2	* drivers/char/watchdog/pnx4008_wdt.c
	3	*
	4	* Watchdog driver for PNX4008 board
	5	*
	6	* Authors: Dmitry Chigirev <source@mvista.com>,
	7	* Vitaly Wool <vitalywool@gmail.com>
	8	* Based on sa1100 driver,
	9	* Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
	10	*
	11	* 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
	12	* the terms of the GNU General Public License version 2. This program
	13	* is licensed "as is" without any warranty of any kind, whether express
	14	* or implied.
	15	*/
	16
9325fa36 VW	17	#include <linux/module.h>
	18	#include <linux/moduleparam.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/fs.h>
	22	#include <linux/miscdevice.h>
	23	#include <linux/watchdog.h>
	24	#include <linux/init.h>
	25	#include <linux/bitops.h>
	26	#include <linux/ioport.h>
	27	#include <linux/device.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/clk.h>
99d2853a	30	#include <linux/spinlock.h>
9325fa36 VW	31
	32	#include <asm/hardware.h>
	33	#include <asm/uaccess.h>
	34	#include <asm/io.h>
	35
	36	#define MODULE_NAME "PNX4008-WDT: "
	37
	38	/* WatchDog Timer - Chapter 23 Page 207 */
	39
	40	#define DEFAULT_HEARTBEAT 19
	41	#define MAX_HEARTBEAT 60
	42
	43	/* Watchdog timer register set definition */
	44	#define WDTIM_INT(p) ((p) + 0x0)
	45	#define WDTIM_CTRL(p) ((p) + 0x4)
	46	#define WDTIM_COUNTER(p) ((p) + 0x8)
	47	#define WDTIM_MCTRL(p) ((p) + 0xC)
	48	#define WDTIM_MATCH0(p) ((p) + 0x10)
	49	#define WDTIM_EMR(p) ((p) + 0x14)
	50	#define WDTIM_PULSE(p) ((p) + 0x18)
	51	#define WDTIM_RES(p) ((p) + 0x1C)
	52
	53	/* WDTIM_INT bit definitions */
	54	#define MATCH_INT 1
	55
	56	/* WDTIM_CTRL bit definitions */
	57	#define COUNT_ENAB 1
	58	#define RESET_COUNT (1<<1)
	59	#define DEBUG_EN (1<<2)
	60
	61	/* WDTIM_MCTRL bit definitions */
	62	#define MR0_INT 1
	63	#undef RESET_COUNT0
	64	#define RESET_COUNT0 (1<<2)
	65	#define STOP_COUNT0 (1<<2)
	66	#define M_RES1 (1<<3)
	67	#define M_RES2 (1<<4)
	68	#define RESFRC1 (1<<5)
	69	#define RESFRC2 (1<<6)
	70
	71	/* WDTIM_EMR bit definitions */
	72	#define EXT_MATCH0 1
	73	#define MATCH_OUTPUT_HIGH (2<<4) /a MATCH_CTRL setting /
	74
	75	/* WDTIM_RES bit definitions */
	76	#define WDOG_RESET 1 /* read only */
	77
	78	#define WDOG_COUNTER_RATE 13000000 /the counter clock is 13 MHz fixed /
	79
28981727	80	static int nowayout = WATCHDOG_NOWAYOUT;
9325fa36 VW	81	static int heartbeat = DEFAULT_HEARTBEAT;
9325fa36 VW	82
99d2853a	83	static spinlock_t io_lock;
9325fa36 VW	84	static unsigned long wdt_status;
	85	#define WDT_IN_USE 0
	86	#define WDT_OK_TO_CLOSE 1
	87	#define WDT_REGION_INITED 2
	88	#define WDT_DEVICE_INITED 3
	89
	90	static unsigned long boot_status;
	91
	92	static struct resource *wdt_mem;
	93	static void __iomem *wdt_base;
	94	struct clk *wdt_clk;
	95
	96	static void wdt_enable(void)
	97	{
99d2853a WVS	98	spin_lock(&io_lock);
99d2853a WVS	99
9325fa36 VW	100	if (wdt_clk)
	101	clk_set_rate(wdt_clk, 1);
	102
	103	/* stop counter, initiate counter reset */
	104	__raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
	105	/wait for reset to complete. 100% guarantee event /
65a64ec3 VW	106	while (__raw_readl(WDTIM_COUNTER(wdt_base)))
65a64ec3 VW	107	cpu_relax();
9325fa36 VW	108	/* internal and external reset, stop after that */
	109	__raw_writel(M_RES2 \| STOP_COUNT0 \| RESET_COUNT0,
	110	WDTIM_MCTRL(wdt_base));
	111	/* configure match output */
	112	__raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
	113	/* clear interrupt, just in case */
	114	__raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
	115	/* the longest pulse period 65541/(1310^6) seconds ~ 5 ms. /
	116	__raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
	117	__raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
	118	/enable counter, stop when debugger active /
	119	__raw_writel(COUNT_ENAB \| DEBUG_EN, WDTIM_CTRL(wdt_base));
99d2853a WVS	120
99d2853a WVS	121	spin_unlock(&io_lock);
9325fa36 VW	122	}
	123
	124	static void wdt_disable(void)
	125	{
99d2853a WVS	126	spin_lock(&io_lock);
99d2853a WVS	127
9325fa36 VW	128	__raw_writel(0, WDTIM_CTRL(wdt_base)); /stop counter /
	129	if (wdt_clk)
	130	clk_set_rate(wdt_clk, 0);
99d2853a WVS	131
99d2853a WVS	132	spin_unlock(&io_lock);
9325fa36 VW	133	}
	134
	135	static int pnx4008_wdt_open(struct inode inode, struct file file)
	136	{
	137	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
	138	return -EBUSY;
	139
	140	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	141
	142	wdt_enable();
	143
	144	return nonseekable_open(inode, file);
	145	}
	146
	147	static ssize_t
	148	pnx4008_wdt_write(struct file file, const char data, size_t len,
	149	loff_t * ppos)
	150	{
	151	/* Can't seek (pwrite) on this device */
	152	if (ppos != &file->f_pos)
	153	return -ESPIPE;
	154
	155	if (len) {
	156	if (!nowayout) {
	157	size_t i;
	158
	159	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	160
	161	for (i = 0; i != len; i++) {
	162	char c;
	163
	164	if (get_user(c, data + i))
	165	return -EFAULT;
	166	if (c == 'V')
	167	set_bit(WDT_OK_TO_CLOSE, &wdt_status);
	168	}
	169	}
	170	wdt_enable();
	171	}
	172
	173	return len;
	174	}
	175
	176	static struct watchdog_info ident = {
	177	.options = WDIOF_CARDRESET \| WDIOF_MAGICCLOSE \|
	178	WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING,
	179	.identity = "PNX4008 Watchdog",
	180	};
	181
	182	static int
	183	pnx4008_wdt_ioctl(struct inode inode, struct file file, unsigned int cmd,
	184	unsigned long arg)
	185	{
f311896a	186	int ret = -ENOTTY;
9325fa36 VW	187	int time;
	188
	189	switch (cmd) {
	190	case WDIOC_GETSUPPORT:
	191	ret = copy_to_user((struct watchdog_info *)arg, &ident,
	192	sizeof(ident)) ? -EFAULT : 0;
	193	break;
	194
	195	case WDIOC_GETSTATUS:
	196	ret = put_user(0, (int *)arg);
	197	break;
	198
	199	case WDIOC_GETBOOTSTATUS:
	200	ret = put_user(boot_status, (int *)arg);
	201	break;
	202
	203	case WDIOC_SETTIMEOUT:
	204	ret = get_user(time, (int *)arg);
	205	if (ret)
	206	break;
	207
	208	if (time <= 0 \|\| time > MAX_HEARTBEAT) {
	209	ret = -EINVAL;
	210	break;
	211	}
	212
	213	heartbeat = time;
	214	wdt_enable();
	215	/* Fall through */
	216
	217	case WDIOC_GETTIMEOUT:
	218	ret = put_user(heartbeat, (int *)arg);
	219	break;
	220
	221	case WDIOC_KEEPALIVE:
	222	wdt_enable();
	223	ret = 0;
	224	break;
	225	}
	226	return ret;
	227	}
	228
	229	static int pnx4008_wdt_release(struct inode inode, struct file file)
	230	{
	231	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
	232	printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");
	233
	234	wdt_disable();
	235	clear_bit(WDT_IN_USE, &wdt_status);
	236	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	237
	238	return 0;
	239	}
	240
2b8693c0	241	static const struct file_operations pnx4008_wdt_fops = {
9325fa36 VW	242	.owner = THIS_MODULE,
	243	.llseek = no_llseek,
	244	.write = pnx4008_wdt_write,
	245	.ioctl = pnx4008_wdt_ioctl,
	246	.open = pnx4008_wdt_open,
	247	.release = pnx4008_wdt_release,
	248	};
	249
	250	static struct miscdevice pnx4008_wdt_miscdev = {
	251	.minor = WATCHDOG_MINOR,
	252	.name = "watchdog",
	253	.fops = &pnx4008_wdt_fops,
	254	};
	255
	256	static int pnx4008_wdt_probe(struct platform_device *pdev)
	257	{
	258	int ret = 0, size;
	259	struct resource *res;
	260
99d2853a WVS	261	spin_lock_init(&io_lock);
99d2853a WVS	262
9325fa36 VW	263	if (heartbeat < 1 \|\| heartbeat > MAX_HEARTBEAT)
	264	heartbeat = DEFAULT_HEARTBEAT;
	265
	266	printk(KERN_INFO MODULE_NAME
	267	"PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);
	268
	269	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	270	if (res == NULL) {
	271	printk(KERN_INFO MODULE_NAME
	272	"failed to get memory region resouce\n");
	273	return -ENOENT;
	274	}
	275
	276	size = res->end - res->start + 1;
	277	wdt_mem = request_mem_region(res->start, size, pdev->name);
	278
	279	if (wdt_mem == NULL) {
	280	printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
	281	return -ENOENT;
	282	}
	283	wdt_base = (void __iomem *)IO_ADDRESS(res->start);
	284
	285	wdt_clk = clk_get(&pdev->dev, "wdt_ck");
	286	if (!wdt_clk) {
	287	release_resource(wdt_mem);
	288	kfree(wdt_mem);
	289	goto out;
	290	} else
	291	clk_set_rate(wdt_clk, 1);
	292
	293	ret = misc_register(&pnx4008_wdt_miscdev);
	294	if (ret < 0) {
	295	printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
	296	release_resource(wdt_mem);
	297	kfree(wdt_mem);
	298	clk_set_rate(wdt_clk, 0);
	299	} else {
	300	boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
	301	WDIOF_CARDRESET : 0;
	302	wdt_disable(); /disable for now /
	303	set_bit(WDT_DEVICE_INITED, &wdt_status);
	304	}
	305
	306	out:
	307	return ret;
	308	}
	309
	310	static int pnx4008_wdt_remove(struct platform_device *pdev)
	311	{
f6764497	312	misc_deregister(&pnx4008_wdt_miscdev);
9325fa36 VW	313	if (wdt_clk) {
	314	clk_set_rate(wdt_clk, 0);
	315	clk_put(wdt_clk);
	316	wdt_clk = NULL;
	317	}
f6764497 WVS	318	if (wdt_mem) {
	319	release_resource(wdt_mem);
	320	kfree(wdt_mem);
	321	wdt_mem = NULL;
	322	}
9325fa36 VW	323	return 0;
	324	}
	325
	326	static struct platform_driver platform_wdt_driver = {
	327	.driver = {
	328	.name = "watchdog",
	329	},
	330	.probe = pnx4008_wdt_probe,
	331	.remove = pnx4008_wdt_remove,
	332	};
	333
	334	static int __init pnx4008_wdt_init(void)
	335	{
	336	return platform_driver_register(&platform_wdt_driver);
	337	}
	338
	339	static void __exit pnx4008_wdt_exit(void)
	340	{
	341	return platform_driver_unregister(&platform_wdt_driver);
	342	}
	343
	344	module_init(pnx4008_wdt_init);
	345	module_exit(pnx4008_wdt_exit);
	346
	347	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	348	MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
	349
	350	module_param(heartbeat, int, 0);
	351	MODULE_PARM_DESC(heartbeat,
	352	"Watchdog heartbeat period in seconds from 1 to "
	353	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	354	__MODULE_STRING(DEFAULT_HEARTBEAT));
	355
	356	module_param(nowayout, int, 0);
	357	MODULE_PARM_DESC(nowayout,
	358	"Set to 1 to keep watchdog running after device release");
	359
	360	MODULE_LICENSE("GPL");
	361	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);