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1 | /***************************************************************************** |
2 | * | |
3 | * Author: Xilinx, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" | |
11 | * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND | |
12 | * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, | |
13 | * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, | |
14 | * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION | |
15 | * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, | |
16 | * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE | |
17 | * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY | |
18 | * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE | |
19 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR | |
20 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF | |
21 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
22 | * FOR A PARTICULAR PURPOSE. | |
23 | * | |
ef141a0b SN |
24 | * (c) Copyright 2003-2007 Xilinx Inc. |
25 | * All rights reserved. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along | |
28 | * with this program; if not, write to the Free Software Foundation, Inc., | |
29 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | *****************************************************************************/ | |
32 | ||
33 | #ifndef XILINX_HWICAP_H_ /* prevent circular inclusions */ | |
34 | #define XILINX_HWICAP_H_ /* by using protection macros */ | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/cdev.h> | |
ef141a0b SN |
38 | #include <linux/platform_device.h> |
39 | ||
1dd24dae | 40 | #include <linux/io.h> |
ef141a0b SN |
41 | |
42 | struct hwicap_drvdata { | |
43 | u32 write_buffer_in_use; /* Always in [0,3] */ | |
44 | u8 write_buffer[4]; | |
45 | u32 read_buffer_in_use; /* Always in [0,3] */ | |
46 | u8 read_buffer[4]; | |
f62f2fdd SN |
47 | resource_size_t mem_start;/* phys. address of the control registers */ |
48 | resource_size_t mem_end; /* phys. address of the control registers */ | |
49 | resource_size_t mem_size; | |
ef141a0b SN |
50 | void __iomem *base_address;/* virt. address of the control registers */ |
51 | ||
52 | struct device *dev; | |
53 | struct cdev cdev; /* Char device structure */ | |
54 | dev_t devt; | |
55 | ||
56 | const struct hwicap_driver_config *config; | |
57 | const struct config_registers *config_regs; | |
58 | void *private_data; | |
59 | bool is_open; | |
f62f2fdd | 60 | struct mutex sem; |
ef141a0b SN |
61 | }; |
62 | ||
63 | struct hwicap_driver_config { | |
6b06fdba SN |
64 | /* Read configuration data given by size into the data buffer. |
65 | Return 0 if successful. */ | |
ef141a0b SN |
66 | int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data, |
67 | u32 size); | |
6b06fdba SN |
68 | /* Write configuration data given by size from the data buffer. |
69 | Return 0 if successful. */ | |
ef141a0b SN |
70 | int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data, |
71 | u32 size); | |
6b06fdba SN |
72 | /* Get the status register, bit pattern given by: |
73 | * D8 - 0 = configuration error | |
74 | * D7 - 1 = alignment found | |
75 | * D6 - 1 = readback in progress | |
76 | * D5 - 0 = abort in progress | |
77 | * D4 - Always 1 | |
78 | * D3 - Always 1 | |
79 | * D2 - Always 1 | |
80 | * D1 - Always 1 | |
81 | * D0 - 1 = operation completed | |
82 | */ | |
83 | u32 (*get_status)(struct hwicap_drvdata *drvdata); | |
84 | /* Reset the hw */ | |
ef141a0b SN |
85 | void (*reset)(struct hwicap_drvdata *drvdata); |
86 | }; | |
87 | ||
84524cf4 MS |
88 | /* Number of times to poll the done register. This has to be large |
89 | * enough to allow an entire configuration to complete. If an entire | |
90 | * page (4kb) is configured at once, that could take up to 4k cycles | |
91 | * with a byte-wide icap interface. In most cases, this driver is | |
92 | * used with a much smaller fifo, but this should be sufficient in the | |
93 | * worst case. | |
94 | */ | |
1790625f | 95 | #define XHI_MAX_RETRIES 5000 |
ef141a0b SN |
96 | |
97 | /************ Constant Definitions *************/ | |
98 | ||
99 | #define XHI_PAD_FRAMES 0x1 | |
100 | ||
101 | /* Mask for calculating configuration packet headers */ | |
102 | #define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL | |
103 | #define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL | |
104 | #define XHI_TYPE_MASK 0x7 | |
105 | #define XHI_REGISTER_MASK 0xF | |
106 | #define XHI_OP_MASK 0x3 | |
107 | ||
108 | #define XHI_TYPE_SHIFT 29 | |
109 | #define XHI_REGISTER_SHIFT 13 | |
110 | #define XHI_OP_SHIFT 27 | |
111 | ||
112 | #define XHI_TYPE_1 1 | |
113 | #define XHI_TYPE_2 2 | |
114 | #define XHI_OP_WRITE 2 | |
115 | #define XHI_OP_READ 1 | |
116 | ||
117 | /* Address Block Types */ | |
118 | #define XHI_FAR_CLB_BLOCK 0 | |
119 | #define XHI_FAR_BRAM_BLOCK 1 | |
120 | #define XHI_FAR_BRAM_INT_BLOCK 2 | |
121 | ||
122 | struct config_registers { | |
123 | u32 CRC; | |
124 | u32 FAR; | |
125 | u32 FDRI; | |
126 | u32 FDRO; | |
127 | u32 CMD; | |
128 | u32 CTL; | |
129 | u32 MASK; | |
130 | u32 STAT; | |
131 | u32 LOUT; | |
132 | u32 COR; | |
133 | u32 MFWR; | |
134 | u32 FLR; | |
135 | u32 KEY; | |
136 | u32 CBC; | |
137 | u32 IDCODE; | |
138 | u32 AXSS; | |
139 | u32 C0R_1; | |
140 | u32 CSOB; | |
141 | u32 WBSTAR; | |
142 | u32 TIMER; | |
143 | u32 BOOTSTS; | |
144 | u32 CTL_1; | |
145 | }; | |
146 | ||
147 | /* Configuration Commands */ | |
148 | #define XHI_CMD_NULL 0 | |
149 | #define XHI_CMD_WCFG 1 | |
150 | #define XHI_CMD_MFW 2 | |
151 | #define XHI_CMD_DGHIGH 3 | |
152 | #define XHI_CMD_RCFG 4 | |
153 | #define XHI_CMD_START 5 | |
154 | #define XHI_CMD_RCAP 6 | |
155 | #define XHI_CMD_RCRC 7 | |
156 | #define XHI_CMD_AGHIGH 8 | |
157 | #define XHI_CMD_SWITCH 9 | |
158 | #define XHI_CMD_GRESTORE 10 | |
159 | #define XHI_CMD_SHUTDOWN 11 | |
160 | #define XHI_CMD_GCAPTURE 12 | |
161 | #define XHI_CMD_DESYNCH 13 | |
162 | #define XHI_CMD_IPROG 15 /* Only in Virtex5 */ | |
163 | #define XHI_CMD_CRCC 16 /* Only in Virtex5 */ | |
164 | #define XHI_CMD_LTIMER 17 /* Only in Virtex5 */ | |
165 | ||
166 | /* Packet constants */ | |
167 | #define XHI_SYNC_PACKET 0xAA995566UL | |
168 | #define XHI_DUMMY_PACKET 0xFFFFFFFFUL | |
169 | #define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT) | |
170 | #define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \ | |
171 | (XHI_OP_READ << XHI_OP_SHIFT)) | |
172 | ||
173 | #define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \ | |
174 | (XHI_OP_WRITE << XHI_OP_SHIFT)) | |
175 | ||
176 | #define XHI_TYPE2_CNT_MASK 0x07FFFFFF | |
177 | ||
178 | #define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL | |
179 | #define XHI_TYPE_1_HEADER_BYTES 4 | |
180 | #define XHI_TYPE_2_HEADER_BYTES 8 | |
181 | ||
182 | /* Constant to use for CRC check when CRC has been disabled */ | |
183 | #define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL | |
184 | ||
6b06fdba SN |
185 | /* Meanings of the bits returned by get_status */ |
186 | #define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */ | |
187 | #define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */ | |
188 | #define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */ | |
189 | #define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */ | |
190 | #define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */ | |
191 | ||
ef141a0b | 192 | /** |
f62f2fdd SN |
193 | * hwicap_type_1_read - Generates a Type 1 read packet header. |
194 | * @reg: is the address of the register to be read back. | |
ef141a0b SN |
195 | * |
196 | * Generates a Type 1 read packet header, which is used to indirectly | |
197 | * read registers in the configuration logic. This packet must then | |
198 | * be sent through the icap device, and a return packet received with | |
199 | * the information. | |
200 | **/ | |
f62f2fdd | 201 | static inline u32 hwicap_type_1_read(u32 reg) |
ef141a0b SN |
202 | { |
203 | return (XHI_TYPE_1 << XHI_TYPE_SHIFT) | | |
f62f2fdd | 204 | (reg << XHI_REGISTER_SHIFT) | |
ef141a0b SN |
205 | (XHI_OP_READ << XHI_OP_SHIFT); |
206 | } | |
207 | ||
208 | /** | |
f62f2fdd SN |
209 | * hwicap_type_1_write - Generates a Type 1 write packet header |
210 | * @reg: is the address of the register to be read back. | |
ef141a0b | 211 | **/ |
f62f2fdd | 212 | static inline u32 hwicap_type_1_write(u32 reg) |
ef141a0b SN |
213 | { |
214 | return (XHI_TYPE_1 << XHI_TYPE_SHIFT) | | |
f62f2fdd | 215 | (reg << XHI_REGISTER_SHIFT) | |
ef141a0b SN |
216 | (XHI_OP_WRITE << XHI_OP_SHIFT); |
217 | } | |
218 | ||
219 | #endif |