[deliverable/linux.git] / drivers / clk / at91 / clk-h32mx.c

/*
 * clk-h32mx.c
 *
 *  Copyright (C) 2014 Atmel
 *
 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#include "pmc.h"

#define H32MX_MAX_FREQ	90000000

struct clk_sama5d4_h32mx {
	struct clk_hw hw;
	struct regmap *regmap;
};

#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)

static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
	unsigned int mckr;

	regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr);
	if (mckr & AT91_PMC_H32MXDIV)
		return parent_rate / 2;

	if (parent_rate > H32MX_MAX_FREQ)
		pr_warn("H32MX clock is too fast\n");
	return parent_rate;
}

static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
				       unsigned long *parent_rate)
{
	unsigned long div;

	if (rate > *parent_rate)
		return *parent_rate;
	div = *parent_rate / 2;
	if (rate < div)
		return div;

	if (rate - div < *parent_rate - rate)
		return div;

	return *parent_rate;
}

static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate)
{
	struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
	u32 mckr = 0;

	if (parent_rate != rate && (parent_rate / 2) != rate)
		return -EINVAL;

	if ((parent_rate / 2) == rate)
		mckr = AT91_PMC_H32MXDIV;

	regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR,
			   AT91_PMC_H32MXDIV, mckr);

	return 0;
}

static const struct clk_ops h32mx_ops = {
	.recalc_rate = clk_sama5d4_h32mx_recalc_rate,
	.round_rate = clk_sama5d4_h32mx_round_rate,
	.set_rate = clk_sama5d4_h32mx_set_rate,
};

static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
{
	struct clk_sama5d4_h32mx *h32mxclk;
	struct clk_init_data init;
	const char *parent_name;
	struct regmap *regmap;
	struct clk *clk;

	regmap = syscon_node_to_regmap(of_get_parent(np));
	if (IS_ERR(regmap))
		return;

	h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
	if (!h32mxclk)
		return;

	parent_name = of_clk_get_parent_name(np, 0);

	init.name = np->name;
	init.ops = &h32mx_ops;
	init.parent_names = parent_name ? &parent_name : NULL;
	init.num_parents = parent_name ? 1 : 0;
	init.flags = CLK_SET_RATE_GATE;

	h32mxclk->hw.init = &init;
	h32mxclk->regmap = regmap;

	clk = clk_register(NULL, &h32mxclk->hw);
	if (IS_ERR(clk)) {
		kfree(h32mxclk);
		return;
	}

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
	       of_sama5d4_clk_h32mx_setup);
Commit	Line	Data
bcc5fd49 AB	1	/*
	2	* clk-h32mx.c
	3	*
	4	* Copyright (C) 2014 Atmel
	5	*
	6	* Alexandre Belloni <alexandre.belloni@free-electrons.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/clk-provider.h>
	16	#include <linux/clkdev.h>
	17	#include <linux/clk/at91_pmc.h>
bcc5fd49	18	#include <linux/of.h>
1bdf0232 BB	19	#include <linux/regmap.h>
1bdf0232 BB	20	#include <linux/mfd/syscon.h>
bcc5fd49 AB	21
	22	#include "pmc.h"
	23
	24	#define H32MX_MAX_FREQ 90000000
	25
	26	struct clk_sama5d4_h32mx {
	27	struct clk_hw hw;
1bdf0232	28	struct regmap *regmap;
bcc5fd49 AB	29	};
	30
	31	#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
	32
	33	static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
	34	unsigned long parent_rate)
	35	{
	36	struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
1bdf0232	37	unsigned int mckr;
bcc5fd49	38
1bdf0232 BB	39	regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr);
1bdf0232 BB	40	if (mckr & AT91_PMC_H32MXDIV)
bcc5fd49 AB	41	return parent_rate / 2;
	42
	43	if (parent_rate > H32MX_MAX_FREQ)
	44	pr_warn("H32MX clock is too fast\n");
	45	return parent_rate;
	46	}
	47
	48	static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
	49	unsigned long *parent_rate)
	50	{
	51	unsigned long div;
	52
	53	if (rate > *parent_rate)
	54	return *parent_rate;
	55	div = *parent_rate / 2;
	56	if (rate < div)
	57	return div;
	58
	59	if (rate - div < *parent_rate - rate)
	60	return div;
	61
	62	return *parent_rate;
	63	}
	64
	65	static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
	66	unsigned long parent_rate)
	67	{
	68	struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
1bdf0232	69	u32 mckr = 0;
bcc5fd49 AB	70
	71	if (parent_rate != rate && (parent_rate / 2) != rate)
	72	return -EINVAL;
	73
bcc5fd49	74	if ((parent_rate / 2) == rate)
1bdf0232 BB	75	mckr = AT91_PMC_H32MXDIV;
	76
	77	regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR,
	78	AT91_PMC_H32MXDIV, mckr);
bcc5fd49 AB	79
	80	return 0;
	81	}
	82
	83	static const struct clk_ops h32mx_ops = {
	84	.recalc_rate = clk_sama5d4_h32mx_recalc_rate,
	85	.round_rate = clk_sama5d4_h32mx_round_rate,
	86	.set_rate = clk_sama5d4_h32mx_set_rate,
	87	};
	88
1bdf0232	89	static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
bcc5fd49 AB	90	{
	91	struct clk_sama5d4_h32mx *h32mxclk;
	92	struct clk_init_data init;
	93	const char *parent_name;
1bdf0232	94	struct regmap *regmap;
bcc5fd49 AB	95	struct clk *clk;
bcc5fd49 AB	96
1bdf0232 BB	97	regmap = syscon_node_to_regmap(of_get_parent(np));
	98	if (IS_ERR(regmap))
	99	return;
	100
bcc5fd49 AB	101	h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
	102	if (!h32mxclk)
	103	return;
	104
	105	parent_name = of_clk_get_parent_name(np, 0);
	106
	107	init.name = np->name;
	108	init.ops = &h32mx_ops;
	109	init.parent_names = parent_name ? &parent_name : NULL;
	110	init.num_parents = parent_name ? 1 : 0;
	111	init.flags = CLK_SET_RATE_GATE;
	112
	113	h32mxclk->hw.init = &init;
1bdf0232	114	h32mxclk->regmap = regmap;
bcc5fd49 AB	115
bcc5fd49 AB	116	clk = clk_register(NULL, &h32mxclk->hw);
cb0ceaf7	117	if (IS_ERR(clk)) {
c76a024e	118	kfree(h32mxclk);
bcc5fd49	119	return;
c76a024e	120	}
bcc5fd49 AB	121
	122	of_clk_add_provider(np, of_clk_src_simple_get, clk);
	123	}
1bdf0232 BB	124	CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
1bdf0232 BB	125	of_sama5d4_clk_h32mx_setup);