[deliverable/linux.git] / drivers / clk / at91 / clk-main.c

/*
 *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/wait.h>

#include "pmc.h"

#define SLOW_CLOCK_FREQ		32768
#define MAINF_DIV		16
#define MAINFRDY_TIMEOUT	(((MAINF_DIV + 1) * USEC_PER_SEC) / \
				 SLOW_CLOCK_FREQ)
#define MAINF_LOOP_MIN_WAIT	(USEC_PER_SEC / SLOW_CLOCK_FREQ)
#define MAINF_LOOP_MAX_WAIT	MAINFRDY_TIMEOUT

#define MOR_KEY_MASK		(0xff << 16)

struct clk_main_osc {
	struct clk_hw hw;
	struct at91_pmc *pmc;
	unsigned int irq;
	wait_queue_head_t wait;
};

#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)

struct clk_main_rc_osc {
	struct clk_hw hw;
	struct at91_pmc *pmc;
	unsigned int irq;
	wait_queue_head_t wait;
	unsigned long frequency;
	unsigned long accuracy;
};

#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)

struct clk_rm9200_main {
	struct clk_hw hw;
	struct at91_pmc *pmc;
};

#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)

struct clk_sam9x5_main {
	struct clk_hw hw;
	struct at91_pmc *pmc;
	unsigned int irq;
	wait_queue_head_t wait;
	u8 parent;
};

#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)

static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id)
{
	struct clk_main_osc *osc = dev_id;

	wake_up(&osc->wait);
	disable_irq_nosync(osc->irq);

	return IRQ_HANDLED;
}

static int clk_main_osc_prepare(struct clk_hw *hw)
{
	struct clk_main_osc *osc = to_clk_main_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp;

	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
	if (tmp & AT91_PMC_OSCBYPASS)
		return 0;

	if (!(tmp & AT91_PMC_MOSCEN)) {
		tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
		pmc_write(pmc, AT91_CKGR_MOR, tmp);
	}

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
		enable_irq(osc->irq);
		wait_event(osc->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
	}

	return 0;
}

static void clk_main_osc_unprepare(struct clk_hw *hw)
{
	struct clk_main_osc *osc = to_clk_main_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);

	if (tmp & AT91_PMC_OSCBYPASS)
		return;

	if (!(tmp & AT91_PMC_MOSCEN))
		return;

	tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
	pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
}

static int clk_main_osc_is_prepared(struct clk_hw *hw)
{
	struct clk_main_osc *osc = to_clk_main_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);

	if (tmp & AT91_PMC_OSCBYPASS)
		return 1;

	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) &&
		  (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN));
}

static const struct clk_ops main_osc_ops = {
	.prepare = clk_main_osc_prepare,
	.unprepare = clk_main_osc_unprepare,
	.is_prepared = clk_main_osc_is_prepared,
};

static struct clk * __init
at91_clk_register_main_osc(struct at91_pmc *pmc,
			   unsigned int irq,
			   const char *name,
			   const char *parent_name,
			   bool bypass)
{
	int ret;
	struct clk_main_osc *osc;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !irq || !name || !parent_name)
		return ERR_PTR(-EINVAL);

	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
	if (!osc)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &main_osc_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = CLK_IGNORE_UNUSED;

	osc->hw.init = &init;
	osc->pmc = pmc;
	osc->irq = irq;

	init_waitqueue_head(&osc->wait);
	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
	ret = request_irq(osc->irq, clk_main_osc_irq_handler,
			  IRQF_TRIGGER_HIGH, name, osc);
	if (ret)
		return ERR_PTR(ret);

	if (bypass)
		pmc_write(pmc, AT91_CKGR_MOR,
			  (pmc_read(pmc, AT91_CKGR_MOR) &
			   ~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) |
			  AT91_PMC_OSCBYPASS | AT91_PMC_KEY);

	clk = clk_register(NULL, &osc->hw);
	if (IS_ERR(clk)) {
		free_irq(irq, osc);
		kfree(osc);
	}

	return clk;
}

void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np,
					     struct at91_pmc *pmc)
{
	struct clk *clk;
	unsigned int irq;
	const char *name = np->name;
	const char *parent_name;
	bool bypass;

	of_property_read_string(np, "clock-output-names", &name);
	bypass = of_property_read_bool(np, "atmel,osc-bypass");
	parent_name = of_clk_get_parent_name(np, 0);

	irq = irq_of_parse_and_map(np, 0);
	if (!irq)
		return;

	clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}

static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id)
{
	struct clk_main_rc_osc *osc = dev_id;

	wake_up(&osc->wait);
	disable_irq_nosync(osc->irq);

	return IRQ_HANDLED;
}

static int clk_main_rc_osc_prepare(struct clk_hw *hw)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp;

	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;

	if (!(tmp & AT91_PMC_MOSCRCEN)) {
		tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY;
		pmc_write(pmc, AT91_CKGR_MOR, tmp);
	}

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) {
		enable_irq(osc->irq);
		wait_event(osc->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS);
	}

	return 0;
}

static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);

	if (!(tmp & AT91_PMC_MOSCRCEN))
		return;

	tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN);
	pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
}

static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
	struct at91_pmc *pmc = osc->pmc;

	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) &&
		  (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN));
}

static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);

	return osc->frequency;
}

static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
						     unsigned long parent_acc)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);

	return osc->accuracy;
}

static const struct clk_ops main_rc_osc_ops = {
	.prepare = clk_main_rc_osc_prepare,
	.unprepare = clk_main_rc_osc_unprepare,
	.is_prepared = clk_main_rc_osc_is_prepared,
	.recalc_rate = clk_main_rc_osc_recalc_rate,
	.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
};

static struct clk * __init
at91_clk_register_main_rc_osc(struct at91_pmc *pmc,
			      unsigned int irq,
			      const char *name,
			      u32 frequency, u32 accuracy)
{
	int ret;
	struct clk_main_rc_osc *osc;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !irq || !name || !frequency)
		return ERR_PTR(-EINVAL);

	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
	if (!osc)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &main_rc_osc_ops;
	init.parent_names = NULL;
	init.num_parents = 0;
	init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;

	osc->hw.init = &init;
	osc->pmc = pmc;
	osc->irq = irq;
	osc->frequency = frequency;
	osc->accuracy = accuracy;

	init_waitqueue_head(&osc->wait);
	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
	ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler,
			  IRQF_TRIGGER_HIGH, name, osc);
	if (ret)
		return ERR_PTR(ret);

	clk = clk_register(NULL, &osc->hw);
	if (IS_ERR(clk)) {
		free_irq(irq, osc);
		kfree(osc);
	}

	return clk;
}

void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np,
						struct at91_pmc *pmc)
{
	struct clk *clk;
	unsigned int irq;
	u32 frequency = 0;
	u32 accuracy = 0;
	const char *name = np->name;

	of_property_read_string(np, "clock-output-names", &name);
	of_property_read_u32(np, "clock-frequency", &frequency);
	of_property_read_u32(np, "clock-accuracy", &accuracy);

	irq = irq_of_parse_and_map(np, 0);
	if (!irq)
		return;

	clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency,
					    accuracy);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}


static int clk_main_probe_frequency(struct at91_pmc *pmc)
{
	unsigned long prep_time, timeout;
	u32 tmp;

	timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
	do {
		prep_time = jiffies;
		tmp = pmc_read(pmc, AT91_CKGR_MCFR);
		if (tmp & AT91_PMC_MAINRDY)
			return 0;
		usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
	} while (time_before(prep_time, timeout));

	return -ETIMEDOUT;
}

static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc,
					  unsigned long parent_rate)
{
	u32 tmp;

	if (parent_rate)
		return parent_rate;

	tmp = pmc_read(pmc, AT91_CKGR_MCFR);
	if (!(tmp & AT91_PMC_MAINRDY))
		return 0;

	return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
}

static int clk_rm9200_main_prepare(struct clk_hw *hw)
{
	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);

	return clk_main_probe_frequency(clkmain->pmc);
}

static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
{
	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);

	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY);
}

static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);

	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
}

static const struct clk_ops rm9200_main_ops = {
	.prepare = clk_rm9200_main_prepare,
	.is_prepared = clk_rm9200_main_is_prepared,
	.recalc_rate = clk_rm9200_main_recalc_rate,
};

static struct clk * __init
at91_clk_register_rm9200_main(struct at91_pmc *pmc,
			      const char *name,
			      const char *parent_name)
{
	struct clk_rm9200_main *clkmain;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !name)
		return ERR_PTR(-EINVAL);

	if (!parent_name)
		return ERR_PTR(-EINVAL);

	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	if (!clkmain)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &rm9200_main_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = 0;

	clkmain->hw.init = &init;
	clkmain->pmc = pmc;

	clk = clk_register(NULL, &clkmain->hw);
	if (IS_ERR(clk))
		kfree(clkmain);

	return clk;
}

void __init of_at91rm9200_clk_main_setup(struct device_node *np,
					 struct at91_pmc *pmc)
{
	struct clk *clk;
	const char *parent_name;
	const char *name = np->name;

	parent_name = of_clk_get_parent_name(np, 0);
	of_property_read_string(np, "clock-output-names", &name);

	clk = at91_clk_register_rm9200_main(pmc, name, parent_name);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}

static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id)
{
	struct clk_sam9x5_main *clkmain = dev_id;

	wake_up(&clkmain->wait);
	disable_irq_nosync(clkmain->irq);

	return IRQ_HANDLED;
}

static int clk_sam9x5_main_prepare(struct clk_hw *hw)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	struct at91_pmc *pmc = clkmain->pmc;

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
		enable_irq(clkmain->irq);
		wait_event(clkmain->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	}

	return clk_main_probe_frequency(pmc);
}

static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);

	return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
}

static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);

	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
}

static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	struct at91_pmc *pmc = clkmain->pmc;
	u32 tmp;

	if (index > 1)
		return -EINVAL;

	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;

	if (index && !(tmp & AT91_PMC_MOSCSEL))
		pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
	else if (!index && (tmp & AT91_PMC_MOSCSEL))
		pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
		enable_irq(clkmain->irq);
		wait_event(clkmain->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	}

	return 0;
}

static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);

	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN);
}

static const struct clk_ops sam9x5_main_ops = {
	.prepare = clk_sam9x5_main_prepare,
	.is_prepared = clk_sam9x5_main_is_prepared,
	.recalc_rate = clk_sam9x5_main_recalc_rate,
	.set_parent = clk_sam9x5_main_set_parent,
	.get_parent = clk_sam9x5_main_get_parent,
};

static struct clk * __init
at91_clk_register_sam9x5_main(struct at91_pmc *pmc,
			      unsigned int irq,
			      const char *name,
			      const char **parent_names,
			      int num_parents)
{
	int ret;
	struct clk_sam9x5_main *clkmain;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !irq || !name)
		return ERR_PTR(-EINVAL);

	if (!parent_names || !num_parents)
		return ERR_PTR(-EINVAL);

	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	if (!clkmain)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &sam9x5_main_ops;
	init.parent_names = parent_names;
	init.num_parents = num_parents;
	init.flags = CLK_SET_PARENT_GATE;

	clkmain->hw.init = &init;
	clkmain->pmc = pmc;
	clkmain->irq = irq;
	clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) &
			     AT91_PMC_MOSCEN);
	init_waitqueue_head(&clkmain->wait);
	irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
	ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler,
			  IRQF_TRIGGER_HIGH, name, clkmain);
	if (ret)
		return ERR_PTR(ret);

	clk = clk_register(NULL, &clkmain->hw);
	if (IS_ERR(clk)) {
		free_irq(clkmain->irq, clkmain);
		kfree(clkmain);
	}

	return clk;
}

void __init of_at91sam9x5_clk_main_setup(struct device_node *np,
					 struct at91_pmc *pmc)
{
	struct clk *clk;
	const char *parent_names[2];
	int num_parents;
	unsigned int irq;
	const char *name = np->name;
	int i;

	num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
	if (num_parents <= 0 || num_parents > 2)
		return;

	for (i = 0; i < num_parents; ++i) {
		parent_names[i] = of_clk_get_parent_name(np, i);
		if (!parent_names[i])
			return;
	}

	of_property_read_string(np, "clock-output-names", &name);

	irq = irq_of_parse_and_map(np, 0);
	if (!irq)
		return;

	clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names,
					    num_parents);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
Commit	Line	Data
38d34c31 BB	1	/*
	2	* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	*/
	10
	11	#include <linux/clk-provider.h>
	12	#include <linux/clkdev.h>
	13	#include <linux/clk/at91_pmc.h>
	14	#include <linux/delay.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/io.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/sched.h>
	22	#include <linux/wait.h>
	23
	24	#include "pmc.h"
	25
	26	#define SLOW_CLOCK_FREQ 32768
	27	#define MAINF_DIV 16
	28	#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
	29	SLOW_CLOCK_FREQ)
	30	#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
	31	#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
	32
27cb1c20 BB	33	#define MOR_KEY_MASK (0xff << 16)
	34
	35	struct clk_main_osc {
38d34c31 BB	36	struct clk_hw hw;
38d34c31 BB	37	struct at91_pmc *pmc;
38d34c31 BB	38	unsigned int irq;
	39	wait_queue_head_t wait;
	40	};
	41
27cb1c20 BB	42	#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
	43
	44	struct clk_main_rc_osc {
	45	struct clk_hw hw;
	46	struct at91_pmc *pmc;
	47	unsigned int irq;
	48	wait_queue_head_t wait;
	49	unsigned long frequency;
	50	unsigned long accuracy;
	51	};
	52
	53	#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
	54
	55	struct clk_rm9200_main {
	56	struct clk_hw hw;
	57	struct at91_pmc *pmc;
	58	};
	59
	60	#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
38d34c31	61
27cb1c20 BB	62	struct clk_sam9x5_main {
	63	struct clk_hw hw;
	64	struct at91_pmc *pmc;
	65	unsigned int irq;
	66	wait_queue_head_t wait;
	67	u8 parent;
	68	};
	69
	70	#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
	71
	72	static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id)
38d34c31	73	{
27cb1c20	74	struct clk_main_osc *osc = dev_id;
38d34c31	75
27cb1c20 BB	76	wake_up(&osc->wait);
27cb1c20 BB	77	disable_irq_nosync(osc->irq);
38d34c31 BB	78
	79	return IRQ_HANDLED;
	80	}
	81
27cb1c20	82	static int clk_main_osc_prepare(struct clk_hw *hw)
38d34c31	83	{
27cb1c20 BB	84	struct clk_main_osc *osc = to_clk_main_osc(hw);
27cb1c20 BB	85	struct at91_pmc *pmc = osc->pmc;
38d34c31 BB	86	u32 tmp;
38d34c31 BB	87
27cb1c20 BB	88	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
	89	if (tmp & AT91_PMC_OSCBYPASS)
	90	return 0;
	91
	92	if (!(tmp & AT91_PMC_MOSCEN)) {
	93	tmp \|= AT91_PMC_MOSCEN \| AT91_PMC_KEY;
	94	pmc_write(pmc, AT91_CKGR_MOR, tmp);
	95	}
	96
38d34c31	97	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
27cb1c20 BB	98	enable_irq(osc->irq);
27cb1c20 BB	99	wait_event(osc->wait,
38d34c31 BB	100	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
	101	}
	102
27cb1c20 BB	103	return 0;
	104	}
	105
	106	static void clk_main_osc_unprepare(struct clk_hw *hw)
	107	{
	108	struct clk_main_osc *osc = to_clk_main_osc(hw);
	109	struct at91_pmc *pmc = osc->pmc;
	110	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
	111
	112	if (tmp & AT91_PMC_OSCBYPASS)
	113	return;
	114
	115	if (!(tmp & AT91_PMC_MOSCEN))
	116	return;
	117
	118	tmp &= ~(AT91_PMC_KEY \| AT91_PMC_MOSCEN);
	119	pmc_write(pmc, AT91_CKGR_MOR, tmp \| AT91_PMC_KEY);
	120	}
	121
	122	static int clk_main_osc_is_prepared(struct clk_hw *hw)
	123	{
	124	struct clk_main_osc *osc = to_clk_main_osc(hw);
	125	struct at91_pmc *pmc = osc->pmc;
	126	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
	127
	128	if (tmp & AT91_PMC_OSCBYPASS)
	129	return 1;
	130
	131	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) &&
	132	(pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN));
	133	}
	134
	135	static const struct clk_ops main_osc_ops = {
	136	.prepare = clk_main_osc_prepare,
	137	.unprepare = clk_main_osc_unprepare,
	138	.is_prepared = clk_main_osc_is_prepared,
	139	};
	140
	141	static struct clk * __init
	142	at91_clk_register_main_osc(struct at91_pmc *pmc,
	143	unsigned int irq,
	144	const char *name,
	145	const char *parent_name,
	146	bool bypass)
	147	{
	148	int ret;
	149	struct clk_main_osc *osc;
	150	struct clk *clk = NULL;
	151	struct clk_init_data init;
	152
	153	if (!pmc \|\| !irq \|\| !name \|\| !parent_name)
	154	return ERR_PTR(-EINVAL);
	155
	156	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
	157	if (!osc)
	158	return ERR_PTR(-ENOMEM);
	159
	160	init.name = name;
	161	init.ops = &main_osc_ops;
	162	init.parent_names = &parent_name;
	163	init.num_parents = 1;
	164	init.flags = CLK_IGNORE_UNUSED;
	165
	166	osc->hw.init = &init;
167	osc->pmc = pmc;
168	osc->irq = irq;
169
170	init_waitqueue_head(&osc->wait);
171	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
172	ret = request_irq(osc->irq, clk_main_osc_irq_handler,
173	IRQF_TRIGGER_HIGH, name, osc);
174	if (ret)
175	return ERR_PTR(ret);
176
177	if (bypass)
178	pmc_write(pmc, AT91_CKGR_MOR,
179	(pmc_read(pmc, AT91_CKGR_MOR) &
180	~(MOR_KEY_MASK \| AT91_PMC_MOSCEN)) \|
181	AT91_PMC_OSCBYPASS \| AT91_PMC_KEY);
182
183	clk = clk_register(NULL, &osc->hw);
184	if (IS_ERR(clk)) {
185	free_irq(irq, osc);
186	kfree(osc);
187	}
188
189	return clk;
190	}
191
192	void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np,
193	struct at91_pmc *pmc)
194	{
195	struct clk *clk;
196	unsigned int irq;
197	const char *name = np->name;
198	const char *parent_name;
199	bool bypass;
200
201	of_property_read_string(np, "clock-output-names", &name);
202	bypass = of_property_read_bool(np, "atmel,osc-bypass");
203	parent_name = of_clk_get_parent_name(np, 0);
204
205	irq = irq_of_parse_and_map(np, 0);
206	if (!irq)
207	return;
208
209	clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass);
210	if (IS_ERR(clk))
211	return;
212
213	of_clk_add_provider(np, of_clk_src_simple_get, clk);
214	}
215
216	static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id)
217	{
218	struct clk_main_rc_osc *osc = dev_id;
219
220	wake_up(&osc->wait);
221	disable_irq_nosync(osc->irq);
222
223	return IRQ_HANDLED;
224	}
225
226	static int clk_main_rc_osc_prepare(struct clk_hw *hw)
227	{
228	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
229	struct at91_pmc *pmc = osc->pmc;
230	u32 tmp;
231
232	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
233
234	if (!(tmp & AT91_PMC_MOSCRCEN)) {
235	tmp \|= AT91_PMC_MOSCRCEN \| AT91_PMC_KEY;
236	pmc_write(pmc, AT91_CKGR_MOR, tmp);
237	}
238
239	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) {
240	enable_irq(osc->irq);
241	wait_event(osc->wait,
242	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS);
243	}
244
245	return 0;
246	}
247
248	static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
249	{
250	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
251	struct at91_pmc *pmc = osc->pmc;
252	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
253
254	if (!(tmp & AT91_PMC_MOSCRCEN))
255	return;
256
257	tmp &= ~(MOR_KEY_MASK \| AT91_PMC_MOSCRCEN);
258	pmc_write(pmc, AT91_CKGR_MOR, tmp \| AT91_PMC_KEY);
259	}
260
261	static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
262	{
263	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
264	struct at91_pmc *pmc = osc->pmc;
265
266	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) &&
267	(pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN));
268	}
269
270	static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
271	unsigned long parent_rate)
272	{
273	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
274
275	return osc->frequency;
276	}
277
278	static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
279	unsigned long parent_acc)
280	{
281	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
282
283	return osc->accuracy;
284	}
285
286	static const struct clk_ops main_rc_osc_ops = {
287	.prepare = clk_main_rc_osc_prepare,
288	.unprepare = clk_main_rc_osc_unprepare,
289	.is_prepared = clk_main_rc_osc_is_prepared,
290	.recalc_rate = clk_main_rc_osc_recalc_rate,
291	.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
292	};
293
294	static struct clk * __init
295	at91_clk_register_main_rc_osc(struct at91_pmc *pmc,
296	unsigned int irq,
297	const char *name,
298	u32 frequency, u32 accuracy)
299	{
300	int ret;
301	struct clk_main_rc_osc *osc;
302	struct clk *clk = NULL;
303	struct clk_init_data init;
304
305	if (!pmc \|\| !irq \|\| !name \|\| !frequency)
306	return ERR_PTR(-EINVAL);
307
308	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
309	if (!osc)
310	return ERR_PTR(-ENOMEM);
311
312	init.name = name;
313	init.ops = &main_rc_osc_ops;
314	init.parent_names = NULL;
315	init.num_parents = 0;
316	init.flags = CLK_IS_ROOT \| CLK_IGNORE_UNUSED;
317
318	osc->hw.init = &init;
319	osc->pmc = pmc;
320	osc->irq = irq;
321	osc->frequency = frequency;
322	osc->accuracy = accuracy;
323
324	init_waitqueue_head(&osc->wait);
325	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
326	ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler,
327	IRQF_TRIGGER_HIGH, name, osc);
328	if (ret)
329	return ERR_PTR(ret);
330
331	clk = clk_register(NULL, &osc->hw);
332	if (IS_ERR(clk)) {
333	free_irq(irq, osc);
334	kfree(osc);
335	}
336
337	return clk;
338	}
339
340	void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np,
341	struct at91_pmc *pmc)
342	{
343	struct clk *clk;
344	unsigned int irq;
345	u32 frequency = 0;
346	u32 accuracy = 0;
347	const char *name = np->name;
348
349	of_property_read_string(np, "clock-output-names", &name);
350	of_property_read_u32(np, "clock-frequency", &frequency);
351	of_property_read_u32(np, "clock-accuracy", &accuracy);
352
353	irq = irq_of_parse_and_map(np, 0);
354	if (!irq)
355	return;
356
357	clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency,
358	accuracy);
359	if (IS_ERR(clk))
360	return;
361
362	of_clk_add_provider(np, of_clk_src_simple_get, clk);
363	}
364
365
366	static int clk_main_probe_frequency(struct at91_pmc *pmc)
367	{
368	unsigned long prep_time, timeout;
369	u32 tmp;
38d34c31 BB	370
	371	timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
	372	do {
27cb1c20	373	prep_time = jiffies;
38d34c31 BB	374	tmp = pmc_read(pmc, AT91_CKGR_MCFR);
	375	if (tmp & AT91_PMC_MAINRDY)
	376	return 0;
	377	usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
27cb1c20	378	} while (time_before(prep_time, timeout));
38d34c31	379
27cb1c20	380	return -ETIMEDOUT;
38d34c31 BB	381	}
38d34c31 BB	382
27cb1c20 BB	383	static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc,
27cb1c20 BB	384	unsigned long parent_rate)
38d34c31	385	{
27cb1c20 BB	386	u32 tmp;
	387
	388	if (parent_rate)
	389	return parent_rate;
	390
	391	tmp = pmc_read(pmc, AT91_CKGR_MCFR);
	392	if (!(tmp & AT91_PMC_MAINRDY))
	393	return 0;
38d34c31	394
27cb1c20	395	return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
38d34c31 BB	396	}
38d34c31 BB	397
27cb1c20	398	static int clk_rm9200_main_prepare(struct clk_hw *hw)
38d34c31	399	{
27cb1c20 BB	400	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
	401
	402	return clk_main_probe_frequency(clkmain->pmc);
	403	}
	404
	405	static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
	406	{
	407	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
	408
	409	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY);
	410	}
	411
	412	static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
	413	unsigned long parent_rate)
	414	{
	415	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
	416
	417	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
	418	}
	419
	420	static const struct clk_ops rm9200_main_ops = {
	421	.prepare = clk_rm9200_main_prepare,
	422	.is_prepared = clk_rm9200_main_is_prepared,
	423	.recalc_rate = clk_rm9200_main_recalc_rate,
	424	};
	425
	426	static struct clk * __init
	427	at91_clk_register_rm9200_main(struct at91_pmc *pmc,
	428	const char *name,
	429	const char *parent_name)
	430	{
	431	struct clk_rm9200_main *clkmain;
	432	struct clk *clk = NULL;
	433	struct clk_init_data init;
	434
	435	if (!pmc \|\| !name)
	436	return ERR_PTR(-EINVAL);
	437
	438	if (!parent_name)
	439	return ERR_PTR(-EINVAL);
	440
	441	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	442	if (!clkmain)
	443	return ERR_PTR(-ENOMEM);
	444
	445	init.name = name;
	446	init.ops = &rm9200_main_ops;
	447	init.parent_names = &parent_name;
	448	init.num_parents = 1;
	449	init.flags = 0;
	450
	451	clkmain->hw.init = &init;
	452	clkmain->pmc = pmc;
	453
	454	clk = clk_register(NULL, &clkmain->hw);
	455	if (IS_ERR(clk))
	456	kfree(clkmain);
	457
	458	return clk;
	459	}
	460
	461	void __init of_at91rm9200_clk_main_setup(struct device_node *np,
	462	struct at91_pmc *pmc)
	463	{
464	struct clk *clk;
465	const char *parent_name;
466	const char *name = np->name;
467
468	parent_name = of_clk_get_parent_name(np, 0);
469	of_property_read_string(np, "clock-output-names", &name);
470
471	clk = at91_clk_register_rm9200_main(pmc, name, parent_name);
472	if (IS_ERR(clk))
473	return;
474
475	of_clk_add_provider(np, of_clk_src_simple_get, clk);
476	}
477
478	static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id)
479	{
480	struct clk_sam9x5_main *clkmain = dev_id;
481
482	wake_up(&clkmain->wait);
483	disable_irq_nosync(clkmain->irq);
484
485	return IRQ_HANDLED;
486	}
487
488	static int clk_sam9x5_main_prepare(struct clk_hw *hw)
489	{
490	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
38d34c31 BB	491	struct at91_pmc *pmc = clkmain->pmc;
38d34c31 BB	492
27cb1c20 BB	493	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
	494	enable_irq(clkmain->irq);
	495	wait_event(clkmain->wait,
	496	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	497	}
	498
	499	return clk_main_probe_frequency(pmc);
	500	}
38d34c31	501
27cb1c20 BB	502	static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
	503	{
	504	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
38d34c31	505
27cb1c20	506	return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
38d34c31 BB	507	}
38d34c31 BB	508
27cb1c20 BB	509	static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
	510	unsigned long parent_rate)
	511	{
	512	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	513
	514	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
	515	}
	516
	517	static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
	518	{
	519	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	520	struct at91_pmc *pmc = clkmain->pmc;
	521	u32 tmp;
	522
	523	if (index > 1)
	524	return -EINVAL;
	525
	526	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
	527
	528	if (index && !(tmp & AT91_PMC_MOSCSEL))
	529	pmc_write(pmc, AT91_CKGR_MOR, tmp \| AT91_PMC_MOSCSEL);
	530	else if (!index && (tmp & AT91_PMC_MOSCSEL))
	531	pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
	532
	533	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
	534	enable_irq(clkmain->irq);
	535	wait_event(clkmain->wait,
	536	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	537	}
	538
	539	return 0;
	540	}
	541
	542	static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
	543	{
	544	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	545
	546	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN);
	547	}
	548
	549	static const struct clk_ops sam9x5_main_ops = {
	550	.prepare = clk_sam9x5_main_prepare,
	551	.is_prepared = clk_sam9x5_main_is_prepared,
	552	.recalc_rate = clk_sam9x5_main_recalc_rate,
	553	.set_parent = clk_sam9x5_main_set_parent,
	554	.get_parent = clk_sam9x5_main_get_parent,
38d34c31 BB	555	};
	556
	557	static struct clk * __init
27cb1c20 BB	558	at91_clk_register_sam9x5_main(struct at91_pmc *pmc,
	559	unsigned int irq,
	560	const char *name,
	561	const char **parent_names,
	562	int num_parents)
38d34c31 BB	563	{
38d34c31 BB	564	int ret;
27cb1c20	565	struct clk_sam9x5_main *clkmain;
38d34c31 BB	566	struct clk *clk = NULL;
	567	struct clk_init_data init;
	568
	569	if (!pmc \|\| !irq \|\| !name)
	570	return ERR_PTR(-EINVAL);
	571
27cb1c20	572	if (!parent_names \|\| !num_parents)
38d34c31 BB	573	return ERR_PTR(-EINVAL);
	574
	575	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	576	if (!clkmain)
	577	return ERR_PTR(-ENOMEM);
	578
	579	init.name = name;
27cb1c20 BB	580	init.ops = &sam9x5_main_ops;
	581	init.parent_names = parent_names;
	582	init.num_parents = num_parents;
	583	init.flags = CLK_SET_PARENT_GATE;
38d34c31 BB	584
38d34c31 BB	585	clkmain->hw.init = &init;
38d34c31 BB	586	clkmain->pmc = pmc;
38d34c31 BB	587	clkmain->irq = irq;
27cb1c20 BB	588	clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) &
27cb1c20 BB	589	AT91_PMC_MOSCEN);
38d34c31 BB	590	init_waitqueue_head(&clkmain->wait);
38d34c31 BB	591	irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
27cb1c20 BB	592	ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler,
27cb1c20 BB	593	IRQF_TRIGGER_HIGH, name, clkmain);
38d34c31 BB	594	if (ret)
	595	return ERR_PTR(ret);
	596
	597	clk = clk_register(NULL, &clkmain->hw);
	598	if (IS_ERR(clk)) {
	599	free_irq(clkmain->irq, clkmain);
	600	kfree(clkmain);
	601	}
	602
	603	return clk;
	604	}
	605
27cb1c20 BB	606	void __init of_at91sam9x5_clk_main_setup(struct device_node *np,
27cb1c20 BB	607	struct at91_pmc *pmc)
38d34c31 BB	608	{
38d34c31 BB	609	struct clk *clk;
27cb1c20 BB	610	const char *parent_names[2];
27cb1c20 BB	611	int num_parents;
38d34c31	612	unsigned int irq;
38d34c31	613	const char *name = np->name;
27cb1c20 BB	614	int i;
	615
	616	num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
	617	if (num_parents <= 0 \|\| num_parents > 2)
	618	return;
	619
	620	for (i = 0; i < num_parents; ++i) {
	621	parent_names[i] = of_clk_get_parent_name(np, i);
	622	if (!parent_names[i])
	623	return;
	624	}
38d34c31	625
38d34c31	626	of_property_read_string(np, "clock-output-names", &name);
27cb1c20	627
38d34c31 BB	628	irq = irq_of_parse_and_map(np, 0);
	629	if (!irq)
	630	return;
	631
27cb1c20 BB	632	clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names,
27cb1c20 BB	633	num_parents);
38d34c31 BB	634	if (IS_ERR(clk))
	635	return;
	636
	637	of_clk_add_provider(np, of_clk_src_simple_get, clk);
	638	}